* [PATCH v3 01/13] powerpc/64s/exception: clean up system call entry
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-07-04 15:52 ` Michael Ellerman
2019-06-28 5:33 ` [PATCH v3 02/13] powerpc/64s/exception: avoid SPR RAW scoreboard stall in real mode entry Nicholas Piggin
` (11 subsequent siblings)
12 siblings, 1 reply; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
syscall / hcall entry unnecessarily differs between KVM and non-KVM
builds. Move the SMT priority instruction to the same location
(after INTERRUPT_TO_KERNEL).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 24 +++++++-----------------
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index f51b3a5fd110..98321ded8df6 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1638,10 +1638,8 @@ EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
std r10,PACA_EXGEN+EX_R10(r13)
INTERRUPT_TO_KERNEL
KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */
- HMT_MEDIUM
mfctr r9
#else
- HMT_MEDIUM
mr r9,r13
GET_PACA(r13)
INTERRUPT_TO_KERNEL
@@ -1653,11 +1651,14 @@ BEGIN_FTR_SECTION
beq- 1f
END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
#endif
- /* We reach here with PACA in r13, r13 in r9, and HMT_MEDIUM. */
- .if ! \virt
+ /* We reach here with PACA in r13, r13 in r9. */
mfspr r11,SPRN_SRR0
mfspr r12,SPRN_SRR1
+
+ HMT_MEDIUM
+
+ .if ! \virt
__LOAD_HANDLER(r10, system_call_common)
mtspr SPRN_SRR0,r10
ld r10,PACAKMSR(r13)
@@ -1665,24 +1666,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
RFI_TO_KERNEL
b . /* prevent speculative execution */
.else
+ li r10,MSR_RI
+ mtmsrd r10,1 /* Set RI (EE=0) */
#ifdef CONFIG_RELOCATABLE
- /*
- * We can't branch directly so we do it via the CTR which
- * is volatile across system calls.
- */
__LOAD_HANDLER(r10, system_call_common)
mtctr r10
- mfspr r11,SPRN_SRR0
- mfspr r12,SPRN_SRR1
- li r10,MSR_RI
- mtmsrd r10,1
bctr
#else
- /* We can branch directly */
- mfspr r11,SPRN_SRR0
- mfspr r12,SPRN_SRR1
- li r10,MSR_RI
- mtmsrd r10,1 /* Set RI (EE=0) */
b system_call_common
#endif
.endif
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 02/13] powerpc/64s/exception: avoid SPR RAW scoreboard stall in real mode entry
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 01/13] powerpc/64s/exception: clean up system call entry Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 03/13] powerpc/64s/exception: mtmsrd L=1 cleanup Nicholas Piggin
` (10 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Move SPR reads ahead of writes. Real mode entry that is not a KVM
guest is rare these days, but bad practice propagates.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 98321ded8df6..c3a9cb8cdfd3 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -183,19 +183,19 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
.endif
.if \hsrr
mfspr r11,SPRN_HSRR0 /* save HSRR0 */
+ mfspr r12,SPRN_HSRR1 /* and HSRR1 */
+ mtspr SPRN_HSRR1,r10
.else
mfspr r11,SPRN_SRR0 /* save SRR0 */
+ mfspr r12,SPRN_SRR1 /* and SRR1 */
+ mtspr SPRN_SRR1,r10
.endif
- LOAD_HANDLER(r12, \label\())
+ LOAD_HANDLER(r10, \label\())
.if \hsrr
- mtspr SPRN_HSRR0,r12
- mfspr r12,SPRN_HSRR1 /* and HSRR1 */
- mtspr SPRN_HSRR1,r10
+ mtspr SPRN_HSRR0,r10
HRFI_TO_KERNEL
.else
- mtspr SPRN_SRR0,r12
- mfspr r12,SPRN_SRR1 /* and SRR1 */
- mtspr SPRN_SRR1,r10
+ mtspr SPRN_SRR0,r10
RFI_TO_KERNEL
.endif
b . /* prevent speculative execution */
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 03/13] powerpc/64s/exception: mtmsrd L=1 cleanup
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 01/13] powerpc/64s/exception: clean up system call entry Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 02/13] powerpc/64s/exception: avoid SPR RAW scoreboard stall in real mode entry Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 04/13] powerpc/64s/exception: windup use r9 consistently to restore SPRs Nicholas Piggin
` (9 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
All supported 64s CPUs support mtmsrd L=1 instruction, so a cleanup
can be made in sreset and mce handlers.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index c3a9cb8cdfd3..0804a86f6f28 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -882,11 +882,8 @@ EXC_COMMON_BEGIN(system_reset_common)
addi r3,r1,STACK_FRAME_OVERHEAD
bl system_reset_exception
- /* This (and MCE) can be simplified with mtmsrd L=1 */
/* Clear MSR_RI before setting SRR0 and SRR1. */
- li r0,MSR_RI
- mfmsr r9
- andc r9,r9,r0
+ li r9,0
mtmsrd r9,1
/*
@@ -1081,9 +1078,7 @@ EXC_COMMON_BEGIN(machine_check_common)
#define MACHINE_CHECK_HANDLER_WINDUP \
/* Clear MSR_RI before setting SRR0 and SRR1. */\
- li r0,MSR_RI; \
- mfmsr r9; /* get MSR value */ \
- andc r9,r9,r0; \
+ li r9,0; \
mtmsrd r9,1; /* Clear MSR_RI */ \
/* Move original SRR0 and SRR1 into the respective regs */ \
ld r9,_MSR(r1); \
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 04/13] powerpc/64s/exception: windup use r9 consistently to restore SPRs
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (2 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 03/13] powerpc/64s/exception: mtmsrd L=1 cleanup Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 05/13] powerpc/64s/exception: move machine check windup in_mce handling Nicholas Piggin
` (8 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Trivial code change, r3->r9.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 0804a86f6f28..b1dfd0af0120 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -909,8 +909,8 @@ EXC_COMMON_BEGIN(system_reset_common)
/* Move original SRR0 and SRR1 into the respective regs */
ld r9,_MSR(r1)
mtspr SPRN_SRR1,r9
- ld r3,_NIP(r1)
- mtspr SPRN_SRR0,r3
+ ld r9,_NIP(r1)
+ mtspr SPRN_SRR0,r9
ld r9,_CTR(r1)
mtctr r9
ld r9,_XER(r1)
@@ -1083,8 +1083,8 @@ EXC_COMMON_BEGIN(machine_check_common)
/* Move original SRR0 and SRR1 into the respective regs */ \
ld r9,_MSR(r1); \
mtspr SPRN_SRR1,r9; \
- ld r3,_NIP(r1); \
- mtspr SPRN_SRR0,r3; \
+ ld r9,_NIP(r1); \
+ mtspr SPRN_SRR0,r9; \
ld r9,_CTR(r1); \
mtctr r9; \
ld r9,_XER(r1); \
@@ -1786,8 +1786,8 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
/* Move original HSRR0 and HSRR1 into the respective regs */
ld r9,_MSR(r1)
mtspr SPRN_HSRR1,r9
- ld r3,_NIP(r1)
- mtspr SPRN_HSRR0,r3
+ ld r9,_NIP(r1)
+ mtspr SPRN_HSRR0,r9
ld r9,_CTR(r1)
mtctr r9
ld r9,_XER(r1)
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 05/13] powerpc/64s/exception: move machine check windup in_mce handling
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (3 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 04/13] powerpc/64s/exception: windup use r9 consistently to restore SPRs Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 06/13] powerpc/64s/exception: simplify hmi windup code Nicholas Piggin
` (7 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Move in_mce decrement earlier before registers are restored (but
still after RI=0). This helps with later consolidation.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index b1dfd0af0120..c1d9ec5fe849 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1080,6 +1080,10 @@ EXC_COMMON_BEGIN(machine_check_common)
/* Clear MSR_RI before setting SRR0 and SRR1. */\
li r9,0; \
mtmsrd r9,1; /* Clear MSR_RI */ \
+ /* Decrement paca->in_mce now RI is clear. */ \
+ lhz r12,PACA_IN_MCE(r13); \
+ subi r12,r12,1; \
+ sth r12,PACA_IN_MCE(r13); \
/* Move original SRR0 and SRR1 into the respective regs */ \
ld r9,_MSR(r1); \
mtspr SPRN_SRR1,r9; \
@@ -1096,10 +1100,6 @@ EXC_COMMON_BEGIN(machine_check_common)
REST_GPR(10, r1); \
ld r11,_CCR(r1); \
mtcr r11; \
- /* Decrement paca->in_mce. */ \
- lhz r12,PACA_IN_MCE(r13); \
- subi r12,r12,1; \
- sth r12,PACA_IN_MCE(r13); \
REST_GPR(11, r1); \
REST_2GPRS(12, r1); \
/* restore original r1. */ \
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 06/13] powerpc/64s/exception: simplify hmi windup code
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (4 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 05/13] powerpc/64s/exception: move machine check windup in_mce handling Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 07/13] powerpc/64s/exception: shuffle windup code around Nicholas Piggin
` (6 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Duplicate the hmi windup code for both cases, rather than to put a
special case branch in the middle of it. Remove unused label. This
helps with later code consolidation.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index c1d9ec5fe849..17bc0166e0e6 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1781,6 +1781,7 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
addi r3,r1,STACK_FRAME_OVERHEAD
BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */
cmpdi cr0,r3,0
+ bne 1f
/* Windup the stack. */
/* Move original HSRR0 and HSRR1 into the respective regs */
@@ -1799,13 +1800,28 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
REST_GPR(10, r1)
ld r11,_CCR(r1)
REST_2GPRS(12, r1)
- bne 1f
mtcr r11
REST_GPR(11, r1)
ld r1,GPR1(r1)
HRFI_TO_USER_OR_KERNEL
-1: mtcr r11
+1:
+ ld r9,_MSR(r1)
+ mtspr SPRN_HSRR1,r9
+ ld r9,_NIP(r1)
+ mtspr SPRN_HSRR0,r9
+ ld r9,_CTR(r1)
+ mtctr r9
+ ld r9,_XER(r1)
+ mtxer r9
+ ld r9,_LINK(r1)
+ mtlr r9
+ REST_GPR(0, r1)
+ REST_8GPRS(2, r1)
+ REST_GPR(10, r1)
+ ld r11,_CCR(r1)
+ REST_2GPRS(12, r1)
+ mtcr r11
REST_GPR(11, r1)
ld r1,GPR1(r1)
@@ -1813,8 +1829,6 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
* Go to virtual mode and pull the HMI event information from
* firmware.
*/
- .globl hmi_exception_after_realmode
-hmi_exception_after_realmode:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0 PACA_EXGEN
b tramp_real_hmi_exception
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 07/13] powerpc/64s/exception: shuffle windup code around
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (5 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 06/13] powerpc/64s/exception: simplify hmi windup code Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 08/13] powerpc/64s/exception: use common macro for windup Nicholas Piggin
` (5 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Restore all SPRs and CR up-front, these are longer latency
instructions. Move register restore around to maximise pairs of
adjacent loads (e.g., restore r0 next to r1).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 40 +++++++++++-----------------
1 file changed, 16 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 17bc0166e0e6..228fa51b9050 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -917,13 +917,11 @@ EXC_COMMON_BEGIN(system_reset_common)
mtxer r9
ld r9,_LINK(r1)
mtlr r9
- REST_GPR(0, r1)
+ ld r9,_CCR(r1)
+ mtcr r9
REST_8GPRS(2, r1)
- REST_GPR(10, r1)
- ld r11,_CCR(r1)
- mtcr r11
- REST_GPR(11, r1)
- REST_2GPRS(12, r1)
+ REST_4GPRS(10, r1)
+ REST_GPR(0, r1)
/* restore original r1. */
ld r1,GPR1(r1)
RFI_TO_USER_OR_KERNEL
@@ -1095,13 +1093,11 @@ EXC_COMMON_BEGIN(machine_check_common)
mtxer r9; \
ld r9,_LINK(r1); \
mtlr r9; \
- REST_GPR(0, r1); \
+ ld r9,_CCR(r1); \
+ mtcr r9; \
REST_8GPRS(2, r1); \
- REST_GPR(10, r1); \
- ld r11,_CCR(r1); \
- mtcr r11; \
- REST_GPR(11, r1); \
- REST_2GPRS(12, r1); \
+ REST_4GPRS(10, r1); \
+ REST_GPR(0, r1); \
/* restore original r1. */ \
ld r1,GPR1(r1)
@@ -1795,13 +1791,11 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
mtxer r9
ld r9,_LINK(r1)
mtlr r9
- REST_GPR(0, r1)
+ ld r9,_CCR(r1)
+ mtcr r9
REST_8GPRS(2, r1)
- REST_GPR(10, r1)
- ld r11,_CCR(r1)
- REST_2GPRS(12, r1)
- mtcr r11
- REST_GPR(11, r1)
+ REST_4GPRS(10, r1)
+ REST_GPR(0, r1)
ld r1,GPR1(r1)
HRFI_TO_USER_OR_KERNEL
@@ -1816,13 +1810,11 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
mtxer r9
ld r9,_LINK(r1)
mtlr r9
- REST_GPR(0, r1)
+ ld r9,_CCR(r1)
+ mtcr r9
REST_8GPRS(2, r1)
- REST_GPR(10, r1)
- ld r11,_CCR(r1)
- REST_2GPRS(12, r1)
- mtcr r11
- REST_GPR(11, r1)
+ REST_4GPRS(10, r1)
+ REST_GPR(0, r1)
ld r1,GPR1(r1)
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 08/13] powerpc/64s/exception: use common macro for windup
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (6 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 07/13] powerpc/64s/exception: shuffle windup code around Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 09/13] powerpc/64s/exception: add dar and dsisr options to exception macro Nicholas Piggin
` (4 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
No generated code change.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 112 +++++++++------------------
1 file changed, 36 insertions(+), 76 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 228fa51b9050..2b3a7d928df6 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -424,6 +424,38 @@ END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
EXCEPTION_PROLOG_COMMON_2(area); \
EXCEPTION_PROLOG_COMMON_3(trap)
+/*
+ * Restore all registers including H/SRR0/1 saved in a stack frame of a
+ * standard exception.
+ */
+.macro EXCEPTION_RESTORE_REGS hsrr
+ /* Move original SRR0 and SRR1 into the respective regs */
+ ld r9,_MSR(r1)
+ .if \hsrr
+ mtspr SPRN_HSRR1,r9
+ .else
+ mtspr SPRN_SRR1,r9
+ .endif
+ ld r9,_NIP(r1)
+ .if \hsrr
+ mtspr SPRN_HSRR0,r9
+ .else
+ mtspr SPRN_SRR0,r9
+ .endif
+ ld r9,_CTR(r1)
+ mtctr r9
+ ld r9,_XER(r1)
+ mtxer r9
+ ld r9,_LINK(r1)
+ mtlr r9
+ ld r9,_CCR(r1)
+ mtcr r9
+ REST_8GPRS(2, r1)
+ REST_4GPRS(10, r1)
+ REST_GPR(0, r1)
+ /* restore original r1. */
+ ld r1,GPR1(r1)
+.endm
#define RUNLATCH_ON \
BEGIN_FTR_SECTION \
@@ -901,29 +933,7 @@ EXC_COMMON_BEGIN(system_reset_common)
ld r10,SOFTE(r1)
stb r10,PACAIRQSOFTMASK(r13)
- /*
- * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP.
- * Should share common bits...
- */
-
- /* Move original SRR0 and SRR1 into the respective regs */
- ld r9,_MSR(r1)
- mtspr SPRN_SRR1,r9
- ld r9,_NIP(r1)
- mtspr SPRN_SRR0,r9
- ld r9,_CTR(r1)
- mtctr r9
- ld r9,_XER(r1)
- mtxer r9
- ld r9,_LINK(r1)
- mtlr r9
- ld r9,_CCR(r1)
- mtcr r9
- REST_8GPRS(2, r1)
- REST_4GPRS(10, r1)
- REST_GPR(0, r1)
- /* restore original r1. */
- ld r1,GPR1(r1)
+ EXCEPTION_RESTORE_REGS EXC_STD
RFI_TO_USER_OR_KERNEL
#ifdef CONFIG_PPC_PSERIES
@@ -1082,24 +1092,7 @@ EXC_COMMON_BEGIN(machine_check_common)
lhz r12,PACA_IN_MCE(r13); \
subi r12,r12,1; \
sth r12,PACA_IN_MCE(r13); \
- /* Move original SRR0 and SRR1 into the respective regs */ \
- ld r9,_MSR(r1); \
- mtspr SPRN_SRR1,r9; \
- ld r9,_NIP(r1); \
- mtspr SPRN_SRR0,r9; \
- ld r9,_CTR(r1); \
- mtctr r9; \
- ld r9,_XER(r1); \
- mtxer r9; \
- ld r9,_LINK(r1); \
- mtlr r9; \
- ld r9,_CCR(r1); \
- mtcr r9; \
- REST_8GPRS(2, r1); \
- REST_4GPRS(10, r1); \
- REST_GPR(0, r1); \
- /* restore original r1. */ \
- ld r1,GPR1(r1)
+ EXCEPTION_RESTORE_REGS EXC_STD
#ifdef CONFIG_PPC_P7_NAP
/*
@@ -1779,48 +1772,15 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
cmpdi cr0,r3,0
bne 1f
- /* Windup the stack. */
- /* Move original HSRR0 and HSRR1 into the respective regs */
- ld r9,_MSR(r1)
- mtspr SPRN_HSRR1,r9
- ld r9,_NIP(r1)
- mtspr SPRN_HSRR0,r9
- ld r9,_CTR(r1)
- mtctr r9
- ld r9,_XER(r1)
- mtxer r9
- ld r9,_LINK(r1)
- mtlr r9
- ld r9,_CCR(r1)
- mtcr r9
- REST_8GPRS(2, r1)
- REST_4GPRS(10, r1)
- REST_GPR(0, r1)
- ld r1,GPR1(r1)
+ EXCEPTION_RESTORE_REGS EXC_HV
HRFI_TO_USER_OR_KERNEL
1:
- ld r9,_MSR(r1)
- mtspr SPRN_HSRR1,r9
- ld r9,_NIP(r1)
- mtspr SPRN_HSRR0,r9
- ld r9,_CTR(r1)
- mtctr r9
- ld r9,_XER(r1)
- mtxer r9
- ld r9,_LINK(r1)
- mtlr r9
- ld r9,_CCR(r1)
- mtcr r9
- REST_8GPRS(2, r1)
- REST_4GPRS(10, r1)
- REST_GPR(0, r1)
- ld r1,GPR1(r1)
-
/*
* Go to virtual mode and pull the HMI event information from
* firmware.
*/
+ EXCEPTION_RESTORE_REGS EXC_HV
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0 PACA_EXGEN
b tramp_real_hmi_exception
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 09/13] powerpc/64s/exception: add dar and dsisr options to exception macro
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (7 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 08/13] powerpc/64s/exception: use common macro for windup Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 10/13] powerpc/64s/exception: machine check use standard macros to save dar/dsisr Nicholas Piggin
` (3 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Some exception entry requires DAR and/or DSISR to be saved into the
paca exception save area. Add options to the standard exception
macros for these.
Generated code changes slightly due to code structure.
- 554: a6 02 72 7d mfdsisr r11
- 558: a8 00 4d f9 std r10,168(r13)
- 55c: b0 00 6d 91 stw r11,176(r13)
+ 554: a8 00 4d f9 std r10,168(r13)
+ 558: a6 02 52 7d mfdsisr r10
+ 55c: b0 00 4d 91 stw r10,176(r13)
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 101 ++++++++++++---------------
1 file changed, 45 insertions(+), 56 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 2b3a7d928df6..4427b6820f51 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -136,7 +136,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
.endm
-.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
+.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, dar, dsisr, bitmask
OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
INTERRUPT_TO_KERNEL
@@ -172,8 +172,22 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
std r11,\area\()+EX_R11(r13)
std r12,\area\()+EX_R12(r13)
+
+ /*
+ * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
+ * because a d-side MCE will clobber those registers so is
+ * not recoverable if they are live.
+ */
GET_SCRATCH0(r10)
std r10,\area\()+EX_R13(r13)
+ .if \dar
+ mfspr r10,SPRN_DAR
+ std r10,\area\()+EX_DAR(r13)
+ .endif
+ .if \dsisr
+ mfspr r10,SPRN_DSISR
+ stw r10,\area\()+EX_DSISR(r13)
+ .endif
.endm
.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
@@ -535,7 +549,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
EXC_REAL_BEGIN(name, start, size); \
SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 area ; \
- EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0 ; \
+ EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
EXC_REAL_END(name, start, size)
@@ -546,7 +560,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
EXC_VIRT_BEGIN(name, start, size); \
SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 area ; \
- EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0; \
+ EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0, 0, 0; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
EXC_VIRT_END(name, start, size)
@@ -557,7 +571,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
EXC_REAL_BEGIN(name, start, size); \
SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, bitmask ; \
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
EXC_REAL_END(name, start, size)
@@ -565,7 +579,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
EXC_VIRT_BEGIN(name, start, size); \
SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
EXC_VIRT_END(name, start, size)
@@ -573,7 +587,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
EXC_REAL_BEGIN(name, start, size); \
SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN; \
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0 ; \
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \
EXC_REAL_END(name, start, size)
@@ -581,7 +595,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
EXC_VIRT_BEGIN(name, start, size); \
SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN; \
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \
EXC_VIRT_END(name, start, size)
@@ -594,7 +608,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_REAL_OOL(name, vec) \
TRAMP_REAL_BEGIN(tramp_real_##name); \
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
#define EXC_REAL_OOL(name, start, size) \
@@ -606,7 +620,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \
TRAMP_REAL_BEGIN(tramp_real_##name); \
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
#define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \
@@ -625,7 +639,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_REAL_OOL_HV(name, vec) \
TRAMP_REAL_BEGIN(tramp_real_##name); \
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1
#define EXC_REAL_OOL_HV(name, start, size) \
@@ -637,7 +651,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \
TRAMP_REAL_BEGIN(tramp_real_##name); \
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1
#define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \
@@ -653,7 +667,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_VIRT_OOL(name, realvec) \
TRAMP_VIRT_BEGIN(tramp_virt_##name); \
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD
#define EXC_VIRT_OOL(name, start, size, realvec) \
@@ -665,7 +679,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \
TRAMP_VIRT_BEGIN(tramp_virt_##name); \
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
#define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \
@@ -677,7 +691,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_VIRT_OOL_HV(name, realvec) \
TRAMP_VIRT_BEGIN(tramp_virt_##name); \
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV
#define EXC_VIRT_OOL_HV(name, start, size, realvec) \
@@ -689,7 +703,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \
TRAMP_VIRT_BEGIN(tramp_virt_##name); \
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, bitmask ; \
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV
#define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \
@@ -944,7 +958,7 @@ TRAMP_REAL_BEGIN(system_reset_fwnmi)
SET_SCRATCH0(r13) /* save r13 */
/* See comment at system_reset exception, don't turn on RI */
EXCEPTION_PROLOG_0 PACA_EXNMI
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0, 0, 0
EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0
#endif /* CONFIG_PPC_PSERIES */
@@ -965,7 +979,7 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
EXC_REAL_END(machine_check, 0x200, 0x100)
EXC_VIRT_NONE(0x4200, 0x100)
TRAMP_REAL_BEGIN(machine_check_common_early)
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0, 0, 0
/*
* Register contents:
* R13 = PACA
@@ -1050,7 +1064,7 @@ BEGIN_FTR_SECTION
b machine_check_common_early
END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
machine_check_pSeries_0:
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0, 0, 0
/*
* MSR_RI is not enabled, because PACA_EXMC is being used, so a
* nested machine check corrupts it. machine_check_common enables
@@ -1267,26 +1281,13 @@ EXC_REAL_BEGIN(data_access, 0x300, 0x80)
EXC_REAL_END(data_access, 0x300, 0x80)
TRAMP_REAL_BEGIN(tramp_real_data_access)
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0
- /*
- * DAR/DSISR must be read before setting MSR[RI], because
- * a d-side MCE will clobber those registers so is not
- * recoverable if they are live.
- */
- mfspr r10,SPRN_DAR
- mfspr r11,SPRN_DSISR
- std r10,PACA_EXGEN+EX_DAR(r13)
- stw r11,PACA_EXGEN+EX_DSISR(r13)
-EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 1, 1, 0
+ EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0
- mfspr r10,SPRN_DAR
- mfspr r11,SPRN_DSISR
- std r10,PACA_EXGEN+EX_DAR(r13)
- stw r11,PACA_EXGEN+EX_DSISR(r13)
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 1, 1, 0
EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD
EXC_VIRT_END(data_access, 0x4300, 0x80)
@@ -1321,17 +1322,13 @@ EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
EXC_REAL_END(data_access_slb, 0x380, 0x80)
TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0
- mfspr r10,SPRN_DAR
- std r10,PACA_EXSLB+EX_DAR(r13)
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 1, 0, 0
EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXSLB
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0
- mfspr r10,SPRN_DAR
- std r10,PACA_EXSLB+EX_DAR(r13)
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 1, 0, 0
EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD
EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
@@ -1416,10 +1413,10 @@ EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
BEGIN_FTR_SECTION
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED
EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1
FTR_SECTION_ELSE
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED
EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
@@ -1428,10 +1425,10 @@ EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
BEGIN_FTR_SECTION
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED
EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV
FTR_SECTION_ELSE
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED
EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
@@ -1444,22 +1441,14 @@ EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
EXC_REAL_BEGIN(alignment, 0x600, 0x100)
SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0
- mfspr r10,SPRN_DAR
- mfspr r11,SPRN_DSISR
- std r10,PACA_EXGEN+EX_DAR(r13)
- stw r11,PACA_EXGEN+EX_DSISR(r13)
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 1, 1, 0
EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1
EXC_REAL_END(alignment, 0x600, 0x100)
EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0
- mfspr r10,SPRN_DAR
- mfspr r11,SPRN_DSISR
- std r10,PACA_EXGEN+EX_DAR(r13)
- stw r11,PACA_EXGEN+EX_DSISR(r13)
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 1, 1, 0
EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD
EXC_VIRT_END(alignment, 0x4600, 0x100)
@@ -1757,7 +1746,7 @@ __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
EXC_VIRT_NONE(0x4e60, 0x20)
TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
TRAMP_REAL_BEGIN(hmi_exception_early)
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0, 0, 0
mr r10,r1 /* Save r1 */
ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
@@ -1942,7 +1931,7 @@ EXC_VIRT_NONE(0x5400, 0x100)
EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
mtspr SPRN_SPRG_HSCRATCH0,r13
EXCEPTION_PROLOG_0 PACA_EXGEN
- EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0
+ EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0, 0, 0
#ifdef CONFIG_PPC_DENORMALISATION
mfspr r10,SPRN_HSRR1
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 10/13] powerpc/64s/exception: machine check use standard macros to save dar/dsisr
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (8 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 09/13] powerpc/64s/exception: add dar and dsisr options to exception macro Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 11/13] powerpc/64s/exception: denorm handler use standard scratch save macro Nicholas Piggin
` (2 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 4427b6820f51..f193a67f02ba 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1064,7 +1064,7 @@ BEGIN_FTR_SECTION
b machine_check_common_early
END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
machine_check_pSeries_0:
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0, 0, 0
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0
/*
* MSR_RI is not enabled, because PACA_EXMC is being used, so a
* nested machine check corrupts it. machine_check_common enables
@@ -1079,10 +1079,6 @@ EXC_COMMON_BEGIN(machine_check_common)
* Machine check is different because we use a different
* save area: PACA_EXMC instead of PACA_EXGEN.
*/
- mfspr r10,SPRN_DAR
- std r10,PACA_EXMC+EX_DAR(r13)
- mfspr r10,SPRN_DSISR
- stw r10,PACA_EXMC+EX_DSISR(r13)
EXCEPTION_COMMON(PACA_EXMC, 0x200)
FINISH_NAP
RECONCILE_IRQ_STATE(r10, r11)
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 11/13] powerpc/64s/exception: denorm handler use standard scratch save macro
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (9 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 10/13] powerpc/64s/exception: machine check use standard macros to save dar/dsisr Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 12/13] powerpc/64s/exception: move SET_SCRATCH0 into EXCEPTION_PROLOG_0 Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 13/13] powerpc/tm: update comment about interrupt re-entrancy Nicholas Piggin
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Although the 0x1500 interrupt only applies to bare metal, it is better
to just use the standard macro for scratch save.
Runtime code path remains unchanged (due to instruction patching).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index f193a67f02ba..bbe29cd80440 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1925,7 +1925,7 @@ EXC_REAL_NONE(0x1400, 0x100)
EXC_VIRT_NONE(0x5400, 0x100)
EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
- mtspr SPRN_SPRG_HSCRATCH0,r13
+ SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0, 0, 0
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 12/13] powerpc/64s/exception: move SET_SCRATCH0 into EXCEPTION_PROLOG_0
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (10 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 11/13] powerpc/64s/exception: denorm handler use standard scratch save macro Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
2019-06-28 5:33 ` [PATCH v3 13/13] powerpc/tm: update comment about interrupt re-entrancy Nicholas Piggin
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
No generated code change.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 25 +------------------------
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index bbe29cd80440..0857c696480c 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -128,6 +128,7 @@ BEGIN_FTR_SECTION_NESTED(943) \
END_FTR_SECTION_NESTED(ftr,ftr,943)
.macro EXCEPTION_PROLOG_0 area
+ SET_SCRATCH0(r13) /* save r13 */
GET_PACA(r13)
std r9,\area\()+EX_R9(r13) /* save r9 */
OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
@@ -547,7 +548,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __EXC_REAL(name, start, size, area) \
EXC_REAL_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 area ; \
EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
@@ -558,7 +558,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __EXC_VIRT(name, start, size, realvec, area) \
EXC_VIRT_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 area ; \
EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0, 0, 0; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
@@ -569,7 +568,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define EXC_REAL_MASKABLE(name, start, size, bitmask) \
EXC_REAL_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
@@ -577,7 +575,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \
EXC_VIRT_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, 0, 0, bitmask ; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
@@ -585,7 +582,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define EXC_REAL_HV(name, start, size) \
EXC_REAL_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN; \
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \
@@ -593,7 +589,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define EXC_VIRT_HV(name, start, size, realvec) \
EXC_VIRT_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0 PACA_EXGEN; \
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, 0 ; \
EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \
@@ -601,7 +596,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __EXC_REAL_OOL(name, start, size) \
EXC_REAL_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); \
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
b tramp_real_##name ; \
EXC_REAL_END(name, start, size)
@@ -629,7 +623,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __EXC_REAL_OOL_HV_DIRECT(name, start, size, handler) \
EXC_REAL_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); \
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
b handler; \
EXC_REAL_END(name, start, size)
@@ -660,7 +653,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define __EXC_VIRT_OOL(name, start, size) \
EXC_VIRT_BEGIN(name, start, size); \
- SET_SCRATCH0(r13); \
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
b tramp_virt_##name; \
EXC_VIRT_END(name, start, size)
@@ -837,7 +829,6 @@ EXC_VIRT_NONE(0x4000, 0x100)
EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
- SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0 PACA_EXNMI
/* This is EXCEPTION_PROLOG_1 with the idle feature section added */
@@ -955,7 +946,6 @@ EXC_COMMON_BEGIN(system_reset_common)
* Vectors for the FWNMI option. Share common code.
*/
TRAMP_REAL_BEGIN(system_reset_fwnmi)
- SET_SCRATCH0(r13) /* save r13 */
/* See comment at system_reset exception, don't turn on RI */
EXCEPTION_PROLOG_0 PACA_EXNMI
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0, 0, 0
@@ -969,7 +959,6 @@ EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
* some code path might still want to branch into the original
* vector
*/
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXMC
BEGIN_FTR_SECTION
b machine_check_common_early
@@ -1058,7 +1047,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
TRAMP_REAL_BEGIN(machine_check_pSeries)
.globl machine_check_fwnmi
machine_check_fwnmi:
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXMC
BEGIN_FTR_SECTION
b machine_check_common_early
@@ -1246,7 +1234,6 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
9:
/* Deliver the machine check to host kernel in V mode. */
MACHINE_CHECK_HANDLER_WINDUP
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXMC
b machine_check_pSeries_0
@@ -1271,7 +1258,6 @@ EXC_COMMON_BEGIN(mce_return)
b .
EXC_REAL_BEGIN(data_access, 0x300, 0x80)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
b tramp_real_data_access
EXC_REAL_END(data_access, 0x300, 0x80)
@@ -1281,7 +1267,6 @@ TRAMP_REAL_BEGIN(tramp_real_data_access)
EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 1, 1, 0
EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD
@@ -1312,7 +1297,6 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXSLB
b tramp_real_data_access_slb
EXC_REAL_END(data_access_slb, 0x380, 0x80)
@@ -1322,7 +1306,6 @@ TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXSLB
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 1, 0, 0
EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD
@@ -1406,7 +1389,6 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
BEGIN_FTR_SECTION
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED
@@ -1418,7 +1400,6 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
BEGIN_FTR_SECTION
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED
@@ -1435,14 +1416,12 @@ EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
EXC_REAL_BEGIN(alignment, 0x600, 0x100)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 1, 1, 0
EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1
EXC_REAL_END(alignment, 0x600, 0x100)
EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
- SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 1, 1, 0
EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD
@@ -1766,7 +1745,6 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
* firmware.
*/
EXCEPTION_RESTORE_REGS EXC_HV
- SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0 PACA_EXGEN
b tramp_real_hmi_exception
@@ -1925,7 +1903,6 @@ EXC_REAL_NONE(0x1400, 0x100)
EXC_VIRT_NONE(0x5400, 0x100)
EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
- SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0, 0, 0
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 13/13] powerpc/tm: update comment about interrupt re-entrancy
2019-06-28 5:33 [PATCH v3 00/13] next batch of interrupt handler improvements Nicholas Piggin
` (11 preceding siblings ...)
2019-06-28 5:33 ` [PATCH v3 12/13] powerpc/64s/exception: move SET_SCRATCH0 into EXCEPTION_PROLOG_0 Nicholas Piggin
@ 2019-06-28 5:33 ` Nicholas Piggin
12 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2019-06-28 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Since the system reset interrupt began to use its own stack, and
machine check interrupts have done so for some time, r1 can be
changed without clearing MSR[RI], provided no other interrupts
(including SLB misses) are taken.
MSR[RI] does have to be cleared when using SCRATCH0, however.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/tm.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 9fabdce255cd..6ba0fdd1e7f8 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -148,7 +148,7 @@ _GLOBAL(tm_reclaim)
/* Stash the stack pointer away for use after reclaim */
std r1, PACAR1(r13)
- /* Clear MSR RI since we are about to change r1, EE is already off. */
+ /* Clear MSR RI since we are about to use SCRATCH0, EE is already off */
li r5, 0
mtmsrd r5, 1
@@ -474,7 +474,7 @@ restore_gprs:
REST_GPR(7, r7)
- /* Clear MSR RI since we are about to change r1. EE is already off */
+ /* Clear MSR RI since we are about to use SCRATCH0. EE is already off */
li r5, 0
mtmsrd r5, 1
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread