* [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
@ 2020-03-26 8:38 Ram Pai
2020-03-26 8:45 ` Cédric Le Goater
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Ram Pai @ 2020-03-26 8:38 UTC (permalink / raw)
To: kvm-ppc, linuxppc-dev
Cc: aik, andmike, linuxram, groug, clg, sukadev, bauerman, david
XIVE interrupt controller use an Event Queue (EQ) to enqueue event
notifications when an exception occurs. The EQ is a single memory page
provided by the O/S defining a circular buffer, one per server and
priority couple.
On baremetal, the EQ page is configured with an OPAL call. On pseries,
an extra hop is necessary and the guest OS uses the hcall
H_INT_SET_QUEUE_CONFIG to configure the XIVE interrupt controller.
The XIVE controller being Hypervisor privileged, it will not be allowed
to enqueue event notifications for a Secure VM unless the EQ pages are
shared by the Secure VM.
Hypervisor/Ultravisor still requires support for the TIMA and ESB page
fault handlers. Until this is complete, QEMU can use the emulated XIVE
device for Secure VMs, option "kernel_irqchip=off" on the QEMU pseries
machine.
Cc: kvm-ppc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Thiago Jung Bauermann <bauerman@linux.ibm.com>
Cc: Michael Anderson <andmike@linux.ibm.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: Greg Kurz <groug@kaod.org>
Cc: Cedric Le Goater <clg@fr.ibm.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
v2: better description of the patch from Cedric.
---
arch/powerpc/sysdev/xive/spapr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 55dc61c..608b52f 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -26,6 +26,8 @@
#include <asm/xive.h>
#include <asm/xive-regs.h>
#include <asm/hvcall.h>
+#include <asm/svm.h>
+#include <asm/ultravisor.h>
#include "xive-internal.h"
@@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
rc = -EIO;
} else {
q->qpage = qpage;
+ if (is_secure_guest())
+ uv_share_page(PHYS_PFN(qpage_phys),
+ 1 << xive_alloc_order(order));
}
fail:
return rc;
@@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
hw_cpu, prio);
alloc_order = xive_alloc_order(xive_queue_shift);
+ if (is_secure_guest())
+ uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
free_pages((unsigned long)q->qpage, alloc_order);
q->qpage = NULL;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-03-26 8:38 [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor Ram Pai
@ 2020-03-26 8:45 ` Cédric Le Goater
2020-03-26 10:04 ` Greg Kurz
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2020-03-26 8:45 UTC (permalink / raw)
To: Ram Pai, kvm-ppc, linuxppc-dev
Cc: aik, andmike, groug, sukadev, bauerman, david
On 3/26/20 9:38 AM, Ram Pai wrote:
> XIVE interrupt controller use an Event Queue (EQ) to enqueue event
The XIVE interrupt controller uses ... (my bad)
> notifications when an exception occurs. The EQ is a single memory page
> provided by the O/S defining a circular buffer, one per server and
> priority couple.
>
> On baremetal, the EQ page is configured with an OPAL call. On pseries,
> an extra hop is necessary and the guest OS uses the hcall
> H_INT_SET_QUEUE_CONFIG to configure the XIVE interrupt controller.
>
> The XIVE controller being Hypervisor privileged, it will not be allowed
> to enqueue event notifications for a Secure VM unless the EQ pages are
> shared by the Secure VM.
>
> Hypervisor/Ultravisor still requires support for the TIMA and ESB page
> fault handlers. Until this is complete, QEMU can use the emulated XIVE
> device for Secure VMs, option "kernel_irqchip=off" on the QEMU pseries
> machine.
>
> Cc: kvm-ppc@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Thiago Jung Bauermann <bauerman@linux.ibm.com>
> Cc: Michael Anderson <andmike@linux.ibm.com>
> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
> Cc: Paul Mackerras <paulus@ozlabs.org>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: Cedric Le Goater <clg@fr.ibm.com>
clg@fr.ibm.com is insecure. Please use clg@kaod.org.
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Reviewed-by: Cedric Le Goater <clg@kaod.org>
Thanks,
C.
>
> v2: better description of the patch from Cedric.
> ---
> arch/powerpc/sysdev/xive/spapr.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
> index 55dc61c..608b52f 100644
> --- a/arch/powerpc/sysdev/xive/spapr.c
> +++ b/arch/powerpc/sysdev/xive/spapr.c
> @@ -26,6 +26,8 @@
> #include <asm/xive.h>
> #include <asm/xive-regs.h>
> #include <asm/hvcall.h>
> +#include <asm/svm.h>
> +#include <asm/ultravisor.h>
>
> #include "xive-internal.h"
>
> @@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
> rc = -EIO;
> } else {
> q->qpage = qpage;
> + if (is_secure_guest())
> + uv_share_page(PHYS_PFN(qpage_phys),
> + 1 << xive_alloc_order(order));
> }
> fail:
> return rc;
> @@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
> hw_cpu, prio);
>
> alloc_order = xive_alloc_order(xive_queue_shift);
> + if (is_secure_guest())
> + uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
> free_pages((unsigned long)q->qpage, alloc_order);
> q->qpage = NULL;
> }
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-03-26 8:38 [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor Ram Pai
2020-03-26 8:45 ` Cédric Le Goater
@ 2020-03-26 10:04 ` Greg Kurz
2020-03-31 23:53 ` Thiago Jung Bauermann
2020-04-26 2:05 ` [PATCH v3] " Ram Pai
3 siblings, 0 replies; 10+ messages in thread
From: Greg Kurz @ 2020-03-26 10:04 UTC (permalink / raw)
To: Ram Pai
Cc: aik, andmike, kvm-ppc, clg, sukadev, linuxppc-dev, bauerman, david
On Thu, 26 Mar 2020 01:38:47 -0700
Ram Pai <linuxram@us.ibm.com> wrote:
> XIVE interrupt controller use an Event Queue (EQ) to enqueue event
> notifications when an exception occurs. The EQ is a single memory page
> provided by the O/S defining a circular buffer, one per server and
> priority couple.
>
> On baremetal, the EQ page is configured with an OPAL call. On pseries,
> an extra hop is necessary and the guest OS uses the hcall
> H_INT_SET_QUEUE_CONFIG to configure the XIVE interrupt controller.
>
> The XIVE controller being Hypervisor privileged, it will not be allowed
> to enqueue event notifications for a Secure VM unless the EQ pages are
> shared by the Secure VM.
>
> Hypervisor/Ultravisor still requires support for the TIMA and ESB page
> fault handlers. Until this is complete, QEMU can use the emulated XIVE
> device for Secure VMs, option "kernel_irqchip=off" on the QEMU pseries
> machine.
>
> Cc: kvm-ppc@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Thiago Jung Bauermann <bauerman@linux.ibm.com>
> Cc: Michael Anderson <andmike@linux.ibm.com>
> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
> Cc: Paul Mackerras <paulus@ozlabs.org>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: Cedric Le Goater <clg@fr.ibm.com>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Ram Pai <linuxram@us.ibm.com>
>
> v2: better description of the patch from Cedric.
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> arch/powerpc/sysdev/xive/spapr.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
> index 55dc61c..608b52f 100644
> --- a/arch/powerpc/sysdev/xive/spapr.c
> +++ b/arch/powerpc/sysdev/xive/spapr.c
> @@ -26,6 +26,8 @@
> #include <asm/xive.h>
> #include <asm/xive-regs.h>
> #include <asm/hvcall.h>
> +#include <asm/svm.h>
> +#include <asm/ultravisor.h>
>
> #include "xive-internal.h"
>
> @@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
> rc = -EIO;
> } else {
> q->qpage = qpage;
> + if (is_secure_guest())
> + uv_share_page(PHYS_PFN(qpage_phys),
> + 1 << xive_alloc_order(order));
> }
> fail:
> return rc;
> @@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
> hw_cpu, prio);
>
> alloc_order = xive_alloc_order(xive_queue_shift);
> + if (is_secure_guest())
> + uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
> free_pages((unsigned long)q->qpage, alloc_order);
> q->qpage = NULL;
> }
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-03-26 8:38 [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor Ram Pai
2020-03-26 8:45 ` Cédric Le Goater
2020-03-26 10:04 ` Greg Kurz
@ 2020-03-31 23:53 ` Thiago Jung Bauermann
2020-04-01 5:32 ` Ram Pai
2020-04-26 2:05 ` [PATCH v3] " Ram Pai
3 siblings, 1 reply; 10+ messages in thread
From: Thiago Jung Bauermann @ 2020-03-31 23:53 UTC (permalink / raw)
To: Ram Pai; +Cc: aik, andmike, groug, kvm-ppc, clg, sukadev, linuxppc-dev, david
Hi Ram,
Ram Pai <linuxram@us.ibm.com> writes:
> diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
> index 55dc61c..608b52f 100644
> --- a/arch/powerpc/sysdev/xive/spapr.c
> +++ b/arch/powerpc/sysdev/xive/spapr.c
> @@ -26,6 +26,8 @@
> #include <asm/xive.h>
> #include <asm/xive-regs.h>
> #include <asm/hvcall.h>
> +#include <asm/svm.h>
> +#include <asm/ultravisor.h>
>
> #include "xive-internal.h"
>
> @@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
> rc = -EIO;
> } else {
> q->qpage = qpage;
> + if (is_secure_guest())
> + uv_share_page(PHYS_PFN(qpage_phys),
> + 1 << xive_alloc_order(order));
If I understand this correctly, you're passing the number of bytes of
the queue to uv_share_page(), but that ultracall expects the number of
pages to be shared.
> }
> fail:
> return rc;
> @@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
> hw_cpu, prio);
>
> alloc_order = xive_alloc_order(xive_queue_shift);
> + if (is_secure_guest())
> + uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
> free_pages((unsigned long)q->qpage, alloc_order);
> q->qpage = NULL;
> }
Same problem here.
--
Thiago Jung Bauermann
IBM Linux Technology Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-03-31 23:53 ` Thiago Jung Bauermann
@ 2020-04-01 5:32 ` Ram Pai
2020-04-03 18:24 ` Thiago Jung Bauermann
0 siblings, 1 reply; 10+ messages in thread
From: Ram Pai @ 2020-04-01 5:32 UTC (permalink / raw)
To: Thiago Jung Bauermann
Cc: aik, andmike, groug, kvm-ppc, clg, sukadev, linuxppc-dev, david
On Tue, Mar 31, 2020 at 08:53:07PM -0300, Thiago Jung Bauermann wrote:
>
> Hi Ram,
>
> Ram Pai <linuxram@us.ibm.com> writes:
>
> > diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
> > index 55dc61c..608b52f 100644
> > --- a/arch/powerpc/sysdev/xive/spapr.c
> > +++ b/arch/powerpc/sysdev/xive/spapr.c
> > @@ -26,6 +26,8 @@
> > #include <asm/xive.h>
> > #include <asm/xive-regs.h>
> > #include <asm/hvcall.h>
> > +#include <asm/svm.h>
> > +#include <asm/ultravisor.h>
> >
> > #include "xive-internal.h"
> >
> > @@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
> > rc = -EIO;
> > } else {
> > q->qpage = qpage;
> > + if (is_secure_guest())
> > + uv_share_page(PHYS_PFN(qpage_phys),
> > + 1 << xive_alloc_order(order));
>
> If I understand this correctly, you're passing the number of bytes of
> the queue to uv_share_page(), but that ultracall expects the number of
> pages to be shared.
static inline u32 xive_alloc_order(u32 queue_shift)
{
return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0;
}
xive_alloc_order(order) returns the order of PAGE_SIZE pages.
Hence the value passed to uv_shared_pages is the number of pages,
and not the number of bytes.
BTW: I did verify through testing that it was indeed passing 1 page to the
uv_share_page().
RP
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-04-01 5:32 ` Ram Pai
@ 2020-04-03 18:24 ` Thiago Jung Bauermann
0 siblings, 0 replies; 10+ messages in thread
From: Thiago Jung Bauermann @ 2020-04-03 18:24 UTC (permalink / raw)
To: Ram Pai; +Cc: aik, andmike, groug, kvm-ppc, clg, sukadev, linuxppc-dev, david
Ram Pai <linuxram@us.ibm.com> writes:
> On Tue, Mar 31, 2020 at 08:53:07PM -0300, Thiago Jung Bauermann wrote:
>>
>> Hi Ram,
>>
>> Ram Pai <linuxram@us.ibm.com> writes:
>>
>> > diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
>> > index 55dc61c..608b52f 100644
>> > --- a/arch/powerpc/sysdev/xive/spapr.c
>> > +++ b/arch/powerpc/sysdev/xive/spapr.c
>> > @@ -26,6 +26,8 @@
>> > #include <asm/xive.h>
>> > #include <asm/xive-regs.h>
>> > #include <asm/hvcall.h>
>> > +#include <asm/svm.h>
>> > +#include <asm/ultravisor.h>
>> >
>> > #include "xive-internal.h"
>> >
>> > @@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
>> > rc = -EIO;
>> > } else {
>> > q->qpage = qpage;
>> > + if (is_secure_guest())
>> > + uv_share_page(PHYS_PFN(qpage_phys),
>> > + 1 << xive_alloc_order(order));
>>
>> If I understand this correctly, you're passing the number of bytes of
>> the queue to uv_share_page(), but that ultracall expects the number of
>> pages to be shared.
>
>
> static inline u32 xive_alloc_order(u32 queue_shift)
> {
> return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0;
> }
>
> xive_alloc_order(order) returns the order of PAGE_SIZE pages.
> Hence the value passed to uv_shared_pages is the number of pages,
> and not the number of bytes.
>
> BTW: I did verify through testing that it was indeed passing 1 page to the
> uv_share_page().
Ah, my mistake. I misunderstood the code. Sorry for the noise and thanks
for clarifying.
--
Thiago Jung Bauermann
IBM Linux Technology Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-03-26 8:38 [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor Ram Pai
` (2 preceding siblings ...)
2020-03-31 23:53 ` Thiago Jung Bauermann
@ 2020-04-26 2:05 ` Ram Pai
2020-04-26 7:27 ` Ram Pai
2020-06-09 5:29 ` Michael Ellerman
3 siblings, 2 replies; 10+ messages in thread
From: Ram Pai @ 2020-04-26 2:05 UTC (permalink / raw)
To: kvm-ppc, linuxppc-dev; +Cc: aik, andmike, groug, clg, sukadev, bauerman, david
From 10ea2eaf492ca3f22f67a5a63a2b7865e45299ad Mon Sep 17 00:00:00 2001
From: Ram Pai <linuxram@us.ibm.com>
Date: Mon, 24 Feb 2020 01:09:48 -0500
Subject: [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the
Hypervisor.
XIVE interrupt controller uses an Event Queue (EQ) to enqueue event
notifications when an exception occurs. The EQ is a single memory page
provided by the O/S defining a circular buffer, one per server and
priority couple.
On baremetal, the EQ page is configured with an OPAL call. On pseries,
an extra hop is necessary and the guest OS uses the hcall
H_INT_SET_QUEUE_CONFIG to configure the XIVE interrupt controller.
The XIVE controller being Hypervisor privileged, it will not be allowed
to enqueue event notifications for a Secure VM unless the EQ pages are
shared by the Secure VM.
Hypervisor/Ultravisor still requires support for the TIMA and ESB page
fault handlers. Until this is complete, QEMU can use the emulated XIVE
device for Secure VMs, option "kernel_irqchip=off" on the QEMU pseries
machine.
Cc: kvm-ppc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Thiago Jung Bauermann <bauerman@linux.ibm.com>
Cc: Michael Anderson <andmike@linux.ibm.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cedric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
v3: fix a minor semantics in description.
and added reviewed-by from Cedric and Greg.
v2: better description of the patch from Cedric.
---
arch/powerpc/sysdev/xive/spapr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 55dc61c..608b52f 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -26,6 +26,8 @@
#include <asm/xive.h>
#include <asm/xive-regs.h>
#include <asm/hvcall.h>
+#include <asm/svm.h>
+#include <asm/ultravisor.h>
#include "xive-internal.h"
@@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
rc = -EIO;
} else {
q->qpage = qpage;
+ if (is_secure_guest())
+ uv_share_page(PHYS_PFN(qpage_phys),
+ 1 << xive_alloc_order(order));
}
fail:
return rc;
@@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
hw_cpu, prio);
alloc_order = xive_alloc_order(xive_queue_shift);
+ if (is_secure_guest())
+ uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
free_pages((unsigned long)q->qpage, alloc_order);
q->qpage = NULL;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-04-26 2:05 ` [PATCH v3] " Ram Pai
@ 2020-04-26 7:27 ` Ram Pai
2020-05-27 3:48 ` Michael Ellerman
2020-06-09 5:29 ` Michael Ellerman
1 sibling, 1 reply; 10+ messages in thread
From: Ram Pai @ 2020-04-26 7:27 UTC (permalink / raw)
To: kvm-ppc, linuxppc-dev; +Cc: aik, andmike, groug, clg, sukadev, bauerman, david
XIVE interrupt controller uses an Event Queue (EQ) to enqueue event
notifications when an exception occurs. The EQ is a single memory page
provided by the O/S defining a circular buffer, one per server and
priority couple.
On baremetal, the EQ page is configured with an OPAL call. On pseries,
an extra hop is necessary and the guest OS uses the hcall
H_INT_SET_QUEUE_CONFIG to configure the XIVE interrupt controller.
The XIVE controller being Hypervisor privileged, it will not be allowed
to enqueue event notifications for a Secure VM unless the EQ pages are
shared by the Secure VM.
Hypervisor/Ultravisor still requires support for the TIMA and ESB page
fault handlers. Until this is complete, QEMU can use the emulated XIVE
device for Secure VMs, option "kernel_irqchip=off" on the QEMU pseries
machine.
Cc: kvm-ppc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Thiago Jung Bauermann <bauerman@linux.ibm.com>
Cc: Michael Anderson <andmike@linux.ibm.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cedric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
v3: fix a minor semantics in description.
and added reviewed-by from Cedric and Greg.
v2: better description of the patch from Cedric.
---
arch/powerpc/sysdev/xive/spapr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 55dc61c..608b52f 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -26,6 +26,8 @@
#include <asm/xive.h>
#include <asm/xive-regs.h>
#include <asm/hvcall.h>
+#include <asm/svm.h>
+#include <asm/ultravisor.h>
#include "xive-internal.h"
@@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
rc = -EIO;
} else {
q->qpage = qpage;
+ if (is_secure_guest())
+ uv_share_page(PHYS_PFN(qpage_phys),
+ 1 << xive_alloc_order(order));
}
fail:
return rc;
@@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
hw_cpu, prio);
alloc_order = xive_alloc_order(xive_queue_shift);
+ if (is_secure_guest())
+ uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
free_pages((unsigned long)q->qpage, alloc_order);
q->qpage = NULL;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-04-26 7:27 ` Ram Pai
@ 2020-05-27 3:48 ` Michael Ellerman
0 siblings, 0 replies; 10+ messages in thread
From: Michael Ellerman @ 2020-05-27 3:48 UTC (permalink / raw)
To: Ram Pai, kvm-ppc, linuxppc-dev
Cc: aik, andmike, groug, clg, sukadev, bauerman, david
Ram Pai <linuxram@us.ibm.com> writes:
> XIVE interrupt controller uses an Event Queue (EQ) to enqueue event
> notifications when an exception occurs. The EQ is a single memory page
> provided by the O/S defining a circular buffer, one per server and
> priority couple.
>
> On baremetal, the EQ page is configured with an OPAL call. On pseries,
> an extra hop is necessary and the guest OS uses the hcall
> H_INT_SET_QUEUE_CONFIG to configure the XIVE interrupt controller.
>
> The XIVE controller being Hypervisor privileged, it will not be allowed
> to enqueue event notifications for a Secure VM unless the EQ pages are
> shared by the Secure VM.
>
> Hypervisor/Ultravisor still requires support for the TIMA and ESB page
> fault handlers. Until this is complete, QEMU can use the emulated XIVE
> device for Secure VMs, option "kernel_irqchip=off" on the QEMU pseries
> machine.
>
> Cc: kvm-ppc@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Thiago Jung Bauermann <bauerman@linux.ibm.com>
> Cc: Michael Anderson <andmike@linux.ibm.com>
> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
> Cc: Paul Mackerras <paulus@ozlabs.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Reviewed-by: Cedric Le Goater <clg@kaod.org>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: Ram Pai <linuxram@us.ibm.com>
>
> v3: fix a minor semantics in description.
> and added reviewed-by from Cedric and Greg.
> v2: better description of the patch from Cedric.
> ---
Please put the change history after the '---' break in future please, I
had to fix this up manually.
cheers
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
2020-04-26 2:05 ` [PATCH v3] " Ram Pai
2020-04-26 7:27 ` Ram Pai
@ 2020-06-09 5:29 ` Michael Ellerman
1 sibling, 0 replies; 10+ messages in thread
From: Michael Ellerman @ 2020-06-09 5:29 UTC (permalink / raw)
To: linuxppc-dev, Ram Pai, kvm-ppc
Cc: aik, andmike, groug, clg, sukadev, bauerman, david
On Sat, 25 Apr 2020 19:05:18 -0700, Ram Pai wrote:
> >From 10ea2eaf492ca3f22f67a5a63a2b7865e45299ad Mon Sep 17 00:00:00 2001
> From: Ram Pai <linuxram@us.ibm.com>
> Date: Mon, 24 Feb 2020 01:09:48 -0500
> Subject: [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the
> Hypervisor.
>
> XIVE interrupt controller uses an Event Queue (EQ) to enqueue event
> notifications when an exception occurs. The EQ is a single memory page
> provided by the O/S defining a circular buffer, one per server and
> priority couple.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/xive: Share the event-queue page with the Hypervisor.
https://git.kernel.org/powerpc/c/094235222d41d68d35de18170058d94a96a82628
cheers
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-06-09 6:11 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-26 8:38 [PATCH v2] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor Ram Pai
2020-03-26 8:45 ` Cédric Le Goater
2020-03-26 10:04 ` Greg Kurz
2020-03-31 23:53 ` Thiago Jung Bauermann
2020-04-01 5:32 ` Ram Pai
2020-04-03 18:24 ` Thiago Jung Bauermann
2020-04-26 2:05 ` [PATCH v3] " Ram Pai
2020-04-26 7:27 ` Ram Pai
2020-05-27 3:48 ` Michael Ellerman
2020-06-09 5:29 ` Michael Ellerman
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