From: Nicholas Piggin <npiggin@gmail.com>
To: kvm-ppc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin <npiggin@gmail.com>
Subject: [PATCH v1 02/55] KVM: PPC: Book3S HV P9: Fixes for TM softpatch interrupt
Date: Mon, 26 Jul 2021 13:49:43 +1000 [thread overview]
Message-ID: <20210726035036.739609-3-npiggin@gmail.com> (raw)
In-Reply-To: <20210726035036.739609-1-npiggin@gmail.com>
The softpatch interrupt sets HSRR0 to the faulting instruction +4, so
it should subtract 4 for the faulting instruction address. Also have it
emulate and deliver HFAC interrupts correctly, which is important for
nested HV and facility demand-faulting in future.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/reg.h | 3 +-
arch/powerpc/kvm/book3s_hv.c | 35 ++++++++++++--------
arch/powerpc/kvm/book3s_hv_tm.c | 57 +++++++++++++++++++++------------
3 files changed, 61 insertions(+), 34 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index be85cf156a1f..e9d27265253b 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -415,6 +415,7 @@
#define FSCR_TAR __MASK(FSCR_TAR_LG)
#define FSCR_EBB __MASK(FSCR_EBB_LG)
#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
+#define FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
@@ -426,7 +427,7 @@
#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
#define HFSCR_FP __MASK(FSCR_FP_LG)
-#define HFSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
+#define HFSCR_INTR_CAUSE FSCR_INTR_CAUSE
#define SPRN_TAR 0x32f /* Target Address Register */
#define SPRN_LPCR 0x13E /* LPAR Control Register */
#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index ce7ff12cfc03..adac1a6431a0 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1682,6 +1682,21 @@ XXX benchmark guest exits
r = RESUME_GUEST;
}
break;
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ case BOOK3S_INTERRUPT_HV_SOFTPATCH:
+ /*
+ * This occurs for various TM-related instructions that
+ * we need to emulate on POWER9 DD2.2. We have already
+ * handled the cases where the guest was in real-suspend
+ * mode and was transitioning to transactional state.
+ */
+ r = kvmhv_p9_tm_emulation(vcpu);
+ if (r != -1)
+ break;
+ fallthrough; /* go to facility unavailable handler */
+#endif
+
/*
* This occurs if the guest (kernel or userspace), does something that
* is prohibited by HFSCR.
@@ -1700,18 +1715,6 @@ XXX benchmark guest exits
}
break;
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
- case BOOK3S_INTERRUPT_HV_SOFTPATCH:
- /*
- * This occurs for various TM-related instructions that
- * we need to emulate on POWER9 DD2.2. We have already
- * handled the cases where the guest was in real-suspend
- * mode and was transitioning to transactional state.
- */
- r = kvmhv_p9_tm_emulation(vcpu);
- break;
-#endif
-
case BOOK3S_INTERRUPT_HV_RM_HARD:
r = RESUME_PASSTHROUGH;
break;
@@ -1814,9 +1817,15 @@ static int kvmppc_handle_nested_exit(struct kvm_vcpu *vcpu)
* mode and was transitioning to transactional state.
*/
r = kvmhv_p9_tm_emulation(vcpu);
- break;
+ if (r != -1)
+ break;
+ fallthrough; /* go to facility unavailable handler */
#endif
+ case BOOK3S_INTERRUPT_H_FAC_UNAVAIL:
+ r = RESUME_HOST;
+ break;
+
case BOOK3S_INTERRUPT_HV_RM_HARD:
vcpu->arch.trap = 0;
r = RESUME_GUEST;
diff --git a/arch/powerpc/kvm/book3s_hv_tm.c b/arch/powerpc/kvm/book3s_hv_tm.c
index cc90b8b82329..e4fd4a9dee08 100644
--- a/arch/powerpc/kvm/book3s_hv_tm.c
+++ b/arch/powerpc/kvm/book3s_hv_tm.c
@@ -74,19 +74,23 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
case PPC_INST_RFEBB:
if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
/* generate an illegal instruction interrupt */
+ vcpu->arch.regs.nip -= 4;
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
return RESUME_GUEST;
}
/* check EBB facility is available */
if (!(vcpu->arch.hfscr & HFSCR_EBB)) {
- /* generate an illegal instruction interrupt */
- kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
- return RESUME_GUEST;
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
+ vcpu->arch.hfscr |= (u64)FSCR_EBB_LG << 56;
+ vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
+ return -1; /* rerun host interrupt handler */
}
if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {
/* generate a facility unavailable interrupt */
- vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
- ((u64)FSCR_EBB_LG << 56);
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
+ vcpu->arch.fscr |= (u64)FSCR_EBB_LG << 56;
kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL);
return RESUME_GUEST;
}
@@ -123,19 +127,23 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
/* check for PR=1 and arch 2.06 bit set in PCR */
if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
/* generate an illegal instruction interrupt */
+ vcpu->arch.regs.nip -= 4;
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
return RESUME_GUEST;
}
/* check for TM disabled in the HFSCR or MSR */
if (!(vcpu->arch.hfscr & HFSCR_TM)) {
- /* generate an illegal instruction interrupt */
- kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
- return RESUME_GUEST;
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
+ vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;
+ vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
+ return -1; /* rerun host interrupt handler */
}
if (!(msr & MSR_TM)) {
/* generate a facility unavailable interrupt */
- vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
- ((u64)FSCR_TM_LG << 56);
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
+ vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;
kvmppc_book3s_queue_irqprio(vcpu,
BOOK3S_INTERRUPT_FAC_UNAVAIL);
return RESUME_GUEST;
@@ -158,20 +166,24 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
case (PPC_INST_TRECLAIM & PO_XOP_OPCODE_MASK):
/* check for TM disabled in the HFSCR or MSR */
if (!(vcpu->arch.hfscr & HFSCR_TM)) {
- /* generate an illegal instruction interrupt */
- kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
- return RESUME_GUEST;
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
+ vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;
+ vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
+ return -1; /* rerun host interrupt handler */
}
if (!(msr & MSR_TM)) {
/* generate a facility unavailable interrupt */
- vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
- ((u64)FSCR_TM_LG << 56);
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
+ vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;
kvmppc_book3s_queue_irqprio(vcpu,
BOOK3S_INTERRUPT_FAC_UNAVAIL);
return RESUME_GUEST;
}
/* If no transaction active, generate TM bad thing */
if (!MSR_TM_ACTIVE(msr)) {
+ vcpu->arch.regs.nip -= 4;
kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
return RESUME_GUEST;
}
@@ -196,20 +208,24 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
/* XXX do we need to check for PR=0 here? */
/* check for TM disabled in the HFSCR or MSR */
if (!(vcpu->arch.hfscr & HFSCR_TM)) {
- /* generate an illegal instruction interrupt */
- kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
- return RESUME_GUEST;
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
+ vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;
+ vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
+ return -1; /* rerun host interrupt handler */
}
if (!(msr & MSR_TM)) {
/* generate a facility unavailable interrupt */
- vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
- ((u64)FSCR_TM_LG << 56);
+ vcpu->arch.regs.nip -= 4;
+ vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
+ vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;
kvmppc_book3s_queue_irqprio(vcpu,
BOOK3S_INTERRUPT_FAC_UNAVAIL);
return RESUME_GUEST;
}
/* If transaction active or TEXASR[FS] = 0, bad thing */
if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {
+ vcpu->arch.regs.nip -= 4;
kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
return RESUME_GUEST;
}
@@ -224,6 +240,7 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
}
/* What should we do here? We didn't recognize the instruction */
+ vcpu->arch.regs.nip -= 4;
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
pr_warn_ratelimited("Unrecognized TM-related instruction %#x for emulation", instr);
--
2.23.0
next prev parent reply other threads:[~2021-07-26 3:52 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-26 3:49 [PATCH v1 00/55] KVM: PPC: Book3S HV P9: entry/exit optimisations Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 01/55] KVM: PPC: Book3S HV: Remove TM emulation from POWER7/8 path Nicholas Piggin
2021-07-26 3:49 ` Nicholas Piggin [this message]
2021-08-06 1:16 ` [PATCH v1 02/55] KVM: PPC: Book3S HV P9: Fixes for TM softpatch interrupt Michael Ellerman
2021-08-06 10:25 ` Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 03/55] KVM: PPC: Book3S HV: Sanitise vcpu registers in nested path Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 04/55] KVM: PPC: Book3S HV: Stop forwarding all HFUs to L1 Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 05/55] KVM: PPC: Book3S HV Nested: Reflect guest PMU in-use to L0 when guest SPRs are live Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 06/55] powerpc/64s: Remove WORT SPR from POWER9/10 Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 07/55] KMV: PPC: Book3S HV P9: Use set_dec to set decrementer to host Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 08/55] KVM: PPC: Book3S HV P9: Use host timer accounting to avoid decrementer read Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 09/55] KVM: PPC: Book3S HV P9: Use large decrementer for HDEC Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 10/55] KVM: PPC: Book3S HV P9: Reduce mftb per guest entry/exit Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 11/55] powerpc/time: add API for KVM to re-arm the host timer/decrementer Nicholas Piggin
2021-08-05 7:22 ` Christophe Leroy
2021-08-06 10:30 ` Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 12/55] KVM: PPC: Book3S HV: POWER10 enable HAIL when running radix guests Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 13/55] powerpc/64s: Keep AMOR SPR a constant ~0 at runtime Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 14/55] KVM: PPC: Book3S HV: Don't always save PMU for guest capable of nesting Nicholas Piggin
2021-08-06 7:34 ` Michael Ellerman
2021-08-06 10:32 ` Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 15/55] powerpc/64s: Always set PMU control registers to frozen/disabled when not in use Nicholas Piggin
2021-07-26 3:49 ` [PATCH v1 16/55] powerpc/64s: Implement PMU override command line option Nicholas Piggin
2021-08-06 7:33 ` Madhavan Srinivasan
2021-08-06 10:38 ` Nicholas Piggin
2021-08-11 12:46 ` Madhavan Srinivasan
2021-08-06 9:28 ` Athira Rajeev
2021-08-06 10:42 ` Nicholas Piggin
2021-08-11 10:54 ` Athira Rajeev
2021-07-26 3:49 ` [PATCH v1 17/55] KVM: PPC: Book3S HV P9: Implement PMU save/restore in C Nicholas Piggin
2021-08-09 3:03 ` Athira Rajeev
2021-08-13 4:24 ` Nicholas Piggin
2021-08-14 7:12 ` Athira Rajeev
2021-07-26 3:49 ` [PATCH v1 18/55] KVM: PPC: Book3S HV P9: Factor PMU save/load into context switch functions Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 19/55] KVM: PPC: Book3S HV P9: Demand fault PMU SPRs when marked not inuse Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 20/55] KVM: PPC: Book3S HV P9: Factor out yield_count increment Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 21/55] KVM: PPC: Book3S HV: CTRL SPR does not require read-modify-write Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 22/55] KVM: PPC: Book3S HV P9: Move SPRG restore to restore_p9_host_os_sprs Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 23/55] KVM: PPC: Book3S HV P9: Reduce mtmsrd instructions required to save host SPRs Nicholas Piggin
2021-07-26 6:57 ` kernel test robot
2021-07-26 7:01 ` kernel test robot
2021-07-26 3:50 ` [PATCH v1 24/55] KVM: PPC: Book3S HV P9: Improve mtmsrd scheduling by delaying MSR[EE] disable Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 25/55] KVM: PPC: Book3S HV P9: Add kvmppc_stop_thread to match kvmppc_start_thread Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 26/55] KVM: PPC: Book3S HV: Change dec_expires to be relative to guest timebase Nicholas Piggin
2021-08-07 23:17 ` Michael Ellerman
2021-07-26 3:50 ` [PATCH v1 27/55] KVM: PPC: Book3S HV P9: Move TB updates Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 28/55] KVM: PPC: Book3S HV P9: Optimise timebase reads Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 29/55] KVM: PPC: Book3S HV P9: Avoid SPR scoreboard stalls Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 30/55] KVM: PPC: Book3S HV P9: Only execute mtSPR if the value changed Nicholas Piggin
2021-08-06 20:45 ` Fabiano Rosas
2021-07-26 3:50 ` [PATCH v1 31/55] KVM: PPC: Book3S HV P9: Juggle SPR switching around Nicholas Piggin
2021-08-06 20:46 ` Fabiano Rosas
2021-07-26 3:50 ` [PATCH v1 32/55] KVM: PPC: Book3S HV P9: Move vcpu register save/restore into functions Nicholas Piggin
2021-08-06 20:49 ` Fabiano Rosas
2021-07-26 3:50 ` [PATCH v1 33/55] KVM: PPC: Book3S HV P9: Move host OS save/restore functions to built-in Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 34/55] KVM: PPC: Book3S HV P9: Move nested guest entry into its own function Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 35/55] KVM: PPC: Book3S HV P9: Move remaining SPR and MSR access into low level entry Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 36/55] KVM: PPC: Book3S HV P9: Implement TM fastpath for guest entry/exit Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 37/55] KVM: PPC: Book3S HV P9: Switch PMU to guest as late as possible Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 38/55] KVM: PPC: Book3S HV P9: Restrict DSISR canary workaround to processors that require it Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 39/55] KVM: PPC: Book3S HV P9: More SPR speed improvements Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 40/55] KVM: PPC: Book3S HV P9: Demand fault EBB facility registers Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 41/55] KVM: PPC: Book3S HV P9: Demand fault TM " Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 42/55] KVM: PPC: Book3S HV P9: Use Linux SPR save/restore to manage some host SPRs Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 43/55] KVM: PPC: Book3S HV P9: Comment and fix MMU context switching code Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 44/55] KVM: PPC: Book3S HV P9: Test dawr_enabled() before saving host DAWR SPRs Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 45/55] KVM: PPC: Book3S HV P9: Don't restore PSSCR if not needed Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 46/55] KVM: PPC: Book3S HV P9: Avoid tlbsync sequence on radix guest exit Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 47/55] KVM: PPC: Book3S HV Nested: Avoid extra mftb() in nested entry Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 48/55] KVM: PPC: Book3S HV P9: Improve mfmsr performance on entry Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 49/55] KVM: PPC: Book3S HV P9: Optimise hash guest SLB saving Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 50/55] KVM: PPC: Book3S HV P9: Add unlikely annotation for !mmu_ready Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 51/55] KVM: PPC: Book3S HV P9: Avoid cpu_in_guest atomics on entry and exit Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 52/55] KVM: PPC: Book3S HV P9: Remove most of the vcore logic Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 53/55] KVM: PPC: Book3S HV P9: Tidy kvmppc_create_dtl_entry Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 54/55] KVM: PPC: Book3S HV P9: Stop using vc->dpdes Nicholas Piggin
2021-07-26 3:50 ` [PATCH v1 55/55] KVM: PPC: Book3S HV P9: Remove subcore HMI handling Nicholas Piggin
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