From: Rob Herring <robh@kernel.org>
To: Russell King <linux@armlinux.org.uk>,
James Morse <james.morse@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Guo Ren <guoren@kernel.org>,
Jonas Bonn <jonas@southpole.se>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>,
Stafford Horne <shorne@gmail.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Yoshinori Sato <ysato@users.sourceforge.jp>,
Rich Felker <dalias@libc.org>,
x86@kernel.org, Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: devicetree@vger.kernel.org,
Florian Fainelli <f.fainelli@gmail.com>,
Scott Branden <sbranden@broadcom.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
linux-sh@vger.kernel.org, Ray Jui <rjui@broadcom.com>,
"H. Peter Anvin" <hpa@zytor.com>,
linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org,
openrisc@lists.librecores.org, linuxppc-dev@lists.ozlabs.org,
Ingo Molnar <mingo@redhat.com>, Paul Mackerras <paulus@samba.org>,
Borislav Petkov <bp@alien8.de>,
bcm-kernel-feedback-list@broadcom.com,
Thomas Gleixner <tglx@linutronix.de>,
Frank Rowand <frowand.list@gmail.com>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id'
Date: Wed, 6 Oct 2021 11:43:31 -0500 [thread overview]
Message-ID: <20211006164332.1981454-12-robh@kernel.org> (raw)
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
In preparation to set the cache 'id' based on the CPU h/w ids, allow for
64-bit bit 'id' value. The only case that needs this is arm64, so
unsigned long is sufficient.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/base/cacheinfo.c | 8 +++++++-
include/linux/cacheinfo.h | 2 +-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index dad296229161..66d10bdb863b 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -366,13 +366,19 @@ static ssize_t file_name##_show(struct device *dev, \
return sysfs_emit(buf, "%u\n", this_leaf->object); \
}
-show_one(id, id);
show_one(level, level);
show_one(coherency_line_size, coherency_line_size);
show_one(number_of_sets, number_of_sets);
show_one(physical_line_partition, physical_line_partition);
show_one(ways_of_associativity, ways_of_associativity);
+static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct cacheinfo *this_leaf = dev_get_drvdata(dev);
+
+ return sysfs_emit(buf, "%lu\n", this_leaf->id);
+}
+
static ssize_t size_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 2f909ed084c6..b2e7f3e40204 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -48,7 +48,7 @@ extern unsigned int coherency_max_size;
* keeping, the remaining members form the core properties of the cache
*/
struct cacheinfo {
- unsigned int id;
+ unsigned long id;
enum cache_type type;
unsigned int level;
unsigned int coherency_line_size;
--
2.30.2
next prev parent reply other threads:[~2021-10-06 16:48 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-06 16:43 [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Rob Herring
2021-10-06 16:43 ` [PATCH 01/12] of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes Rob Herring
2021-10-18 13:26 ` Sudeep Holla
2021-10-06 16:43 ` [PATCH 02/12] ARM: Use of_get_cpu_hwid() Rob Herring
2021-10-06 16:43 ` [PATCH 03/12] ARM: broadcom: " Rob Herring
2021-10-07 2:24 ` Florian Fainelli
2021-10-06 16:43 ` [PATCH 04/12] arm64: " Rob Herring
2021-10-07 8:07 ` Will Deacon
2021-10-18 13:27 ` Sudeep Holla
2021-10-06 16:43 ` [PATCH 05/12] csky: " Rob Herring
2021-10-06 16:43 ` [PATCH 06/12] openrisc: " Rob Herring
2021-10-06 20:44 ` Stafford Horne
2021-10-06 21:08 ` Rob Herring
2021-10-06 21:25 ` Stafford Horne
2021-10-06 21:27 ` Segher Boessenkool
2021-10-06 22:37 ` Stafford Horne
2021-10-07 7:53 ` David Laight
2021-10-06 16:43 ` [PATCH 07/12] powerpc: " Rob Herring
2021-10-08 11:01 ` Michael Ellerman
2021-10-06 16:43 ` [PATCH 08/12] riscv: " Rob Herring
2021-10-06 16:43 ` [PATCH 09/12] sh: " Rob Herring
2021-10-27 14:26 ` Rich Felker
2021-10-06 16:43 ` [PATCH 10/12] x86: dt: " Rob Herring
2021-10-06 16:43 ` Rob Herring [this message]
2021-10-18 13:30 ` [PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id' Sudeep Holla
2021-10-06 16:43 ` [PATCH 12/12] cacheinfo: Set cache 'id' based on DT data Rob Herring
2021-10-18 13:31 ` Sudeep Holla
2021-10-07 2:24 ` [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Florian Fainelli
2021-10-20 18:47 ` Rob Herring
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