From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
To: mpe@ellerman.id.au, acme@kernel.org, jolsa@kernel.org
Cc: kjain@linux.ibm.com, maddy@linux.vnet.ibm.com,
linuxppc-dev@lists.ozlabs.org, rnsastry@linux.ibm.com
Subject: [V3 3/4] powerpc/perf: Expose instruction and data address registers as part of extended regs
Date: Thu, 7 Oct 2021 12:25:04 +0530 [thread overview]
Message-ID: <20211007065505.27809-4-atrajeev@linux.vnet.ibm.com> (raw)
In-Reply-To: <20211007065505.27809-1-atrajeev@linux.vnet.ibm.com>
Patch adds support to include Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
PERF_REG_EXTENDED_MAX to include these SPR's.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Daniel Axtens <dja@axtens.net>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 11 +++++++----
arch/powerpc/perf/perf_regs.c | 4 ++++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/powerpc/include/uapi/asm/perf_regs.h
index 085094553f3b..749a2e3af89e 100644
--- a/arch/powerpc/include/uapi/asm/perf_regs.h
+++ b/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -61,17 +61,19 @@ enum perf_event_powerpc_regs {
PERF_REG_POWERPC_PMC4,
PERF_REG_POWERPC_PMC5,
PERF_REG_POWERPC_PMC6,
+ PERF_REG_POWERPC_SDAR,
+ PERF_REG_POWERPC_SIAR,
/* Max mask value for interrupt regs w/o extended regs */
PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
/* Max mask value for interrupt regs including extended regs */
- PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_PMC6 + 1,
+ PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_SIAR + 1,
};
#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
/*
* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
- * includes 9 SPRS from MMCR0 to PMC6 excluding the
+ * includes 11 SPRS from MMCR0 to SIAR excluding the
* unsupported SPRS MMCR3, SIER2 and SIER3.
*/
#define PERF_REG_PMU_MASK_300 \
@@ -79,11 +81,12 @@ enum perf_event_powerpc_regs {
(1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \
(1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \
(1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \
- (1ULL << PERF_REG_POWERPC_PMC6))
+ (1ULL << PERF_REG_POWERPC_PMC6) | (1ULL << PERF_REG_POWERPC_SDAR) | \
+ (1ULL << PERF_REG_POWERPC_SIAR))
/*
* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
- * includes 12 SPRs from MMCR0 to PMC6.
+ * includes 14 SPRs from MMCR0 to SIAR.
*/
#define PERF_REG_PMU_MASK_31 \
(PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \
diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
index b931eed482c9..51d31b65e423 100644
--- a/arch/powerpc/perf/perf_regs.c
+++ b/arch/powerpc/perf/perf_regs.c
@@ -90,7 +90,11 @@ static u64 get_ext_regs_value(int idx)
return mfspr(SPRN_SIER2);
case PERF_REG_POWERPC_SIER3:
return mfspr(SPRN_SIER3);
+ case PERF_REG_POWERPC_SDAR:
+ return mfspr(SPRN_SDAR);
#endif
+ case PERF_REG_POWERPC_SIAR:
+ return mfspr(SPRN_SIAR);
default: return 0;
}
}
--
2.30.1 (Apple Git-130)
next prev parent reply other threads:[~2021-10-07 6:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 6:55 [V3 0/4] powerpc/perf: Add instruction and data address registers to extended regs Athira Rajeev
2021-10-07 6:55 ` [V3 1/4] powerpc/perf: Refactor the code definition of perf reg extended mask Athira Rajeev
2021-10-07 6:55 ` [V3 2/4] tools/perf: Refactor the code definition of perf reg extended mask in tools side header file Athira Rajeev
2021-10-07 6:55 ` Athira Rajeev [this message]
2021-10-07 6:55 ` [V3 4/4] tools/perf: Add perf tools support to expose instruction and data address registers as part of extended regs Athira Rajeev
2021-10-11 13:09 ` [V3 0/4] powerpc/perf: Add instruction and data address registers to " kajoljain
2021-10-17 12:32 ` Michael Ellerman
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