* [PATCH 01/20] selftest/powerpc/pmu: Include mmap_buffer field as part of struct event
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
@ 2022-01-27 7:19 ` Kajol Jain
2022-01-27 7:19 ` [PATCH 02/20] selftest/powerpc/pmu: Add support for perf sampling tests Kajol Jain
` (19 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:19 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
To enable the capturing of samples as part of perf event,
add a new field "mmap_buffer" to "struct event". This
field is a place-holder for sample collection
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
tools/testing/selftests/powerpc/pmu/event.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/event.h b/tools/testing/selftests/powerpc/pmu/event.h
index 302eaab51706..23d20340a160 100644
--- a/tools/testing/selftests/powerpc/pmu/event.h
+++ b/tools/testing/selftests/powerpc/pmu/event.h
@@ -22,6 +22,11 @@ struct event {
u64 running;
u64 enabled;
} result;
+ /*
+ * mmap buffer used while recording sample.
+ * Accessed as "struct perf_event_mmap_page"
+ */
+ void *mmap_buffer;
};
void event_init(struct event *e, u64 config);
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 02/20] selftest/powerpc/pmu: Add support for perf sampling tests
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
2022-01-27 7:19 ` [PATCH 01/20] selftest/powerpc/pmu: Include mmap_buffer field as part of struct event Kajol Jain
@ 2022-01-27 7:19 ` Kajol Jain
2022-01-27 7:19 ` [PATCH 03/20] selftest/powerpc/pmu: Add macros to parse event codes Kajol Jain
` (18 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:19 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Add support functions for enabling perf sampling test in
a new folder "sampling_tests" under "selftests/powerpc/pmu".
This includes support functions for allocating and processing
the mmap buffer. These functions are added/defined in
"sampling_tests/misc.*" files.
Also updates the corresponding Makefiles in "selftests/powerpc"
and "sampling_tests" folder.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
tools/testing/selftests/powerpc/pmu/Makefile | 11 +-
.../powerpc/pmu/sampling_tests/Makefile | 20 ++++
.../powerpc/pmu/sampling_tests/misc.c | 105 ++++++++++++++++++
.../powerpc/pmu/sampling_tests/misc.h | 9 ++
4 files changed, 143 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
diff --git a/tools/testing/selftests/powerpc/pmu/Makefile b/tools/testing/selftests/powerpc/pmu/Makefile
index 904672fb78dd..edbd96d3b2ab 100644
--- a/tools/testing/selftests/powerpc/pmu/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/Makefile
@@ -8,7 +8,7 @@ EXTRA_SOURCES := ../harness.c event.c lib.c ../utils.c
top_srcdir = ../../../../..
include ../../lib.mk
-all: $(TEST_GEN_PROGS) ebb
+all: $(TEST_GEN_PROGS) ebb sampling_tests
$(TEST_GEN_PROGS): $(EXTRA_SOURCES)
@@ -26,25 +26,32 @@ DEFAULT_RUN_TESTS := $(RUN_TESTS)
override define RUN_TESTS
$(DEFAULT_RUN_TESTS)
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
+ TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
endef
DEFAULT_EMIT_TESTS := $(EMIT_TESTS)
override define EMIT_TESTS
$(DEFAULT_EMIT_TESTS)
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
+ TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
endef
DEFAULT_INSTALL_RULE := $(INSTALL_RULE)
override define INSTALL_RULE
$(DEFAULT_INSTALL_RULE)
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
+ TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
endef
clean:
$(RM) $(TEST_GEN_PROGS) $(OUTPUT)/loop.o
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
+ TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
ebb:
TARGET=$@; BUILD_TARGET=$$OUTPUT/$$TARGET; mkdir -p $$BUILD_TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -k -C $$TARGET all
-.PHONY: all run_tests clean ebb
+sampling_tests:
+ TARGET=$@; BUILD_TARGET=$$OUTPUT/$$TARGET; mkdir -p $$BUILD_TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -k -C $$TARGET all
+
+.PHONY: all run_tests clean ebb sampling_tests
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
new file mode 100644
index 000000000000..eb00c9f931ec
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+include ../../../../../../scripts/Kbuild.include
+
+all: $(TEST_GEN_PROGS)
+
+noarg:
+ $(MAKE) -C ../../
+
+CFLAGS += -m64 -I../../../../../lib/
+
+# Toolchains may build PIE by default which breaks the assembly
+no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
+ $(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
+
+LDFLAGS += $(no-pie-option)
+
+top_srcdir = ../../../../../..
+include ../../../lib.mk
+
+$(TEST_GEN_PROGS): ../../harness.c ../../utils.c ../event.c ../lib.c misc.c misc.h
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
new file mode 100644
index 000000000000..4779b107f43b
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <unistd.h>
+#include <sys/syscall.h>
+#include <string.h>
+#include <stdio.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <stdlib.h>
+#include <ctype.h>
+
+#include "misc.h"
+
+#define PAGE_SIZE sysconf(_SC_PAGESIZE)
+
+/*
+ * Allocate mmap buffer of "mmap_pages" number of
+ * pages.
+ */
+void *event_sample_buf_mmap(int fd, int mmap_pages)
+{
+ size_t page_size = sysconf(_SC_PAGESIZE);
+ size_t mmap_size;
+ void *buff;
+
+ if (mmap_pages <= 0)
+ return NULL;
+
+ if (fd <= 0)
+ return NULL;
+
+ mmap_size = page_size * (1 + mmap_pages);
+ buff = mmap(NULL, mmap_size,
+ PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+
+ if (buff == MAP_FAILED) {
+ perror("mmap() failed.");
+ return NULL;
+ }
+ return buff;
+}
+
+/*
+ * Post process the mmap buffer.
+ * - If sample_count != NULL then return count of total
+ * number of samples present in the mmap buffer.
+ * - If sample_count == NULL then return the address
+ * of first sample from the mmap buffer
+ */
+void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count)
+{
+ size_t page_size = sysconf(_SC_PAGESIZE);
+ struct perf_event_header *header = sample_buff + page_size;
+ struct perf_event_mmap_page *metadata_page = sample_buff;
+ unsigned long data_head, data_tail;
+
+ /*
+ * PERF_RECORD_SAMPLE:
+ * struct {
+ * struct perf_event_header hdr;
+ * u64 data[];
+ * };
+ */
+
+ data_head = metadata_page->data_head;
+ /* sync memory before reading sample */
+ mb();
+ data_tail = metadata_page->data_tail;
+
+ /* Check for sample_count */
+ if (sample_count)
+ *sample_count = 0;
+
+ while (1) {
+ /*
+ * Reads the mmap data buffer by moving
+ * the data_tail to know the last read data.
+ * data_head points to head in data buffer.
+ * refer "struct perf_event_mmap_page" in
+ * "include/uapi/linux/perf_event.h".
+ */
+ if (data_head - data_tail < sizeof(header))
+ return NULL;
+
+ data_tail += sizeof(header);
+ if (header->type == PERF_RECORD_SAMPLE) {
+ *size = (header->size - sizeof(header));
+ if (!sample_count)
+ return sample_buff + page_size + data_tail;
+ data_tail += *size;
+ *sample_count += 1;
+ } else {
+ *size = (header->size - sizeof(header));
+ if ((metadata_page->data_tail + *size) > metadata_page->data_head)
+ data_tail = metadata_page->data_head;
+ else
+ data_tail += *size;
+ }
+ header = (struct perf_event_header *)((void *)header + header->size);
+ }
+ return NULL;
+}
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
new file mode 100644
index 000000000000..291f9adba817
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include "../event.h"
+
+void *event_sample_buf_mmap(int fd, int mmap_pages);
+void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count);
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 03/20] selftest/powerpc/pmu: Add macros to parse event codes
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
2022-01-27 7:19 ` [PATCH 01/20] selftest/powerpc/pmu: Include mmap_buffer field as part of struct event Kajol Jain
2022-01-27 7:19 ` [PATCH 02/20] selftest/powerpc/pmu: Add support for perf sampling tests Kajol Jain
@ 2022-01-27 7:19 ` Kajol Jain
2022-01-27 7:19 ` [PATCH 04/20] selftest/powerpc/pmu: Add utility functions to post process the mmap buffer Kajol Jain
` (17 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:19 UTC (permalink / raw)
To: mpe; +Cc: atrajeev, rnsastry, kjain, maddy, Madhavan Srinivasan, linuxppc-dev
From: Madhavan Srinivasan <maddy@linux.ibm.com>
Each platform has raw event encoding format which specifies
the bit positions for different fields. The fields from event
code gets translated into performance monitoring mode control
register (MMCRx) settings. Patch add macros to extract individual
fields from the event code.
Patch adds function for sanity checks, since testcases currently
are only supported in power9 and power10.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/misc.c | 227 ++++++++++++++++++
.../powerpc/pmu/sampling_tests/misc.h | 50 ++++
2 files changed, 277 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index 4779b107f43b..fcd139c95971 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2022, Athira Rajeev, IBM Corp.
+ * Copyright 2022, Madhavan Srinivasan, IBM Corp.
*/
#include <unistd.h>
@@ -16,6 +17,232 @@
#define PAGE_SIZE sysconf(_SC_PAGESIZE)
+/* Storage for platform version */
+int pvr, pvr_dd;
+u64 platform_extended_mask;
+int pSeries;
+
+/* Mask and Shift for Event code fields */
+int ev_mask_pmcxsel, ev_shift_pmcxsel; //pmcxsel field
+int ev_mask_marked, ev_shift_marked; //marked filed
+int ev_mask_comb, ev_shift_comb; //combine field
+int ev_mask_unit, ev_shift_unit; //unit field
+int ev_mask_pmc, ev_shift_pmc; //pmc field
+int ev_mask_cache, ev_shift_cache; //Cache sel field
+int ev_mask_sample, ev_shift_sample; //Random sampling field
+int ev_mask_thd_sel, ev_shift_thd_sel; //thresh_sel field
+int ev_mask_thd_start, ev_shift_thd_start; //thresh_start field
+int ev_mask_thd_stop, ev_shift_thd_stop; //thresh_stop field
+int ev_mask_thd_cmp, ev_shift_thd_cmp; //thresh cmp field
+int ev_mask_sm, ev_shift_sm; //SDAR mode field
+int ev_mask_rsq, ev_shift_rsq; //radix scope qual field
+int ev_mask_l2l3, ev_shift_l2l3; //l2l3 sel field
+int ev_mask_mmcr3_src, ev_shift_mmcr3_src; //mmcr3 field
+
+static void init_ev_encodes(void)
+{
+ ev_mask_pmcxsel = 0xff;
+ ev_shift_pmcxsel = 0;
+ ev_mask_marked = 1;
+ ev_shift_marked = 8;
+ ev_mask_unit = 0xf;
+ ev_shift_unit = 12;
+ ev_mask_pmc = 0xf;
+ ev_shift_pmc = 16;
+ ev_mask_sample = 0x1f;
+ ev_shift_sample = 24;
+ ev_mask_thd_sel = 0x7;
+ ev_shift_thd_sel = 29;
+ ev_mask_thd_start = 0xf;
+ ev_shift_thd_start = 36;
+ ev_mask_thd_stop = 0xf;
+ ev_shift_thd_stop = 32;
+
+ switch (pvr) {
+ case POWER10:
+ ev_mask_rsq = 1;
+ ev_shift_rsq = 9;
+ ev_mask_comb = 3;
+ ev_shift_comb = 10;
+ ev_mask_cache = 3;
+ ev_shift_cache = 20;
+ ev_mask_sm = 0x3;
+ ev_shift_sm = 22;
+ ev_mask_l2l3 = 0x1f;
+ ev_shift_l2l3 = 40;
+ ev_mask_mmcr3_src = 0x7fff;
+ ev_shift_mmcr3_src = 45;
+ break;
+ case POWER9:
+ ev_mask_comb = 3;
+ ev_shift_comb = 10;
+ ev_mask_cache = 0xf;
+ ev_shift_cache = 20;
+ ev_mask_thd_cmp = 0x3ff;
+ ev_shift_thd_cmp = 40;
+ ev_mask_sm = 0x3;
+ ev_shift_sm = 50;
+ break;
+ default:
+ FAIL_IF_EXIT(1);
+ }
+}
+
+static int __get_pvr(int flg)
+{
+ FILE *fd;
+ char *buf = NULL, *search_string = "revision", tmp[4];
+ size_t len = 0;
+ int ret = -1;
+
+ fd = fopen("/proc/cpuinfo", "r");
+ if (!fd)
+ return -1;
+
+ /* get to the line that matters */
+ while (getline(&buf, &len, fd) > 0) {
+ ret = strncmp(buf, search_string, strlen(search_string));
+ if (!ret)
+ break;
+ }
+
+ switch (flg) {
+ case 1: /* get processor version number */
+ /* seek to pvr hex values within the line */
+ while (*buf++ != '(')
+ ; /* nothing to run */
+ buf += 5;
+ strncpy(tmp, buf, 3);
+
+ fclose(fd);
+ return strtol(tmp, NULL, 16);
+
+ case 2: /* get processor major revision number */
+ /* seek to pvr hex values within the line */
+ while (*buf++ != ':')
+ ; /* nothing to run */
+ strncpy(tmp, buf, 3);
+
+ fclose(fd);
+ return (int)strtof(tmp, NULL);
+ default:
+ return -1;
+ }
+}
+
+static int init_platform(void)
+{
+ FILE *fd;
+ char *buf = NULL, *search_string = "pSeries", *sim = "Mambo", *ptr;
+ size_t len = 0;
+
+ fd = fopen("/proc/cpuinfo", "r");
+ if (!fd)
+ return -1;
+
+ /* check for sim (like mambo) */
+ while (getline(&buf, &len, fd) > 0) {
+ ptr = strstr(buf, sim);
+ if (ptr)
+ return -1;
+ }
+
+ fseek(fd, 0, SEEK_SET);
+
+ /* get to the line that matters */
+ while (getline(&buf, &len, fd) > 0) {
+ ptr = strstr(buf, search_string);
+ if (ptr) {
+ pSeries = 1;
+ break;
+ }
+ }
+
+ fclose(fd);
+ return 0;
+}
+
+static int get_ver(void)
+{
+ return __get_pvr(1);
+}
+
+static int get_rev_maj(void)
+{
+ return __get_pvr(2);
+}
+
+/* Return the extended regs mask value */
+static u64 perf_get_platform_reg_mask(void)
+{
+ if (have_hwcap2(PPC_FEATURE2_ARCH_3_1))
+ return PERF_POWER10_MASK;
+ if (have_hwcap2(PPC_FEATURE2_ARCH_3_00))
+ return PERF_POWER9_MASK;
+
+ return -1;
+}
+
+int check_extended_regs_support(void)
+{
+ int fd;
+ struct event event;
+
+ event_init(&event, 0x1001e);
+
+ event.attr.type = 4;
+ event.attr.sample_period = 1;
+ event.attr.disabled = 1;
+ event.attr.sample_type = PERF_SAMPLE_REGS_INTR;
+ event.attr.sample_regs_intr = platform_extended_mask;
+
+ fd = event_open(&event);
+ if (fd != -1)
+ return 0;
+
+ return -1;
+}
+
+int check_pvr_for_sampling_tests(void)
+{
+ pvr = get_ver();
+ /* Exit if it fails to fetch pvr */
+ if (pvr < 0) {
+ printf("%s: Failed to fetch pvr\n", __func__);
+ FAIL_IF_EXIT(1);
+ }
+
+ platform_extended_mask = perf_get_platform_reg_mask();
+
+ /*
+ * Check for supported platforms
+ * for sampling test
+ */
+ if ((pvr != POWER10) && (pvr != POWER9))
+ goto out;
+
+ /*
+ * Check PMU driver registered by looking for
+ * PPC_FEATURE2_EBB bit in AT_HWCAP2
+ */
+ if (!have_hwcap2(PPC_FEATURE2_EBB))
+ goto out;
+
+ /* check if platform supports extended regs */
+ if (check_extended_regs_support())
+ goto out;
+
+ pvr_dd = get_rev_maj();
+
+ if (init_platform())
+ goto out;
+
+ init_ev_encodes();
+ return 0;
+out:
+ printf("%s: Sampling tests un-supported\n", __func__);
+ return -1;
+}
/*
* Allocate mmap buffer of "mmap_pages" number of
* pages.
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 291f9adba817..8526c15d4c90 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -1,9 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2022, Athira Rajeev, IBM Corp.
+ * Copyright 2022, Madhavan Srinivasan, IBM Corp.
*/
#include "../event.h"
+#define POWER10 0x80
+#define POWER9 0x4e
+#define PERF_POWER9_MASK 0x7f8ffffffffffff
+#define PERF_POWER10_MASK 0x7ffffffffffffff
+
+extern int ev_mask_pmcxsel, ev_shift_pmcxsel;
+extern int ev_mask_marked, ev_shift_marked;
+extern int ev_mask_comb, ev_shift_comb;
+extern int ev_mask_unit, ev_shift_unit;
+extern int ev_mask_pmc, ev_shift_pmc;
+extern int ev_mask_cache, ev_shift_cache;
+extern int ev_mask_sample, ev_shift_sample;
+extern int ev_mask_thd_sel, ev_shift_thd_sel;
+extern int ev_mask_thd_start, ev_shift_thd_start;
+extern int ev_mask_thd_stop, ev_shift_thd_stop;
+extern int ev_mask_thd_cmp, ev_shift_thd_cmp;
+extern int ev_mask_sm, ev_shift_sm;
+extern int ev_mask_rsq, ev_shift_rsq;
+extern int ev_mask_l2l3, ev_shift_l2l3;
+extern int ev_mask_mmcr3_src, ev_shift_mmcr3_src;
+extern int pvr, pvr_dd, pSeries;
+extern u64 platform_extended_mask;
+extern int check_pvr_for_sampling_tests(void);
+
+/*
+ * Event code field extraction macro.
+ * Raw event code is combination of multiple
+ * fields. Macro to extract individual fields
+ *
+ * x - Raw event code value
+ * y - Field to extract
+ */
+#define EV_CODE_EXTRACT(x, y) \
+ ((x >> ev_shift_##y) & ev_mask_##y)
+
+/*
+ * Event attribute extraction macro.
+ *
+ * x - struct event
+ * y - attribute field
+ */
+#define GET_ATTR_FIELD(x, y) \
+ ((x)->attr.y)
+
+static inline int is_pSeries(void)
+{
+ return pSeries;
+}
+
void *event_sample_buf_mmap(int fd, int mmap_pages);
void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count);
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 04/20] selftest/powerpc/pmu: Add utility functions to post process the mmap buffer
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (2 preceding siblings ...)
2022-01-27 7:19 ` [PATCH 03/20] selftest/powerpc/pmu: Add macros to parse event codes Kajol Jain
@ 2022-01-27 7:19 ` Kajol Jain
2022-01-27 7:19 ` [PATCH 05/20] selftest/powerpc/pmu: Add event_init_sampling function Kajol Jain
` (16 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:19 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
Add couple of basic utility functions to post process the
mmap buffer. It includes function to read the total
number of samples present in the mmap buffer and function
to get the address of the first sample.
Add function "get_intr_regs" which will return pointer to
interrupt registers present in the sample, incase sample
type PERF_SAMPLE_REGS_INTR is set.
Add functions "get_reg_value" which can be used to read any
interrupt register value from a given sample.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/misc.c | 175 ++++++++++++++++++
.../powerpc/pmu/sampling_tests/misc.h | 4 +
2 files changed, 179 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index fcd139c95971..5712df1bd3c2 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -2,6 +2,7 @@
/*
* Copyright 2022, Athira Rajeev, IBM Corp.
* Copyright 2022, Madhavan Srinivasan, IBM Corp.
+ * Copyright 2022, Kajol Jain, IBM Corp.
*/
#include <unistd.h>
@@ -330,3 +331,177 @@ void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count)
}
return NULL;
}
+
+int collect_samples(void *sample_buff)
+{
+ u64 sample_count;
+ size_t size = 0;
+
+ __event_read_samples(sample_buff, &size, &sample_count);
+ return sample_count;
+}
+
+static void *perf_read_first_sample(void *sample_buff, size_t *size)
+{
+ return __event_read_samples(sample_buff, size, NULL);
+}
+
+u64 *get_intr_regs(struct event *event, void *sample_buff)
+{
+ u64 type = event->attr.sample_type;
+ u64 *intr_regs;
+ size_t size = 0;
+
+ if ((type ^ PERF_SAMPLE_REGS_INTR))
+ return NULL;
+
+ intr_regs = (u64 *)perf_read_first_sample(sample_buff, &size);
+ if (!intr_regs)
+ return NULL;
+
+ /*
+ * First entry in the sample buffer used to specify
+ * PERF_SAMPLE_REGS_ABI_64, skip perf regs abi to access
+ * interrupt registers.
+ */
+ ++intr_regs;
+
+ return intr_regs;
+}
+
+static const unsigned int __perf_reg_mask(const char *register_name)
+{
+ if (!strcmp(register_name, "R0"))
+ return 0;
+ else if (!strcmp(register_name, "R1"))
+ return 1;
+ else if (!strcmp(register_name, "R2"))
+ return 2;
+ else if (!strcmp(register_name, "R3"))
+ return 3;
+ else if (!strcmp(register_name, "R4"))
+ return 4;
+ else if (!strcmp(register_name, "R5"))
+ return 5;
+ else if (!strcmp(register_name, "R6"))
+ return 6;
+ else if (!strcmp(register_name, "R7"))
+ return 7;
+ else if (!strcmp(register_name, "R8"))
+ return 8;
+ else if (!strcmp(register_name, "R9"))
+ return 9;
+ else if (!strcmp(register_name, "R10"))
+ return 10;
+ else if (!strcmp(register_name, "R11"))
+ return 11;
+ else if (!strcmp(register_name, "R12"))
+ return 12;
+ else if (!strcmp(register_name, "R13"))
+ return 13;
+ else if (!strcmp(register_name, "R14"))
+ return 14;
+ else if (!strcmp(register_name, "R15"))
+ return 15;
+ else if (!strcmp(register_name, "R16"))
+ return 16;
+ else if (!strcmp(register_name, "R17"))
+ return 17;
+ else if (!strcmp(register_name, "R18"))
+ return 18;
+ else if (!strcmp(register_name, "R19"))
+ return 19;
+ else if (!strcmp(register_name, "R20"))
+ return 20;
+ else if (!strcmp(register_name, "R21"))
+ return 21;
+ else if (!strcmp(register_name, "R22"))
+ return 22;
+ else if (!strcmp(register_name, "R23"))
+ return 23;
+ else if (!strcmp(register_name, "R24"))
+ return 24;
+ else if (!strcmp(register_name, "R25"))
+ return 25;
+ else if (!strcmp(register_name, "R26"))
+ return 26;
+ else if (!strcmp(register_name, "R27"))
+ return 27;
+ else if (!strcmp(register_name, "R28"))
+ return 28;
+ else if (!strcmp(register_name, "R29"))
+ return 29;
+ else if (!strcmp(register_name, "R30"))
+ return 30;
+ else if (!strcmp(register_name, "R31"))
+ return 31;
+ else if (!strcmp(register_name, "NIP"))
+ return 32;
+ else if (!strcmp(register_name, "MSR"))
+ return 33;
+ else if (!strcmp(register_name, "ORIG_R3"))
+ return 34;
+ else if (!strcmp(register_name, "CTR"))
+ return 35;
+ else if (!strcmp(register_name, "LINK"))
+ return 36;
+ else if (!strcmp(register_name, "XER"))
+ return 37;
+ else if (!strcmp(register_name, "CCR"))
+ return 38;
+ else if (!strcmp(register_name, "SOFTE"))
+ return 39;
+ else if (!strcmp(register_name, "TRAP"))
+ return 40;
+ else if (!strcmp(register_name, "DAR"))
+ return 41;
+ else if (!strcmp(register_name, "DSISR"))
+ return 42;
+ else if (!strcmp(register_name, "SIER"))
+ return 43;
+ else if (!strcmp(register_name, "MMCRA"))
+ return 44;
+ else if (!strcmp(register_name, "MMCR0"))
+ return 45;
+ else if (!strcmp(register_name, "MMCR1"))
+ return 46;
+ else if (!strcmp(register_name, "MMCR2"))
+ return 47;
+ else if (!strcmp(register_name, "MMCR3"))
+ return 48;
+ else if (!strcmp(register_name, "SIER2"))
+ return 49;
+ else if (!strcmp(register_name, "SIER3"))
+ return 50;
+ else if (!strcmp(register_name, "PMC1"))
+ return 51;
+ else if (!strcmp(register_name, "PMC2"))
+ return 52;
+ else if (!strcmp(register_name, "PMC3"))
+ return 53;
+ else if (!strcmp(register_name, "PMC4"))
+ return 54;
+ else if (!strcmp(register_name, "PMC5"))
+ return 55;
+ else if (!strcmp(register_name, "PMC6"))
+ return 56;
+ else if (!strcmp(register_name, "SDAR"))
+ return 57;
+ else if (!strcmp(register_name, "SIAR"))
+ return 58;
+ else
+ return -1;
+}
+
+u64 get_reg_value(u64 *intr_regs, char *register_name)
+{
+ int register_bit_position;
+
+ register_bit_position = __perf_reg_mask(register_name);
+
+ if (register_bit_position < 0 || (!((platform_extended_mask >>
+ (register_bit_position - 1)) & 1)))
+ return -1;
+
+ return *(intr_regs + register_bit_position);
+}
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 8526c15d4c90..3cfe98716b1e 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -2,6 +2,7 @@
/*
* Copyright 2022, Athira Rajeev, IBM Corp.
* Copyright 2022, Madhavan Srinivasan, IBM Corp.
+ * Copyright 2022, Kajol Jain, IBM Corp.
*/
#include "../event.h"
@@ -57,3 +58,6 @@ static inline int is_pSeries(void)
void *event_sample_buf_mmap(int fd, int mmap_pages);
void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count);
+int collect_samples(void *sample_buff);
+u64 *get_intr_regs(struct event *event, void *sample_buff);
+u64 get_reg_value(u64 *intr_regs, char *register_name);
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 05/20] selftest/powerpc/pmu: Add event_init_sampling function
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (3 preceding siblings ...)
2022-01-27 7:19 ` [PATCH 04/20] selftest/powerpc/pmu: Add utility functions to post process the mmap buffer Kajol Jain
@ 2022-01-27 7:19 ` Kajol Jain
2022-01-27 7:19 ` [PATCH 06/20] selftest/powerpc/pmu: Add macros to extract mmcr fields Kajol Jain
` (15 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:19 UTC (permalink / raw)
To: mpe; +Cc: atrajeev, rnsastry, kjain, maddy, Madhavan Srinivasan, linuxppc-dev
From: Madhavan Srinivasan <maddy@linux.ibm.com>
Extended event_init_opts() to include initialization
of sampling testcases. Patch adds an event_init_sampling()
wrapper to initialize event attribute fields for sampling
events. This includes initializing sample period, sample type
and event type.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
tools/testing/selftests/powerpc/pmu/event.c | 18 +++++++++++++++++-
tools/testing/selftests/powerpc/pmu/event.h | 1 +
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/powerpc/pmu/event.c b/tools/testing/selftests/powerpc/pmu/event.c
index 48e3a413b15d..cbba74c1170f 100644
--- a/tools/testing/selftests/powerpc/pmu/event.c
+++ b/tools/testing/selftests/powerpc/pmu/event.c
@@ -20,7 +20,8 @@ int perf_event_open(struct perf_event_attr *attr, pid_t pid, int cpu,
group_fd, flags);
}
-void event_init_opts(struct event *e, u64 config, int type, char *name)
+static void __event_init_opts(struct event *e, u64 config,
+ int type, char *name, int sampling)
{
memset(e, 0, sizeof(*e));
@@ -32,6 +33,16 @@ void event_init_opts(struct event *e, u64 config, int type, char *name)
/* This has to match the structure layout in the header */
e->attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED | \
PERF_FORMAT_TOTAL_TIME_RUNNING;
+ if (sampling) {
+ e->attr.sample_period = 1000;
+ e->attr.sample_type = PERF_SAMPLE_REGS_INTR;
+ e->attr.disabled = 1;
+ }
+}
+
+void event_init_opts(struct event *e, u64 config, int type, char *name)
+{
+ __event_init_opts(e, config, type, name, 0);
}
void event_init_named(struct event *e, u64 config, char *name)
@@ -44,6 +55,11 @@ void event_init(struct event *e, u64 config)
event_init_opts(e, config, PERF_TYPE_RAW, "event");
}
+void event_init_sampling(struct event *e, u64 config)
+{
+ __event_init_opts(e, config, PERF_TYPE_RAW, "event", 1);
+}
+
#define PERF_CURRENT_PID 0
#define PERF_NO_PID -1
#define PERF_NO_CPU -1
diff --git a/tools/testing/selftests/powerpc/pmu/event.h b/tools/testing/selftests/powerpc/pmu/event.h
index 23d20340a160..51aad0b6d9ad 100644
--- a/tools/testing/selftests/powerpc/pmu/event.h
+++ b/tools/testing/selftests/powerpc/pmu/event.h
@@ -32,6 +32,7 @@ struct event {
void event_init(struct event *e, u64 config);
void event_init_named(struct event *e, u64 config, char *name);
void event_init_opts(struct event *e, u64 config, int type, char *name);
+void event_init_sampling(struct event *e, u64 config);
int event_open_with_options(struct event *e, pid_t pid, int cpu, int group_fd);
int event_open_with_group(struct event *e, int group_fd);
int event_open_with_pid(struct event *e, pid_t pid);
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 06/20] selftest/powerpc/pmu: Add macros to extract mmcr fields
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (4 preceding siblings ...)
2022-01-27 7:19 ` [PATCH 05/20] selftest/powerpc/pmu: Add event_init_sampling function Kajol Jain
@ 2022-01-27 7:19 ` Kajol Jain
2022-01-27 7:19 ` [PATCH 07/20] selftest/powerpc/pmu: Add macro to extract mmcr0/mmcr1 fields Kajol Jain
` (14 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:19 UTC (permalink / raw)
To: mpe; +Cc: atrajeev, rnsastry, kjain, maddy, Madhavan Srinivasan, linuxppc-dev
From: Madhavan Srinivasan <maddy@linux.ibm.com>
Generic macro (GET_MMCR_FIELD) added to extract specific fields of
a given MMCRx. Along with it, patch also adds macro and utility
functions to fetch individual fields from
Monitor Mode Control Register 2(MMCR2) register.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/misc.h | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 3cfe98716b1e..0f5446b56463 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -61,3 +61,73 @@ void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count);
int collect_samples(void *sample_buff);
u64 *get_intr_regs(struct event *event, void *sample_buff);
u64 get_reg_value(u64 *intr_regs, char *register_name);
+
+static inline int get_mmcr2_fcs(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (63 - (((pmc) - 1) * 9)))) >> (63 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fcp(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (62 - (((pmc) - 1) * 9)))) >> (62 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fcpc(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (61 - (((pmc) - 1) * 9)))) >> (61 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fcm1(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (60 - (((pmc) - 1) * 9)))) >> (60 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fcm0(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (59 - (((pmc) - 1) * 9)))) >> (59 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fcwait(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (58 - (((pmc) - 1) * 9)))) >> (58 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fch(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (57 - (((pmc) - 1) * 9)))) >> (57 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fcti(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (56 - (((pmc) - 1) * 9)))) >> (56 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_fcta(u64 mmcr2, int pmc)
+{
+ return ((mmcr2 & (1ull << (55 - (((pmc) - 1) * 9)))) >> (55 - (((pmc) - 1) * 9)));
+}
+
+static inline int get_mmcr2_l2l3(u64 mmcr2, int pmc)
+{
+ if (pvr == POWER10)
+ return ((mmcr2 & 0xf8) >> 3);
+ return 0;
+}
+
+#define GET_MMCR2(a, b, c) get_mmcr2_##c(a, b)
+
+/*
+ * Generic MMCR macro to get specific field value
+ * from a specific MMCR.
+ *
+ * Input:
+ * 'x' - MMCRx
+ * 'a' - u64
+ * 'b' - PMC#
+ * 'c' - Field#
+ *
+ * Output:
+ * u32
+ */
+#define GET_MMCR_FIELD(x, a, b, c) \
+ GET_MMCR##x(a, b, c)
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 07/20] selftest/powerpc/pmu: Add macro to extract mmcr0/mmcr1 fields
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (5 preceding siblings ...)
2022-01-27 7:19 ` [PATCH 06/20] selftest/powerpc/pmu: Add macros to extract mmcr fields Kajol Jain
@ 2022-01-27 7:19 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 08/20] selftest/powerpc/pmu: Add macro to extract mmcr3 and mmcra fields Kajol Jain
` (13 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:19 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Add macro and utility functions to fetch individual
fields from Monitor Mode Control Register 0(MMCR0) and
Monitor Mode Control Register 1(MMCR1) PMU register.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/misc.h | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 0f5446b56463..fea029506aa3 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -12,6 +12,10 @@
#define PERF_POWER9_MASK 0x7f8ffffffffffff
#define PERF_POWER10_MASK 0x7ffffffffffffff
+#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
+#define MMCR0_PMCCEXT 0x00000200UL /* PMCCEXT control */
+#define MMCR1_RSQ 0x200000000000ULL /* radix scope qual field */
+
extern int ev_mask_pmcxsel, ev_shift_pmcxsel;
extern int ev_mask_marked, ev_shift_marked;
extern int ev_mask_comb, ev_shift_comb;
@@ -62,6 +66,66 @@ int collect_samples(void *sample_buff);
u64 *get_intr_regs(struct event *event, void *sample_buff);
u64 get_reg_value(u64 *intr_regs, char *register_name);
+static inline int get_mmcr0_fc56(u64 mmcr0, int pmc)
+{
+ return (mmcr0 & MMCR0_FC56);
+}
+
+static inline int get_mmcr0_pmccext(u64 mmcr0, int pmc)
+{
+ return (mmcr0 & MMCR0_PMCCEXT);
+}
+
+static inline int get_mmcr0_pmao(u64 mmcr0, int pmc)
+{
+ return ((mmcr0 >> 7) & 0x1);
+}
+
+static inline int get_mmcr0_cc56run(u64 mmcr0, int pmc)
+{
+ return ((mmcr0 >> 8) & 0x1);
+}
+
+static inline int get_mmcr0_pmcjce(u64 mmcr0, int pmc)
+{
+ return ((mmcr0 >> 14) & 0x1);
+}
+
+static inline int get_mmcr0_pmc1ce(u64 mmcr0, int pmc)
+{
+ return ((mmcr0 >> 15) & 0x1);
+}
+
+static inline int get_mmcr0_pmae(u64 mmcr0, int pmc)
+{
+ return ((mmcr0 >> 27) & 0x1);
+}
+
+static inline int get_mmcr1_pmcxsel(u64 mmcr1, int pmc)
+{
+ return ((mmcr1 >> ((24 - (((pmc) - 1) * 8))) & 0xff));
+}
+
+static inline int get_mmcr1_unit(u64 mmcr1, int pmc)
+{
+ return ((mmcr1 >> ((60 - (4 * ((pmc) - 1))))) & 0xf);
+}
+
+static inline int get_mmcr1_comb(u64 mmcr1, int pmc)
+{
+ return ((mmcr1 >> (38 - ((pmc - 1) * 2))) & 0x3);
+}
+
+static inline int get_mmcr1_cache(u64 mmcr1, int pmc)
+{
+ return ((mmcr1 >> 46) & 0x3);
+}
+
+static inline int get_mmcr1_rsq(u64 mmcr1, int pmc)
+{
+ return mmcr1 & MMCR1_RSQ;
+}
+
static inline int get_mmcr2_fcs(u64 mmcr2, int pmc)
{
return ((mmcr2 & (1ull << (63 - (((pmc) - 1) * 9)))) >> (63 - (((pmc) - 1) * 9)));
@@ -114,6 +178,8 @@ static inline int get_mmcr2_l2l3(u64 mmcr2, int pmc)
return 0;
}
+#define GET_MMCR0(a, b, c) get_mmcr0_##c(a, b)
+#define GET_MMCR1(a, b, c) get_mmcr1_##c(a, b)
#define GET_MMCR2(a, b, c) get_mmcr2_##c(a, b)
/*
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 08/20] selftest/powerpc/pmu: Add macro to extract mmcr3 and mmcra fields
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (6 preceding siblings ...)
2022-01-27 7:19 ` [PATCH 07/20] selftest/powerpc/pmu: Add macro to extract mmcr0/mmcr1 fields Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 09/20] selftest/powerpc/pmu/: Add interface test for mmcr0 exception bits Kajol Jain
` (12 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
Add macro and utility functions to fetch individual
fields from Monitor Mode Control Register 3(MMCR3)and
Monitor Mode Control Register A(MMCRA) PMU registers
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/misc.h | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index fea029506aa3..b4995d4e6588 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -15,6 +15,7 @@
#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
#define MMCR0_PMCCEXT 0x00000200UL /* PMCCEXT control */
#define MMCR1_RSQ 0x200000000000ULL /* radix scope qual field */
+#define BHRB_DISABLE 0x2000000000ULL /* MMCRA BHRB DISABLE bit */
extern int ev_mask_pmcxsel, ev_shift_pmcxsel;
extern int ev_mask_marked, ev_shift_marked;
@@ -178,9 +179,72 @@ static inline int get_mmcr2_l2l3(u64 mmcr2, int pmc)
return 0;
}
+static inline int get_mmcr3_src(u64 mmcr3, int pmc)
+{
+ if (pvr != POWER10)
+ return 0;
+ return ((mmcr3 >> ((49 - (15 * ((pmc) - 1))))) & 0x7fff);
+}
+
+static inline int get_mmcra_thd_cmp(u64 mmcra, int pmc)
+{
+ if (pvr == POWER10)
+ return ((mmcra >> 45) & 0x7ff);
+ return ((mmcra >> 45) & 0x3ff);
+}
+
+static inline int get_mmcra_sm(u64 mmcra, int pmc)
+{
+ return ((mmcra >> 42) & 0x3);
+}
+
+static inline int get_mmcra_bhrb_disable(u64 mmcra, int pmc)
+{
+ if (pvr == POWER10)
+ return mmcra & BHRB_DISABLE;
+ return 0;
+}
+
+static inline int get_mmcra_ifm(u64 mmcra, int pmc)
+{
+ return ((mmcra >> 30) & 0x3);
+}
+
+static inline int get_mmcra_thd_sel(u64 mmcra, int pmc)
+{
+ return ((mmcra >> 16) & 0x7);
+}
+
+static inline int get_mmcra_thd_start(u64 mmcra, int pmc)
+{
+ return ((mmcra >> 12) & 0xf);
+}
+
+static inline int get_mmcra_thd_stop(u64 mmcra, int pmc)
+{
+ return ((mmcra >> 8) & 0xf);
+}
+
+static inline int get_mmcra_rand_samp_elig(u64 mmcra, int pmc)
+{
+ return ((mmcra >> 4) & 0x7);
+}
+
+static inline int get_mmcra_sample_mode(u64 mmcra, int pmc)
+{
+ return ((mmcra >> 1) & 0x3);
+}
+
+static inline int get_mmcra_marked(u64 mmcra, int pmc)
+{
+ return mmcra & 0x1;
+}
+
#define GET_MMCR0(a, b, c) get_mmcr0_##c(a, b)
#define GET_MMCR1(a, b, c) get_mmcr1_##c(a, b)
#define GET_MMCR2(a, b, c) get_mmcr2_##c(a, b)
+#define GET_MMCR3(a, b, c) get_mmcr3_##c(a, b)
+#define GET_MMCRA(a, b, c) get_mmcra_##c(a, b)
/*
* Generic MMCR macro to get specific field value
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 09/20] selftest/powerpc/pmu/: Add interface test for mmcr0 exception bits
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (7 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 08/20] selftest/powerpc/pmu: Add macro to extract mmcr3 and mmcra fields Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 10/20] selftest/powerpc/pmu/: Add interface test for mmcr0_cc56run field Kajol Jain
` (11 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses "instructions" event to verify two
bits(PMAE and PMAO) in Monitor Mode Control Register 0
(MMCR0). At the time of interrupt, pmae bit ( which enables
performance monitor exception ) is expected to be cleared
and pmao (which indicates performance monitor alert) bit
is expected to be set in MMCR0. And testcases handles
these checks.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 6 +-
.../sampling_tests/mmcr0_exceptionbits_test.c | 59 +++++++++++++++++++
2 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_exceptionbits_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index eb00c9f931ec..aee25c7037ac 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
include ../../../../../../scripts/Kbuild.include
-all: $(TEST_GEN_PROGS)
+all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c
noarg:
$(MAKE) -C ../../
@@ -12,9 +12,11 @@ CFLAGS += -m64 -I../../../../../lib/
no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
+TEST_GEN_PROGS := mmcr0_exceptionbits_test
+
LDFLAGS += $(no-pie-option)
top_srcdir = ../../../../../..
include ../../../lib.mk
-$(TEST_GEN_PROGS): ../../harness.c ../../utils.c ../event.c ../lib.c misc.c misc.h
+$(TEST_GEN_PROGS): ../../harness.c ../../utils.c ../event.c ../lib.c misc.c misc.h ../loop.S
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_exceptionbits_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_exceptionbits_test.c
new file mode 100644
index 000000000000..4de0b40264c9
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_exceptionbits_test.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/*
+ * A perf sampling test for mmcr0
+ * fields : pmae, pmao.
+ */
+static int mmcr0_exceptionbits(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, 0x500fa);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(10000);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that pmae is cleared and pmao is set in MMCR0 */
+ FAIL_IF(GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 5, pmae));
+ FAIL_IF(!GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 5, pmao));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr0_exceptionbits, "mmcr0_exceptionbits"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 10/20] selftest/powerpc/pmu/: Add interface test for mmcr0_cc56run field
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (8 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 09/20] selftest/powerpc/pmu/: Add interface test for mmcr0 exception bits Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 11/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmccext bit Kajol Jain
` (10 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses event code 0x500fa ("instructions") to check
the CC56RUN bit setting in Monitor Mode Control Register 0(MMCR0).
In ISA v3.1 platform, this bit is expected to be set in MMCR0
when using Performance Monitor Counter 5 and 6 (PMC5 and PMC6).
Verify this is done correctly by perf interface.
CC56RUN bit makes PMC5 and PMC6 count regardless
of the run latch state. This bit is set in power10
since PMC5 and PMC6 is used in power10 for counting
instructions and cycles. Hence added a check to skip
this test in other platforms
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../pmu/sampling_tests/mmcr0_cc56run_test.c | 59 +++++++++++++++++++
2 files changed, 61 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_cc56run_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index aee25c7037ac..9827bf20b90b 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
include ../../../../../../scripts/Kbuild.include
-all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c
+all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c
noarg:
$(MAKE) -C ../../
@@ -12,7 +12,7 @@ CFLAGS += -m64 -I../../../../../lib/
no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
-TEST_GEN_PROGS := mmcr0_exceptionbits_test
+TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_cc56run_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_cc56run_test.c
new file mode 100644
index 000000000000..da97676b56b2
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_cc56run_test.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/*
+ * A perf sampling test for mmcr0
+ * field: cc56run.
+ */
+static int mmcr0_cc56run(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, 0x500fa);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(10000);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that cc56run bit is set in MMCR0 */
+ FAIL_IF(!GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 5, cc56run));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr0_cc56run, "mmcr0_cc56run"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 11/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmccext bit
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (9 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 10/20] selftest/powerpc/pmu/: Add interface test for mmcr0_cc56run field Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 12/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmcjce field Kajol Jain
` (9 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses cycles event to check the PMCCEXT
bit setting in Monitor Mode Control Register 0 (MMCR0).
Check if perf interface sets this control bit in MMCR0
on ISA v3.1 platform.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../pmu/sampling_tests/mmcr0_pmccext_test.c | 59 +++++++++++++++++++
2 files changed, 61 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmccext_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 9827bf20b90b..111ecfae5dbe 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
include ../../../../../../scripts/Kbuild.include
-all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c
+all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c
noarg:
$(MAKE) -C ../../
@@ -12,7 +12,7 @@ CFLAGS += -m64 -I../../../../../lib/
no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
-TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
+TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmccext_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmccext_test.c
new file mode 100644
index 000000000000..c4e6f290d12a
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmccext_test.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/*
+ * A perf sampling test for mmcr0
+ * field: pmccext
+ */
+static int mmcr0_pmccext(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, 0x4001e);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(10000);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that pmccext field is set in MMCR0 */
+ FAIL_IF(!GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 4, pmccext));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr0_pmccext, "mmcr0_pmccext"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 12/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmcjce field
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (10 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 11/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmccext bit Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 13/20] selftest/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1 Kajol Jain
` (8 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses event code 0x500fa ("instructions") to verify
the PMCjCE bit setting in Monitor Mode Control Register 0 (MMCR0).
This bit is expected to be set in MMCR0 when using Performance
Monitor Counter 5 (PMC5). Checks if perf interface sets this
bit correctly.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 6 +-
.../pmu/sampling_tests/mmcr0_pmcjce_test.c | 58 +++++++++++++++++++
2 files changed, 62 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmcjce_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 111ecfae5dbe..4ff9031abfb5 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
include ../../../../../../scripts/Kbuild.include
-all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c
+all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
+ mmcr0_pmcjce_test.c
noarg:
$(MAKE) -C ../../
@@ -12,7 +13,8 @@ CFLAGS += -m64 -I../../../../../lib/
no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
-TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test
+TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
+ mmcr0_pmcjce_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmcjce_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmcjce_test.c
new file mode 100644
index 000000000000..f453510ab592
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_pmcjce_test.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/*
+ * A perf sampling test for mmcr0
+ * field: pmcjce
+ */
+static int mmcr0_pmcjce(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, 0x500fa);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(10000);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that pmcjce field is set in MMCR0 */
+ FAIL_IF(!GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 5, pmcjce));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr0_pmcjce, "mmcr0_pmcjce"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 13/20] selftest/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (11 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 12/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmcjce field Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 14/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5 Kajol Jain
` (7 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses event code 0x1001e to verify two bit settings
(FC5-6 and PMC1CE) in Monitor Mode Control Register 0 (MMCR0).
Check if FC5-6 bit to be set in MMCR0 when not using Performance
Monitor Counter 5 and 6 (PMC5 and PMC6). And also PMC1CE is
expected to be set when using PMC1. Test if these fields are
programmed correctly via perf interface.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../sampling_tests/mmcr0_fc56_pmc1ce_test.c | 58 +++++++++++++++++++
2 files changed, 60 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc1ce_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 4ff9031abfb5..b82e63dfed26 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -2,7 +2,7 @@
include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
- mmcr0_pmcjce_test.c
+ mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c
noarg:
$(MAKE) -C ../../
@@ -14,7 +14,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
- mmcr0_pmcjce_test
+ mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc1ce_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc1ce_test.c
new file mode 100644
index 000000000000..d62ef3d881e5
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc1ce_test.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/*
+ * A perf sampling test for mmcr0
+ * fields: fc56, pmc1ce.
+ */
+static int mmcr0_fc56_pmc1ce(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, 0x1001e);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(10000);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that fc56, pmc1ce fields are set in MMCR0 */
+ FAIL_IF(!GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 1, fc56));
+ FAIL_IF(!GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 1, pmc1ce));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr0_fc56_pmc1ce, "mmcr0_fc56_pmc1ce"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 14/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (12 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 13/20] selftest/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1 Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 15/20] selftest/powerpc/pmu/: Add interface test for mmcr1_comb field Kajol Jain
` (6 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses event code 0x500fa to verify the
FC5-6 bit setting in Monitor Mode Control Register 0 (MMCR0).
Check if FC5-6 bit is not set in MMCR0 when using Performance
Monitor Counter 5 and 6 (PMC5 and PMC6).
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../sampling_tests/mmcr0_fc56_pmc56_test.c | 58 +++++++++++++++++++
2 files changed, 60 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc56_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index b82e63dfed26..d27d5084a3ce 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -2,7 +2,7 @@
include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
- mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c
+ mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c
noarg:
$(MAKE) -C ../../
@@ -14,7 +14,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
- mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test
+ mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc56_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc56_test.c
new file mode 100644
index 000000000000..2c824a67e975
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr0_fc56_pmc56_test.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/*
+ * A perf sampling test for mmcr0
+ * fields: fc56_pmc56
+ */
+static int mmcr0_fc56_pmc56(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, 0x500fa);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(10000);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that fc56 is not set in MMCR0 when using PMC5 */
+ FAIL_IF(GET_MMCR_FIELD(0, get_reg_value(intr_regs, "MMCR0"), 5, fc56));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr0_fc56_pmc56, "mmcr0_fc56_pmc56"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 15/20] selftest/powerpc/pmu/: Add interface test for mmcr1_comb field
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (13 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 14/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5 Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields Kajol Jain
` (5 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses event code "0x26880" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The field include PMCxCOMB.
Checks if this field are translated correctly via perf
interface to MMCR1
Add selftest for mmcr1 comb field.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 6 +-
.../pmu/sampling_tests/mmcr1_comb_test.c | 66 +++++++++++++++++++
2 files changed, 70 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_comb_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index d27d5084a3ce..bb5ffd2e322d 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -2,7 +2,8 @@
include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
- mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c
+ mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
+ mmcr1_comb_test.c
noarg:
$(MAKE) -C ../../
@@ -14,7 +15,8 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
- mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test
+ mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
+ mmcr1_comb_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_comb_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_comb_test.c
new file mode 100644
index 000000000000..0f183c2f074d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_comb_test.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/* All successful D-side store dispatches for this thread that were L2 Miss */
+#define EventCode 0x46880
+
+extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target);
+
+/*
+ * A perf sampling test for mmcr1
+ * fields : comb.
+ */
+static int mmcr1_comb(void)
+{
+ struct event event;
+ u64 *intr_regs;
+ u64 dummy;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop_with_ll_sc(10000000, &dummy);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /*
+ * Verify that comb field match with
+ * corresponding event code fields
+ */
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, comb) != GET_MMCR_FIELD(1,
+ get_reg_value(intr_regs, "MMCR1"), 4, comb));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr1_comb, "mmcr1_comb"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (14 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 15/20] selftest/powerpc/pmu/: Add interface test for mmcr1_comb field Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-03-10 7:49 ` Christophe Leroy
2022-01-27 7:20 ` [PATCH 17/20] selftest/powerpc/pmu/: Add interface test for mmcr2_l2l3 field Kajol Jain
` (4 subsequent siblings)
20 siblings, 1 reply; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
The testcase uses event code "0x1340000001c040" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
PMCxUNIT, cache. Checks if these fields are translated
correctly via perf interface to MMCR1
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../mmcr1_sel_unit_cache_test.c | 70 +++++++++++++++++++
2 files changed, 72 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index bb5ffd2e322d..345ad66bd1b2 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -3,7 +3,7 @@ include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
- mmcr1_comb_test.c
+ mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c
noarg:
$(MAKE) -C ../../
@@ -16,7 +16,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
- mmcr1_comb_test
+ mmcr1_comb_test mmcr1_sel_unit_cache_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
new file mode 100644
index 000000000000..1a4d19c11017
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target);
+
+/* The data cache was reloaded from local core's L3 due to a demand load */
+#define EventCode 0x21c040
+
+/*
+ * A perf sampling test for mmcr1
+ * fields : pmcxsel, unit, cache.
+ */
+static int mmcr1_sel_unit_cache(void)
+{
+ struct event event;
+ u64 *intr_regs;
+ u64 dummy;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop_with_ll_sc(10000000, &dummy);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /*
+ * Verify that pmcxsel, unit and cache field of MMCR1
+ * match with corresponding event code fields
+ */
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, pmcxsel) !=
+ GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, pmcxsel));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, unit) !=
+ GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, unit));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, cache) !=
+ GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, cache));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr1_sel_unit_cache, "mmcr1_sel_unit_cache"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields
2022-01-27 7:20 ` [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields Kajol Jain
@ 2022-03-10 7:49 ` Christophe Leroy
2022-03-10 12:11 ` Michael Ellerman
0 siblings, 1 reply; 25+ messages in thread
From: Christophe Leroy @ 2022-03-10 7:49 UTC (permalink / raw)
To: Kajol Jain, mpe; +Cc: linuxppc-dev, atrajeev, maddy, rnsastry
Le 27/01/2022 à 08:20, Kajol Jain a écrit :
> From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>
> The testcase uses event code "0x1340000001c040" to verify
> the settings for different fields in Monitor Mode Control
> Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
> PMCxUNIT, cache. Checks if these fields are translated
> correctly via perf interface to MMCR1
>
> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
I see the series has been accepted but this patch has been left over.
Any reason ?
Thanks
Christophe
> ---
> .../powerpc/pmu/sampling_tests/Makefile | 4 +-
> .../mmcr1_sel_unit_cache_test.c | 70 +++++++++++++++++++
> 2 files changed, 72 insertions(+), 2 deletions(-)
> create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
>
> diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
> index bb5ffd2e322d..345ad66bd1b2 100644
> --- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
> +++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
> @@ -3,7 +3,7 @@ include ../../../../../../scripts/Kbuild.include
>
> all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
> mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
> - mmcr1_comb_test.c
> + mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c
>
> noarg:
> $(MAKE) -C ../../
> @@ -16,7 +16,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
>
> TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
> mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
> - mmcr1_comb_test
> + mmcr1_comb_test mmcr1_sel_unit_cache_test
>
> LDFLAGS += $(no-pie-option)
>
> diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
> new file mode 100644
> index 000000000000..1a4d19c11017
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2022, Athira Rajeev, IBM Corp.
> + */
> +
> +#include <stdio.h>
> +#include <stdlib.h>
> +
> +#include "../event.h"
> +#include "misc.h"
> +#include "utils.h"
> +
> +extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target);
> +
> +/* The data cache was reloaded from local core's L3 due to a demand load */
> +#define EventCode 0x21c040
> +
> +/*
> + * A perf sampling test for mmcr1
> + * fields : pmcxsel, unit, cache.
> + */
> +static int mmcr1_sel_unit_cache(void)
> +{
> + struct event event;
> + u64 *intr_regs;
> + u64 dummy;
> +
> + /* Check for platform support for the test */
> + SKIP_IF(check_pvr_for_sampling_tests());
> +
> + /* Init the event for the sampling test */
> + event_init_sampling(&event, EventCode);
> + event.attr.sample_regs_intr = platform_extended_mask;
> + FAIL_IF(event_open(&event));
> + event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
> +
> + event_enable(&event);
> +
> + /* workload to make the event overflow */
> + thirty_two_instruction_loop_with_ll_sc(10000000, &dummy);
> +
> + event_disable(&event);
> +
> + /* Check for sample count */
> + FAIL_IF(!collect_samples(event.mmap_buffer));
> +
> + intr_regs = get_intr_regs(&event, event.mmap_buffer);
> +
> + /* Check for intr_regs */
> + FAIL_IF(!intr_regs);
> +
> + /*
> + * Verify that pmcxsel, unit and cache field of MMCR1
> + * match with corresponding event code fields
> + */
> + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, pmcxsel) !=
> + GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, pmcxsel));
> + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, unit) !=
> + GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, unit));
> + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, cache) !=
> + GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, cache));
> +
> + event_close(&event);
> + return 0;
> +}
> +
> +int main(void)
> +{
> + FAIL_IF(test_harness(mmcr1_sel_unit_cache, "mmcr1_sel_unit_cache"));
> +}
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields
2022-03-10 7:49 ` Christophe Leroy
@ 2022-03-10 12:11 ` Michael Ellerman
2022-03-10 12:29 ` kajoljain
0 siblings, 1 reply; 25+ messages in thread
From: Michael Ellerman @ 2022-03-10 12:11 UTC (permalink / raw)
To: Christophe Leroy, Kajol Jain; +Cc: linuxppc-dev, atrajeev, maddy, rnsastry
Christophe Leroy <christophe.leroy@csgroup.eu> writes:
> Le 27/01/2022 à 08:20, Kajol Jain a écrit :
>> From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>>
>> The testcase uses event code "0x1340000001c040" to verify
>> the settings for different fields in Monitor Mode Control
>> Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
>> PMCxUNIT, cache. Checks if these fields are translated
>> correctly via perf interface to MMCR1
>>
>> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>
> I see the series has been accepted but this patch has been left over.
>
> Any reason ?
Yeah it's flakey. It counts cache loads but the workload it runs doesn't
necessarily cause any, so it sometimes fails. I've reported that
privately to Kajol.
cheers
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields
2022-03-10 12:11 ` Michael Ellerman
@ 2022-03-10 12:29 ` kajoljain
0 siblings, 0 replies; 25+ messages in thread
From: kajoljain @ 2022-03-10 12:29 UTC (permalink / raw)
To: Michael Ellerman, Christophe Leroy
Cc: linuxppc-dev, atrajeev, maddy, rnsastry
On 3/10/22 17:41, Michael Ellerman wrote:
> Christophe Leroy <christophe.leroy@csgroup.eu> writes:
>> Le 27/01/2022 à 08:20, Kajol Jain a écrit :
>>> From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>>>
>>> The testcase uses event code "0x1340000001c040" to verify
>>> the settings for different fields in Monitor Mode Control
>>> Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
>>> PMCxUNIT, cache. Checks if these fields are translated
>>> correctly via perf interface to MMCR1
>>>
>>> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>>
>> I see the series has been accepted but this patch has been left over.
>>
>> Any reason ?
>
> Yeah it's flakey. It counts cache loads but the workload it runs doesn't
> necessarily cause any, so it sometimes fails. I've reported that
> privately to Kajol.
>
Hi Christophe,
As Michael mentioned, with the current workload we used in this
patch, the testcase was failing sometimes as required cache load not
happening everytime. We will send this patch separately with proper
workload in next version.
Thanks,
Kajol Jain
> cheers
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 17/20] selftest/powerpc/pmu/: Add interface test for mmcr2_l2l3 field
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (15 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 18/20] selftest/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fields Kajol Jain
` (3 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: atrajeev, rnsastry, kjain, maddy, Madhavan Srinivasan, linuxppc-dev
From: Madhavan Srinivasan <maddy@linux.ibm.com>
The testcases uses event code 0x010000046080 to verify
the l2l3 bit setting for Monitor Mode Control Register 2
(MMCR2). check if this bit is set correctly via perf interface
in ISA v3.1 platform.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../pmu/sampling_tests/mmcr2_l2l3_test.c | 74 +++++++++++++++++++
2 files changed, 76 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_l2l3_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 345ad66bd1b2..f01666d7f2e0 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -3,7 +3,7 @@ include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
- mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c
+ mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c mmcr2_l2l3_test.c
noarg:
$(MAKE) -C ../../
@@ -16,7 +16,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
- mmcr1_comb_test mmcr1_sel_unit_cache_test
+ mmcr1_comb_test mmcr1_sel_unit_cache_test mmcr2_l2l3_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_l2l3_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_l2l3_test.c
new file mode 100644
index 000000000000..7167e2217ba8
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_l2l3_test.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Madhavan Srinivasan, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/* All successful D-side store dispatches for this thread */
+#define EventCode 0x010000046080
+
+#define MALLOC_SIZE (0x10000 * 10) /* Ought to be enough .. */
+
+/*
+ * A perf sampling test for mmcr2
+ * fields : l2l3
+ */
+static int mmcr2_l2l3(void)
+{
+ struct event event;
+ u64 *intr_regs;
+ char *p;
+ int i;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ p = malloc(MALLOC_SIZE);
+ FAIL_IF(!p);
+
+ for (i = 0; i < MALLOC_SIZE; i += 0x10000)
+ p[i] = i;
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /*
+ * Verify that l2l3 field of MMCR2 match with
+ * corresponding event code field
+ */
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, l2l3) !=
+ GET_MMCR_FIELD(2, get_reg_value(intr_regs, "MMCR2"), 4, l2l3));
+
+ event_close(&event);
+ free(p);
+
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr2_l2l3, "mmcr2_l2l3"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 18/20] selftest/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fields
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (16 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 17/20] selftest/powerpc/pmu/: Add interface test for mmcr2_l2l3 field Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 19/20] selftest/powerpc/pmu/: Add interface test for mmcr3_src fields Kajol Jain
` (2 subsequent siblings)
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: atrajeev, rnsastry, kjain, maddy, Madhavan Srinivasan, linuxppc-dev
From: Madhavan Srinivasan <maddy@linux.ibm.com>
The testcases uses cycles event to verify the freeze counter
settings in Monitor Mode Control Register 2 (MMCR2). Event
modifier (exclude_kernel) setting is used for the event attribute
to check the FCxS and FCxH ( Freeze counter in privileged and
hypervisor state ) settings via perf interface.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 6 +-
.../pmu/sampling_tests/mmcr2_fcs_fch_test.c | 67 +++++++++++++++++++
2 files changed, 71 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_fcs_fch_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index f01666d7f2e0..1deaab5a4ebf 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -3,7 +3,8 @@ include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
- mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c mmcr2_l2l3_test.c
+ mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c mmcr2_l2l3_test.c \
+ mmcr2_fcs_fch_test.c
noarg:
$(MAKE) -C ../../
@@ -16,7 +17,8 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
- mmcr1_comb_test mmcr1_sel_unit_cache_test mmcr2_l2l3_test
+ mmcr1_comb_test mmcr1_sel_unit_cache_test mmcr2_l2l3_test \
+ mmcr2_fcs_fch_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_fcs_fch_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_fcs_fch_test.c
new file mode 100644
index 000000000000..1c1c48ca7d4c
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_fcs_fch_test.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Madhavan Srinivasan, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/*
+ * A perf sampling test for mmcr2
+ * fields : fcs, fch.
+ */
+static int mmcr2_fcs_fch(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, 0x1001e);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ event.attr.exclude_kernel = 1;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(10000);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /*
+ * Verify that fcs and fch field of MMCR2 match
+ * with corresponding modifier fields.
+ */
+ if (is_pSeries())
+ FAIL_IF(GET_ATTR_FIELD(&event, exclude_kernel) !=
+ GET_MMCR_FIELD(2, get_reg_value(intr_regs, "MMCR2"), 1, fcs));
+ else
+ FAIL_IF(GET_ATTR_FIELD(&event, exclude_kernel) !=
+ GET_MMCR_FIELD(2, get_reg_value(intr_regs, "MMCR2"), 1, fch));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr2_fcs_fch, "mmcr2_fcs_fch"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 19/20] selftest/powerpc/pmu/: Add interface test for mmcr3_src fields
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (17 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 18/20] selftest/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fields Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-01-27 7:20 ` [PATCH 20/20] selftest/powerpc/pmu: Add interface test for mmcra register fields Kajol Jain
2022-03-02 12:41 ` [PATCH 00/20] Add perf sampling tests as part of selftest Michael Ellerman
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
The testcase uses event code 0x1340000001c040 to verify
the settings for different src fields in Monitor Mode Control
Register 3 (MMCR3). Checks if these fields are translated
correctly via perf interface to MMCR3 on ISA v3.1 platform.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../pmu/sampling_tests/mmcr3_src_test.c | 67 +++++++++++++++++++
2 files changed, 69 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr3_src_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 1deaab5a4ebf..58d3ddf779d2 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -4,7 +4,7 @@ include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c mmcr2_l2l3_test.c \
- mmcr2_fcs_fch_test.c
+ mmcr2_fcs_fch_test.c mmcr3_src_test.c
noarg:
$(MAKE) -C ../../
@@ -18,7 +18,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
mmcr1_comb_test mmcr1_sel_unit_cache_test mmcr2_l2l3_test \
- mmcr2_fcs_fch_test
+ mmcr2_fcs_fch_test mmcr3_src_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr3_src_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr3_src_test.c
new file mode 100644
index 000000000000..d8d6ee0bb696
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr3_src_test.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target);
+
+/* The data cache was reloaded from local core's L3 due to a demand load */
+#define EventCode 0x1340000001c040
+
+/*
+ * A perf sampling test for mmcr3
+ * fields.
+ */
+static int mmcr3_src(void)
+{
+ struct event event;
+ u64 *intr_regs;
+ u64 dummy;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make event overflow */
+ thirty_two_instruction_loop_with_ll_sc(1000000, &dummy);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /*
+ * Verify that src field of MMCR3 match with
+ * corresponding event code field
+ */
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, mmcr3_src) !=
+ GET_MMCR_FIELD(3, get_reg_value(intr_regs, "MMCR3"), 1, src));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(mmcr3_src, "mmcr3_src");
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 20/20] selftest/powerpc/pmu: Add interface test for mmcra register fields
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (18 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 19/20] selftest/powerpc/pmu/: Add interface test for mmcr3_src fields Kajol Jain
@ 2022-01-27 7:20 ` Kajol Jain
2022-03-02 12:41 ` [PATCH 00/20] Add perf sampling tests as part of selftest Michael Ellerman
20 siblings, 0 replies; 25+ messages in thread
From: Kajol Jain @ 2022-01-27 7:20 UTC (permalink / raw)
To: mpe; +Cc: kjain, atrajeev, maddy, linuxppc-dev, rnsastry
The testcase uses event code 0x35340401e0 to verify
the settings for different fields in Monitor Mode Control
Register A (MMCRA). The fields include thresh_start, thresh_stop
thresh_select, sdar mode, sample and marked bit. Checks if
these fields are translated correctly via perf interface to MMCRA.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
.../mmcra_thresh_marked_sample_test.c | 80 +++++++++++++++++++
2 files changed, 82 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 58d3ddf779d2..a9bf343df911 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -4,7 +4,7 @@ include ../../../../../../scripts/Kbuild.include
all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c mmcr2_l2l3_test.c \
- mmcr2_fcs_fch_test.c mmcr3_src_test.c
+ mmcr2_fcs_fch_test.c mmcr3_src_test.c mmcra_thresh_marked_sample_test.c
noarg:
$(MAKE) -C ../../
@@ -18,7 +18,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
mmcr1_comb_test mmcr1_sel_unit_cache_test mmcr2_l2l3_test \
- mmcr2_fcs_fch_test mmcr3_src_test
+ mmcr2_fcs_fch_test mmcr3_src_test mmcra_thresh_marked_sample_test
LDFLAGS += $(no-pie-option)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c
new file mode 100644
index 000000000000..ca6bdb335fa5
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/*
+ * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
+ * Threshold event selection used is issue to complete for cycles
+ * Sampling criteria is Load only sampling
+ */
+#define EventCode 0x35340401e0
+
+extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target);
+
+/* A perf sampling test to test mmcra fields */
+static int mmcra_thresh_marked_sample(void)
+{
+ struct event event;
+ u64 *intr_regs;
+ u64 dummy;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Init the event for the sampling test */
+ event_init_sampling(&event, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open(&event));
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable(&event);
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop_with_ll_sc(1000000, &dummy);
+
+ event_disable(&event);
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /*
+ * Verify that thresh sel/start/stop, marked, random sample
+ * eligibility, sdar mode and sample mode fields match with
+ * the corresponding event code fields
+ */
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_sel) !=
+ GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, thd_sel));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_start) !=
+ GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, thd_start));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_stop) !=
+ GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, thd_stop));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, marked) !=
+ GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, marked));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample >> 2) !=
+ GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, rand_samp_elig));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample & 0x3) !=
+ GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, sample_mode));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sm) !=
+ GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, sm));
+
+ event_close(&event);
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcra_thresh_marked_sample, "mmcra_thresh_marked_sample"));
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 00/20] Add perf sampling tests as part of selftest
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
` (19 preceding siblings ...)
2022-01-27 7:20 ` [PATCH 20/20] selftest/powerpc/pmu: Add interface test for mmcra register fields Kajol Jain
@ 2022-03-02 12:41 ` Michael Ellerman
20 siblings, 0 replies; 25+ messages in thread
From: Michael Ellerman @ 2022-03-02 12:41 UTC (permalink / raw)
To: mpe, Kajol Jain; +Cc: atrajeev, linuxppc-dev, rnsastry, maddy
On Thu, 27 Jan 2022 12:49:52 +0530, Kajol Jain wrote:
> Patch series adds support for perf sampling tests that
> enables capturing sampling data in perf mmap buffer and
> further support for reading and processing the samples.
> It also addds basic utility functions to process the
> mmap buffer inorder to read total count of samples as
> well as the contents of sample.
>
> [...]
Patches 1-15 and 17-20 applied to powerpc/next.
[01/20] selftest/powerpc/pmu: Include mmap_buffer field as part of struct event
https://git.kernel.org/powerpc/c/f961e20f15ed35e9ca154a099897d600b78b0311
[02/20] selftest/powerpc/pmu: Add support for perf sampling tests
https://git.kernel.org/powerpc/c/c315669e2fbd71bb9387066f60f0d91b0ceb28f3
[03/20] selftest/powerpc/pmu: Add macros to parse event codes
https://git.kernel.org/powerpc/c/6523dce86222451e5ca2df8a46597a217084bfdf
[04/20] selftest/powerpc/pmu: Add utility functions to post process the mmap buffer
https://git.kernel.org/powerpc/c/5f6c3061af7ca3b0f9f8a20ec7a445671f7e6b5a
[05/20] selftest/powerpc/pmu: Add event_init_sampling function
https://git.kernel.org/powerpc/c/54d4ba7f22d1ed5bfbc915771cf2e3e147cf03b2
[06/20] selftest/powerpc/pmu: Add macros to extract mmcr fields
https://git.kernel.org/powerpc/c/79c4e6aba8dfc9206acc68884498080f451121f7
[07/20] selftest/powerpc/pmu: Add macro to extract mmcr0/mmcr1 fields
https://git.kernel.org/powerpc/c/2b49e641063e7569493371ef433b9c4ce8c8dd8b
[08/20] selftest/powerpc/pmu: Add macro to extract mmcr3 and mmcra fields
https://git.kernel.org/powerpc/c/13307f9584ea9408d9959302074dc4e8308b6cab
[09/20] selftest/powerpc/pmu/: Add interface test for mmcr0 exception bits
https://git.kernel.org/powerpc/c/eb7aa044df18c6f7a88bc17fc4c9f4524652a290
[10/20] selftest/powerpc/pmu/: Add interface test for mmcr0_cc56run field
https://git.kernel.org/powerpc/c/a7c0ab2e61484c0844eae2f208a06cc940338d83
[11/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmccext bit
https://git.kernel.org/powerpc/c/b24142b9d2401468bcd8df157013306d5b4f6626
[12/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmcjce field
https://git.kernel.org/powerpc/c/9ac7c6d5e4b570f416d849b263a6f67a617b4fa5
[13/20] selftest/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1
https://git.kernel.org/powerpc/c/d5172f2585cd0fc9788aa9b25d3dce6483321792
[14/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5
https://git.kernel.org/powerpc/c/6e11374b08723b2c43ae83bd5d48000d695f13a0
[15/20] selftest/powerpc/pmu/: Add interface test for mmcr1_comb field
https://git.kernel.org/powerpc/c/2becea3b6acf308642d6c0e9bd41caf7820753f5
[17/20] selftest/powerpc/pmu/: Add interface test for mmcr2_l2l3 field
https://git.kernel.org/powerpc/c/ac575b2606bf99a0d01a054196e24e1ad82c194d
[18/20] selftest/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fields
https://git.kernel.org/powerpc/c/9ee241f1b1447c7e8ca90902ab1888aa9e7a3c00
[19/20] selftest/powerpc/pmu/: Add interface test for mmcr3_src fields
https://git.kernel.org/powerpc/c/02f02feb6b50c67171fd56bc3fd0fd96118c5c12
[20/20] selftest/powerpc/pmu: Add interface test for mmcra register fields
https://git.kernel.org/powerpc/c/29cf373c5766e6bd1b97056d2d678a41777669aa
cheers
^ permalink raw reply [flat|nested] 25+ messages in thread