* [PATCH 1/4] powerpc: book3e: _PAGE_LENDIAN must be _PAGE_ENDIAN
@ 2013-07-26 5:46 Bharat Bhushan
2013-07-26 5:46 ` [PATCH 2/4] kvm: powerpc: allow guest control "E" attribute in mas2 Bharat Bhushan
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Bharat Bhushan @ 2013-07-26 5:46 UTC (permalink / raw)
To: kvm-ppc, kvm, linuxppc-dev, agraf, benh, scottwood; +Cc: Bharat Bhushan
For booke3e _PAGE_ENDIAN is not defined. Infact what is defined
is "_PAGE_LENDIAN" which is wrong and that should be _PAGE_ENDIAN.
There are no compilation errors as
arch/powerpc/include/asm/pte-common.h defines _PAGE_ENDIAN to 0
as it is not defined anywhere.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/include/asm/pte-book3e.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/pte-book3e.h b/arch/powerpc/include/asm/pte-book3e.h
index 0156702..576ad88 100644
--- a/arch/powerpc/include/asm/pte-book3e.h
+++ b/arch/powerpc/include/asm/pte-book3e.h
@@ -40,7 +40,7 @@
#define _PAGE_U1 0x010000
#define _PAGE_U0 0x020000
#define _PAGE_ACCESSED 0x040000
-#define _PAGE_LENDIAN 0x080000
+#define _PAGE_ENDIAN 0x080000
#define _PAGE_GUARDED 0x100000
#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/4] kvm: powerpc: allow guest control "E" attribute in mas2
2013-07-26 5:46 [PATCH 1/4] powerpc: book3e: _PAGE_LENDIAN must be _PAGE_ENDIAN Bharat Bhushan
@ 2013-07-26 5:46 ` Bharat Bhushan
2013-07-26 5:46 ` [PATCH 3/4] kvm: powerpc: allow guest control "G" " Bharat Bhushan
2013-07-26 5:46 ` [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages Bharat Bhushan
2 siblings, 0 replies; 13+ messages in thread
From: Bharat Bhushan @ 2013-07-26 5:46 UTC (permalink / raw)
To: kvm-ppc, kvm, linuxppc-dev, agraf, benh, scottwood; +Cc: Bharat Bhushan
"E" bit in MAS2 bit indicates whether the page is accessed
in Little-Endian or Big-Endian byte order.
There is no reason to stop guest setting "E", so allow him."
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/kvm/e500.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index c2e5e98..277cb18 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -117,7 +117,7 @@ static inline struct kvmppc_vcpu_e500 *to_e500(struct kvm_vcpu *vcpu)
#define E500_TLB_USER_PERM_MASK (MAS3_UX|MAS3_UR|MAS3_UW)
#define E500_TLB_SUPER_PERM_MASK (MAS3_SX|MAS3_SR|MAS3_SW)
#define MAS2_ATTRIB_MASK \
- (MAS2_X0 | MAS2_X1)
+ (MAS2_X0 | MAS2_X1 | MAS2_E)
#define MAS3_ATTRIB_MASK \
(MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3 \
| E500_TLB_USER_PERM_MASK | E500_TLB_SUPER_PERM_MASK)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/4] kvm: powerpc: allow guest control "G" attribute in mas2
2013-07-26 5:46 [PATCH 1/4] powerpc: book3e: _PAGE_LENDIAN must be _PAGE_ENDIAN Bharat Bhushan
2013-07-26 5:46 ` [PATCH 2/4] kvm: powerpc: allow guest control "E" attribute in mas2 Bharat Bhushan
@ 2013-07-26 5:46 ` Bharat Bhushan
2013-07-26 5:46 ` [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages Bharat Bhushan
2 siblings, 0 replies; 13+ messages in thread
From: Bharat Bhushan @ 2013-07-26 5:46 UTC (permalink / raw)
To: kvm-ppc, kvm, linuxppc-dev, agraf, benh, scottwood; +Cc: Bharat Bhushan
"G" bit in MAS2 indicates whether the page is Guarded.
There is no reason to stop guest setting "G", so allow him.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/kvm/e500.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index 277cb18..4fd9650 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -117,7 +117,7 @@ static inline struct kvmppc_vcpu_e500 *to_e500(struct kvm_vcpu *vcpu)
#define E500_TLB_USER_PERM_MASK (MAS3_UX|MAS3_UR|MAS3_UW)
#define E500_TLB_SUPER_PERM_MASK (MAS3_SX|MAS3_SR|MAS3_SW)
#define MAS2_ATTRIB_MASK \
- (MAS2_X0 | MAS2_X1 | MAS2_E)
+ (MAS2_X0 | MAS2_X1 | MAS2_E | MAS2_G)
#define MAS3_ATTRIB_MASK \
(MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3 \
| E500_TLB_USER_PERM_MASK | E500_TLB_SUPER_PERM_MASK)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 5:46 [PATCH 1/4] powerpc: book3e: _PAGE_LENDIAN must be _PAGE_ENDIAN Bharat Bhushan
2013-07-26 5:46 ` [PATCH 2/4] kvm: powerpc: allow guest control "E" attribute in mas2 Bharat Bhushan
2013-07-26 5:46 ` [PATCH 3/4] kvm: powerpc: allow guest control "G" " Bharat Bhushan
@ 2013-07-26 5:46 ` Bharat Bhushan
2013-07-26 8:26 ` Benjamin Herrenschmidt
2 siblings, 1 reply; 13+ messages in thread
From: Bharat Bhushan @ 2013-07-26 5:46 UTC (permalink / raw)
To: kvm-ppc, kvm, linuxppc-dev, agraf, benh, scottwood; +Cc: Bharat Bhushan
If the page is RAM then map this as cacheable and coherent (set "M" bit)
otherwise this page is treated as I/O and map this as cache inhibited
and guarded (set "I + G")
This helps setting proper MMU mapping for direct assigned device.
NOTE: There can be devices that require cacheable mapping, which is not yet supported.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/kvm/e500_mmu_host.c | 24 +++++++++++++++++++-----
1 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
index 1c6a9d7..5cbdc8f 100644
--- a/arch/powerpc/kvm/e500_mmu_host.c
+++ b/arch/powerpc/kvm/e500_mmu_host.c
@@ -64,13 +64,27 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode)
return mas3;
}
-static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode)
+static inline u32 e500_shadow_mas2_attrib(u32 mas2, pfn_t pfn)
{
+ u32 mas2_attr;
+
+ mas2_attr = mas2 & MAS2_ATTRIB_MASK;
+
+ if (kvm_is_mmio_pfn(pfn)) {
+ /*
+ * If page is not RAM then it is treated as I/O page.
+ * Map it with cache inhibited and guarded (set "I" + "G").
+ */
+ mas2_attr |= MAS2_I | MAS2_G;
+ return mas2_attr;
+ }
+
+ /* Map RAM pages as cacheable (Not setting "I" in MAS2) */
#ifdef CONFIG_SMP
- return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M;
-#else
- return mas2 & MAS2_ATTRIB_MASK;
+ /* Also map as coherent (set "M") in SMP */
+ mas2_attr |= MAS2_M;
#endif
+ return mas2_attr;
}
/*
@@ -313,7 +327,7 @@ static void kvmppc_e500_setup_stlbe(
/* Force IPROT=0 for all guest mappings. */
stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID;
stlbe->mas2 = (gvaddr & MAS2_EPN) |
- e500_shadow_mas2_attrib(gtlbe->mas2, pr);
+ e500_shadow_mas2_attrib(gtlbe->mas2, pfn);
stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) |
e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 5:46 ` [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages Bharat Bhushan
@ 2013-07-26 8:26 ` Benjamin Herrenschmidt
2013-07-26 8:50 ` Alexander Graf
2013-07-26 8:51 ` Bhushan Bharat-R65777
0 siblings, 2 replies; 13+ messages in thread
From: Benjamin Herrenschmidt @ 2013-07-26 8:26 UTC (permalink / raw)
To: Bharat Bhushan
Cc: kvm, agraf, kvm-ppc, Bharat Bhushan, scottwood, linuxppc-dev
On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
> If the page is RAM then map this as cacheable and coherent (set "M" bit)
> otherwise this page is treated as I/O and map this as cache inhibited
> and guarded (set "I + G")
>
> This helps setting proper MMU mapping for direct assigned device.
>
> NOTE: There can be devices that require cacheable mapping, which is not yet supported.
Why don't you do like server instead and enforce the use of the same I
and M bits as the corresponding qemu PTE ?
Cheers,
Ben.
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> ---
> arch/powerpc/kvm/e500_mmu_host.c | 24 +++++++++++++++++++-----
> 1 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
> index 1c6a9d7..5cbdc8f 100644
> --- a/arch/powerpc/kvm/e500_mmu_host.c
> +++ b/arch/powerpc/kvm/e500_mmu_host.c
> @@ -64,13 +64,27 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode)
> return mas3;
> }
>
> -static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode)
> +static inline u32 e500_shadow_mas2_attrib(u32 mas2, pfn_t pfn)
> {
> + u32 mas2_attr;
> +
> + mas2_attr = mas2 & MAS2_ATTRIB_MASK;
> +
> + if (kvm_is_mmio_pfn(pfn)) {
> + /*
> + * If page is not RAM then it is treated as I/O page.
> + * Map it with cache inhibited and guarded (set "I" + "G").
> + */
> + mas2_attr |= MAS2_I | MAS2_G;
> + return mas2_attr;
> + }
> +
> + /* Map RAM pages as cacheable (Not setting "I" in MAS2) */
> #ifdef CONFIG_SMP
> - return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M;
> -#else
> - return mas2 & MAS2_ATTRIB_MASK;
> + /* Also map as coherent (set "M") in SMP */
> + mas2_attr |= MAS2_M;
> #endif
> + return mas2_attr;
> }
>
> /*
> @@ -313,7 +327,7 @@ static void kvmppc_e500_setup_stlbe(
> /* Force IPROT=0 for all guest mappings. */
> stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID;
> stlbe->mas2 = (gvaddr & MAS2_EPN) |
> - e500_shadow_mas2_attrib(gtlbe->mas2, pr);
> + e500_shadow_mas2_attrib(gtlbe->mas2, pfn);
> stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) |
> e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 8:26 ` Benjamin Herrenschmidt
@ 2013-07-26 8:50 ` Alexander Graf
2013-07-26 8:52 ` Bhushan Bharat-R65777
2013-07-26 15:03 ` Bhushan Bharat-R65777
2013-07-26 8:51 ` Bhushan Bharat-R65777
1 sibling, 2 replies; 13+ messages in thread
From: Alexander Graf @ 2013-07-26 8:50 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: kvm, kvm-ppc, Bharat Bhushan, Bharat Bhushan, scottwood, linuxppc-dev
On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote:
> On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
>> If the page is RAM then map this as cacheable and coherent (set "M" =
bit)
>> otherwise this page is treated as I/O and map this as cache inhibited
>> and guarded (set "I + G")
>>=20
>> This helps setting proper MMU mapping for direct assigned device.
>>=20
>> NOTE: There can be devices that require cacheable mapping, which is =
not yet supported.
>=20
> Why don't you do like server instead and enforce the use of the same I
> and M bits as the corresponding qemu PTE ?
Specifically, Ben is talking about this code:
/* Translate to host virtual address */
hva =3D __gfn_to_hva_memslot(memslot, gfn);
/* Look up the Linux PTE for the backing page */
pte_size =3D psize;
pte =3D lookup_linux_pte(pgdir, hva, writing, =
&pte_size);
if (pte_present(pte)) {
if (writing && !pte_write(pte))
/* make the actual HPTE be read-only */
ptel =3D hpte_make_readonly(ptel);
is_io =3D hpte_cache_bits(pte_val(pte));
pa =3D pte_pfn(pte) << PAGE_SHIFT;
}
Alex
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 8:26 ` Benjamin Herrenschmidt
2013-07-26 8:50 ` Alexander Graf
@ 2013-07-26 8:51 ` Bhushan Bharat-R65777
1 sibling, 0 replies; 13+ messages in thread
From: Bhushan Bharat-R65777 @ 2013-07-26 8:51 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Wood Scott-B07421, linuxppc-dev, kvm, kvm-ppc, agraf
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^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 8:50 ` Alexander Graf
@ 2013-07-26 8:52 ` Bhushan Bharat-R65777
2013-07-26 15:03 ` Bhushan Bharat-R65777
1 sibling, 0 replies; 13+ messages in thread
From: Bhushan Bharat-R65777 @ 2013-07-26 8:52 UTC (permalink / raw)
To: Alexander Graf, Benjamin Herrenschmidt
Cc: Wood Scott-B07421, linuxppc-dev, kvm, kvm-ppc
> -----Original Message-----
> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org=
] On
> Behalf Of Alexander Graf
> Sent: Friday, July 26, 2013 2:20 PM
> To: Benjamin Herrenschmidt
> Cc: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org; kvm@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Bhushan Bharat-R65777
> Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM p=
ages
>=20
>=20
> On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote:
>=20
> > On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
> >> If the page is RAM then map this as cacheable and coherent (set "M"
> >> bit) otherwise this page is treated as I/O and map this as cache
> >> inhibited and guarded (set "I + G")
> >>
> >> This helps setting proper MMU mapping for direct assigned device.
> >>
> >> NOTE: There can be devices that require cacheable mapping, which is no=
t yet
> supported.
> >
> > Why don't you do like server instead and enforce the use of the same I
> > and M bits as the corresponding qemu PTE ?
>=20
> Specifically, Ben is talking about this code:
>=20
>=20
> /* Translate to host virtual address */
> hva =3D __gfn_to_hva_memslot(memslot, gfn);
>=20
> /* Look up the Linux PTE for the backing page */
> pte_size =3D psize;
> pte =3D lookup_linux_pte(pgdir, hva, writing, &pte_size);
> if (pte_present(pte)) {
> if (writing && !pte_write(pte))
> /* make the actual HPTE be read-only */
> ptel =3D hpte_make_readonly(ptel);
> is_io =3D hpte_cache_bits(pte_val(pte));
> pa =3D pte_pfn(pte) << PAGE_SHIFT;
> }
>=20
Ok
Thanks
-Bharat
>=20
> Alex
>=20
> --
> To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the=
body
> of a message to majordomo@vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 8:50 ` Alexander Graf
2013-07-26 8:52 ` Bhushan Bharat-R65777
@ 2013-07-26 15:03 ` Bhushan Bharat-R65777
2013-07-26 22:26 ` Benjamin Herrenschmidt
1 sibling, 1 reply; 13+ messages in thread
From: Bhushan Bharat-R65777 @ 2013-07-26 15:03 UTC (permalink / raw)
To: Alexander Graf, Benjamin Herrenschmidt
Cc: Wood Scott-B07421, linuxppc-dev, kvm, kvm-ppc
> -----Original Message-----
> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org=
] On
> Behalf Of Alexander Graf
> Sent: Friday, July 26, 2013 2:20 PM
> To: Benjamin Herrenschmidt
> Cc: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org; kvm@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Bhushan Bharat-R65777
> Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM p=
ages
>=20
>=20
> On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote:
>=20
> > On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
> >> If the page is RAM then map this as cacheable and coherent (set "M"
> >> bit) otherwise this page is treated as I/O and map this as cache
> >> inhibited and guarded (set "I + G")
> >>
> >> This helps setting proper MMU mapping for direct assigned device.
> >>
> >> NOTE: There can be devices that require cacheable mapping, which is no=
t yet
> supported.
> >
> > Why don't you do like server instead and enforce the use of the same I
> > and M bits as the corresponding qemu PTE ?
>=20
> Specifically, Ben is talking about this code:
>=20
>=20
> /* Translate to host virtual address */
> hva =3D __gfn_to_hva_memslot(memslot, gfn);
>=20
> /* Look up the Linux PTE for the backing page */
> pte_size =3D psize;
> pte =3D lookup_linux_pte(pgdir, hva, writing, &pte_size);
> if (pte_present(pte)) {
> if (writing && !pte_write(pte))
> /* make the actual HPTE be read-only */
> ptel =3D hpte_make_readonly(ptel);
> is_io =3D hpte_cache_bits(pte_val(pte));
> pa =3D pte_pfn(pte) << PAGE_SHIFT;
> }
>=20
Will not searching the Linux PTE is a overkill?
=3DBharat
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 15:03 ` Bhushan Bharat-R65777
@ 2013-07-26 22:26 ` Benjamin Herrenschmidt
2013-07-30 16:22 ` Bhushan Bharat-R65777
0 siblings, 1 reply; 13+ messages in thread
From: Benjamin Herrenschmidt @ 2013-07-26 22:26 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Wood Scott-B07421, linuxppc-dev, Alexander Graf, kvm-ppc, kvm
On Fri, 2013-07-26 at 15:03 +0000, Bhushan Bharat-R65777 wrote:
> Will not searching the Linux PTE is a overkill?
That's the best approach. Also we are searching it already to resolve
the page fault. That does mean we search twice but on the other hand
that also means it's hot in the cache.
Cheers,
Ben
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-26 22:26 ` Benjamin Herrenschmidt
@ 2013-07-30 16:22 ` Bhushan Bharat-R65777
2013-07-30 18:49 ` Scott Wood
0 siblings, 1 reply; 13+ messages in thread
From: Bhushan Bharat-R65777 @ 2013-07-30 16:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Wood Scott-B07421, linuxppc-dev, Alexander Graf, kvm-ppc, kvm
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-30 16:22 ` Bhushan Bharat-R65777
@ 2013-07-30 18:49 ` Scott Wood
2013-07-31 5:23 ` Bhushan Bharat-R65777
0 siblings, 1 reply; 13+ messages in thread
From: Scott Wood @ 2013-07-30 18:49 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Wood Scott-B07421, kvm, Alexander Graf, kvm-ppc, linuxppc-dev
On 07/30/2013 11:22:54 AM, Bhushan Bharat-R65777 wrote:
> diff --git a/arch/powerpc/kvm/e500_mmu_host.c =20
> b/arch/powerpc/kvm/e500_mmu_host.c
> index 5cbdc8f..a48c13f 100644
> --- a/arch/powerpc/kvm/e500_mmu_host.c
> +++ b/arch/powerpc/kvm/e500_mmu_host.c
> @@ -40,6 +40,84 @@
>=20
> static struct kvmppc_e500_tlb_params host_tlb_params[E500_TLB_NUM];
>=20
> +/*
> + * find_linux_pte returns the address of a linux pte for a given
> + * effective address and directory. If not found, it returns zero.
> + */
> +static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
> +{
> + pgd_t *pg;
> + pud_t *pu;
> + pmd_t *pm;
> + pte_t *pt =3D NULL;
> +
> + pg =3D pgdir + pgd_index(ea);
> + if (!pgd_none(*pg)) {
> + pu =3D pud_offset(pg, ea);
> + if (!pud_none(*pu)) {
> + pm =3D pmd_offset(pu, ea);
> + if (pmd_present(*pm))
> + pt =3D pte_offset_kernel(pm, ea);
> + }
> + }
> + return pt;
> +}
How is this specific to KVM or e500?
> +#ifdef CONFIG_HUGETLB_PAGE
> +pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
> + unsigned *shift);
> +#else
> +static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, =20
> unsigned long ea,
> + unsigned *shift)
> +{
> + if (shift)
> + *shift =3D 0;
> + return find_linux_pte(pgdir, ea);
> +}
> +#endif /* !CONFIG_HUGETLB_PAGE */
This is already declared in asm/pgtable.h. If we need a non-hugepage =20
alternative, that should also go in asm/pgtable.h.
> +/*
> + * Lock and read a linux PTE. If it's present and writable, =20
> atomically
> + * set dirty and referenced bits and return the PTE, otherwise =20
> return 0.
> + */
> +static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int =20
> writing)
> +{
> + pte_t pte =3D pte_val(*p);
> +
> + if (pte_present(pte)) {
> + pte =3D pte_mkyoung(pte);
> + if (writing && pte_write(pte))
> + pte =3D pte_mkdirty(pte);
> + }
> +
> + *p =3D pte;
> +
> + return pte;
> +}
> +
> +static pte_t lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
> + int writing, unsigned long *pte_sizep)
> +{
> + pte_t *ptep;
> + unsigned long ps =3D *pte_sizep;
> + unsigned int shift;
> +
> + ptep =3D find_linux_pte_or_hugepte(pgdir, hva, &shift);
> + if (!ptep)
> + return __pte(0);
> + if (shift)
> + *pte_sizep =3D 1ul << shift;
> + else
> + *pte_sizep =3D PAGE_SIZE;
> +
> + if (ps > *pte_sizep)
> + return __pte(0);
> + if (!pte_present(*ptep))
> + return __pte(0);
> +
> + return kvmppc_read_update_linux_pte(ptep, writing);
> +}
> +
None of this belongs in this file either.
> @@ -326,8 +405,8 @@ static void kvmppc_e500_setup_stlbe(
>=20
> /* Force IPROT=3D0 for all guest mappings. */
> stlbe->mas1 =3D MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | =20
> MAS1_VALID;
> - stlbe->mas2 =3D (gvaddr & MAS2_EPN) |
> - e500_shadow_mas2_attrib(gtlbe->mas2, pfn);
> + stlbe->mas2 =3D (gvaddr & MAS2_EPN) | (ref->flags & =20
> E500_TLB_WIMGE_MASK);
> +// e500_shadow_mas2_attrib(gtlbe->mas2, pfn);
MAS2_E and MAS2_G should be safe to come from the guest.
How does this work for TLB1? One ref corresponds to one guest entry, =20
which may correspond to multiple host entries, potentially each with =20
different WIM settings.
> stlbe->mas7_3 =3D ((u64)pfn << PAGE_SHIFT) |
> e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
>=20
> @@ -346,6 +425,8 @@ static inline int kvmppc_e500_shadow_map(struct =20
> kvmppc_vcpu_e500 *vcpu_e500,
> unsigned long hva;
> int pfnmap =3D 0;
> int tsize =3D BOOK3E_PAGESZ_4K;
> + pte_t pte;
> + int wimg =3D 0;
>=20
> /*
> * Translate guest physical to true physical, acquiring
> @@ -451,6 +532,8 @@ static inline int kvmppc_e500_shadow_map(struct =20
> kvmppc_vcpu_e500 *vcpu_e500,
>=20
> if (likely(!pfnmap)) {
> unsigned long tsize_pages =3D 1 << (tsize + 10 - =20
> PAGE_SHIFT);
> + pgd_t *pgdir;
> +
> pfn =3D gfn_to_pfn_memslot(slot, gfn);
> if (is_error_noslot_pfn(pfn)) {
> printk(KERN_ERR "Couldn't get real page for =20
> gfn %lx!\n",
> @@ -461,9 +544,15 @@ static inline int kvmppc_e500_shadow_map(struct =20
> kvmppc_vcpu_e500 *vcpu_e500,
> /* Align guest and physical address to page map =20
> boundaries */
> pfn &=3D ~(tsize_pages - 1);
> gvaddr &=3D ~((tsize_pages << PAGE_SHIFT) - 1);
> + pgdir =3D vcpu_e500->vcpu.arch.pgdir;
> + pte =3D lookup_linux_pte(pgdir, hva, 1, &tsize_pages);
> + if (pte_present(pte))
> + wimg =3D (pte >> PTE_WIMGE_SHIFT) & =20
> MAS2_WIMGE_MASK;
> + else
> + wimg =3D MAS2_I | MAS2_G;
If the PTE is not present, then we can't map it, right? So why I+G?
-Scott=
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
2013-07-30 18:49 ` Scott Wood
@ 2013-07-31 5:23 ` Bhushan Bharat-R65777
0 siblings, 0 replies; 13+ messages in thread
From: Bhushan Bharat-R65777 @ 2013-07-31 5:23 UTC (permalink / raw)
To: Wood Scott-B07421; +Cc: linuxppc-dev, Alexander Graf, kvm-ppc, kvm
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, July 31, 2013 12:19 AM
> To: Bhushan Bharat-R65777
> Cc: Benjamin Herrenschmidt; Alexander Graf; kvm-ppc@vger.kernel.org;
> kvm@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421
> Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM p=
ages
>=20
> On 07/30/2013 11:22:54 AM, Bhushan Bharat-R65777 wrote:
> > diff --git a/arch/powerpc/kvm/e500_mmu_host.c
> > b/arch/powerpc/kvm/e500_mmu_host.c
> > index 5cbdc8f..a48c13f 100644
> > --- a/arch/powerpc/kvm/e500_mmu_host.c
> > +++ b/arch/powerpc/kvm/e500_mmu_host.c
> > @@ -40,6 +40,84 @@
> >
> > static struct kvmppc_e500_tlb_params host_tlb_params[E500_TLB_NUM];
> >
> > +/*
> > + * find_linux_pte returns the address of a linux pte for a given
> > + * effective address and directory. If not found, it returns zero.
> > + */
> > +static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea) {
> > + pgd_t *pg;
> > + pud_t *pu;
> > + pmd_t *pm;
> > + pte_t *pt =3D NULL;
> > +
> > + pg =3D pgdir + pgd_index(ea);
> > + if (!pgd_none(*pg)) {
> > + pu =3D pud_offset(pg, ea);
> > + if (!pud_none(*pu)) {
> > + pm =3D pmd_offset(pu, ea);
> > + if (pmd_present(*pm))
> > + pt =3D pte_offset_kernel(pm, ea);
> > + }
> > + }
> > + return pt;
> > +}
>=20
> How is this specific to KVM or e500?
>=20
> > +#ifdef CONFIG_HUGETLB_PAGE
> > +pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
> > + unsigned *shift); #else static
> > +inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir,
> > unsigned long ea,
> > + unsigned *shift) {
> > + if (shift)
> > + *shift =3D 0;
> > + return find_linux_pte(pgdir, ea); } #endif /*
> > +!CONFIG_HUGETLB_PAGE */
>=20
> This is already declared in asm/pgtable.h. If we need a non-hugepage
> alternative, that should also go in asm/pgtable.h.
>=20
> > +/*
> > + * Lock and read a linux PTE. If it's present and writable,
> > atomically
> > + * set dirty and referenced bits and return the PTE, otherwise
> > return 0.
> > + */
> > +static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int
> > writing)
> > +{
> > + pte_t pte =3D pte_val(*p);
> > +
> > + if (pte_present(pte)) {
> > + pte =3D pte_mkyoung(pte);
> > + if (writing && pte_write(pte))
> > + pte =3D pte_mkdirty(pte);
> > + }
> > +
> > + *p =3D pte;
> > +
> > + return pte;
> > +}
> > +
> > +static pte_t lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
> > + int writing, unsigned long *pte_sizep) {
> > + pte_t *ptep;
> > + unsigned long ps =3D *pte_sizep;
> > + unsigned int shift;
> > +
> > + ptep =3D find_linux_pte_or_hugepte(pgdir, hva, &shift);
> > + if (!ptep)
> > + return __pte(0);
> > + if (shift)
> > + *pte_sizep =3D 1ul << shift;
> > + else
> > + *pte_sizep =3D PAGE_SIZE;
> > +
> > + if (ps > *pte_sizep)
> > + return __pte(0);
> > + if (!pte_present(*ptep))
> > + return __pte(0);
> > +
> > + return kvmppc_read_update_linux_pte(ptep, writing); }
> > +
>=20
> None of this belongs in this file either.
>=20
> > @@ -326,8 +405,8 @@ static void kvmppc_e500_setup_stlbe(
> >
> > /* Force IPROT=3D0 for all guest mappings. */
> > stlbe->mas1 =3D MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) |
> > MAS1_VALID;
> > - stlbe->mas2 =3D (gvaddr & MAS2_EPN) |
> > - e500_shadow_mas2_attrib(gtlbe->mas2, pfn);
> > + stlbe->mas2 =3D (gvaddr & MAS2_EPN) | (ref->flags &
> > E500_TLB_WIMGE_MASK);
> > +// e500_shadow_mas2_attrib(gtlbe->mas2, pfn);
>=20
> MAS2_E and MAS2_G should be safe to come from the guest.
This is handled when setting WIMGE in ref->flags.
>=20
> How does this work for TLB1? One ref corresponds to one guest entry, whi=
ch may
> correspond to multiple host entries, potentially each with different WIM
> settings.
Yes, one ref corresponds to one guest entry. To understand how this will wo=
rk when a one guest tlb1 entry may maps to many host tlb0/1 entry;=20
on guest tlbwe, KVM setup one guest tlb entry and then pre-map one host tlb=
entry (out of many) and ref (ref->pfn etc) points to this pre-map entry fo=
r that guest entry.
Now a guest TLB miss happens which falls on same guest tlb entry and but de=
mands another host tlb entry. In that flow we change/overwrite ref (ref->pf=
n etc) to point to new host mapping for same guest mapping.
>=20
> > stlbe->mas7_3 =3D ((u64)pfn << PAGE_SHIFT) |
> > e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
> >
> > @@ -346,6 +425,8 @@ static inline int kvmppc_e500_shadow_map(struct
> > kvmppc_vcpu_e500 *vcpu_e500,
> > unsigned long hva;
> > int pfnmap =3D 0;
> > int tsize =3D BOOK3E_PAGESZ_4K;
> > + pte_t pte;
> > + int wimg =3D 0;
> >
> > /*
> > * Translate guest physical to true physical, acquiring @@
> > -451,6 +532,8 @@ static inline int kvmppc_e500_shadow_map(struct
> > kvmppc_vcpu_e500 *vcpu_e500,
> >
> > if (likely(!pfnmap)) {
> > unsigned long tsize_pages =3D 1 << (tsize + 10 -
> > PAGE_SHIFT);
> > + pgd_t *pgdir;
> > +
> > pfn =3D gfn_to_pfn_memslot(slot, gfn);
> > if (is_error_noslot_pfn(pfn)) {
> > printk(KERN_ERR "Couldn't get real page for
> > gfn %lx!\n", @@ -461,9 +544,15 @@ static inline int
> > kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
> > /* Align guest and physical address to page map
> > boundaries */
> > pfn &=3D ~(tsize_pages - 1);
> > gvaddr &=3D ~((tsize_pages << PAGE_SHIFT) - 1);
> > + pgdir =3D vcpu_e500->vcpu.arch.pgdir;
> > + pte =3D lookup_linux_pte(pgdir, hva, 1, &tsize_pages);
> > + if (pte_present(pte))
> > + wimg =3D (pte >> PTE_WIMGE_SHIFT) &
> > MAS2_WIMGE_MASK;
> > + else
> > + wimg =3D MAS2_I | MAS2_G;
>=20
> If the PTE is not present, then we can't map it, right?
Right, we should return error :)
-Bharat
> So why I+G?
>=20
> -Scott
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2013-07-31 5:23 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-07-26 5:46 [PATCH 1/4] powerpc: book3e: _PAGE_LENDIAN must be _PAGE_ENDIAN Bharat Bhushan
2013-07-26 5:46 ` [PATCH 2/4] kvm: powerpc: allow guest control "E" attribute in mas2 Bharat Bhushan
2013-07-26 5:46 ` [PATCH 3/4] kvm: powerpc: allow guest control "G" " Bharat Bhushan
2013-07-26 5:46 ` [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages Bharat Bhushan
2013-07-26 8:26 ` Benjamin Herrenschmidt
2013-07-26 8:50 ` Alexander Graf
2013-07-26 8:52 ` Bhushan Bharat-R65777
2013-07-26 15:03 ` Bhushan Bharat-R65777
2013-07-26 22:26 ` Benjamin Herrenschmidt
2013-07-30 16:22 ` Bhushan Bharat-R65777
2013-07-30 18:49 ` Scott Wood
2013-07-31 5:23 ` Bhushan Bharat-R65777
2013-07-26 8:51 ` Bhushan Bharat-R65777
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