* [PATCH 1/3] powerpc: Rework setting up H/FSCR bit definitions
@ 2013-08-05 7:28 Michael Neuling
2013-08-05 7:28 ` [PATCH 2/3] powerpc: Fix hypervisor facility unavaliable vector number Michael Neuling
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Michael Neuling @ 2013-08-05 7:28 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Anton Blanchard
This reworks the Facility Status and Control Regsiter (FSCR) config bit
definitions so that we can access the bit numbers. This will be useful when
looking at the status in the facility unavailable interrupt.
HFSCR and FSCR versions are the same, so reuse them.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/reg.h | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a6840e4..75199581 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -254,19 +254,28 @@
#define SPRN_HRMOR 0x139 /* Real mode offset register */
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
+/* HFSCR and FSCR bit numbers are the same */
+#define FSCR_TAR_LG 8 /* Enable Target Address Register */
+#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
+#define FSCR_TM_LG 6 /* Enable Transactional Memory */
+#define FSCR_PM_LG 5 /* Enable prob/priv access to PMU SPRs */
+#define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/
+#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */
+#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
+#define FSCR_FP_LG 0 /* Enable Floating Point */
#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
-#define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */
-#define FSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */
-#define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */
+#define FSCR_TAR __MASK(FSCR_TAR_LG)
+#define FSCR_EBB __MASK(FSCR_EBB_LG)
+#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
-#define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */
-#define HFSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */
-#define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */
-#define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
-#define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/
-#define HFSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */
-#define HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX */
-#define HFSCR_FP (1 << (63-63)) /* Enable Floating Point */
+#define HFSCR_TAR __MASK(FSCR_TAR_LG)
+#define HFSCR_EBB __MASK(FSCR_EBB_LG)
+#define HFSCR_TM __MASK(FSCR_TM_LG)
+#define HFSCR_PM __MASK(FSCR_PM_LG)
+#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
+#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
+#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
+#define HFSCR_FP __MASK(FSCR_FP_LG)
#define SPRN_TAR 0x32f /* Target Address Register */
#define SPRN_LPCR 0x13E /* LPAR Control Register */
#define LPCR_VPM0 (1ul << (63-0))
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] powerpc: Fix hypervisor facility unavaliable vector number
2013-08-05 7:28 [PATCH 1/3] powerpc: Rework setting up H/FSCR bit definitions Michael Neuling
@ 2013-08-05 7:28 ` Michael Neuling
2013-08-05 7:28 ` [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8 Michael Neuling
2013-08-09 3:46 ` [PATCH v2 1/3] powerpc: Rework setting up H/FSCR bit definitions Michael Neuling
2 siblings, 0 replies; 9+ messages in thread
From: Michael Neuling @ 2013-08-05 7:28 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Anton Blanchard
Currently if we take hypervisor facility unavaliable (from 0xf80/0x4f80) we
mark it as an OS facility unavaliable (0xf60) as the two share the same code
path.
The becomes a problem in facility_unavailable_exception() as we aren't able to
see the hypervisor facility unavailable exceptions.
Below fixes this by duplication the required macros.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/exceptions-64s.S | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 4e00d22..902ca3c 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -848,7 +848,7 @@ hv_facility_unavailable_relon_trampoline:
. = 0x4f80
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
- b facility_unavailable_relon_hv
+ b hv_facility_unavailable_relon_hv
STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint)
#ifdef CONFIG_PPC_DENORMALISATION
@@ -1175,6 +1175,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
b .ret_from_except
STD_EXCEPTION_COMMON(0xf60, facility_unavailable, .facility_unavailable_exception)
+ STD_EXCEPTION_COMMON(0xf80, hv_facility_unavailable, .facility_unavailable_exception)
.align 7
.globl __end_handlers
@@ -1188,7 +1189,7 @@ __end_handlers:
STD_RELON_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable)
STD_RELON_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable)
STD_RELON_EXCEPTION_PSERIES_OOL(0xf60, facility_unavailable)
- STD_RELON_EXCEPTION_HV_OOL(0xf80, facility_unavailable)
+ STD_RELON_EXCEPTION_HV_OOL(0xf80, hv_facility_unavailable)
#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
/*
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8
2013-08-05 7:28 [PATCH 1/3] powerpc: Rework setting up H/FSCR bit definitions Michael Neuling
2013-08-05 7:28 ` [PATCH 2/3] powerpc: Fix hypervisor facility unavaliable vector number Michael Neuling
@ 2013-08-05 7:28 ` Michael Neuling
2013-08-05 8:42 ` Stephen Rothwell
2013-08-09 3:46 ` [PATCH v2 1/3] powerpc: Rework setting up H/FSCR bit definitions Michael Neuling
2 siblings, 1 reply; 9+ messages in thread
From: Michael Neuling @ 2013-08-05 7:28 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Anton Blanchard
POWER8 allows the DSCR to be accessed directly from userspace via a new SPR
number 0x3 (Rather than 0x11. DSCR SPR number 0x11 is still used on POWER8 but
like POWER7, is only accessible in HV and OS modes). Currently, we allow this
by setting H/FSCR DSCR bit on boot.
Unfortunately this doesn't work, as the kernel needs to see the DSCR change so
that it knows to no longer restore the system wide version of DSCR on context
switch (ie. to set thread.dscr_inherit).
This clears the H/FSCR DSCR bit initially. If a process then accesses the DSCR
(via SPR 0x3), it'll trap into the kernel where we set thread.dscr_inherit in
facility_unavailable_exception().
We also change _switch() so that we set or clear the H/FSCR DSCR bit based on
the thread.dscr_inherit.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/cpu_setup_power.S | 8 ++++--
arch/powerpc/kernel/entry_64.S | 27 +++++++++++++++++-
arch/powerpc/kernel/traps.c | 54 +++++++++++++++++++++--------------
3 files changed, 65 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 18b5b9c..c7a3b81 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -123,14 +123,18 @@ __init_LPCR:
__init_FSCR:
mfspr r3,SPRN_FSCR
- ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
+ ori r3,r3,FSCR_TAR|FSCR_EBB
+ li r5,HFSCR_DSCR
+ andc r3,r3,r5
mtspr SPRN_FSCR,r3
blr
__init_HFSCR:
mfspr r3,SPRN_HFSCR
ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
- HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
+ HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
+ li r5,HFSCR_DSCR
+ andc r3,r3,r5
mtspr SPRN_HFSCR,r3
blr
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index ab15b8d..4674fe6 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -584,9 +584,34 @@ BEGIN_FTR_SECTION
ld r7,DSCR_DEFAULT@toc(2)
ld r0,THREAD_DSCR(r4)
cmpwi r6,0
+ li r8, FSCR_DSCR
bne 1f
ld r0,0(r7)
-1: cmpd r0,r25
+ b 3f
+1:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ or r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ or r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ b 4f
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+3:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ andc r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ andc r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+4: cmpd r0,r25
beq 2f
mtspr SPRN_DSCR,r0
2:
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index bf33c22..be7930e 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -44,9 +44,7 @@
#include <asm/machdep.h>
#include <asm/rtas.h>
#include <asm/pmc.h>
-#ifdef CONFIG_PPC32
#include <asm/reg.h>
-#endif
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
@@ -1296,43 +1294,56 @@ void vsx_unavailable_exception(struct pt_regs *regs)
die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
}
+#ifdef CONFIG_PPC64
void facility_unavailable_exception(struct pt_regs *regs)
{
static char *facility_strings[] = {
- "FPU",
- "VMX/VSX",
- "DSCR",
- "PMU SPRs",
- "BHRB",
- "TM",
- "AT",
- "EBB",
- "TAR",
+ [FSCR_FP_LG] = "FPU",
+ [FSCR_VECVSX_LG] = "VMX/VSX",
+ [FSCR_DSCR_LG] = "DSCR",
+ [FSCR_PM_LG] = "PMU SPRs",
+ [FSCR_BHRB_LG] = "BHRB",
+ [FSCR_TM_LG] = "TM",
+ [FSCR_EBB_LG] = "EBB",
+ [FSCR_TAR_LG] = "TAR",
};
- char *facility, *prefix;
+ char *facility;
u64 value;
+ u8 status;
+ bool hv;
if (regs->trap == 0xf60) {
value = mfspr(SPRN_FSCR);
- prefix = "";
+ hv = false;
} else {
value = mfspr(SPRN_HFSCR);
- prefix = "Hypervisor ";
+ hv = true;
}
- value = value >> 56;
+ status = value >> 56;
+
+ if (status < ARRAY_SIZE(facility_strings))
+ facility = facility_strings[status];
+ else
+ facility = "unknown";
+
+ if (status == FSCR_DSCR_LG) {
+ /* user wants to set it. Hence clear the inherit bit
+ * and allow them to set it via the H/FSCR */
+ current->thread.dscr_inherit = 1;
+ if (hv)
+ mtspr(SPRN_HFSCR, value | HFSCR_DSCR);
+ else
+ mtspr(SPRN_FSCR, value | FSCR_DSCR);
+ return;
+ }
/* We restore the interrupt state now */
if (!arch_irq_disabled_regs(regs))
local_irq_enable();
- if (value < ARRAY_SIZE(facility_strings))
- facility = facility_strings[value];
- else
- facility = "unknown";
-
pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
- prefix, facility, regs->nip, regs->msr);
+ hv ? "Hypervisor ":"", facility, regs->nip, regs->msr);
if (user_mode(regs)) {
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
@@ -1341,6 +1352,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
die("Unexpected facility unavailable exception", regs, SIGABRT);
}
+#endif
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8
2013-08-05 7:28 ` [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8 Michael Neuling
@ 2013-08-05 8:42 ` Stephen Rothwell
2013-08-05 9:26 ` Michael Neuling
0 siblings, 1 reply; 9+ messages in thread
From: Stephen Rothwell @ 2013-08-05 8:42 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, Anton Blanchard
[-- Attachment #1: Type: text/plain, Size: 2032 bytes --]
[This time from a good email address :-)]
Hi Mikey,
On Mon, 5 Aug 2013 17:28:06 +1000 Michael Neuling
<mikey@neuling.org> wrote:
>
> +++ b/arch/powerpc/kernel/traps.c
> @@ -1296,43 +1294,56 @@ void vsx_unavailable_exception(struct pt_regs *regs)
> die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
> }
>
> +#ifdef CONFIG_PPC64
> void facility_unavailable_exception(struct pt_regs *regs)
> {
> static char *facility_strings[] = {
> - "FPU",
> - "VMX/VSX",
> - "DSCR",
> - "PMU SPRs",
> - "BHRB",
> - "TM",
> - "AT",
> - "EBB",
> - "TAR",
> + [FSCR_FP_LG] = "FPU",
> + [FSCR_VECVSX_LG] = "VMX/VSX",
> + [FSCR_DSCR_LG] = "DSCR",
> + [FSCR_PM_LG] = "PMU SPRs",
> + [FSCR_BHRB_LG] = "BHRB",
> + [FSCR_TM_LG] = "TM",
> + [FSCR_EBB_LG] = "EBB",
> + [FSCR_TAR_LG] = "TAR",
I assume that you intentionally dropped "AT".
> };
> - char *facility, *prefix;
> + char *facility;
> u64 value;
> + u8 status;
> + bool hv;
>
> if (regs->trap == 0xf60) {
> value = mfspr(SPRN_FSCR);
> - prefix = "";
> + hv = false;
> } else {
> value = mfspr(SPRN_HFSCR);
> - prefix = "Hypervisor ";
> + hv = true;
> }
Maybe:
hv = regs->trap == 0xf60;
if (hv)
value = mfspr(SPRN_HFSCR);
else
value = mfspr(SPRN_HFSCR);
or
value = mfspr(hv ? SPRN_HFSCR : SPRN_HFSCR);
> - value = value >> 56;
> + status = value >> 56;
> +
> + if (status < ARRAY_SIZE(facility_strings))
> + facility = facility_strings[status];
> + else
> + facility = "unknown";
For entries in the array that are not set, this will give facility ==
NULL. Is that what you intended?
> pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
> - prefix, facility, regs->nip, regs->msr);
> + hv ? "Hypervisor ":"", facility, regs->nip, regs->msr);
... and this may attempt to print a NULL pointer with %s. Also please
put spaces around the : .
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8
2013-08-05 8:42 ` Stephen Rothwell
@ 2013-08-05 9:26 ` Michael Neuling
2013-08-05 10:16 ` Michael Neuling
0 siblings, 1 reply; 9+ messages in thread
From: Michael Neuling @ 2013-08-05 9:26 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, Anton Blanchard
Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> [This time from a good email address :-)]
>
> Hi Mikey,
>
> On Mon, 5 Aug 2013 17:28:06 +1000 Michael Neuling
> <mikey@neuling.org> wrote:
> >
> > +++ b/arch/powerpc/kernel/traps.c
> > @@ -1296,43 +1294,56 @@ void vsx_unavailable_exception(struct pt_regs *regs)
> > die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
> > }
> >
> > +#ifdef CONFIG_PPC64
> > void facility_unavailable_exception(struct pt_regs *regs)
> > {
> > static char *facility_strings[] = {
> > - "FPU",
> > - "VMX/VSX",
> > - "DSCR",
> > - "PMU SPRs",
> > - "BHRB",
> > - "TM",
> > - "AT",
> > - "EBB",
> > - "TAR",
> > + [FSCR_FP_LG] = "FPU",
> > + [FSCR_VECVSX_LG] = "VMX/VSX",
> > + [FSCR_DSCR_LG] = "DSCR",
> > + [FSCR_PM_LG] = "PMU SPRs",
> > + [FSCR_BHRB_LG] = "BHRB",
> > + [FSCR_TM_LG] = "TM",
> > + [FSCR_EBB_LG] = "EBB",
> > + [FSCR_TAR_LG] = "TAR",
>
> I assume that you intentionally dropped "AT".
Yeah.
>
> > };
> > - char *facility, *prefix;
> > + char *facility;
> > u64 value;
> > + u8 status;
> > + bool hv;
> >
> > if (regs->trap == 0xf60) {
> > value = mfspr(SPRN_FSCR);
> > - prefix = "";
> > + hv = false;
> > } else {
> > value = mfspr(SPRN_HFSCR);
> > - prefix = "Hypervisor ";
> > + hv = true;
> > }
>
> Maybe:
> hv = regs->trap == 0xf60;
> if (hv)
> value = mfspr(SPRN_HFSCR);
> else
> value = mfspr(SPRN_HFSCR);
> or
> value = mfspr(hv ? SPRN_HFSCR : SPRN_HFSCR);
ok.
>
> > - value = value >> 56;
> > + status = value >> 56;
> > +
> > + if (status < ARRAY_SIZE(facility_strings))
> > + facility = facility_strings[status];
> > + else
> > + facility = "unknown";
>
> For entries in the array that are not set, this will give facility ==
> NULL. Is that what you intended?
No it wasn't, I'll catch that case, thanks.
>
> > pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
> > - prefix, facility, regs->nip, regs->msr);
> > + hv ? "Hypervisor ":"", facility, regs->nip, regs->msr);
>
> ... and this may attempt to print a NULL pointer with %s. Also please
> put spaces around the : .
OK.
Mikey
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8
2013-08-05 9:26 ` Michael Neuling
@ 2013-08-05 10:16 ` Michael Neuling
2013-08-05 11:00 ` [PATCH v2 " Michael Neuling
0 siblings, 1 reply; 9+ messages in thread
From: Michael Neuling @ 2013-08-05 10:16 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, Anton Blanchard
> > > };
> > > - char *facility, *prefix;
> > > + char *facility;
> > > u64 value;
> > > + u8 status;
> > > + bool hv;
> > >
> > > if (regs->trap == 0xf60) {
> > > value = mfspr(SPRN_FSCR);
> > > - prefix = "";
> > > + hv = false;
> > > } else {
> > > value = mfspr(SPRN_HFSCR);
> > > - prefix = "Hypervisor ";
> > > + hv = true;
> > > }
> >
> > Maybe:
> > hv = regs->trap == 0xf60;
> > if (hv)
> > value = mfspr(SPRN_HFSCR);
> > else
> > value = mfspr(SPRN_HFSCR);
> > or
> > value = mfspr(hv ? SPRN_HFSCR : SPRN_HFSCR);
>
> ok.
So this doesn't work... I forgot that mfspr is just a macro around the
mfspr instruction, so we can't dynamically pass in the SPR number,
So I have to use your first version.
Mikey
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] powerpc: Correctly context switch DSCR on POWER8
2013-08-05 10:16 ` Michael Neuling
@ 2013-08-05 11:00 ` Michael Neuling
2013-08-09 5:49 ` [PATCH v3 " Michael Neuling
0 siblings, 1 reply; 9+ messages in thread
From: Michael Neuling @ 2013-08-05 11:00 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, Anton Blanchard
POWER8 allows the DSCR to be accessed directly from userspace via a new SPR
number 0x3 (Rather than 0x11. DSCR SPR number 0x11 is still used on POWER8 but
like POWER7, is only accessible in HV and OS modes). Currently, we allow this
by setting H/FSCR DSCR bit on boot.
Unfortunately this doesn't work, as the kernel needs to see the DSCR change so
that it knows to no longer restore the system wide version of DSCR on context
switch (ie. to set thread.dscr_inherit).
This clears the H/FSCR DSCR bit initially. If a process then accesses the DSCR
(via SPR 0x3), it'll trap into the kernel where we set thread.dscr_inherit in
facility_unavailable_exception().
We also change _switch() so that we set or clear the H/FSCR DSCR bit based on
the thread.dscr_inherit.
Signed-off-by: Michael Neuling <mikey@neuling.org>
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 18b5b9c..c7a3b81 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -123,14 +123,18 @@ __init_LPCR:
__init_FSCR:
mfspr r3,SPRN_FSCR
- ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
+ ori r3,r3,FSCR_TAR|FSCR_EBB
+ li r5,HFSCR_DSCR
+ andc r3,r3,r5
mtspr SPRN_FSCR,r3
blr
__init_HFSCR:
mfspr r3,SPRN_HFSCR
ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
- HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
+ HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
+ li r5,HFSCR_DSCR
+ andc r3,r3,r5
mtspr SPRN_HFSCR,r3
blr
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index ab15b8d..4674fe6 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -584,9 +584,34 @@ BEGIN_FTR_SECTION
ld r7,DSCR_DEFAULT@toc(2)
ld r0,THREAD_DSCR(r4)
cmpwi r6,0
+ li r8, FSCR_DSCR
bne 1f
ld r0,0(r7)
-1: cmpd r0,r25
+ b 3f
+1:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ or r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ or r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ b 4f
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+3:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ andc r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ andc r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+4: cmpd r0,r25
beq 2f
mtspr SPRN_DSCR,r0
2:
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index bf33c22..e435bc0 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -44,9 +44,7 @@
#include <asm/machdep.h>
#include <asm/rtas.h>
#include <asm/pmc.h>
-#ifdef CONFIG_PPC32
#include <asm/reg.h>
-#endif
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
@@ -1296,43 +1294,54 @@ void vsx_unavailable_exception(struct pt_regs *regs)
die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
}
+#ifdef CONFIG_PPC64
void facility_unavailable_exception(struct pt_regs *regs)
{
static char *facility_strings[] = {
- "FPU",
- "VMX/VSX",
- "DSCR",
- "PMU SPRs",
- "BHRB",
- "TM",
- "AT",
- "EBB",
- "TAR",
+ [FSCR_FP_LG] = "FPU",
+ [FSCR_VECVSX_LG] = "VMX/VSX",
+ [FSCR_DSCR_LG] = "DSCR",
+ [FSCR_PM_LG] = "PMU SPRs",
+ [FSCR_BHRB_LG] = "BHRB",
+ [FSCR_TM_LG] = "TM",
+ [FSCR_EBB_LG] = "EBB",
+ [FSCR_TAR_LG] = "TAR",
};
- char *facility, *prefix;
+ char *facility = "unknown";
u64 value;
+ u8 status;
+ bool hv;
- if (regs->trap == 0xf60) {
- value = mfspr(SPRN_FSCR);
- prefix = "";
- } else {
+ hv = (regs->trap == 0xf80);
+ if (hv)
value = mfspr(SPRN_HFSCR);
- prefix = "Hypervisor ";
+ else
+ value = mfspr(SPRN_FSCR);
+
+ status = value >> 56;
+ if (status == FSCR_DSCR_LG) {
+ /* User is acessing the DSCR. Set the inherit bit and allow
+ * the user to set it directly in future by setting via the
+ * H/FSCR DSCR bit.
+ */
+ current->thread.dscr_inherit = 1;
+ if (hv)
+ mtspr(SPRN_HFSCR, value | HFSCR_DSCR);
+ else
+ mtspr(SPRN_FSCR, value | FSCR_DSCR);
+ return;
}
- value = value >> 56;
+ if ((status < ARRAY_SIZE(facility_strings)) &&
+ facility_strings[status])
+ facility = facility_strings[status];
/* We restore the interrupt state now */
if (!arch_irq_disabled_regs(regs))
local_irq_enable();
- if (value < ARRAY_SIZE(facility_strings))
- facility = facility_strings[value];
- else
- facility = "unknown";
-
pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
- prefix, facility, regs->nip, regs->msr);
+ hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
if (user_mode(regs)) {
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
@@ -1341,6 +1350,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
die("Unexpected facility unavailable exception", regs, SIGABRT);
}
+#endif
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] powerpc: Rework setting up H/FSCR bit definitions
2013-08-05 7:28 [PATCH 1/3] powerpc: Rework setting up H/FSCR bit definitions Michael Neuling
2013-08-05 7:28 ` [PATCH 2/3] powerpc: Fix hypervisor facility unavaliable vector number Michael Neuling
2013-08-05 7:28 ` [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8 Michael Neuling
@ 2013-08-09 3:46 ` Michael Neuling
2 siblings, 0 replies; 9+ messages in thread
From: Michael Neuling @ 2013-08-09 3:46 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Anton Blanchard
powerpc: Rework setting up H/FSCR bit definitions
This reworks the Facility Status and Control Regsiter (FSCR) config bit
definitions so that we can access the bit numbers. This will be useful when
looking at the status in the facility unavailable interrupt.
HFSCR and FSCR versions are the same, so reuse them.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
v2: Fix bit numbers:
-#define FSCR_TM_LG 6
-#define FSCR_PM_LG 5
-#define FSCR_BHRB_LG 4
+#define FSCR_TM_LG 5
+#define FSCR_PM_LG 4
+#define FSCR_BHRB_LG 3
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a6840e4..99222e2 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -254,19 +254,28 @@
#define SPRN_HRMOR 0x139 /* Real mode offset register */
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
+/* HFSCR and FSCR bit numbers are the same */
+#define FSCR_TAR_LG 8 /* Enable Target Address Register */
+#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
+#define FSCR_TM_LG 5 /* Enable Transactional Memory */
+#define FSCR_PM_LG 4 /* Enable prob/priv access to PMU SPRs */
+#define FSCR_BHRB_LG 3 /* Enable Branch History Rolling Buffer*/
+#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */
+#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
+#define FSCR_FP_LG 0 /* Enable Floating Point */
#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
-#define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */
-#define FSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */
-#define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */
+#define FSCR_TAR __MASK(FSCR_TAR_LG)
+#define FSCR_EBB __MASK(FSCR_EBB_LG)
+#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
-#define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */
-#define HFSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */
-#define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */
-#define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
-#define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/
-#define HFSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */
-#define HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX */
-#define HFSCR_FP (1 << (63-63)) /* Enable Floating Point */
+#define HFSCR_TAR __MASK(FSCR_TAR_LG)
+#define HFSCR_EBB __MASK(FSCR_EBB_LG)
+#define HFSCR_TM __MASK(FSCR_TM_LG)
+#define HFSCR_PM __MASK(FSCR_PM_LG)
+#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
+#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
+#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
+#define HFSCR_FP __MASK(FSCR_FP_LG)
#define SPRN_TAR 0x32f /* Target Address Register */
#define SPRN_LPCR 0x13E /* LPAR Control Register */
#define LPCR_VPM0 (1ul << (63-0))
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] powerpc: Correctly context switch DSCR on POWER8
2013-08-05 11:00 ` [PATCH v2 " Michael Neuling
@ 2013-08-09 5:49 ` Michael Neuling
0 siblings, 0 replies; 9+ messages in thread
From: Michael Neuling @ 2013-08-09 5:49 UTC (permalink / raw)
To: benh; +Cc: Stephen Rothwell, linuxppc-dev, Anton Blanchard
POWER8 allows the DSCR to be accessed directly from userspace via a new SPR
number 0x3 (Rather than 0x11. DSCR SPR number 0x11 is still used on POWER8 but
like POWER7, is only accessible in HV and OS modes). Currently, we allow this
by setting H/FSCR DSCR bit on boot.
Unfortunately this doesn't work, as the kernel needs to see the DSCR change so
that it knows to no longer restore the system wide version of DSCR on context
switch (ie. to set thread.dscr_inherit).
This clears the H/FSCR DSCR bit initially. If a process then accesses the DSCR
(via SPR 0x3), it'll trap into the kernel where we set thread.dscr_inherit in
facility_unavailable_exception().
We also change _switch() so that we set or clear the H/FSCR DSCR bit based on
the thread.dscr_inherit.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
v3: remove unnecessary clearing of H/FSCR at boot.
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index ab15b8d..4674fe6 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -584,9 +584,34 @@ BEGIN_FTR_SECTION
ld r7,DSCR_DEFAULT@toc(2)
ld r0,THREAD_DSCR(r4)
cmpwi r6,0
+ li r8, FSCR_DSCR
bne 1f
ld r0,0(r7)
-1: cmpd r0,r25
+ b 3f
+1:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ or r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ or r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ b 4f
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+3:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ andc r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ andc r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+4: cmpd r0,r25
beq 2f
mtspr SPRN_DSCR,r0
2:
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index bf33c22..e435bc0 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -44,9 +44,7 @@
#include <asm/machdep.h>
#include <asm/rtas.h>
#include <asm/pmc.h>
-#ifdef CONFIG_PPC32
#include <asm/reg.h>
-#endif
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
@@ -1296,43 +1294,54 @@ void vsx_unavailable_exception(struct pt_regs *regs)
die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
}
+#ifdef CONFIG_PPC64
void facility_unavailable_exception(struct pt_regs *regs)
{
static char *facility_strings[] = {
- "FPU",
- "VMX/VSX",
- "DSCR",
- "PMU SPRs",
- "BHRB",
- "TM",
- "AT",
- "EBB",
- "TAR",
+ [FSCR_FP_LG] = "FPU",
+ [FSCR_VECVSX_LG] = "VMX/VSX",
+ [FSCR_DSCR_LG] = "DSCR",
+ [FSCR_PM_LG] = "PMU SPRs",
+ [FSCR_BHRB_LG] = "BHRB",
+ [FSCR_TM_LG] = "TM",
+ [FSCR_EBB_LG] = "EBB",
+ [FSCR_TAR_LG] = "TAR",
};
- char *facility, *prefix;
+ char *facility = "unknown";
u64 value;
+ u8 status;
+ bool hv;
- if (regs->trap == 0xf60) {
- value = mfspr(SPRN_FSCR);
- prefix = "";
- } else {
+ hv = (regs->trap == 0xf80);
+ if (hv)
value = mfspr(SPRN_HFSCR);
- prefix = "Hypervisor ";
+ else
+ value = mfspr(SPRN_FSCR);
+
+ status = value >> 56;
+ if (status == FSCR_DSCR_LG) {
+ /* User is acessing the DSCR. Set the inherit bit and allow
+ * the user to set it directly in future by setting via the
+ * H/FSCR DSCR bit.
+ */
+ current->thread.dscr_inherit = 1;
+ if (hv)
+ mtspr(SPRN_HFSCR, value | HFSCR_DSCR);
+ else
+ mtspr(SPRN_FSCR, value | FSCR_DSCR);
+ return;
}
- value = value >> 56;
+ if ((status < ARRAY_SIZE(facility_strings)) &&
+ facility_strings[status])
+ facility = facility_strings[status];
/* We restore the interrupt state now */
if (!arch_irq_disabled_regs(regs))
local_irq_enable();
- if (value < ARRAY_SIZE(facility_strings))
- facility = facility_strings[value];
- else
- facility = "unknown";
-
pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
- prefix, facility, regs->nip, regs->msr);
+ hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
if (user_mode(regs)) {
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
@@ -1341,6 +1350,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
die("Unexpected facility unavailable exception", regs, SIGABRT);
}
+#endif
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-08-09 5:49 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-08-05 7:28 [PATCH 1/3] powerpc: Rework setting up H/FSCR bit definitions Michael Neuling
2013-08-05 7:28 ` [PATCH 2/3] powerpc: Fix hypervisor facility unavaliable vector number Michael Neuling
2013-08-05 7:28 ` [PATCH 3/3] powerpc: Correctly context switch DSCR on POWER8 Michael Neuling
2013-08-05 8:42 ` Stephen Rothwell
2013-08-05 9:26 ` Michael Neuling
2013-08-05 10:16 ` Michael Neuling
2013-08-05 11:00 ` [PATCH v2 " Michael Neuling
2013-08-09 5:49 ` [PATCH v3 " Michael Neuling
2013-08-09 3:46 ` [PATCH v2 1/3] powerpc: Rework setting up H/FSCR bit definitions Michael Neuling
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