From: Michael Ellerman <mpe@ellerman.id.au>
To: Claudio Carvalho <cclaudio@linux.ibm.com>, linuxppc-dev@ozlabs.org
Cc: Ryan Grimm <grimm@linux.vnet.ibm.com>,
Madhavan Srinivasan <maddy@linux.vnet.ibm.com>,
Michael Anderson <andmike@linux.ibm.com>,
Ram Pai <linuxram@us.ibm.com>,
kvm-ppc@vger.kernel.org, Bharata B Rao <bharata@linux.ibm.com>,
Ryan Grimm <grimm@linux.ibm.com>,
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>,
Thiago Bauermann <bauerman@linux.ibm.com>,
Anshuman Khandual <khandual@linux.vnet.ibm.com>
Subject: Re: [PATCH v4 4/8] KVM: PPC: Ultravisor: Use UV_WRITE_PATE ucall to register a PATE
Date: Fri, 19 Jul 2019 12:25:54 +1000 [thread overview]
Message-ID: <87ef2m92vh.fsf@concordia.ellerman.id.au> (raw)
In-Reply-To: <6688060f-3744-cae5-635e-f1ee3ff48c19@linux.ibm.com>
Claudio Carvalho <cclaudio@linux.ibm.com> writes:
> On 7/11/19 9:57 AM, Michael Ellerman wrote:
>>> static pmd_t *get_pmd_from_cache(struct mm_struct *mm)
>>> diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c
>>> index 8904aa1243d8..da6a6b76a040 100644
>>> --- a/arch/powerpc/mm/book3s64/radix_pgtable.c
>>> +++ b/arch/powerpc/mm/book3s64/radix_pgtable.c
>>> @@ -656,8 +656,10 @@ void radix__early_init_mmu_secondary(void)
>>> lpcr = mfspr(SPRN_LPCR);
>>> mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
>>>
>>> - mtspr(SPRN_PTCR,
>>> - __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
>>> + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
>>> + mtspr(SPRN_PTCR, __pa(partition_tb) |
>>> + (PATB_SIZE_SHIFT - 12));
>>> +
>>> radix_init_amor();
>>> }
>>>
>>> @@ -673,7 +675,8 @@ void radix__mmu_cleanup_all(void)
>>> if (!firmware_has_feature(FW_FEATURE_LPAR)) {
>>> lpcr = mfspr(SPRN_LPCR);
>>> mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
>>> - mtspr(SPRN_PTCR, 0);
>>> + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
>>> + mtspr(SPRN_PTCR, 0);
>>> powernv_set_nmmu_ptcr(0);
>>> radix__flush_tlb_all();
>>> }
>> There's four of these case where we skip touching the PTCR, which is
>> right on the borderline of warranting an accessor. I guess we can do it
>> as a cleanup later.
>
> I agree.
>
> Since the kernel doesn't need to access a big number of ultravisor
> privileged registers, maybe we can define mtspr_<reg> and mfspr_<reg>
> inline functions that in ultravisor.h that skip touching the register if an
> ultravisor is present and and the register is ultravisor privileged. Thus,
> we don't need to replicate comments and that also would make it easier for
> developers to know what are the ultravisor privileged registers.
>
> Something like this:
>
> --- a/arch/powerpc/include/asm/ultravisor.h
> +++ b/arch/powerpc/include/asm/ultravisor.h
> @@ -10,10 +10,21 @@
>
> #include <asm/ultravisor-api.h>
> #include <asm/asm-prototypes.h>
> +#include <asm/reg.h>
>
> int early_init_dt_scan_ultravisor(unsigned long node, const char *uname,
> int depth, void *data);
>
> +static inline void mtspr_ptcr(unsigned long val)
> +{
> + /*
> + * If the ultravisor firmware is present, it maintains the partition
> + * table. PTCR becomes ultravisor privileged only for writing.
> + */
> + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
> + mtspr(SPRN_PTCR, val);
> +}
+
> static inline int uv_register_pate(u64 lpid, u64 dw0, u64 dw1)
> {
> return ucall_norets(UV_WRITE_PATE, lpid, dw0, dw1);
> diff --git a/arch/powerpc/mm/book3s64/pgtable.c
> b/arch/powerpc/mm/book3s64/pgtable.c
> index e1bbc48e730f..25156f9dfde8 100644
> --- a/arch/powerpc/mm/book3s64/pgtable.c
> +++ b/arch/powerpc/mm/book3s64/pgtable.c
> @@ -220,7 +220,7 @@ void __init mmu_partition_table_init(void)
> * 64 K size.
> */
> ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);
> - mtspr(SPRN_PTCR, ptcr);
> + mtspr_ptcr(ptcr);
> powernv_set_nmmu_ptcr(ptcr);
> }
>
> What do you think?
I don't think that's actually clearer.
If the logic was always:
if (ultravisor)
do_ucall()
else
mtspr()
Then a wrapper called eg. set_ptcr() would make sense.
But because in some cases you do a ucall and some you don't, I don't
think it helps to hide that in an accessor like above.
That is confusing to a reader who sees all this code to setup a value
and then the write to PTCR does nothing.
And in fact you didn't explain why it's OK for those cases to not do the
write at all.
> An alternative could be to change the mtspr() and mfspr() macros as we
> proposed in the v1, but access to non-ultravisor privileged registers would
> be performance impacted because we always would need to check if the
> register is one of the few ultravisor registers that the kernel needs to
> access.
Yeah that and it would be very confusing to a reader who sees:
ptcr = ...;
mtspr(SPRN_PTCR, ptcr);
...
And then they discover the mtspr does *nothing* when the Ultravisor is
enabled.
cheers
next prev parent reply other threads:[~2019-07-19 2:28 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 20:08 [PATCH v4 0/8] kvmppc: Paravirtualize KVM to support ultravisor Claudio Carvalho
2019-06-28 20:08 ` [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit Claudio Carvalho
2019-07-08 17:38 ` janani
2019-07-11 12:57 ` Michael Ellerman
2019-07-12 0:59 ` Nicholas Piggin
2019-07-12 0:57 ` Nicholas Piggin
2019-07-12 6:29 ` Michael Ellerman
2019-07-12 21:07 ` Claudio Carvalho
2019-06-28 20:08 ` [PATCH v4 2/8] powerpc: Introduce FW_FEATURE_ULTRAVISOR Claudio Carvalho
2019-07-08 17:40 ` janani
2019-07-11 12:57 ` Michael Ellerman
2019-07-12 18:01 ` Claudio Carvalho
2019-07-15 4:10 ` Michael Ellerman
2019-06-28 20:08 ` [PATCH v4 3/8] KVM: PPC: Ultravisor: Add generic ultravisor call handler Claudio Carvalho
2019-07-08 17:55 ` janani
2019-07-11 12:57 ` Michael Ellerman
2019-07-13 17:42 ` Claudio Carvalho
2019-07-15 4:46 ` Michael Ellerman
2019-07-12 1:18 ` Nicholas Piggin
2019-06-28 20:08 ` [PATCH v4 4/8] KVM: PPC: Ultravisor: Use UV_WRITE_PATE ucall to register a PATE Claudio Carvalho
2019-07-08 17:57 ` janani
2019-07-11 12:57 ` Michael Ellerman
2019-07-17 14:59 ` Ryan Grimm
2019-07-18 21:25 ` Claudio Carvalho
2019-07-19 2:25 ` Michael Ellerman [this message]
2019-06-28 20:08 ` [PATCH v4 5/8] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache Claudio Carvalho
2019-07-01 5:54 ` Alexey Kardashevskiy
2019-07-08 20:05 ` Claudio Carvalho
2019-07-08 19:54 ` janani
2019-07-10 17:09 ` Ram Pai
2019-06-28 20:08 ` [PATCH v4 6/8] KVM: PPC: Ultravisor: Restrict LDBAR access Claudio Carvalho
2019-07-01 5:54 ` Alexey Kardashevskiy
2019-07-01 6:17 ` maddy
2019-07-01 6:30 ` Alexey Kardashevskiy
2019-07-01 6:46 ` Ram Pai
2019-07-13 17:56 ` Claudio Carvalho
2019-07-08 20:22 ` janani
2019-07-11 12:57 ` Michael Ellerman
2019-07-15 0:38 ` Claudio Carvalho
2019-06-28 20:08 ` [PATCH v4 7/8] KVM: PPC: Ultravisor: Enter a secure guest Claudio Carvalho
2019-07-08 20:53 ` janani
2019-07-08 20:52 ` Claudio Carvalho
2019-07-11 12:57 ` Michael Ellerman
2019-07-18 2:47 ` Sukadev Bhattiprolu
2019-07-22 11:05 ` Michael Ellerman
2019-07-12 2:03 ` Nicholas Piggin
2019-06-28 20:08 ` [PATCH v4 8/8] KVM: PPC: Ultravisor: Check for MSR_S during hv_reset_msr Claudio Carvalho
2019-07-08 20:54 ` janani
2019-07-11 12:57 ` Michael Ellerman
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