* [PATCH 1/2] powerpc: document the FSL MPIC message register binding
@ 2012-02-17 2:49 Jia Hongtao
2012-02-17 2:49 ` [PATCH 2/2] powerpc: add support for MPIC message register API Jia Hongtao
2012-02-17 15:50 ` [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register binding Yoder Stuart-B08248
0 siblings, 2 replies; 6+ messages in thread
From: Jia Hongtao @ 2012-02-17 2:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: meador_inge, b38951
This binding documents how the message register blocks found in some FSL
MPIC implementations shall be represented in a device tree.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
.../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 62 ++++++++++++++++++++
1 files changed, 62 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
new file mode 100644
index 0000000..b4ae70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
@@ -0,0 +1,62 @@
+* FSL MPIC Message Registers
+
+This binding specifies what properties must be available in the device tree
+representation of the message register blocks found in some FSL MPIC
+implementations.
+
+Required properties:
+
+ - compatible: Specifies the compatibility list for the message register
+ block. The type shall be <string> and the value shall be of the form
+ "fsl,mpic-v<version>-msgr", where <version> is the version number of
+ the MPIC containing the message registers.
+
+ - reg: Specifies the base physical address(s) and size(s) of the
+ message register block's addressable register space. The type shall be
+ <prop-encoded-array>.
+
+ - interrupts: Specifies a list of interrupt source and level-sense pairs.
+ The type shall be <prop-encoded-array>. The length shall be equal to
+ the number of registers that are available for receiving interrupts.
+
+Optional properties:
+
+ - mpic-msgr-receive-mask: Specifies what registers in the containing block
+ are allowed to receive interrupts. The value is a bit mask where a set
+ bit at bit 'n' indicates that message register 'n' can receive interrupts.
+ The type shall be <prop-encoded-array>. If not present, then all of
+ the message registers in the block are available.
+
+Aliases:
+
+ An alias should be created for every message register block. They are not
+ required, though. However, a particular implementation of this binding
+ may require aliases to be present. Aliases are of the form
+ 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number.
+ Numbers shall start at 0.
+
+Example:
+
+ aliases {
+ mpic-msgr-block0 = &mpic_msgr_block0;
+ mpic-msgr-block1 = &mpic_msgr_block1;
+ };
+
+ mpic_msgr_block0: mpic-msgr-block@41400 {
+ compatible = "fsl,mpic-v3.1-msgr";
+ reg = <0x41400 0x200>;
+ // Message registers 0 and 2 in this block can receive interrupts on
+ // sources 0xb0 and 0xb2, respectively.
+ interrupts = <0xb0 2 0xb2 2>;
+ mpic-msgr-receive-mask = <0x5>;
+ };
+
+ mpic_msgr_block1: mpic-msgr-block@42400 {
+ compatible = "fsl,mpic-v3.1-msgr";
+ reg = <0x42400 0x200>;
+ // Message registers 0 and 2 in this block can receive interrupts on
+ // sources 0xb4 and 0xb6, respectively.
+ interrupts = <0xb4 2 0xb6 2>;
+ mpic-msgr-receive-mask = <0x5>;
+ };
+
--
1.7.5.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] powerpc: add support for MPIC message register API
2012-02-17 2:49 [PATCH 1/2] powerpc: document the FSL MPIC message register binding Jia Hongtao
@ 2012-02-17 2:49 ` Jia Hongtao
2012-03-21 17:21 ` Kumar Gala
2012-02-17 15:50 ` [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register binding Yoder Stuart-B08248
1 sibling, 1 reply; 6+ messages in thread
From: Jia Hongtao @ 2012-02-17 2:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: meador_inge, b38951
Some MPIC implementations contain one or more blocks of message registers
that are used to send messages between cores via IPIs. A simple API has
been added to access (get/put, read, write, etc ...) these message registers.
The available message registers are initially discovered via nodes in the
device tree. A separate commit contains a binding for the message register
nodes.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
This patch is an update for : http://patchwork.ozlabs.org/patch/98075/
Meador Inge addressed the following points from Ben's feedback:
* Drop the 'mpic_msgr.msr' field.
* Drop the 'mpic_msgr.mer' field in favor of address arithmetic off of 'mpic_msgr.addr'.
* Document the API.
* Disable MPIC register in 'mpic_msgr_put'.
* Put locking in 'mpic_msgr_disable'.
* s/EXPORT_SYMBOL/EXPORT_SYMBOL_GPL/g.
* Make 'mpic_msgr_write' and 'mpic_msgr_read' 'static inline'.
I just fixed the checkpatch errors and addressed the following item:
* In 'mpic_msgr_set_destination' have a wrapper that goes from Linux
CPU number to HW CPU number.
arch/powerpc/include/asm/mpic_msgr.h | 132 ++++++++++++++++
arch/powerpc/platforms/Kconfig | 8 +
arch/powerpc/sysdev/Makefile | 2 +
arch/powerpc/sysdev/mpic_msgr.c | 282 ++++++++++++++++++++++++++++++++++
4 files changed, 424 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/mpic_msgr.h
create mode 100644 arch/powerpc/sysdev/mpic_msgr.c
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
new file mode 100644
index 0000000..3ec37dc
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#ifndef _ASM_MPIC_MSGR_H
+#define _ASM_MPIC_MSGR_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+struct mpic_msgr {
+ u32 __iomem *base;
+ u32 __iomem *mer;
+ int irq;
+ unsigned char in_use;
+ raw_spinlock_t lock;
+ int num;
+};
+
+/* Get a message register
+ *
+ * @reg_num: the MPIC message register to get
+ *
+ * A pointer to the message register is returned. If
+ * the message register asked for is already in use, then
+ * EBUSY is returned. If the number given is not associated
+ * with an actual message register, then ENODEV is returned.
+ * Successfully getting the register marks it as in use.
+ */
+extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
+
+/* Relinquish a message register
+ *
+ * @msgr: the message register to return
+ *
+ * Disables the given message register and marks it as free.
+ * After this call has completed successully the message
+ * register is available to be acquired by a call to
+ * mpic_msgr_get.
+ */
+extern void mpic_msgr_put(struct mpic_msgr *msgr);
+
+/* Enable a message register
+ *
+ * @msgr: the message register to enable
+ *
+ * The given message register is enabled for sending
+ * messages.
+ */
+extern void mpic_msgr_enable(struct mpic_msgr *msgr);
+
+/* Disable a message register
+ *
+ * @msgr: the message register to disable
+ *
+ * The given message register is disabled for sending
+ * messages.
+ */
+extern void mpic_msgr_disable(struct mpic_msgr *msgr);
+
+/* Write a message to a message register
+ *
+ * @msgr: the message register to write to
+ * @message: the message to write
+ *
+ * The given 32-bit message is written to the given message
+ * register. Writing to an enabled message registers fires
+ * an interrupt.
+ */
+static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
+{
+ out_be32(msgr->base, message);
+}
+
+/* Read a message from a message register
+ *
+ * @msgr: the message register to read from
+ *
+ * Returns the 32-bit value currently in the given message register.
+ * Upon reading the register any interrupts for that register are
+ * cleared.
+ */
+static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
+{
+ return in_be32(msgr->base);
+}
+
+/* Clear a message register
+ *
+ * @msgr: the message register to clear
+ *
+ * Clears any interrupts associated with the given message register.
+ */
+static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
+{
+ (void) mpic_msgr_read(msgr);
+}
+
+/* Set the destination CPU for the message register
+ *
+ * @msgr: the message register whose destination is to be set
+ * @cpu_num: the Linux CPU number to bind the message register to
+ *
+ * Note that the CPU number given is the CPU number used by the kernel
+ * and *not* the actual hardware CPU number.
+ */
+static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
+ u32 cpu_num)
+{
+ out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num));
+}
+
+/* Get the IRQ number for the message register
+ * @msgr: the message register whose IRQ is to be returned
+ *
+ * Returns the IRQ number associated with the given message register.
+ * NO_IRQ is returned if this message register is not capable of
+ * receiving interrupts. What message register can and cannot receive
+ * interrupts is specified in the device tree for the system.
+ */
+static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr)
+{
+ return msgr->irq;
+}
+
+#endif
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index eb294a6..fc4f5580 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -87,6 +87,14 @@ config MPIC_WEIRD
bool
default n
+config MPIC_MSGR
+ bool "MPIC message register support"
+ depends on MPIC
+ default n
+ help
+ Enables support for the MPIC message registers. These
+ registers are used for inter-processor communication.
+
config PPC_I8259
bool
default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5e37b47..1951dc7 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,8 @@ ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
+mpic-msgr-obj-$(CONFIG_MPIC_MSGR) += mpic_msgr.o
+obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o
fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
new file mode 100644
index 0000000..6e7fa38
--- /dev/null
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
+ *
+ * Some ideas based on un-pushed work done by Vivek Mahajan, Jason Jin, and
+ * Mingkai Hu from Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#include <linux/list.h>
+#include <linux/of_platform.h>
+#include <linux/errno.h>
+#include <asm/prom.h>
+#include <asm/hw_irq.h>
+#include <asm/ppc-pci.h>
+#include <asm/mpic_msgr.h>
+
+#define MPIC_MSGR_REGISTERS_PER_BLOCK 4
+#define MPIC_MSGR_STRIDE 0x10
+#define MPIC_MSGR_MER_OFFSET 0x100
+#define MSGR_INUSE 0
+#define MSGR_FREE 1
+
+static struct mpic_msgr **mpic_msgrs;
+static unsigned int mpic_msgr_count;
+
+static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
+{
+ out_be32(msgr->mer, value);
+}
+
+static inline u32 _mpic_msgr_mer_read(struct mpic_msgr *msgr)
+{
+ return in_be32(msgr->mer);
+}
+
+static inline void _mpic_msgr_disable(struct mpic_msgr *msgr)
+{
+ u32 mer = _mpic_msgr_mer_read(msgr);
+
+ _mpic_msgr_mer_write(msgr, mer & ~(1 << msgr->num));
+}
+
+struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
+{
+ unsigned long flags;
+ struct mpic_msgr *msgr;
+
+ /* Assume busy until proven otherwise. */
+ msgr = ERR_PTR(-EBUSY);
+
+ if (reg_num >= mpic_msgr_count)
+ return ERR_PTR(-ENODEV);
+
+ raw_spin_lock_irqsave(&msgr->lock, flags);
+ if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
+ msgr = mpic_msgrs[reg_num];
+ msgr->in_use = MSGR_INUSE;
+ }
+ raw_spin_unlock_irqrestore(&msgr->lock, flags);
+
+ return msgr;
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_get);
+
+void mpic_msgr_put(struct mpic_msgr *msgr)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&msgr->lock, flags);
+ msgr->in_use = MSGR_FREE;
+ _mpic_msgr_disable(msgr);
+ raw_spin_unlock_irqrestore(&msgr->lock, flags);
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_put);
+
+void mpic_msgr_enable(struct mpic_msgr *msgr)
+{
+ unsigned long flags;
+ u32 mer;
+
+ raw_spin_lock_irqsave(&msgr->lock, flags);
+ mer = _mpic_msgr_mer_read(msgr);
+ _mpic_msgr_mer_write(msgr, mer | (1 << msgr->num));
+ raw_spin_unlock_irqrestore(&msgr->lock, flags);
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_enable);
+
+void mpic_msgr_disable(struct mpic_msgr *msgr)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&msgr->lock, flags);
+ _mpic_msgr_disable(msgr);
+ raw_spin_unlock_irqrestore(&msgr->lock, flags);
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_disable);
+
+/* The following three functions are used to compute the order and number of
+ * the message register blocks. They are clearly very inefficent. However,
+ * they are called *only* a few times during device initialization.
+ */
+static unsigned int mpic_msgr_number_of_blocks(void)
+{
+ unsigned int count;
+ struct device_node *aliases;
+
+ count = 0;
+ aliases = of_find_node_by_name(NULL, "aliases");
+
+ if (aliases) {
+ char buf[32];
+
+ for (;;) {
+ snprintf(buf, sizeof(buf), "mpic-msgr-block%d", count);
+ if (!of_find_property(aliases, buf, NULL))
+ break;
+
+ count += 1;
+ }
+ }
+
+ return count;
+}
+
+static unsigned int mpic_msgr_number_of_registers(void)
+{
+ return mpic_msgr_number_of_blocks() * MPIC_MSGR_REGISTERS_PER_BLOCK;
+}
+
+static int mpic_msgr_block_number(struct device_node *node)
+{
+ struct device_node *aliases;
+ unsigned int index, number_of_blocks;
+ char buf[64];
+
+ number_of_blocks = mpic_msgr_number_of_blocks();
+ aliases = of_find_node_by_name(NULL, "aliases");
+ if (!aliases)
+ return -1;
+
+ for (index = 0; index < number_of_blocks; ++index) {
+ struct property *prop;
+
+ snprintf(buf, sizeof(buf), "mpic-msgr-block%d", index);
+ prop = of_find_property(aliases, buf, NULL);
+ if (node == of_find_node_by_path(prop->value))
+ break;
+ }
+
+ return index == number_of_blocks ? -1 : index;
+}
+
+/* The probe function for a single message register block.
+ */
+static __devinit int mpic_msgr_probe(struct platform_device *dev)
+{
+ void __iomem *msgr_block_addr;
+ int block_number;
+ struct resource rsrc;
+ unsigned int i;
+ unsigned int irq_index;
+ struct device_node *np = dev->dev.of_node;
+ unsigned int receive_mask;
+ const unsigned int *prop;
+
+ if (!np) {
+ dev_err(&dev->dev, "Device OF-Node is NULL");
+ return -EFAULT;
+ }
+
+ /* Allocate the message register array upon the first device
+ * registered.
+ */
+ if (!mpic_msgrs) {
+ mpic_msgr_count = mpic_msgr_number_of_registers();
+ dev_info(&dev->dev, "Found %d message registers\n",
+ mpic_msgr_count);
+
+ mpic_msgrs = kzalloc(sizeof(struct mpic_msgr) * mpic_msgr_count,
+ GFP_KERNEL);
+ if (!mpic_msgrs) {
+ dev_err(&dev->dev,
+ "No memory for message register blocks\n");
+ return -ENOMEM;
+ }
+ }
+ dev_info(&dev->dev, "Of-device full name %s\n", np->full_name);
+
+ /* IO map the message register block. */
+ of_address_to_resource(np, 0, &rsrc);
+ msgr_block_addr = ioremap(rsrc.start, rsrc.end - rsrc.start);
+ if (!msgr_block_addr) {
+ dev_err(&dev->dev, "Failed to iomap MPIC message registers");
+ return -EFAULT;
+ }
+
+ /* Ensure the block has a defined order. */
+ block_number = mpic_msgr_block_number(np);
+ if (block_number < 0) {
+ dev_err(&dev->dev,
+ "Failed to find message register block alias\n");
+ return -ENODEV;
+ }
+ dev_info(&dev->dev, "Setting up message register block %d\n",
+ block_number);
+
+ /* Grab the receive mask which specifies what registers can receive
+ * interrupts.
+ */
+ prop = of_get_property(np, "mpic-msgr-receive-mask", NULL);
+ receive_mask = (prop) ? *prop : 0xF;
+
+ /* Build up the appropriate message register data structures. */
+ for (i = 0, irq_index = 0; i < MPIC_MSGR_REGISTERS_PER_BLOCK; ++i) {
+ struct mpic_msgr *msgr;
+ unsigned int reg_number;
+
+ msgr = kzalloc(sizeof(struct mpic_msgr), GFP_KERNEL);
+ if (!msgr) {
+ dev_err(&dev->dev, "No memory for message register\n");
+ return -ENOMEM;
+ }
+
+ reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
+ msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
+ msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
+ msgr->in_use = MSGR_FREE;
+ msgr->num = i;
+ raw_spin_lock_init(&msgr->lock);
+
+ if (receive_mask & (1 << i)) {
+ struct resource irq;
+
+ if (of_irq_to_resource(np, irq_index, &irq) == NO_IRQ) {
+ dev_err(&dev->dev,
+ "Missing interrupt specifier");
+ kfree(msgr);
+ return -EFAULT;
+ }
+ msgr->irq = irq.start;
+ irq_index += 1;
+ } else {
+ msgr->irq = NO_IRQ;
+ }
+
+ mpic_msgrs[reg_number] = msgr;
+ mpic_msgr_disable(msgr);
+ dev_info(&dev->dev, "Register %d initialized: irq %d\n",
+ reg_number, msgr->irq);
+
+ }
+
+ return 0;
+}
+
+static const struct of_device_id mpic_msgr_ids[] = {
+ {
+ .compatible = "fsl,mpic-v3.1-msgr",
+ .data = NULL,
+ },
+ {}
+};
+
+static struct platform_driver mpic_msgr_driver = {
+ .driver = {
+ .name = "mpic-msgr",
+ .owner = THIS_MODULE,
+ .of_match_table = mpic_msgr_ids,
+ },
+ .probe = mpic_msgr_probe,
+};
+
+static __init int mpic_msgr_init(void)
+{
+ return platform_driver_register(&mpic_msgr_driver);
+}
+subsys_initcall(mpic_msgr_init);
--
1.7.5.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register binding
2012-02-17 2:49 [PATCH 1/2] powerpc: document the FSL MPIC message register binding Jia Hongtao
2012-02-17 2:49 ` [PATCH 2/2] powerpc: add support for MPIC message register API Jia Hongtao
@ 2012-02-17 15:50 ` Yoder Stuart-B08248
2012-02-18 0:47 ` Scott Wood
1 sibling, 1 reply; 6+ messages in thread
From: Yoder Stuart-B08248 @ 2012-02-17 15:50 UTC (permalink / raw)
To: Jia Hongtao-B38951, linuxppc-dev; +Cc: meador_inge, Li Yang-R58472
> -----Original Message-----
> From: linuxppc-release-bounces@linux.freescale.net [mailto:linuxppc-relea=
se-
> bounces@linux.freescale.net] On Behalf Of Jia Hongtao-B38951
> Sent: Thursday, February 16, 2012 8:49 PM
> To: linuxppc-dev@lists.ozlabs.org
> Cc: meador_inge@mentor.com; Li Yang-R58472; Jia Hongtao-B38951
> Subject: [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC me=
ssage register
> binding
>=20
> This binding documents how the message register blocks found in some FSL =
MPIC implementations
> shall be represented in a device tree.
>=20
> Signed-off-by: Meador Inge <meador_inge@mentor.com>
> Signed-off-by: Jia Hongtao <B38951@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> .../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 62 ++++++++++++++=
++++++
> 1 files changed, 62 insertions(+), 0 deletions(-) create mode 100644
> Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
>=20
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
> b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
> new file mode 100644
> index 0000000..b4ae70e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
> @@ -0,0 +1,62 @@
> +* FSL MPIC Message Registers
> +
> +This binding specifies what properties must be available in the device
> +tree representation of the message register blocks found in some FSL
> +MPIC implementations.
> +
> +Required properties:
> +
> + - compatible: Specifies the compatibility list for the message regis=
ter
> + block. The type shall be <string> and the value shall be of the f=
orm
> + "fsl,mpic-v<version>-msgr", where <version> is the version number =
of
> + the MPIC containing the message registers.
The type for compatibles is a <string-list>.
> + - reg: Specifies the base physical address(s) and size(s) of the
> + message register block's addressable register space. The type sha=
ll be
> + <prop-encoded-array>.
> +
> + - interrupts: Specifies a list of interrupt source and level-sense p=
airs.
> + The type shall be <prop-encoded-array>. The length shall be equal=
to
> + the number of registers that are available for receiving interrupt=
s.
How many interrupts are there? If more than 1, this is where
you need to specify what each interrupt is for.
> +Optional properties:
> +
> + - mpic-msgr-receive-mask: Specifies what registers in the containing=
block
> + are allowed to receive interrupts. The value is a bit mask where =
a set
> + bit at bit 'n' indicates that message register 'n' can receive int=
errupts.
> + The type shall be <prop-encoded-array>. If not present, then all =
of
> + the message registers in the block are available.
Your example implies that this is 1 32-bit cell. If that is the case then
this really should be of type '<u32>'.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register binding
2012-02-17 15:50 ` [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register binding Yoder Stuart-B08248
@ 2012-02-18 0:47 ` Scott Wood
2012-02-20 14:00 ` Yoder Stuart-B08248
0 siblings, 1 reply; 6+ messages in thread
From: Scott Wood @ 2012-02-18 0:47 UTC (permalink / raw)
To: Yoder Stuart-B08248
Cc: meador_inge, linuxppc-dev, Li Yang-R58472, Jia Hongtao-B38951
On 02/17/2012 09:50 AM, Yoder Stuart-B08248 wrote:
>
>
>> -----Original Message-----
>> From: linuxppc-release-bounces@linux.freescale.net [mailto:linuxppc-release-
>> bounces@linux.freescale.net] On Behalf Of Jia Hongtao-B38951
>> Sent: Thursday, February 16, 2012 8:49 PM
>> To: linuxppc-dev@lists.ozlabs.org
>> Cc: meador_inge@mentor.com; Li Yang-R58472; Jia Hongtao-B38951
>> Subject: [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register
>> binding
>>
>> This binding documents how the message register blocks found in some FSL MPIC implementations
>> shall be represented in a device tree.
>>
>> Signed-off-by: Meador Inge <meador_inge@mentor.com>
>> Signed-off-by: Jia Hongtao <B38951@freescale.com>
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> ---
>> .../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 62 ++++++++++++++++++++
>> 1 files changed, 62 insertions(+), 0 deletions(-) create mode 100644
>> Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
>>
>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
>> b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
>> new file mode 100644
>> index 0000000..b4ae70e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
>> @@ -0,0 +1,62 @@
>> +* FSL MPIC Message Registers
>> +
>> +This binding specifies what properties must be available in the device
>> +tree representation of the message register blocks found in some FSL
>> +MPIC implementations.
>> +
>> +Required properties:
>> +
>> + - compatible: Specifies the compatibility list for the message register
>> + block. The type shall be <string> and the value shall be of the form
>> + "fsl,mpic-v<version>-msgr", where <version> is the version number of
>> + the MPIC containing the message registers.
>
> The type for compatibles is a <string-list>.
>
>> + - reg: Specifies the base physical address(s) and size(s) of the
>> + message register block's addressable register space. The type shall be
>> + <prop-encoded-array>.
>> +
>> + - interrupts: Specifies a list of interrupt source and level-sense pairs.
>> + The type shall be <prop-encoded-array>. The length shall be equal to
>> + the number of registers that are available for receiving interrupts.
>
> How many interrupts are there? If more than 1, this is where
> you need to specify what each interrupt is for.
They aren't "for" anything in particular -- each interrupt is associated
with a message register. The binding does say that the number of
interrupts corresponds to the bits set in the receive mask.
>> +Optional properties:
>> +
>> + - mpic-msgr-receive-mask: Specifies what registers in the containing block
>> + are allowed to receive interrupts. The value is a bit mask where a set
>> + bit at bit 'n' indicates that message register 'n' can receive interrupts.
>> + The type shall be <prop-encoded-array>. If not present, then all of
>> + the message registers in the block are available.
>
> Your example implies that this is 1 32-bit cell. If that is the case then
> this really should be of type '<u32>'.
And should clarify that "bit 'n'" means numbered from LSB, given how PPC
hardware docs tend to use the opposite convention.
-Scott
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register binding
2012-02-18 0:47 ` Scott Wood
@ 2012-02-20 14:00 ` Yoder Stuart-B08248
0 siblings, 0 replies; 6+ messages in thread
From: Yoder Stuart-B08248 @ 2012-02-20 14:00 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: meador_inge, linuxppc-dev, Li Yang-R58472, Jia Hongtao-B38951
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Friday, February 17, 2012 6:48 PM
> To: Yoder Stuart-B08248
> Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; meador_inge@mentor=
.com; Li Yang-R58472
> Subject: Re: [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPI=
C message register
> binding
>=20
> On 02/17/2012 09:50 AM, Yoder Stuart-B08248 wrote:
> >
> >
> >> -----Original Message-----
> >> From: linuxppc-release-bounces@linux.freescale.net
> >> [mailto:linuxppc-release- bounces@linux.freescale.net] On Behalf Of
> >> Jia Hongtao-B38951
> >> Sent: Thursday, February 16, 2012 8:49 PM
> >> To: linuxppc-dev@lists.ozlabs.org
> >> Cc: meador_inge@mentor.com; Li Yang-R58472; Jia Hongtao-B38951
> >> Subject: [linuxppc-release] [PATCH 1/2] powerpc: document the FSL
> >> MPIC message register binding
> >>
> >> This binding documents how the message register blocks found in some
> >> FSL MPIC implementations shall be represented in a device tree.
> >>
> >> Signed-off-by: Meador Inge <meador_inge@mentor.com>
> >> Signed-off-by: Jia Hongtao <B38951@freescale.com>
> >> Signed-off-by: Li Yang <leoli@freescale.com>
> >> ---
> >> .../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 62 +++++++++++=
+++++++++
> >> 1 files changed, 62 insertions(+), 0 deletions(-) create mode
> >> 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
> >> b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
> >> new file mode 100644
> >> index 0000000..b4ae70e
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
> >> @@ -0,0 +1,62 @@
> >> +* FSL MPIC Message Registers
> >> +
> >> +This binding specifies what properties must be available in the
> >> +device tree representation of the message register blocks found in
> >> +some FSL MPIC implementations.
> >> +
> >> +Required properties:
> >> +
> >> + - compatible: Specifies the compatibility list for the message re=
gister
> >> + block. The type shall be <string> and the value shall be of th=
e form
> >> + "fsl,mpic-v<version>-msgr", where <version> is the version numb=
er of
> >> + the MPIC containing the message registers.
> >
> > The type for compatibles is a <string-list>.
> >
> >> + - reg: Specifies the base physical address(s) and size(s) of the
> >> + message register block's addressable register space. The type =
shall be
> >> + <prop-encoded-array>.
> >> +
> >> + - interrupts: Specifies a list of interrupt source and level-sens=
e pairs.
> >> + The type shall be <prop-encoded-array>. The length shall be eq=
ual to
> >> + the number of registers that are available for receiving interr=
upts.
> >
> > How many interrupts are there? If more than 1, this is where
> > you need to specify what each interrupt is for.
>=20
> They aren't "for" anything in particular -- each interrupt is associated =
with a message
> register. The binding does say that the number of interrupts corresponds=
to the bits set in
> the receive mask.
Then make that clear, it also should use the term 'interrupt-specifier'
not 'interrupt source and level-sense pairs', which implies a particular
parent interrupt controller configuration.
Stuart
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] powerpc: add support for MPIC message register API
2012-02-17 2:49 ` [PATCH 2/2] powerpc: add support for MPIC message register API Jia Hongtao
@ 2012-03-21 17:21 ` Kumar Gala
0 siblings, 0 replies; 6+ messages in thread
From: Kumar Gala @ 2012-03-21 17:21 UTC (permalink / raw)
To: Jia Hongtao; +Cc: meador_inge, linuxppc-dev
On Feb 16, 2012, at 8:49 PM, Jia Hongtao wrote:
> Some MPIC implementations contain one or more blocks of message =
registers
> that are used to send messages between cores via IPIs. A simple API =
has
> been added to access (get/put, read, write, etc ...) these message =
registers.
> The available message registers are initially discovered via nodes in =
the
> device tree. A separate commit contains a binding for the message =
register
> nodes.
>=20
> Signed-off-by: Meador Inge <meador_inge@mentor.com>
> Signed-off-by: Jia Hongtao <B38951@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> This patch is an update for : http://patchwork.ozlabs.org/patch/98075/
>=20
> Meador Inge addressed the following points from Ben's feedback:
> * Drop the 'mpic_msgr.msr' field.
> * Drop the 'mpic_msgr.mer' field in favor of address arithmetic off of =
'mpic_msgr.addr'.
> * Document the API.
> * Disable MPIC register in 'mpic_msgr_put'.
> * Put locking in 'mpic_msgr_disable'.
> * s/EXPORT_SYMBOL/EXPORT_SYMBOL_GPL/g.
> * Make 'mpic_msgr_write' and 'mpic_msgr_read' 'static inline'.
>=20
> I just fixed the checkpatch errors and addressed the following item:
> * In 'mpic_msgr_set_destination' have a wrapper that goes from Linux
> CPU number to HW CPU number.
>=20
> arch/powerpc/include/asm/mpic_msgr.h | 132 ++++++++++++++++
> arch/powerpc/platforms/Kconfig | 8 +
> arch/powerpc/sysdev/Makefile | 2 +
> arch/powerpc/sysdev/mpic_msgr.c | 282 =
++++++++++++++++++++++++++++++++++
> 4 files changed, 424 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/include/asm/mpic_msgr.h
> create mode 100644 arch/powerpc/sysdev/mpic_msgr.c
applied
- k=
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-03-21 17:21 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-02-17 2:49 [PATCH 1/2] powerpc: document the FSL MPIC message register binding Jia Hongtao
2012-02-17 2:49 ` [PATCH 2/2] powerpc: add support for MPIC message register API Jia Hongtao
2012-03-21 17:21 ` Kumar Gala
2012-02-17 15:50 ` [linuxppc-release] [PATCH 1/2] powerpc: document the FSL MPIC message register binding Yoder Stuart-B08248
2012-02-18 0:47 ` Scott Wood
2012-02-20 14:00 ` Yoder Stuart-B08248
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