RE: [RFC 2/2] powerpc/cputable: add wait feature for CPU kernel features

RE: [RFC 2/2] powerpc/cputable: add wait feature for CPU kernel features

[Wang Dongsheng-B40534]

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Re: [RFC 2/2] powerpc/cputable: add wait feature for CPU kernel features

[Benjamin Herrenschmidt]

On Wed, 2013-07-10 at 09:29 +0000, Wang Dongsheng-B40534 wrote:
> > 
> Yes, the wait instructions is for cpu idle, It will be make cpu into
> low power mode, like DOZE & NAP. Each thread have this.

I don't need you to tell me by email, I need you to put a proper
comment in the patch submission so it ends up in the repository
and if possible a bit more detailed than that.

Ben.

RE: [RFC 2/2] powerpc/cputable: add wait feature for CPU kernel features

[Wang Dongsheng-B40534]

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RE: [RFC 2/2] powerpc/cputable: add wait feature for CPU kernel features

[Wang Dongsheng-B40534]

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Tuesday, July 30, 2013 1:27 AM
> To: Wang Dongsheng-B40534
> Cc: benh@kernel.crashing.org; galak@kernel.crashing.org; Zhao Chenhui-
> B35336; Li Yang-R58472; Wang Dongsheng-B40534
> Subject: Re: [RFC 2/2] powerpc/cputable: add wait feature for CPU kernel
> features
>=20
> On 07/10/2013 03:27:56 AM, Dongsheng Wang wrote:
> > From: Wang Dongsheng <dongsheng.wang@freescale.com>
> >
> > Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> >
> > diff --git a/arch/powerpc/include/asm/cputable.h
> > b/arch/powerpc/include/asm/cputable.h
> > index 6f3887d..0a8d0cb 100644
> > --- a/arch/powerpc/include/asm/cputable.h
> > +++ b/arch/powerpc/include/asm/cputable.h
> > @@ -138,6 +138,7 @@ extern const char *powerpc_base_platform;
> >  #define CPU_FTR_NOEXECUTE		ASM_CONST(0x10000000)
> >  #define CPU_FTR_INDEXED_DCR		ASM_CONST(0x20000000)
> >  #define CPU_FTR_EMB_HV			ASM_CONST(0x40000000)
> > +#define CPU_FTR_CAN_WAIT		ASM_CONST(0x80000000)
>=20
> Note that this is the last 32-bit CPU feature flag; it's time to start
> thinking about other mechanisms.  We should probably reserve feature
> flags for things that need to use code patching due to being on a
> performance critical path, and move other things into struct cpu_spec.
> CPU_FTR_CAN_WAIT seems like a good candidate to be moved.
>=20
First of all, why should I do, I need to distinguish between the core, whic=
h
is to support the wait instruction. The CPU_FTR_CAN_WAIT looks easy.

How to fix this problem:
1/ I can drop this cpu feature, and move it into struct cpu_spec.
Add a pm_feature in struct cpu_spec? like,

struct cpu_spec {
	...
	unsigned long pm_features;
	...
}

2/ Drop this cpu feature, using CPU_FTRS_E6500/CPU_FTRS_E5500.. to distingu=
ish wait or doze/nap.
Like,

CPU_FTRS_E500/CPU_FTRS_E500_2 support doze/nap.

CPU_FTRS_E500MC/CPU_FTRS_E5500/CPU_FTRS_E6500 support wait.

If using this method, inside the cpuidle driver needs to do a lot of judgme=
nt. So I'm not sure this
is a very good solution.

Thanks.
- dongsheng

RE: [RFC 1/2] fsl/pm: combined the idle(PH&PW) state

[Wang Dongsheng-B40534]

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Tuesday, July 30, 2013 1:22 AM
> To: Wang Dongsheng-B40534
> Cc: benh@kernel.crashing.org; galak@kernel.crashing.org; Zhao Chenhui-
> B35336; Li Yang-R58472; Wang Dongsheng-B40534
> Subject: Re: [RFC 1/2] fsl/pm: combined the idle(PH&PW) state
>=20
> On 07/10/2013 03:27:55 AM, Dongsheng Wang wrote:
> > From: Wang Dongsheng <dongsheng.wang@freescale.com>
> >
> > move wait instructions from idle_e500.S to idle_book3e.S
> >
> > idle_e500.S: rename e500_idle to e500_idle_ph.
>=20
> What does _ph mean?
>=20
> If this is a reference to the new PHnn/PWnn terminology used on e6500, I
> don't see how that's relevant to this file, which isn't used on e6500.
> Or if you do plan to use this on e6500, why?
>=20
ph10/ph15 means doze/nap on freescale e500 family processors. On the IBM
platform does not "ph" concept.

Yes, "ph" maybe that's not a good idea. We should keep e500_idle.
On e500 processor, there is doze/nap, but e500mc/e5500/e6500 is using "wait=
".

I want to move "wait" from idle_e500.S into idle_book3e.S, but "book3e" mea=
ns
64bit mode... Now 32bit using idle_e500, 64bit using idle_book3e, and the i=
dle method
does not distinguish according to the platform, only in accordance with the=
 CPU
running mode(32bit/64bit) to distinguish.

So did you have any idea about this? Or another way as follows,

We do not touch idle_e500.S and idle_e6500.S, add fsl_cpuidle_wait() into "=
machdep.h"

arch/powerpc/include/asm/machdep.h
/* Wait for Interrupt */
static inline void fsl_cpuidle_wait(void)
{
#ifdef CONFIG_PPC64
        book3e_idle();
#else
        e500_idle();
#endif
}

[RFC 2/2] powerpc/cputable: add wait feature for CPU kernel features

[Dongsheng Wang]

From: Wang Dongsheng <dongsheng.wang@freescale.com>

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>

diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 6f3887d..0a8d0cb 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -138,6 +138,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_NOEXECUTE		ASM_CONST(0x10000000)
 #define CPU_FTR_INDEXED_DCR		ASM_CONST(0x20000000)
 #define CPU_FTR_EMB_HV			ASM_CONST(0x40000000)
+#define CPU_FTR_CAN_WAIT		ASM_CONST(0x80000000)
 
 /*
  * Add the 64-bit processor unique features in the top half of the word;
@@ -250,9 +251,11 @@ extern const char *powerpc_base_platform;
 #ifndef CONFIG_BDI_SWITCH
 #define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
 #define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
+#define CPU_FTR_MAYBE_CAN_WAIT	CPU_FTR_CAN_WAIT
 #else
 #define CPU_FTR_MAYBE_CAN_DOZE	0
 #define CPU_FTR_MAYBE_CAN_NAP	0
+#define CPU_FTR_MAYBE_CAN_WAIT	0
 #endif
 
 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
@@ -370,15 +373,17 @@ extern const char *powerpc_base_platform;
 	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_E500MC	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
-	    CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
+	    CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | \
+	    CPU_FTR_MAYBE_CAN_WAIT)
 #define CPU_FTRS_E5500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
+	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_MAYBE_CAN_WAIT)
 #define CPU_FTRS_E6500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
+	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
+	    CPU_FTR_MAYBE_CAN_WAIT)
 #define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
-- 
1.8.0