* [PATCH v3 1/5] dt-bindings: powerpc: define apm,apm82181 binding
2020-09-05 22:06 [PATCH v3 0/5] powerpc: apm82181: adding customer devices Christian Lamparter
@ 2020-09-05 22:06 ` Christian Lamparter
2020-09-15 1:02 ` Rob Herring
2020-09-05 22:06 ` [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone Christian Lamparter
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Christian Lamparter @ 2020-09-05 22:06 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
make a binding for the various boards based on the
AppliedMicro/APM APM82181 SoC.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
.../bindings/powerpc/4xx/apm,apm82181.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml b/Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml
new file mode 100644
index 000000000000..03a3c02fe920
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/powerpc/4xx/apm,apm82181.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: APM APM82181 device tree bindings
+
+description:
+ AppliedMicro APM82181 Wi-Fi/network SoCs based
+ on the PPC464-CPU architecture.
+
+maintainers:
+ - Christian Lamparter <chunkeey@gmail.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: APM82181 based boards
+ items:
+ - enum:
+ - apm,bluestone
+ - meraki,mr24
+ - wd,mybooklive
+ - const: amcc,apm82181
+
+...
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 1/5] dt-bindings: powerpc: define apm,apm82181 binding
2020-09-05 22:06 ` [PATCH v3 1/5] dt-bindings: powerpc: define apm,apm82181 binding Christian Lamparter
@ 2020-09-15 1:02 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2020-09-15 1:02 UTC (permalink / raw)
To: Christian Lamparter; +Cc: devicetree, Chris Blake, Paul Mackerras, linuxppc-dev
On Sun, Sep 06, 2020 at 12:06:11AM +0200, Christian Lamparter wrote:
> make a binding for the various boards based on the
> AppliedMicro/APM APM82181 SoC.
>
> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
> ---
> .../bindings/powerpc/4xx/apm,apm82181.yaml | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml
>
> diff --git a/Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml b/Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml
> new file mode 100644
> index 000000000000..03a3c02fe920
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/4xx/apm,apm82181.yaml
> @@ -0,0 +1,29 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/powerpc/4xx/apm,apm82181.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: APM APM82181 device tree bindings
> +
> +description:
> + AppliedMicro APM82181 Wi-Fi/network SoCs based
> + on the PPC464-CPU architecture.
> +
> +maintainers:
> + - Christian Lamparter <chunkeey@gmail.com>
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: APM82181 based boards
> + items:
> + - enum:
> + - apm,bluestone
> + - meraki,mr24
> + - wd,mybooklive
> + - const: amcc,apm82181
This doesn't match neither the existing dts nor your modifications.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone
2020-09-05 22:06 [PATCH v3 0/5] powerpc: apm82181: adding customer devices Christian Lamparter
2020-09-05 22:06 ` [PATCH v3 1/5] dt-bindings: powerpc: define apm,apm82181 binding Christian Lamparter
@ 2020-09-05 22:06 ` Christian Lamparter
2020-09-15 1:05 ` Rob Herring
2020-09-05 22:06 ` [PATCH v3 3/5] powerpc: apm82181: add WD MyBook Live NAS Christian Lamparter
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Christian Lamparter @ 2020-09-05 22:06 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
This patch adds an DTSI-File that can be used by various device-tree
files for APM82181-based devices.
Some of the nodes (like UART, PCIE, SATA) are used by the uboot and
need to stick with the naming-conventions of the old times'.
I've added comments whenever this was the case.
Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
rfc v1 -> v2:
- removed PKA (this CryptoPU will need driver)
- stick with compatibles, nodes, ... from either
Bluestone (APM82181) or Canyonlands (PPC460EX).
- add labels for NAND and NOR to help with access.
v2 -> v3:
- nodename of pciex@d.... was changed to pcie@d..
due to upstream patch.
- use simple-bus on the ebc, opb and plb nodes
---
arch/powerpc/boot/dts/apm82181.dtsi | 466 ++++++++++++++++++++++++++++
1 file changed, 466 insertions(+)
create mode 100644 arch/powerpc/boot/dts/apm82181.dtsi
diff --git a/arch/powerpc/boot/dts/apm82181.dtsi b/arch/powerpc/boot/dts/apm82181.dtsi
new file mode 100644
index 000000000000..60283430978d
--- /dev/null
+++ b/arch/powerpc/boot/dts/apm82181.dtsi
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree template include for various APM82181 boards.
+ *
+ * The SoC is an evolution of the PPC460EX predecessor.
+ * This is why dt-nodes from the canyonlands EBC, OPB, USB,
+ * DMA, SATA, EMAC, ... ended up in here.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>,
+ * Christian Lamparter <chunkeey@gmail.com>,
+ * Chris Blake <chrisrblake93@gmail.com>
+ */
+
+#include <dt-bindings/dma/dw-dmac.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ ethernet0 = &EMAC0; /* needed for BSP u-boot */
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,apm82181";
+ reg = <0x00000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ next-level-cache = <&L2C0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "apm,uic-apm82181", "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0x0c0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "apm,uic-apm82181", "ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0x0d0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x1e IRQ_TYPE_LEVEL_HIGH>,
+ <0x1f IRQ_TYPE_LEVEL_HIGH>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "apm,uic-apm82181", "ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0x0e0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x0a IRQ_TYPE_LEVEL_HIGH>,
+ <0x0b IRQ_TYPE_LEVEL_HIGH>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "apm,uic-apm82181","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0x0f0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x10 IRQ_TYPE_LEVEL_HIGH>,
+ <0x11 IRQ_TYPE_LEVEL_HIGH>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ OCM: ocm@400040000 {
+ compatible = "ibm,ocm";
+ status = "okay";
+ cell-index = <1>;
+ /* configured in U-Boot */
+ reg = <4 0x00040000 0x8000>; /* 32K */
+ };
+
+ SDR0: sdr {
+ compatible = "apm,sdr-apm821xx";
+ dcr-reg = <0x00e 0x002>;
+ };
+
+ CPR0: cpr {
+ compatible = "apm,cpr-apm821xx";
+ dcr-reg = <0x00c 0x002>;
+ };
+
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
+ dcr-reg = <0x020 0x008
+ 0x030 0x008>;
+ cache-line-size = <32>;
+ cache-size = <262144>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0xb IRQ_TYPE_EDGE_RISING>;
+ };
+
+ CPM0: cpm {
+ compatible = "ibm,cpm";
+ dcr-access-method = "native";
+ dcr-reg = <0x160 0x003>;
+ unused-units = <0x00000100>;
+ idle-doze = <0x02000000>;
+ standby = <0xfeff791d>;
+ };
+
+ plb {
+ compatible = "simple-bus"; /* PLB4 - Part of IBM's CoreConnect concept */
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges; /* Filled in by U-Boot */
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: sdram {
+ compatible = "apm,sdram-apm82181", "ibm,sdram-460ex", "ibm,sdram-405gp";
+ dcr-reg = <0x010 0x002>;
+ };
+
+ HWRNG: trng@110000 {
+ compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
+ reg = <4 0x00110000 0x100>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled"; /* hardware option */
+ };
+
+ CRYPTO: crypto@180000 {
+ compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
+ reg = <4 0x00180000 0x80400>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1d IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled"; /* hardware option */
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
+ descriptor-memory = "ocm";
+ dcr-reg = <0x180 0x062>;
+ num-tx-chans = <1>;
+ num-rx-chans = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-parent = <&UIC2>;
+ interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>,
+ <0x07 IRQ_TYPE_LEVEL_HIGH>,
+ <0x03 IRQ_TYPE_LEVEL_HIGH>,
+ <0x04 IRQ_TYPE_LEVEL_HIGH>,
+ <0x05 IRQ_TYPE_LEVEL_HIGH>,
+ <0x08 IRQ_TYPE_EDGE_FALLING>,
+ <0x09 IRQ_TYPE_EDGE_FALLING>,
+ <0x0c IRQ_TYPE_EDGE_FALLING>,
+ <0x0d IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "txeob", "rxeob", "serr",
+ "txde", "rxde",
+ "tx0coal", "tx1coal",
+ "rx0coal", "rx1coal";
+ };
+
+ POB0: opb {
+ compatible = "simple-bus"; /* on-chip peripheral bus */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "simple-bus"; /* external bus controller */
+ dcr-reg = <0x012 0x002>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ /* ranges property is supplied by U-Boot */
+ ranges = <0x00000003 0x00000000 0xe0000000 0x8000000>;
+ interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&UIC1>;
+
+ NOR: nor_flash@0,0 {
+ compatible = "cfi-flash";
+ bank-width = <1>;
+ reg = <0x00000000 0x00000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
+ NAND: ndfc@1,0 {
+ compatible = "ibm,ndfc";
+ reg = <00000003 00000000 00002000>;
+ ccr = <0x00001000>;
+ bank-settings = <0x80002222>;
+ status = "disabled";
+
+ nand {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+ };
+
+ UART0: serial@ef600300 {
+ /*
+ * AMCC's BSP u-boot scans for the "ns16550"
+ * compatible, without it, u-boot wouldn't
+ * set the required "clock-frequency".
+ *
+ * The hardware documentation states:
+ * "Register compatibility with 16750 register set"
+ */
+ compatible = "ns16750", "ns16550";
+ reg = <0xef600300 0x00000008>;
+ virtual-reg = <0xef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ UART1: serial@ef600400 {
+ /* same "ns16750" as with UART0 */
+ compatible = "ns16750", "ns16550";
+ reg = <0xef600400 0x00000008>;
+ virtual-reg = <0xef600400>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic";
+ reg = <0xef600700 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x02 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic";
+ reg = <0xef600800 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ GPIO0: gpio@ef600b00 {
+ compatible = "ibm,ppc4xx-gpio";
+ reg = <0xef600b00 0x00000048>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ status = "disabled";
+ };
+
+ EMAC0: ethernet@ef600c00 {
+ device_type = "network";
+ compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH>,
+ <1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "status", "wake";
+
+ reg = <0xef600c00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <16384>;
+ tx-fifo-size = <2048>;
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ status = "disabled";
+ };
+
+ TAH0: emac-tah@ef601350 {
+ compatible = "ibm,tah";
+ reg = <0xef601350 0x00000030>;
+ };
+
+ RGMII0: emac-rgmii@ef601500 {
+ compatible = "ibm,rgmii";
+ reg = <0xef601500 0x00000008>;
+ has-mdio;
+ };
+ };
+
+ USBOTG0: usbotg@bff80000 {
+ compatible = "amcc,dwc-otg";
+ reg = <4 0xbff80000 0x10000>;
+ interrupt-parent = <&USBOTG0>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &UIC2 0x1c IRQ_TYPE_LEVEL_HIGH>,
+ <1 &UIC1 0x1a IRQ_TYPE_LEVEL_LOW>,
+ <2 &UIC0 0x0c IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "usb-otg", "high-power", "dma";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ AHBDMA0: dma@bffd0800 {
+ compatible = "snps,dma-spear1340";
+ reg = <4 0xbffd0800 0x400>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x19 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <3>;
+
+ dma-channels = <2>;
+ dma-masters = <3>;
+ block_size = <4095>;
+ data-width = <4>, <4>, <4>;
+ multi-block = <1>, <1>;
+
+ chan_allocation_order = <1>;
+ chan_priority = <1>;
+
+ snps,dma-protection-control =
+ <(DW_DMAC_HPROT1_PRIVILEGED_MODE |
+ DW_DMAC_HPROT2_BUFFERABLE)>;
+ is_memcpy;
+ };
+
+ SATA0: sata@bffd1000 {
+ compatible = "amcc,sata-460ex";
+ reg = <4 0xbffd1000 0x800>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&AHBDMA0 0 0 1>;
+ dma-names = "sata-dma";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ SATA1: sata@bffd1800 {
+ compatible = "amcc,sata-460ex";
+ reg = <4 0xbffd1800 0x800>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1b IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&AHBDMA0 1 0 2>;
+ dma-names = "sata-dma";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ MSI: ppc4xx-msi@c10000000 {
+ compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+ reg = <0xc 0x10000000 0x100
+ 0xc 0x10000000 0x100>;
+ sdr-base = <0x36C>;
+ msi-data = <0x00004440>;
+ msi-mask = <0x0000ffe0>;
+ interrupts =<0 1 2 3 4 5 6 7>;
+ interrupt-parent = <&MSI>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ msi-available-ranges = <0x0 0x100>;
+ interrupt-map =
+ <0 &UIC3 0x18 IRQ_TYPE_EDGE_RISING>,
+ <1 &UIC3 0x19 IRQ_TYPE_EDGE_RISING>,
+ <2 &UIC3 0x1a IRQ_TYPE_EDGE_RISING>,
+ <3 &UIC3 0x1b IRQ_TYPE_EDGE_RISING>,
+ <4 &UIC3 0x1c IRQ_TYPE_EDGE_RISING>,
+ <5 &UIC3 0x1d IRQ_TYPE_EDGE_RISING>,
+ <6 &UIC3 0x1e IRQ_TYPE_EDGE_RISING>,
+ <7 &UIC3 0x1f IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ PCIE0: pcie@d00000000 {
+ device_type = "pci"; /* see ppc4xx_pci_find_bridge */
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
+ primary;
+ port = <0x0>; /* port number */
+ reg = <0x0000000d 0x00000000 0x20000000>, /* Config space access */
+ <0x0000000c 0x08010000 0x00001000>; /* Registers */
+ dcr-reg = <0x100 0x020>;
+ sdr-base = <0x300>;
+
+ /*
+ * Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000>,
+ <0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000>,
+ <0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 0x40 to 0x7f */
+ bus-range = <0x40 0x7f>;
+
+ /*
+ * Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map =
+ <0x0 0x0 0x0 0x1 &UIC3 0x0c IRQ_TYPE_LEVEL_HIGH>, /* swizzled int A */
+ <0x0 0x0 0x0 0x2 &UIC3 0x0d IRQ_TYPE_LEVEL_HIGH>, /* swizzled int B */
+ <0x0 0x0 0x0 0x3 &UIC3 0x0e IRQ_TYPE_LEVEL_HIGH>, /* swizzled int C */
+ <0x0 0x0 0x0 0x4 &UIC3 0x0f IRQ_TYPE_LEVEL_HIGH>; /* swizzled int D */
+ status = "disabled";
+ };
+ };
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone
2020-09-05 22:06 ` [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone Christian Lamparter
@ 2020-09-15 1:05 ` Rob Herring
2020-09-19 20:23 ` Christian Lamparter
0 siblings, 1 reply; 14+ messages in thread
From: Rob Herring @ 2020-09-15 1:05 UTC (permalink / raw)
To: Christian Lamparter; +Cc: devicetree, Chris Blake, Paul Mackerras, linuxppc-dev
On Sun, Sep 06, 2020 at 12:06:12AM +0200, Christian Lamparter wrote:
> This patch adds an DTSI-File that can be used by various device-tree
> files for APM82181-based devices.
>
> Some of the nodes (like UART, PCIE, SATA) are used by the uboot and
> need to stick with the naming-conventions of the old times'.
> I've added comments whenever this was the case.
>
> Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
> ---
> rfc v1 -> v2:
> - removed PKA (this CryptoPU will need driver)
> - stick with compatibles, nodes, ... from either
> Bluestone (APM82181) or Canyonlands (PPC460EX).
> - add labels for NAND and NOR to help with access.
> v2 -> v3:
> - nodename of pciex@d.... was changed to pcie@d..
> due to upstream patch.
> - use simple-bus on the ebc, opb and plb nodes
> ---
> arch/powerpc/boot/dts/apm82181.dtsi | 466 ++++++++++++++++++++++++++++
> 1 file changed, 466 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/apm82181.dtsi
>
> diff --git a/arch/powerpc/boot/dts/apm82181.dtsi b/arch/powerpc/boot/dts/apm82181.dtsi
> new file mode 100644
> index 000000000000..60283430978d
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/apm82181.dtsi
> @@ -0,0 +1,466 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Device Tree template include for various APM82181 boards.
> + *
> + * The SoC is an evolution of the PPC460EX predecessor.
> + * This is why dt-nodes from the canyonlands EBC, OPB, USB,
> + * DMA, SATA, EMAC, ... ended up in here.
> + *
> + * Copyright (c) 2010, Applied Micro Circuits Corporation
> + * Author: Tirumala R Marri <tmarri@apm.com>,
> + * Christian Lamparter <chunkeey@gmail.com>,
> + * Chris Blake <chrisrblake93@gmail.com>
> + */
> +
> +#include <dt-bindings/dma/dw-dmac.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + dcr-parent = <&{/cpus/cpu@0}>;
> +
> + aliases {
> + ethernet0 = &EMAC0; /* needed for BSP u-boot */
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + model = "PowerPC,apm82181";
This doesn't match the existing bluestone dts file.
Please separate any restructuring from changes.
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone
2020-09-15 1:05 ` Rob Herring
@ 2020-09-19 20:23 ` Christian Lamparter
2020-09-22 19:14 ` Rob Herring
0 siblings, 1 reply; 14+ messages in thread
From: Christian Lamparter @ 2020-09-19 20:23 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, arnd, Chris Blake, Paul Mackerras, andriy.shevchenko,
linuxppc-dev
On 2020-09-15 03:05, Rob Herring wrote:
> On Sun, Sep 06, 2020 at 12:06:12AM +0200, Christian Lamparter wrote:
>> This patch adds an DTSI-File that can be used by various device-tree
>> files for APM82181-based devices.
>>
>> Some of the nodes (like UART, PCIE, SATA) are used by the uboot and
>> need to stick with the naming-conventions of the old times'.
>> I've added comments whenever this was the case.
>>
>> Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
>> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
>> ---
>> rfc v1 -> v2:
>> - removed PKA (this CryptoPU will need driver)
>> - stick with compatibles, nodes, ... from either
>> Bluestone (APM82181) or Canyonlands (PPC460EX).
>> - add labels for NAND and NOR to help with access.
>> v2 -> v3:
>> - nodename of pciex@d.... was changed to pcie@d..
>> due to upstream patch.
>> - use simple-bus on the ebc, opb and plb nodes
>> ---
>> arch/powerpc/boot/dts/apm82181.dtsi | 466 ++++++++++++++++++++++++++++
>> 1 file changed, 466 insertions(+)
>> create mode 100644 arch/powerpc/boot/dts/apm82181.dtsi
>>
>> diff --git a/arch/powerpc/boot/dts/apm82181.dtsi b/arch/powerpc/boot/dts/apm82181.dtsi
>> new file mode 100644
>> index 000000000000..60283430978d
>> --- /dev/null
>> +++ b/arch/powerpc/boot/dts/apm82181.dtsi
>> @@ -0,0 +1,466 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * Device Tree template include for various APM82181 boards.
>> + *
>> + * The SoC is an evolution of the PPC460EX predecessor.
>> + * This is why dt-nodes from the canyonlands EBC, OPB, USB,
>> + * DMA, SATA, EMAC, ... ended up in here.
>> + *
>> + * Copyright (c) 2010, Applied Micro Circuits Corporation
>> + * Author: Tirumala R Marri <tmarri@apm.com>,
>> + * Christian Lamparter <chunkeey@gmail.com>,
>> + * Chris Blake <chrisrblake93@gmail.com>
>> + */
>> +
>> +#include <dt-bindings/dma/dw-dmac.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + dcr-parent = <&{/cpus/cpu@0}>;
>> +
>> + aliases {
>> + ethernet0 = &EMAC0; /* needed for BSP u-boot */
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
>> + device_type = "cpu";
>> + model = "PowerPC,apm82181";
>
> This doesn't match the existing bluestone dts file.
>
> Please separate any restructuring from changes.
"I see" (I'm including your comment of the dt-binding as well).
I'm getting the vibe that I better should not touch that bluestone.dts.
An honestly, looking at the series and patches that the APM-engineers
posted back in the day, I can see why this well is so poisoned... and
stuff like SATA/AHBDMA/USB/GPIO/CPM/... was missing.
As for the devices. In the spirit of Arnd Bergmann's post of
<https://lkml.org/lkml/2020/3/30/195>
|It would be nice to move over the the bluestone .dts to the apm82181.dtsi file
|when that gets added, if only to ensure they use the same description for each
|node, but that shouldn't stop the addition of the new file if that is needed for
|distros to make use of a popular device.
|I see a couple of additional files in openwrt.
I mean I don't have the bluestone dev board, just the consumer devices.
Would it be possible to support those? I can start from a "skeleton" apm82181.dtsi
This would just include CPU, Memory (SD-RAM+L2C+OCM), UIC (Interrupt-Controller),
the PLB+OBP+EBC Busses and UART. Just enough to make a board "boot from ram".
And then add nodes for PCIE+MSI, AHBDMA+SATA, I2C, Ethernet, NAND+NOR and finally
the Crypto each in separate patches.
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone
2020-09-19 20:23 ` Christian Lamparter
@ 2020-09-22 19:14 ` Rob Herring
2020-09-27 17:42 ` Christian Lamparter
0 siblings, 1 reply; 14+ messages in thread
From: Rob Herring @ 2020-09-22 19:14 UTC (permalink / raw)
To: Christian Lamparter
Cc: devicetree, Arnd Bergmann, Chris Blake, Paul Mackerras,
Andy Shevchenko, linuxppc-dev
On Sat, Sep 19, 2020 at 2:23 PM Christian Lamparter <chunkeey@gmail.com> wrote:
>
> On 2020-09-15 03:05, Rob Herring wrote:
> > On Sun, Sep 06, 2020 at 12:06:12AM +0200, Christian Lamparter wrote:
> >> This patch adds an DTSI-File that can be used by various device-tree
> >> files for APM82181-based devices.
> >>
> >> Some of the nodes (like UART, PCIE, SATA) are used by the uboot and
> >> need to stick with the naming-conventions of the old times'.
> >> I've added comments whenever this was the case.
> >>
> >> Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
> >> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
> >> ---
> >> rfc v1 -> v2:
> >> - removed PKA (this CryptoPU will need driver)
> >> - stick with compatibles, nodes, ... from either
> >> Bluestone (APM82181) or Canyonlands (PPC460EX).
> >> - add labels for NAND and NOR to help with access.
> >> v2 -> v3:
> >> - nodename of pciex@d.... was changed to pcie@d..
> >> due to upstream patch.
> >> - use simple-bus on the ebc, opb and plb nodes
> >> ---
> >> arch/powerpc/boot/dts/apm82181.dtsi | 466 ++++++++++++++++++++++++++++
> >> 1 file changed, 466 insertions(+)
> >> create mode 100644 arch/powerpc/boot/dts/apm82181.dtsi
> >>
> >> diff --git a/arch/powerpc/boot/dts/apm82181.dtsi b/arch/powerpc/boot/dts/apm82181.dtsi
> >> new file mode 100644
> >> index 000000000000..60283430978d
> >> --- /dev/null
> >> +++ b/arch/powerpc/boot/dts/apm82181.dtsi
> >> @@ -0,0 +1,466 @@
> >> +// SPDX-License-Identifier: GPL-2.0-or-later
> >> +/*
> >> + * Device Tree template include for various APM82181 boards.
> >> + *
> >> + * The SoC is an evolution of the PPC460EX predecessor.
> >> + * This is why dt-nodes from the canyonlands EBC, OPB, USB,
> >> + * DMA, SATA, EMAC, ... ended up in here.
> >> + *
> >> + * Copyright (c) 2010, Applied Micro Circuits Corporation
> >> + * Author: Tirumala R Marri <tmarri@apm.com>,
> >> + * Christian Lamparter <chunkeey@gmail.com>,
> >> + * Chris Blake <chrisrblake93@gmail.com>
> >> + */
> >> +
> >> +#include <dt-bindings/dma/dw-dmac.h>
> >> +#include <dt-bindings/input/input.h>
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >> +#include <dt-bindings/gpio/gpio.h>
> >> +
> >> +/ {
> >> + #address-cells = <2>;
> >> + #size-cells = <1>;
> >> + dcr-parent = <&{/cpus/cpu@0}>;
> >> +
> >> + aliases {
> >> + ethernet0 = &EMAC0; /* needed for BSP u-boot */
> >> + };
> >> +
> >> + cpus {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + CPU0: cpu@0 {
> >> + device_type = "cpu";
> >> + model = "PowerPC,apm82181";
> >
> > This doesn't match the existing bluestone dts file.
> >
> > Please separate any restructuring from changes.
>
>
> "I see" (I'm including your comment of the dt-binding as well).
>
> I'm getting the vibe that I better should not touch that bluestone.dts.
I don't know about that.
> An honestly, looking at the series and patches that the APM-engineers
> posted back in the day, I can see why this well is so poisoned... and
> stuff like SATA/AHBDMA/USB/GPIO/CPM/... was missing.
>
> As for the devices. In the spirit of Arnd Bergmann's post of
> <https://lkml.org/lkml/2020/3/30/195>
>
> |It would be nice to move over the the bluestone .dts to the apm82181.dtsi file
> |when that gets added, if only to ensure they use the same description for each
> |node, but that shouldn't stop the addition of the new file if that is needed for
> |distros to make use of a popular device.
> |I see a couple of additional files in openwrt.
>
> I mean I don't have the bluestone dev board, just the consumer devices.
This stuff is old enough, I'd guess no one cares about a dev board.
But we should figure that out and document that with any changes.
> Would it be possible to support those? I can start from a "skeleton" apm82181.dtsi
> This would just include CPU, Memory (SD-RAM+L2C+OCM), UIC (Interrupt-Controller),
> the PLB+OBP+EBC Busses and UART. Just enough to make a board "boot from ram".
This skeleton would be chunks moved over or duplicated? I don't think
we want 2 of the same thing.
The order I would go is split into an apm82181.dtsi with 0 changes to
the built dtb(s). Then make changes/additions you need. As far as
changes to existing bindings, it's only an ABI if someone notices.
Rob
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone
2020-09-22 19:14 ` Rob Herring
@ 2020-09-27 17:42 ` Christian Lamparter
0 siblings, 0 replies; 14+ messages in thread
From: Christian Lamparter @ 2020-09-27 17:42 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Arnd Bergmann, Chris Blake, Paul Mackerras,
Andy Shevchenko, linuxppc-dev
On Tue, Sep 22, 2020 at 9:14 PM Rob Herring <robh@kernel.org> wrote:
>
> On Sat, Sep 19, 2020 at 2:23 PM Christian Lamparter <chunkeey@gmail.com> wrote:
> >
> > On 2020-09-15 03:05, Rob Herring wrote:
> > > On Sun, Sep 06, 2020 at 12:06:12AM +0200, Christian Lamparter wrote:
> > >> This patch adds an DTSI-File that can be used by various device-tree
> > >> files for APM82181-based devices.
> > >>
> > >> Some of the nodes (like UART, PCIE, SATA) are used by the uboot and
> > >> need to stick with the naming-conventions of the old times'.
> > >> I've added comments whenever this was the case.
> > >>
> > >> Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
> > >> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
> > >> ---
> > >> rfc v1 -> v2:
> > >> - removed PKA (this CryptoPU will need driver)
> > >> - stick with compatibles, nodes, ... from either
> > >> Bluestone (APM82181) or Canyonlands (PPC460EX).
> > >> - add labels for NAND and NOR to help with access.
> > >> v2 -> v3:
> > >> - nodename of pciex@d.... was changed to pcie@d..
> > >> due to upstream patch.
> > >> - use simple-bus on the ebc, opb and plb nodes
> > >> ---
> > >> arch/powerpc/boot/dts/apm82181.dtsi | 466 ++++++++++++++++++++++++++++
> > >> 1 file changed, 466 insertions(+)
> > >> create mode 100644 arch/powerpc/boot/dts/apm82181.dtsi
> > >>
> > >> diff --git a/arch/powerpc/boot/dts/apm82181.dtsi b/arch/powerpc/boot/dts/apm82181.dtsi
> > >> new file mode 100644
> > >> index 000000000000..60283430978d
> > >> --- /dev/null
> > >> +++ b/arch/powerpc/boot/dts/apm82181.dtsi
> > >> @@ -0,0 +1,466 @@
> > >> +// SPDX-License-Identifier: GPL-2.0-or-later
> > >> +/*
> > >> + * Device Tree template include for various APM82181 boards.
> > >> + *
> > >> + * The SoC is an evolution of the PPC460EX predecessor.
> > >> + * This is why dt-nodes from the canyonlands EBC, OPB, USB,
> > >> + * DMA, SATA, EMAC, ... ended up in here.
> > >> + *
> > >> + * Copyright (c) 2010, Applied Micro Circuits Corporation
> > >> + * Author: Tirumala R Marri <tmarri@apm.com>,
> > >> + * Christian Lamparter <chunkeey@gmail.com>,
> > >> + * Chris Blake <chrisrblake93@gmail.com>
> > >> + */
> > >> +
> > >> +#include <dt-bindings/dma/dw-dmac.h>
> > >> +#include <dt-bindings/input/input.h>
> > >> +#include <dt-bindings/interrupt-controller/irq.h>
> > >> +#include <dt-bindings/gpio/gpio.h>
> > >> +
> > >> +/ {
> > >> + #address-cells = <2>;
> > >> + #size-cells = <1>;
> > >> + dcr-parent = <&{/cpus/cpu@0}>;
> > >> +
> > >> + aliases {
> > >> + ethernet0 = &EMAC0; /* needed for BSP u-boot */
> > >> + };
> > >> +
> > >> + cpus {
> > >> + #address-cells = <1>;
> > >> + #size-cells = <0>;
> > >> +
> > >> + CPU0: cpu@0 {
> > >> + device_type = "cpu";
> > >> + model = "PowerPC,apm82181";
> > >
> > > This doesn't match the existing bluestone dts file.
> > >
> > > Please separate any restructuring from changes.
> >
> >
> > "I see" (I'm including your comment of the dt-binding as well).
> >
> > I'm getting the vibe that I better should not touch that bluestone.dts.
>
> I don't know about that.
k, understood.
>
> > An honestly, looking at the series and patches that the APM-engineers
> > posted back in the day, I can see why this well is so poisoned... and
> > stuff like SATA/AHBDMA/USB/GPIO/CPM/... was missing.
> >
> > As for the devices. In the spirit of Arnd Bergmann's post of
> > <https://lkml.org/lkml/2020/3/30/195>
> >
> > |It would be nice to move over the the bluestone .dts to the apm82181.dtsi file
> > |when that gets added, if only to ensure they use the same description for each
> > |node, but that shouldn't stop the addition of the new file if that is needed for
> > |distros to make use of a popular device.
> > |I see a couple of additional files in openwrt.
> >
> > I mean I don't have the bluestone dev board, just the consumer devices.
>
> This stuff is old enough, I'd guess no one cares about a dev board.
> But we should figure that out and document that with any changes.
>
> > Would it be possible to support those? I can start from a "skeleton" apm82181.dtsi
> > This would just include CPU, Memory (SD-RAM+L2C+OCM), UIC (Interrupt-Controller),
> > the PLB+OBP+EBC Busses and UART. Just enough to make a board "boot from ram".
>
> This skeleton would be chunks moved over or duplicated? I don't think
> we want 2 of the same thing.
My Idea was copying the working apm82181.dtsi we have in OpenWrt
and stripping the nodes we added for SATA, USB, GPIO and the likes.
so the remaining nodes would be very close to what bluestone.dts had.
The main differences would be:
- It's a bit smaller since I made a separate patch for the NOR/NAND on the EBC.
Reason being that the SoC uses glue-logic for mapping NOR/NAND (and other
external peripherals like the GPIOs on the WD) into the memory and I thought
this needed some explanation as to why this weird thing works.
- it would already use the dt-bindings/interrupt-controller/irq.h macros
for LEVEL/EDGE cell values
- it contains valuable comments about the uboot. Because ethernet0 alias
and the /plb/obc/ebc node-name requirements).
- UART are using 16750 compatible (as per hardware docs)
>
> The order I would go is split into an apm82181.dtsi with 0 changes to
> the built dtb(s). Then make changes/additions you need. As far as
> changes to existing bindings, it's only an ABI if someone notices.
This will rewriting the history, as the development of apm82181.dtsi
did happen differently (basically, each device started with its own full dts.
But early on in 2016 we merged the common nodes and switched over
to the macros). This is fine though, I'll need some time to rebase and rewrite
the patches.
(Note: I've already wrote a patch for a the apm82181 dwc USB binding for
this: <https://www.spinics.net/lists/devicetree/msg378884.html>. Not sure
about uic, sata and dw-dma as these drivers each use a common binding.
I hope there's some leeway for this old stuff.)
Cheers,
Christian
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 3/5] powerpc: apm82181: add WD MyBook Live NAS
2020-09-05 22:06 [PATCH v3 0/5] powerpc: apm82181: adding customer devices Christian Lamparter
2020-09-05 22:06 ` [PATCH v3 1/5] dt-bindings: powerpc: define apm,apm82181 binding Christian Lamparter
2020-09-05 22:06 ` [PATCH v3 2/5] powerpc: apm82181: create shared dtsi for APM bluestone Christian Lamparter
@ 2020-09-05 22:06 ` Christian Lamparter
2020-09-05 22:06 ` [PATCH v3 4/5] powerpc: apm82181: add Meraki MR24 AP Christian Lamparter
` (2 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Christian Lamparter @ 2020-09-05 22:06 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
This patch adds the device-tree definitions for
Western Digital MyBook Live NAS devices.
CPU: AMCC PowerPC APM82181 (PVR=12c41c83) at 800 MHz
(PLB=200, OPB=100, EBC=100 MHz)
32 kB I-Cache 32 kB D-Cache, 256 kB L2-Cache, 32 kB OnChip Memory
DRAM: 256 MB (2x NT5TU64M16GG-AC)
FLASH: 512 kB
Ethernet: 1xRGMII - 1 Gbit - Broadcom PHY BCM54610
SATA: 2*SATA (DUO Variant) / 1*SATA (Single Variant)
USB: 1xUSB2.0 (Only DUO)
Technically, this devicetree file is shared by two, very
similar devices.
There's the My Book Live and the My Book Live Duo. WD's uboot
on the device will enable/disable the nodes for the device.
This device boots from a u-boot on a 512 KiB NOR Flash onto a
Linux image stored on one of the harddrives.
Ready to go images and install instruction can be found @OpenWrt.org
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
rfc v1 -> v2:
- use new LED naming scheme
- dish out read-only; for essential NOR partitions
- remove openwrt led-aliases
- comment on the location of linux kernel (on the HDD)
- overhauled commit message
v2 -> v3:
- "jedec-probe" should be "jedec,spi-nor"
---
arch/powerpc/boot/dts/wd-mybooklive.dts | 200 +++++++++++++++++++++
arch/powerpc/platforms/44x/ppc44x_simple.c | 3 +-
2 files changed, 202 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/wd-mybooklive.dts
diff --git a/arch/powerpc/boot/dts/wd-mybooklive.dts b/arch/powerpc/boot/dts/wd-mybooklive.dts
new file mode 100644
index 000000000000..8fe868252cb5
--- /dev/null
+++ b/arch/powerpc/boot/dts/wd-mybooklive.dts
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * (c) Copyright 2010 Western Digital Technologies, Inc. All Rights Reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "apm82181.dtsi"
+
+/ {
+ compatible = "wd,mybooklive";
+ model = "MyBook Live";
+
+ aliases {
+ serial0 = &UART0;
+ };
+};
+
+&POB0 {
+ GPIO1: gpio@e0000000 {
+ compatible = "wd,mbl-gpio";
+ reg-names = "dat";
+ reg = <0xe0000000 0x1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ enable-button {
+ /* Defined in u-boot as: NOT_NOR
+ * "enables features other than NOR
+ * specifically, the buffer at CS2"
+ * (button).
+ *
+ * Note: This option is disabled as
+ * it prevents the system from being
+ * rebooted successfully.
+ */
+
+ gpio-hog;
+ line-name = "Enable Reset Button, disable NOR";
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ GPIO2: gpio@e0100000 {
+ compatible = "wd,mbl-gpio";
+ reg-names = "dat";
+ reg = <0xe0100000 0x1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ no-output;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* There's just one tri-color LED. */
+ failsafe: power-red {
+ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&GPIO1 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "panic";
+ };
+
+ power-green {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&GPIO1 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ power-blue {
+ function = LED_FUNCTION_DISK;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&GPIO1 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <60>; /* 3 * 20 = 60ms */
+ autorepeat;
+
+ reset-button {
+ label = "Reset button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&GPIO2 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ usbpwr: usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "Power USB Core";
+ gpios = <&GPIO1 2 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ sata1pwr: sata1-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "Power Drive Port 1";
+ gpios = <&GPIO1 3 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on; /* needed to read OS from HDD */
+ };
+
+ sata0pwr: sata0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "Power Drive Port 0";
+ gpios = <&GPIO1 7 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on; /* needed to read OS from HDD */
+ };
+};
+
+&NOR {
+ status = "okay";
+ compatible = "jedec,spi-nor";
+ bank-width = <1>;
+ reg = <0x00000000 0x00000000 0x00080000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ /* Part of bootrom - Don't use it without a jump */
+ label = "bootrom";
+ reg = <0x00000000 0x0001e000>;
+ read-only;
+ };
+
+ partition@1e000 {
+ label = "env";
+ reg = <0x0001e000 0x00002000>;
+ };
+
+ partition@20000 {
+ label = "uboot";
+ reg = <0x00020000 0x00050000>;
+ read-only;
+ };
+};
+
+&EMAC0 {
+ status = "okay";
+
+ phy-map = <0x2>;
+ phy-address = <0x1>;
+ phy-handle = <&phy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&GPIO1 0 GPIO_ACTIVE_LOW>;
+
+ phy: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&CRYPTO {
+ status = "okay";
+};
+
+&HWRNG {
+ status = "okay";
+};
+
+&SATA0 {
+ status = "okay";
+
+ drive0: sata-port@0 {
+ reg = <0>;
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&SATA1 {
+ status = "okay";
+
+ drive1: sata-port@0 {
+ reg = <0>;
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&UART0 {
+ status = "okay";
+};
+
+&USBOTG0 {
+ status = "okay";
+ dr_mode = "host";
+ vbus-supply = <&usbpwr>;
+};
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c
index 3dbd8ddd734a..1122702c804a 100644
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -59,7 +59,8 @@ static char *board[] __initdata = {
"amcc,sequoia",
"amcc,taishan",
"amcc,yosemite",
- "mosaixtech,icon"
+ "mosaixtech,icon",
+ "wd,mybooklive",
};
static int __init ppc44x_probe(void)
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 4/5] powerpc: apm82181: add Meraki MR24 AP
2020-09-05 22:06 [PATCH v3 0/5] powerpc: apm82181: adding customer devices Christian Lamparter
` (2 preceding siblings ...)
2020-09-05 22:06 ` [PATCH v3 3/5] powerpc: apm82181: add WD MyBook Live NAS Christian Lamparter
@ 2020-09-05 22:06 ` Christian Lamparter
2020-09-05 22:06 ` [PATCH v3 5/5] powerpc: apm82181: integrate bluestone.dts Christian Lamparter
2021-07-23 19:19 ` [PATCH v3 0/5] powerpc: apm82181: adding customer devices Andy Shevchenko
5 siblings, 0 replies; 14+ messages in thread
From: Christian Lamparter @ 2020-09-05 22:06 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
This patch adds the device-tree definitions for Meraki MR24
Accesspoint devices.
Board: MR24 - Meraki MR24 Cloud Managed Access Point
CPU: APM82181 SoC 800 MHz (PLB=200 OPB=100 EBC=100)
Flash size: 32MiB
RAM Size: 128MiB
Wireless: Atheros AR9380 5.0GHz + Atheros AR9380 2.4GHz
EPHY: 1x Gigabit Atheros AR8035
Ready to go images and install instruction can be found @OpenWrt.
Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
rfc v1 -> v2:
- use new led naming scheme
- space-vs-tab snafu cleanup
- remove led-aliases (openwrt specific)
- overhauled commit message
v2 -> v3:
- added interrupt-properties legacy pci interrupt signalling
to fix wifi
---
arch/powerpc/boot/dts/meraki-mr24.dts | 237 +++++++++++++++++++++
arch/powerpc/platforms/44x/ppc44x_simple.c | 1 +
2 files changed, 238 insertions(+)
create mode 100644 arch/powerpc/boot/dts/meraki-mr24.dts
diff --git a/arch/powerpc/boot/dts/meraki-mr24.dts b/arch/powerpc/boot/dts/meraki-mr24.dts
new file mode 100644
index 000000000000..f91c243e7678
--- /dev/null
+++ b/arch/powerpc/boot/dts/meraki-mr24.dts
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for Meraki MR24 (Ikarem)
+ *
+ * Copyright (C) 2016 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * Based on Cisco Meraki GPL Release r23-20150601 MR24 DTS
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "apm82181.dtsi"
+
+/ {
+ model = "Meraki MR24 Access Point";
+ compatible = "meraki,mr24";
+
+ aliases {
+ serial0 = &UART1;
+ };
+
+ chosen {
+ stdout-path = "/plb/opb/serial@ef600400";
+ };
+};
+
+&CRYPTO {
+ status = "okay";
+};
+
+&HWRNG {
+ status = "okay";
+};
+
+&NAND {
+ status = "okay";
+
+ /* 32 MiB NAND Flash */
+ nand {
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x00150000>;
+ read-only;
+ };
+
+ partition@150000 {
+ /*
+ * The u-boot environment size is one NAND
+ * block (16KiB). u-boot allocates four NAND
+ * blocks (64KiB) in order to have spares
+ * around for bad block management
+ */
+ label = "u-boot-env";
+ reg = <0x00150000 0x00010000>;
+ read-only;
+ };
+
+ partition@160000 {
+ /*
+ * redundant u-boot environment.
+ * has to be kept it in sync with the
+ * data in "u-boot-env".
+ */
+ label = "u-boot-env-redundant";
+ reg = <0x00160000 0x00010000>;
+ read-only;
+ };
+
+ partition@170000 {
+ label = "oops";
+ reg = <0x00170000 0x00010000>;
+ };
+
+ partition@180000 {
+ label = "ubi";
+ reg = <0x00180000 0x01e80000>;
+ };
+ };
+};
+
+&UART1 {
+ status = "okay";
+};
+
+&GPIO0 {
+ status = "okay";
+};
+
+&IIC0 {
+ status = "okay";
+ /* Boot ROM is at 0x52-0x53, do not touch */
+ /* Unknown chip at 0x6e, not sure what it is */
+};
+
+&EMAC0 {
+ status = "okay";
+
+ phy-mode = "rgmii-id";
+ phy-map = <0x2>;
+ phy-address = <0x1>;
+ phy-handle = <&phy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&POB0 {
+ leds {
+ compatible = "gpio-leds";
+
+ status: power-green {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&GPIO0 18 GPIO_ACTIVE_LOW>;
+ };
+
+ failsafe: power-amber {
+ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&GPIO0 19 GPIO_ACTIVE_LOW>;
+ };
+
+ lan {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&GPIO0 17 GPIO_ACTIVE_LOW>;
+ };
+
+ /* signal strength indicator */
+ ssi-0 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&GPIO0 23 GPIO_ACTIVE_LOW>;
+ };
+
+ ssi-1 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&GPIO0 22 GPIO_ACTIVE_LOW>;
+ };
+
+ ssi-2 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&GPIO0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ ssi-3 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&GPIO0 20 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ /* Label as per Meraki's "MR24 Installation Guide" */
+ label = "Factory Reset Button";
+ linux,code = <KEY_RESTART>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x15 IRQ_TYPE_EDGE_FALLING>;
+ gpios = <&GPIO0 16 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+ };
+};
+
+&PCIE0 {
+ status = "okay";
+ /*
+ * relevant lspci topology:
+ *
+ * -+-[0000:40]---00.0-[41-7f]----00.0-[42-45]--+-02.0-[43]----00.0
+ * +-03.0-[44]----00.0
+ *
+ */
+
+ bridge@40,0 {
+ reg = <0x00400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ bridge@41,0 {
+ /* IDT PES3T3 PCI Express Switch */
+ compatible = "pci111d,8039";
+ reg = <0x00410000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ bridge@42,2 {
+ compatible = "pci111d,8039";
+ reg = <0x00421000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi0: wifi@43,0 {
+ /* Atheros AR9380 2.4GHz */
+ compatible = "pci168c,0030";
+ reg = <0x00430000 0 0 0 0>;
+ interrupts = <3>; /* INTC */
+ };
+ };
+
+ bridge@42,3 {
+ compatible = "pci111d,8039";
+ reg = <0x00421800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi1: wifi@44,0 {
+ /* Atheros AR9380 5GHz */
+ compatible = "pci168c,0030";
+ reg = <0x00440000 0 0 0 0>;
+ interrupts = <4>; /* INTD */
+ };
+ };
+ };
+ };
+};
+
+&MSI {
+ status = "okay";
+};
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c
index 1122702c804a..7d479928fd48 100644
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -60,6 +60,7 @@ static char *board[] __initdata = {
"amcc,taishan",
"amcc,yosemite",
"mosaixtech,icon",
+ "meraki,mr24",
"wd,mybooklive",
};
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 5/5] powerpc: apm82181: integrate bluestone.dts
2020-09-05 22:06 [PATCH v3 0/5] powerpc: apm82181: adding customer devices Christian Lamparter
` (3 preceding siblings ...)
2020-09-05 22:06 ` [PATCH v3 4/5] powerpc: apm82181: add Meraki MR24 AP Christian Lamparter
@ 2020-09-05 22:06 ` Christian Lamparter
2021-07-23 19:19 ` [PATCH v3 0/5] powerpc: apm82181: adding customer devices Andy Shevchenko
5 siblings, 0 replies; 14+ messages in thread
From: Christian Lamparter @ 2020-09-05 22:06 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
This patch tries to integrate the existing bluestone.dts into the
apm82181.dtsi framework.
The original bluestone.dts produces a peculiar warning message.
> bluestone.dts:120.10-125.4: Warning (i2c_bus_reg):
> /plb/opb/i2c@ef600700/sttm@4C: I2C bus unit address format error, expected "4c"
For now, this has been kept as-is.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
rfc -> v1:
- no changes
v2 -> v3:
- incorporated pcie@d node-name switch
---
arch/powerpc/boot/dts/bluestone.dts | 458 +++++++---------------------
1 file changed, 104 insertions(+), 354 deletions(-)
diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts
index aa1ae94cd776..b568fe7ae526 100644
--- a/arch/powerpc/boot/dts/bluestone.dts
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -8,388 +8,138 @@
/dts-v1/;
+#include "apm82181.dtsi"
+
/ {
- #address-cells = <2>;
- #size-cells = <1>;
model = "apm,bluestone";
compatible = "apm,bluestone";
- dcr-parent = <&{/cpus/cpu@0}>;
aliases {
- ethernet0 = &EMAC0;
serial0 = &UART0;
serial1 = &UART1;
};
+};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,apm821xx";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <32768>;
- d-cache-size = <32768>;
- dcr-controller;
- dcr-access-method = "native";
- next-level-cache = <&L2C0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller0 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
+&CRYPTO {
+ status = "okay";
+};
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
+&HWRNG {
+ status = "okay";
+};
- UIC3: interrupt-controller3 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <3>;
- dcr-reg = <0x0f0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
+&NOR {
+ status = "okay";
- OCM: ocm@400040000 {
- compatible = "ibm,ocm";
- status = "okay";
- cell-index = <1>;
- /* configured in U-Boot */
- reg = <4 0x00040000 0x8000>; /* 32K */
- };
+ compatible = "amd,s29gl512n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0x00000000 0x00000000 0x00400000>;
- SDR0: sdr {
- compatible = "ibm,sdr-apm821xx";
- dcr-reg = <0x00e 0x002>;
+ partition@0 {
+ label = "kernel";
+ reg = <0x00000000 0x00180000>;
};
-
- CPR0: cpr {
- compatible = "ibm,cpr-apm821xx";
- dcr-reg = <0x00c 0x002>;
+ partition@180000 {
+ label = "env";
+ reg = <0x00180000 0x00020000>;
};
-
- L2C0: l2c {
- compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
- dcr-reg = <0x020 0x008
- 0x030 0x008>;
- cache-line-size = <32>;
- cache-size = <262144>;
- interrupt-parent = <&UIC1>;
- interrupts = <11 1>;
+ partition@1a0000 {
+ label = "u-boot";
+ reg = <0x001a0000 0x00060000>;
};
+};
- plb {
- compatible = "ibm,plb4";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
+&NAND {
+ status = "okay";
- SDRAM0: sdram {
- compatible = "ibm,sdram-apm821xx";
- dcr-reg = <0x010 0x002>;
+ /* 2Gb Nand Flash */
+ nand {
+ partition@0 {
+ label = "firmware";
+ reg = <0x00000000 0x00C00000>;
};
-
- MAL0: mcmal {
- compatible = "ibm,mcmal2";
- descriptor-memory = "ocm";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <1>;
- num-rx-chans = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-parent = <&UIC2>;
- interrupts = < /*TXEOB*/ 0x6 0x4
- /*RXEOB*/ 0x7 0x4
- /*SERR*/ 0x3 0x4
- /*TXDE*/ 0x4 0x4
- /*RXDE*/ 0x5 0x4>;
+ partition@c00000 {
+ label = "environment";
+ reg = <0x00C00000 0x00B00000>;
};
+ partition@1700000 {
+ label = "kernel";
+ reg = <0x01700000 0x00E00000>;
+ };
+ partition@2500000 {
+ label = "root";
+ reg = <0x02500000 0x08200000>;
+ };
+ partition@a700000 {
+ label = "device-tree";
+ reg = <0x0A700000 0x00B00000>;
+ };
+ partition@b200000 {
+ label = "config";
+ reg = <0x0B200000 0x00D00000>;
+ };
+ partition@bf00000 {
+ label = "diag";
+ reg = <0x0BF00000 0x00C00000>;
+ };
+ partition@cb00000 {
+ label = "vendor";
+ reg = <0x0CB00000 0x3500000>;
+ };
+ };
+};
- POB0: opb {
- compatible = "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
- interrupts = <0x6 0x4>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x00400000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x00180000>;
- };
- partition@180000 {
- label = "env";
- reg = <0x00180000 0x00020000>;
- };
- partition@1a0000 {
- label = "u-boot";
- reg = <0x001a0000 0x00060000>;
- };
- };
-
- ndfc@1,0 {
- compatible = "ibm,ndfc";
- reg = <0x00000003 0x00000000 0x00002000>;
- ccr = <0x00001000>;
- bank-settings = <0x80002222>;
- #address-cells = <1>;
- #size-cells = <1>;
- /* 2Gb Nand Flash */
- nand {
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "firmware";
- reg = <0x00000000 0x00C00000>;
- };
- partition@c00000 {
- label = "environment";
- reg = <0x00C00000 0x00B00000>;
- };
- partition@1700000 {
- label = "kernel";
- reg = <0x01700000 0x00E00000>;
- };
- partition@2500000 {
- label = "root";
- reg = <0x02500000 0x08200000>;
- };
- partition@a700000 {
- label = "device-tree";
- reg = <0x0A700000 0x00B00000>;
- };
- partition@b200000 {
- label = "config";
- reg = <0x0B200000 0x00D00000>;
- };
- partition@bf00000 {
- label = "diag";
- reg = <0x0BF00000 0x00C00000>;
- };
- partition@cb00000 {
- label = "vendor";
- reg = <0x0CB00000 0x3500000>;
- };
- };
- };
- };
-
- UART0: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC1>;
- interrupts = <0x1 0x4>;
- };
-
- UART1: serial@ef600400 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600400 0x00000008>;
- virtual-reg = <0xef600400>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- IIC0: i2c@ef600700 {
- compatible = "ibm,iic";
- reg = <0xef600700 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
- rtc@68 {
- compatible = "st,m41t80";
- reg = <0x68>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x9 0x8>;
- };
- sttm@4C {
- compatible = "adm,adm1032";
- reg = <0x4C>;
- interrupt-parent = <&UIC1>;
- interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
- };
- };
-
- IIC1: i2c@ef600800 {
- compatible = "ibm,iic";
- reg = <0xef600800 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x3 0x4>;
- };
+&UART0 {
+ status = "okay";
+};
- RGMII0: emac-rgmii@ef601500 {
- compatible = "ibm,rgmii";
- reg = <0xef601500 0x00000008>;
- has-mdio;
- };
+&UART1 {
+ status = "okay";
+};
- TAH0: emac-tah@ef601350 {
- compatible = "ibm,tah";
- reg = <0xef601350 0x00000030>;
- };
+&IIC0 {
+ status = "okay";
+ rtc@68 {
+ compatible = "st,m41t80";
+ reg = <0x68>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x9 0x8>;
+ };
+ sttm@4C {
+ compatible = "adm,adm1032";
+ reg = <0x4C>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
+ };
+};
- EMAC0: ethernet@ef600c00 {
- device_type = "network";
- compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
- /*Wake*/ 0x1 &UIC2 0x14 0x4>;
- reg = <0xef600c00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <16384>;
- tx-fifo-size = <2048>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- tah-device = <&TAH0>;
- tah-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
- };
+&IIC1 {
+ status = "okay";
+};
- PCIE0: pcie@d00000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
- primary;
- port = <0x0>; /* port number */
- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
- 0x0000000c 0x08010000 0x00001000>; /* Registers */
- dcr-reg = <0x100 0x020>;
- sdr-base = <0x300>;
+&RGMII0 {
+ status = "okay";
+};
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+&TAH0 {
+ status = "okay";
+};
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+&MAL0 {
+ status = "okay";
+};
- /* This drives busses 40 to 0x7f */
- bus-range = <0x40 0x7f>;
+&EMAC0 {
+ status = "okay";
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+};
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
- };
+&PCIE0 {
+ status = "okay";
+};
- MSI: ppc4xx-msi@C10000000 {
- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
- reg = < 0xC 0x10000000 0x100
- 0xC 0x10000000 0x100>;
- sdr-base = <0x36C>;
- msi-data = <0x00004440>;
- msi-mask = <0x0000ffe0>;
- interrupts =<0 1 2 3 4 5 6 7>;
- interrupt-parent = <&MSI>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- msi-available-ranges = <0x0 0x100>;
- interrupt-map = <
- 0 &UIC3 0x18 1
- 1 &UIC3 0x19 1
- 2 &UIC3 0x1A 1
- 3 &UIC3 0x1B 1
- 4 &UIC3 0x1C 1
- 5 &UIC3 0x1D 1
- 6 &UIC3 0x1E 1
- 7 &UIC3 0x1F 1
- >;
- };
- };
+&MSI {
+ status = "okay";
};
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 0/5] powerpc: apm82181: adding customer devices
2020-09-05 22:06 [PATCH v3 0/5] powerpc: apm82181: adding customer devices Christian Lamparter
` (4 preceding siblings ...)
2020-09-05 22:06 ` [PATCH v3 5/5] powerpc: apm82181: integrate bluestone.dts Christian Lamparter
@ 2021-07-23 19:19 ` Andy Shevchenko
2021-07-23 22:08 ` Christian Lamparter
5 siblings, 1 reply; 14+ messages in thread
From: Andy Shevchenko @ 2021-07-23 19:19 UTC (permalink / raw)
To: Christian Lamparter
Cc: devicetree, Chris Blake, Rob Herring, Paul Mackerras, linuxppc-dev
On Sun, Sep 06, 2020 at 12:06:10AM +0200, Christian Lamparter wrote:
> Hello,
>
> I've been holding on to these devices dts' for a while now.
> But ever since the recent purge of the PPC405, I'm feeling
> the urge to move forward.
>
> The devices in question have been running with OpenWrt since
> around 2016/2017. Back then it was linux v4.4 and required
> many out-of-tree patches (for WIFI, SATA, CRYPTO...), that
> since have been integrated. So, there's nothing else in the
> way I think.
>
> A patch that adds the Meraki vendor-prefix has been sent
> separately, as there's also the Meraki MR32 that I'm working
> on as well. Here's the link to the patch:
> <https://lore.kernel.org/linuxppc-dev/20200822154045.16036-1-chunkeey@gmail.com/>
>
> Now, I've looked around in the arch/powerpc for recent .dts
> and device submissions to get an understanding of what is
> required.
> >From the looks of it, it seems like every device gets a
> skeleton defconfig and a CONFIG_$DEVICE symbol (Like:
> CONFIG_MERAKI_MR24, CONFIG_WD_MYBOOKLIVE).
>
> Will this be the case? Or would it make sense to further
> unite the Bluestone, MR24 and MBL under a common CONFIG_APM82181
> and integrate the BLUESTONE device's defconfig into it as well?
> (I've stumbled across the special machine compatible
> handling of ppc in the Documentation/devicetree/usage-model.rst
> already.)
I haven't found any traces of this to be applied. What is the status of this
patch series? And what is the general state of affairs for the PPC44x?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 0/5] powerpc: apm82181: adding customer devices
2021-07-23 19:19 ` [PATCH v3 0/5] powerpc: apm82181: adding customer devices Andy Shevchenko
@ 2021-07-23 22:08 ` Christian Lamparter
2021-07-26 9:43 ` Andy Shevchenko
0 siblings, 1 reply; 14+ messages in thread
From: Christian Lamparter @ 2021-07-23 22:08 UTC (permalink / raw)
To: Andy Shevchenko
Cc: devicetree, Chris Blake, Rob Herring, Paul Mackerras, linuxppc-dev
Hi Andy!
On 23/07/2021 21:19, Andy Shevchenko wrote:
> On Sun, Sep 06, 2020 at 12:06:10AM +0200, Christian Lamparter wrote:
>> I've been holding on to these devices dts' for a while now.
>> But ever since the recent purge of the PPC405, I'm feeling
>> the urge to move forward.
>>
>> The devices in question have been running with OpenWrt since
>> around 2016/2017. Back then it was linux v4.4 and required
>> many out-of-tree patches (for WIFI, SATA, CRYPTO...), that
>> since have been integrated. So, there's nothing else in the
>> way I think.
>>
>> A patch that adds the Meraki vendor-prefix has been sent
>> separately, as there's also the Meraki MR32 that I'm working
>> on as well. Here's the link to the patch:
>> <https://lore.kernel.org/linuxppc-dev/20200822154045.16036-1-chunkeey@gmail.com/>
>>
>> Now, I've looked around in the arch/powerpc for recent .dts
>> and device submissions to get an understanding of what is
>> required.
>> >From the looks of it, it seems like every device gets a
>> skeleton defconfig and a CONFIG_$DEVICE symbol (Like:
>> CONFIG_MERAKI_MR24, CONFIG_WD_MYBOOKLIVE).
>>
>> Will this be the case? Or would it make sense to further
>> unite the Bluestone, MR24 and MBL under a common CONFIG_APM82181
>> and integrate the BLUESTONE device's defconfig into it as well?
>> (I've stumbled across the special machine compatible
>> handling of ppc in the Documentation/devicetree/usage-model.rst
>> already.)
>
> I haven't found any traces of this to be applied. What is the status of this
> patch series? And what is the general state of affairs for the PPC44x?
My best guess is: It's complicated. While there was a recent big
UPSET EVENT regarding the My Book Live (MBL) that affected "hundreds"
and "thousands": "An unpleasant surprise for My Book Live owners"
(<https://lwn.net/Articles/861235/>). Sadly this wasn't getting any
traction.
I can tell that the mentioned Cisco Meraki MR32 (Broadcom ARM SoC)
got merged. So this is off the plate 😌.
But APM821xx sadly went nowhere 😕. One reason being that I haven't
yet posted a V4, V5 and so on...
In theory, for v4 I would have liked to know how to handle the
kConfig aspect of the series: Would it be "OK" to have a
single CONFIG_APM82181/CONFIG_APM821XX symbol or should there
be a CONFIG_MBL the CONFIG_MR24 (CONFIG_WNDR4700 and CONFIG_MX60W
in the future)?
As for the MBL: Well, If you (or any one else) is interested in
having a more up-to-date Debian. Then I have something:
A while back, I made a "build.sh". This will build a
"out-of-the-box" Debian unstable/SID powerpc system image.
This includes sensible NAS defaults + programs as well as
a Cockpit Web-GUI. But also makes it easily possible to do
the DTBs development on the latest vanilla (5.14-rc2 as of
the time of writing this) kernel for the
MyBook Live Single and Duo:
<https://github.com/chunkeey/mbl-debian>
I can't really make one for the MR24 though. Its 32MiB NAND
makes it difficult to install anything else than OpenWrt
(and get some use out of the device).
So, how to proceed?
Cheers,
Christian
PS.: As for PPC44x health regarding APM82181: It works!
This is with a My Book Live (MBL) and the 5.14.0-rc2(+) kernel.
[ 0.000000] printk: bootconsole [udbg0] enabled
[ 0.000000] Activating Kernel Userspace Execution Prevention
[ 0.000000] Linux version 5.14.0-rc2+ (root@debian64) (powerpc-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 Fri Jul 23 22:59:56 CEST 2021
[ 0.000000] Found initrd at 0xcf000000:0xcfe73b70
[ 0.000000] Using PowerPC 44x Platform machine description
[ 0.000000] -----------------------------------------------------
[ 0.000000] phys_mem_size = 0x10000000
[ 0.000000] dcache_bsize = 0x20
[ 0.000000] icache_bsize = 0x20
[ 0.000000] cpu_features = 0x0000000000000100
[ 0.000000] possible = 0x0000000040000100
[ 0.000000] always = 0x0000000000000100
[ 0.000000] cpu_user_features = 0x8c008000 0x00000000
[ 0.000000] mmu_features = 0x00000008
[ 0.000000] -----------------------------------------------------
[ 0.000000] Top of RAM: 0x10000000, Total RAM: 0x10000000
[ 0.000000] Memory hole size: 0MB
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000000000000-0x000000000fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x000000000fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000000fffffff]
[ 0.000000] MMU: Allocated 1088 bytes of context maps for 255 contexts
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 16352
[ 0.000000] Kernel command line: root=UUID=ef4e8942-768b-4d2e-ba57-486397c97081 console=ttyS0,115200
[ 0.000000] Dentry cache hash table entries: 32768 (order: 3, 131072 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 16384 (order: 2, 65536 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Kernel virtual memory layout:
[ 0.000000] * 0xffbdc000..0xffffc000 : fixmap
[ 0.000000] * 0xd1000000..0xffbdc000 : vmalloc & ioremap
[ 0.000000] Memory: 237088K/262144K available (6096K kernel code, 832K rwdata, 1888K rodata, 256K init, 338K bss, 25056K reserved, 0K cma-reserved)
[ 0.000000] random: get_random_u32 called from cache_random_seq_create+0x68/0x148 with crng_init=0
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 512, nr_irqs: 512, preallocated irqs: 16
[ 0.000000] UIC0 (32 IRQ sources) at DCR 0xc0
[ 0.000000] UIC1 (32 IRQ sources) at DCR 0xd0
[ 0.000000] UIC2 (32 IRQ sources) at DCR 0xe0
[ 0.000000] UIC3 (32 IRQ sources) at DCR 0xf0
[ 0.000000] time_init: decrementer frequency = 800.000008 MHz
[ 0.000000] time_init: processor frequency = 800.000008 MHz
[ 0.000008] clocksource: timebase: mask: 0xffffffffffffffff max_cycles: 0xb881274fa3, max_idle_ns: 440795210636 ns
[ 0.008985] clocksource: timebase mult[1400000] shift[24] registered
[ 0.014006] clockevent: decrementer mult[ccccccef] shift[32] cpu[0]
[ 0.019181] Console: colour dummy device 80x25
[ 0.022289] pid_max: default: 32768 minimum: 301
[ 0.025979] Mount-cache hash table entries: 4096 (order: 0, 16384 bytes, linear)
[ 0.032024] Mountpoint-cache hash table entries: 4096 (order: 0, 16384 bytes, linear)
[ 0.041291] devtmpfs: initialized
...
The "+" Patch is:
<https://github.com/chunkeey/mbl-debian/blob/master/patches/kernel/9999-powerpc-apm82181-add-WD-MyBook-Live-NAS.patch>
(which adds the "wd,mybooklive" to the list of
supported devices to ppc44x_simple.c)
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 0/5] powerpc: apm82181: adding customer devices
2021-07-23 22:08 ` Christian Lamparter
@ 2021-07-26 9:43 ` Andy Shevchenko
0 siblings, 0 replies; 14+ messages in thread
From: Andy Shevchenko @ 2021-07-26 9:43 UTC (permalink / raw)
To: Christian Lamparter
Cc: devicetree, Chris Blake, Rob Herring, Paul Mackerras, linuxppc-dev
On Sat, Jul 24, 2021 at 12:08:30AM +0200, Christian Lamparter wrote:
> On 23/07/2021 21:19, Andy Shevchenko wrote:
> > On Sun, Sep 06, 2020 at 12:06:10AM +0200, Christian Lamparter wrote:
> > > I've been holding on to these devices dts' for a while now.
> > > But ever since the recent purge of the PPC405, I'm feeling
> > > the urge to move forward.
> > >
> > > The devices in question have been running with OpenWrt since
> > > around 2016/2017. Back then it was linux v4.4 and required
> > > many out-of-tree patches (for WIFI, SATA, CRYPTO...), that
> > > since have been integrated. So, there's nothing else in the
> > > way I think.
> > >
> > > A patch that adds the Meraki vendor-prefix has been sent
> > > separately, as there's also the Meraki MR32 that I'm working
> > > on as well. Here's the link to the patch:
> > > <https://lore.kernel.org/linuxppc-dev/20200822154045.16036-1-chunkeey@gmail.com/>
> > >
> > > Now, I've looked around in the arch/powerpc for recent .dts
> > > and device submissions to get an understanding of what is
> > > required.
> > > >From the looks of it, it seems like every device gets a
> > > skeleton defconfig and a CONFIG_$DEVICE symbol (Like:
> > > CONFIG_MERAKI_MR24, CONFIG_WD_MYBOOKLIVE).
> > >
> > > Will this be the case? Or would it make sense to further
> > > unite the Bluestone, MR24 and MBL under a common CONFIG_APM82181
> > > and integrate the BLUESTONE device's defconfig into it as well?
> > > (I've stumbled across the special machine compatible
> > > handling of ppc in the Documentation/devicetree/usage-model.rst
> > > already.)
> >
> > I haven't found any traces of this to be applied. What is the status of this
> > patch series? And what is the general state of affairs for the PPC44x?
>
>
> My best guess is: It's complicated. While there was a recent big
> UPSET EVENT regarding the My Book Live (MBL) that affected "hundreds"
> and "thousands": "An unpleasant surprise for My Book Live owners"
> (<https://lwn.net/Articles/861235/>). Sadly this wasn't getting any
> traction.
>
> I can tell that the mentioned Cisco Meraki MR32 (Broadcom ARM SoC)
> got merged. So this is off the plate 😌.
>
> But APM821xx sadly went nowhere 😕. One reason being that I haven't
> yet posted a V4, V5 and so on...
I will help with testing if needed, please continue this, it's helpful!
> In theory, for v4 I would have liked to know how to handle the
> kConfig aspect of the series: Would it be "OK" to have a
> single CONFIG_APM82181/CONFIG_APM821XX symbol or should there
> be a CONFIG_MBL the CONFIG_MR24 (CONFIG_WNDR4700 and CONFIG_MX60W
> in the future)?
No idea. Not a PPC maintainer here.
> As for the MBL: Well, If you (or any one else) is interested in
> having a more up-to-date Debian. Then I have something:
>
> A while back, I made a "build.sh". This will build a
> "out-of-the-box" Debian unstable/SID powerpc system image.
> This includes sensible NAS defaults + programs as well as
> a Cockpit Web-GUI. But also makes it easily possible to do
> the DTBs development on the latest vanilla (5.14-rc2 as of
> the time of writing this) kernel for the
> MyBook Live Single and Duo:
>
> <https://github.com/chunkeey/mbl-debian>
Thanks for the pointer.
> I can't really make one for the MR24 though. Its 32MiB NAND
> makes it difficult to install anything else than OpenWrt
> (and get some use out of the device).
Not interested in MR24, up to you.
> So, how to proceed?
At least send a v4 :-)
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 14+ messages in thread