PIIX4 DMA Timeout

PIIX4 DMA Timeout

[Gavin Shan]

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Hi All,

There has one MV64460 on my board, which includes 2 PCI bridges. PIIX4 is on slot 3 of PCI1.
But now, IDE driver reported it's timeouted on DMA operation. Thanks in advance for your
suggestions.

Resources of PIIX4 function 1
=====================
0001:00:03.1: idx=0 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=1 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=2 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=3 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=4 flags=0x00000101 start=0xd8000000 end=0xd800000f

Console Output
============
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
PIIX4: IDE controller at PCI slot 0001:00:03.1
0001:00:03.1: idx=0 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=1 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=2 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=3 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=4 flags=0x00000101 start=0xd8000000 end=0xd800000f
PIIX4: chipset revision 1
PIIX4: not 100% native mode: will probe irqs later
    ide0: BM-DMA at 0xd8000000-0xd8000007, BIOS settings: hda:pio, hdb:pio
    ide1: BM-DMA at 0xd8000008-0xd800000f, BIOS settings: hdc:pio, hdd:pio
hdc: HTE721010G9AT00, ATA DISK drive
hdc: max request size: 512KiB
hdc: 195371568 sectors (100030 MB) w/7539KiB Cache, CHS=16383/255/63, UDMA(33)
hdc: cache flushes supported
 hdc:<4>hdc: dma_timer_expiry: dma status == 0x26
hdc: DMA interrupt recovery
hdc: lost interrupt
hdc: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
ide: failed opcode was: unknown
hdc: DMA disabled
ide1: reset: success
 hdc2 hdc3 hdc4

Thanks in advance,
Gavinÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

Re: PIIX4 DMA Timeout

[Maciej W. Rozycki]

On Tue, 20 May 2008, Gavin Shan wrote:

> There has one MV64460 on my board, which includes 2 PCI bridges. PIIX4 is on slot 3 of PCI1.
> But now, IDE driver reported it's timeouted on DMA operation. Thanks in advance for your
> suggestions.
[...]
> PIIX4: chipset revision 1
> PIIX4: not 100% native mode: will probe irqs later
>     ide0: BM-DMA at 0xd8000000-0xd8000007, BIOS settings: hda:pio, hdb:pio
>     ide1: BM-DMA at 0xd8000008-0xd800000f, BIOS settings: hdc:pio, hdd:pio
> hdc: HTE721010G9AT00, ATA DISK drive
> hdc: max request size: 512KiB
> hdc: 195371568 sectors (100030 MB) w/7539KiB Cache, CHS=16383/255/63, UDMA(33)
> hdc: cache flushes supported
>  hdc:<4>hdc: dma_timer_expiry: dma status == 0x26
> hdc: DMA interrupt recovery
> hdc: lost interrupt
> hdc: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
> ide: failed opcode was: unknown
> hdc: DMA disabled
> ide1: reset: success
>  hdc2 hdc3 hdc4

 It looks like some problem with interrupt routing.  At least with some of
the PIIX chips I recall there was some limitation about how the IDE
interrupts had to be used for DMA to be operational.  For PIO modes there
were no restrictions.  Do you have chip-level documentation for your
board?

  Maciej

Re: PIIX4 DMA Timeout

[gshan]

Maciej W. Rozycki wrote:
> On Tue, 20 May 2008, Gavin Shan wrote:
>
>   
>> There has one MV64460 on my board, which includes 2 PCI bridges. PIIX4 is on slot 3 of PCI1.
>> But now, IDE driver reported it's timeouted on DMA operation. Thanks in advance for your
>> suggestions.
>>     
> [...]
>   
>> PIIX4: chipset revision 1
>> PIIX4: not 100% native mode: will probe irqs later
>>     ide0: BM-DMA at 0xd8000000-0xd8000007, BIOS settings: hda:pio, hdb:pio
>>     ide1: BM-DMA at 0xd8000008-0xd800000f, BIOS settings: hdc:pio, hdd:pio
>> hdc: HTE721010G9AT00, ATA DISK drive
>> hdc: max request size: 512KiB
>> hdc: 195371568 sectors (100030 MB) w/7539KiB Cache, CHS=16383/255/63, UDMA(33)
>> hdc: cache flushes supported
>>  hdc:<4>hdc: dma_timer_expiry: dma status == 0x26
>> hdc: DMA interrupt recovery
>> hdc: lost interrupt
>> hdc: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
>> ide: failed opcode was: unknown
>> hdc: DMA disabled
>> ide1: reset: success
>>  hdc2 hdc3 hdc4
>>     
>
>  It looks like some problem with interrupt routing.  At least with some of
> the PIIX chips I recall there was some limitation about how the IDE
> interrupts had to be used for DMA to be operational.  For PIO modes there
> were no restrictions.  Do you have chip-level documentation for your
> board?
>
>   Maciej
>   
Maciej, thank you very much for your reply. I don't think this was caused by
interrupt routing. I added lots of "printk" before following output, and saw
interrupts could be triggered correctly.

hdc: 195371568 sectors (100030 MB) w/7539KiB Cache, CHS=16383/255/63, UDMA(33)

LynxOS has been run successfully on this board, and we want port it to Linux recently.

I'm not sure which resource (I/O or Memory space) should be used for DMA operation because
all memory resources haven't been set (the flag is 0x2xxxxxxx). So my question is DMA operation
could succeed with I/O resource?

Re: PIIX4 DMA Timeout

[Maciej W. Rozycki]

On Wed, 21 May 2008, gshan wrote:

> Maciej, thank you very much for your reply. I don't think this was caused by
> interrupt routing. I added lots of "printk" before following output, and saw
> interrupts could be triggered correctly.

 As I wrote, that was a restriction that did not affect PIO operation.  
IIRC, you had to wire IDE interrupt lines to motherboard interrupt (MIRQ)  
lines of the south-bridge rather than regular IRQ14/15 lines and then
route them to IRQ14/15 inputs of the embedded slave 8259A core via some
internal interrupt routing register for DMA to work correctly.  PIO worked
just fine either way, because the interrupts were delivered to the CPU
after all, but some internal logic of the IDE adapter used them too in the
DMA mode and expected them on MIRQ lines.

 This is from memory -- I have the relevant datasheets somewhere, but you
could double-check it as well as cross-check with board documentation
yourself.  It may not apply to the PIIX4 specifically -- it may have only
been earlier south-bridges of the PIIX line, but I cannot remember for
sure.

> hdc: 195371568 sectors (100030 MB) w/7539KiB Cache, CHS=16383/255/63, UDMA(33)
> 
> LynxOS has been run successfully on this board, and we want port it to Linux recently.

 That does not mean anything here -- do you know for sure it uses DMA with
IDE?  I suppose Linux would run correctly if you configured the IDE driver
for PIO operation too.  Of course you do not want to make regular use of
IDE PIO modes unless you cannot spell performance; never mind additional
data protection in UDMA modes.

> I'm not sure which resource (I/O or Memory space) should be used for DMA operation because
> all memory resources haven't been set (the flag is 0x2xxxxxxx). So my question is DMA operation
> could succeed with I/O resource?

 The I/O BAR has been configured, though I have to admit the values set
may be problematic:

    ide0: BM-DMA at 0xd8000000-0xd8000007, BIOS settings: hda:pio, hdb:pio
    ide1: BM-DMA at 0xd8000008-0xd800000f, BIOS settings: hdc:pio, hdd:pio

Port I/O over PCI is generally not supported outside the low 64kB of
space, although it may work in some configurations.  Also here you need a
couple of ports in a range above 3GB as well as the usual ports in the
first 1kB implied by the PIIX4.  Given host bridges can usually only
allocate contiguous areas for I/O purposes you would need over 3GB of host
address space for port I/O.  That may be available in a 64-bit system, but
I would be suspicious.

 Linux's PCI subsystem can automatically assign address space to PCI port
and memory I/O resources reasonably if you ask it to do so.  You have to
tell it what host CPU address space is available for this purpose first
though.  You can get this information from configuration registers of the
host bridge.  Of course these registers have to be set in a sensible way
in the first place, which may not necessarily be the case.  This is the
area I would look into first.  Good luck!

  Maciej

PIIX4 DMA Timeout

[Gavin Shan]

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Hi All,

There has one MV64460 on my board, which includes 2 PCI bridges. PIIX4 is on slot 3 of PCI1.
But now, IDE driver reported it's timeouted on DMA operation. Thanks in advance for your
suggestions.

Resources of PIIX4 function 1
=====================
0001:00:03.1: idx=0 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=1 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=2 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=3 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=4 flags=0x00000101 start=0xd8000000 end=0xd800000f

Console Output
============
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
PIIX4: IDE controller at PCI slot 0001:00:03.1
0001:00:03.1: idx=0 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=1 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=2 flags=0x20000110 start=0x00000000 end=0x00000007
0001:00:03.1: idx=3 flags=0x20000110 start=0x00000000 end=0x00000000
0001:00:03.1: idx=4 flags=0x00000101 start=0xd8000000 end=0xd800000f
PIIX4: chipset revision 1
PIIX4: not 100% native mode: will probe irqs later
    ide0: BM-DMA at 0xd8000000-0xd8000007, BIOS settings: hda:pio, hdb:pio
    ide1: BM-DMA at 0xd8000008-0xd800000f, BIOS settings: hdc:pio, hdd:pio
hdc: HTE721010G9AT00, ATA DISK drive
hdc: max request size: 512KiB
hdc: 195371568 sectors (100030 MB) w/7539KiB Cache, CHS=16383/255/63, UDMA(33)
hdc: cache flushes supported
 hdc:<4>hdc: dma_timer_expiry: dma status == 0x26
hdc: DMA interrupt recovery
hdc: lost interrupt
hdc: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
ide: failed opcode was: unknown
hdc: DMA disabled
ide1: reset: success
 hdc2 hdc3 hdc4

Thanks in advance,
Gavinÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥