From: Christopher Lameter <cl@linux.com>
To: Barret Rhoden <brho@google.com>
Cc: Dennis Zhou <dennis@kernel.org>,
Eial Czerwacki <eial@scalemp.com>,
tj@kernel.org, linux-kernel@vger.kernel.org,
Shai Fultheim <shai@scalemp.com>, Oren Twaig <oren@scalemp.com>,
"Paul E. McKenney" <paulmck@linux.ibm.com>
Subject: Re: [PATCH] percpu/module resevation: change resevation size iff X86_VSMP is set
Date: Fri, 1 Mar 2019 21:54:21 +0000 [thread overview]
Message-ID: <010001693b404440-248fa987-624c-4587-940b-56e2ed4226d9-000000@email.amazonses.com> (raw)
In-Reply-To: <c72402f2-967e-cd56-99d8-9139c9e7f267@google.com>
On Fri, 1 Mar 2019, Barret Rhoden wrote:
> I'm not familiar with VSMP - how bad is it to use L1 cache alignment instead
> of 4K page alignment? Maybe some structures can use the smaller alignment?
> Or maybe have VSMP require SRCU-using modules to be built-in?
It is very expensive. VMSP exchanges 4K segments via RDMA between servers
to build a large address space and run a kernel in the large address
space. Using smaller segments can cause a lot of
"cacheline" bouncing (meaning transfers of 4K segments back and forth
between servers).
next prev parent reply other threads:[~2019-03-01 21:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-21 11:47 [PATCH] percpu/module resevation: change resevation size iff X86_VSMP is set Eial Czerwacki
2019-01-30 10:33 ` Eial Czerwacki
2019-03-01 18:30 ` Barret Rhoden
2019-03-01 20:34 ` Dennis Zhou
2019-03-01 21:27 ` Barret Rhoden
2019-03-01 21:54 ` Christopher Lameter [this message]
2019-03-13 19:40 ` Barret Rhoden
2019-03-13 20:26 ` Tejun Heo
2019-03-13 21:22 ` Paul E. McKenney
2019-03-13 21:29 ` Tejun Heo
2019-03-13 23:11 ` Paul E. McKenney
2019-03-14 17:36 ` Tejun Heo
2019-03-14 22:19 ` Paul E. McKenney
2019-03-18 8:18 ` Eial Czerwacki
2019-03-18 14:27 ` Paul E. McKenney
2019-04-04 20:53 ` Christopher Lameter
2019-03-04 7:42 ` Eial Czerwacki
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