From: Lokesh Vutla <lokeshvutla@ti.com>
To: Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Rob Herring <robh+dt@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 3/9] dt-bindings: interrupt-controller: arm, gic-v3: Describe ESPI range support
Date: Tue, 23 Jul 2019 18:29:29 +0530 [thread overview]
Message-ID: <04e80def-c8e3-a403-036e-2a64db935ed4@ti.com> (raw)
In-Reply-To: <20190723104437.154403-4-maz@kernel.org>
On 23/07/19 4:14 PM, Marc Zyngier wrote:
> GICv3.1 introduces support for new interrupt ranges, one of them being
> the Extended SPI range (ESPI). The DT binding is extended to deal with
> it as a new interrupt class.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> .../devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> index c34df35a25fc..98a3ecda8e07 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> @@ -44,11 +44,12 @@ properties:
> be at least 4.
>
> The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
> - interrupts. Other values are reserved for future use.
> + interrupts, 2 for interrupts in the Extended SPI range. Other values
> + are reserved for future use.
Any reason why hardware did not consider extending SPIs from 1020:2043? This way
only EPPI would have been introduced. Just a thought.
Either ways, just to be consistent with hardware numbering can ESPI range be 3
and EPPI range be 2?
Thanks and regards,
Lokesh
>
> The 2nd cell contains the interrupt number for the interrupt type.
> SPI interrupts are in the range [0-987]. PPI interrupts are in the
> - range [0-15].
> + range [0-15]. Extented SPI interrupts are in the range [0-1023].
>
> The 3rd cell is the flags, encoded as follows:
> bits[3:0] trigger type and level flags.
>
next prev parent reply other threads:[~2019-07-23 13:00 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-23 10:44 [PATCH 0/9] irqchip/gic-v3: Add support for GICv3.1 extended PPI/SPI ranges Marc Zyngier
2019-07-23 10:44 ` [PATCH 1/9] irqchip/gic: Rework gic_configure_irq to take the full ICFGR base Marc Zyngier
2019-07-23 10:44 ` [PATCH 2/9] irqchip/gic-v3: Add INTID range and convertion primitives Marc Zyngier
2019-07-23 10:44 ` [PATCH 3/9] dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support Marc Zyngier
2019-07-23 12:59 ` Lokesh Vutla [this message]
2019-07-23 13:15 ` [PATCH 3/9] dt-bindings: interrupt-controller: arm, gic-v3: " Marc Zyngier
2019-07-23 13:35 ` Lokesh Vutla
2019-07-23 10:44 ` [PATCH 4/9] irqchip/gic-v3: Add " Marc Zyngier
2019-07-23 12:50 ` Lokesh Vutla
2019-07-23 13:04 ` Marc Zyngier
2019-07-23 10:44 ` [PATCH 5/9] irqchip/gic: Prepare for more than 16 PPIs Marc Zyngier
2019-07-23 10:44 ` [PATCH 6/9] irqchip/gic-v3: Dynamically allocate PPI NMI refcounts Marc Zyngier
2019-07-23 10:44 ` [PATCH 7/9] irqchip/gic-v3: Dynamically allocate PPI partition descriptors Marc Zyngier
2019-07-23 10:44 ` [PATCH 8/9] dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support Marc Zyngier
2019-07-23 10:44 ` [PATCH 9/9] irqchip/gic-v3: Add " Marc Zyngier
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