[PATCH] crypto: caam - set RDB bit in security configuration register

[PATCH] crypto: caam - set RDB bit in security configuration register

[Vakul Garg]

This change is required for post SEC-5.0 devices which have RNG4. Setting RDB
in security configuration register allows CAAM to use the "Random Data Buffer"
to be filled by a single request. The Random Data Buffer is large enough for
ten packets to get their IVs from a single request. If the Random Data Buffer
is not enabled, then each IV causes a separate request, and RNG4 hardware
cannot keep up resulting in lower IPSEC throughput.

Signed-off-by: Vakul Garg <vakul@freescale.com>
---

 drivers/crypto/caam/ctrl.c |    3 +++
 drivers/crypto/caam/regs.h |    4 +++-
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index b3fecfa..53dd54e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -234,6 +234,9 @@ static int caam_probe(struct platform_device *pdev)
 	setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
 		  (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 
+	if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
+		setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
+
 	if (sizeof(dma_addr_t) == sizeof(u64))
 		if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
 			dma_set_mask(dev, DMA_BIT_MASK(40));
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 3223fc6..cd6feda 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -252,7 +252,8 @@ struct caam_ctrl {
 	/* Read/Writable					        */
 	u32 rsvd1;
 	u32 mcr;		/* MCFG      Master Config Register  */
-	u32 rsvd2[2];
+	u32 rsvd2;
+	u32 scfgr;		/* SCFGR, Security Config Register */
 
 	/* Bus Access Configuration Section			010-11f */
 	/* Read/Writable                                                */
@@ -299,6 +300,7 @@ struct caam_ctrl {
 #define MCFGR_WDFAIL		0x20000000 /* DECO watchdog force-fail */
 #define MCFGR_DMA_RESET		0x10000000
 #define MCFGR_LONG_PTR		0x00010000 /* Use >32-bit desc addressing */
+#define SCFGR_RDBENABLE		0x00000400
 
 /* AXI read cache control */
 #define MCFGR_ARCACHE_SHIFT	12
-- 
1.7.7.6

Re: [PATCH] crypto: caam - set RDB bit in security configuration register

[Kim Phillips]

On Wed, 6 Feb 2013 17:17:46 +0530
Vakul Garg <vakul@freescale.com> wrote:

> This change is required for post SEC-5.0 devices which have RNG4. Setting RDB

wrap your commit message text to 75 chars

> in security configuration register allows CAAM to use the "Random Data Buffer"
> to be filled by a single request. The Random Data Buffer is large enough for
> ten packets to get their IVs from a single request. If the Random Data Buffer
> is not enabled, then each IV causes a separate request, and RNG4 hardware
> cannot keep up resulting in lower IPSEC throughput.

Linux kernel IPSec or another IPSEC stack?  how much lower?

> +	if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
> +		setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
> +

this belongs further down - at the end of the RNG4 initialization
section.

Kim

RE: [PATCH] crypto: caam - set RDB bit in security configuration register

[Garg Vakul-B16394]

> -----Original Message-----
> From: Phillips Kim-R1AAHA
> Sent: Thursday, February 07, 2013 7:03 AM
> To: Garg Vakul-B16394
> Cc: linux-crypto@vger.kernel.org; Herbert Xu; David S. Miller; Liu
> Shengzhou-B36685; Porosanu Alexandru-B06830; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] crypto: caam - set RDB bit in security configuration
> register
> 
> On Wed, 6 Feb 2013 17:17:46 +0530
> Vakul Garg <vakul@freescale.com> wrote:
> 
> > This change is required for post SEC-5.0 devices which have RNG4.
> > Setting RDB
> 
> wrap your commit message text to 75 chars
Ok 


> 
> > in security configuration register allows CAAM to use the "Random Data
> Buffer"
> > to be filled by a single request. The Random Data Buffer is large
> > enough for ten packets to get their IVs from a single request. If the
> > Random Data Buffer is not enabled, then each IV causes a separate
> > request, and RNG4 hardware cannot keep up resulting in lower IPSEC
> throughput.
> 
> Linux kernel IPSec or another IPSEC stack?  how much lower?

We measured USDPAA IPSEC throughput to be 1.9 times better on T4240 with this change.

> 
> > +	if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
> > +		setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
> > +
> 
> this belongs further down - at the end of the RNG4 initialization
> section.

Ok

> 
> Kim