[PATCH 1/5] dt-bindings: memory: Document Tegra210 EMC table

[PATCH 1/5] dt-bindings: memory: Document Tegra210 EMC table

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add device tree bindings for the Tegra210 EMC table that is passed via a
reserved-memory device tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../nvidia,tegra210-emc-table.yaml            | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra210-emc-table.yaml

diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra210-emc-table.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra210-emc-table.yaml
new file mode 100644
index 000000000000..035a50fe3ee4
--- /dev/null
+++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra210-emc-table.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra210-emc-table.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra210 EMC Frequency Table Device Tree Bindings
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: On Tegra210, firmware passes a binary representation of the
+  EMC frequency table via a reserved memory region.
+
+allOf:
+  - $ref: "reserved-memory.yaml"
+
+properties:
+  compatible:
+    const: nvidia,tegra210-emc-table
+
+  reg:
+    description: region of memory reserved by firmware to pass the EMC
+      frequency table
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
-- 
2.34.1

[PATCH 2/5] dt-bindings: memory: Add Tegra210 memory controller bindings

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Document the bindings for the memory controller found on Tegra210 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../nvidia,tegra210-mc.yaml                   | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
new file mode 100644
index 000000000000..ef21c11052e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra210 SoC Memory Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+  The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split into two 32 bit
+  channels to support LPDDR3 and LPDDR4 with x16 subpartitions. The MC handles memory requests for
+  34-bit virtual addresses from internal clients and arbitrates among them to allocate memory
+  bandwidth.
+
+  Up to 8 GiB of physical memory can be supported. Security features such as encryption of traffic
+  to and from DRAM via general security apertures are available for video and other secure
+  applications.
+
+properties:
+  $nodename:
+    pattern: "^memory-controller@[0-9a-f]+$"
+
+  compatible:
+    items:
+      - enum:
+          - nvidia,tegra210-mc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  clock-names:
+    items:
+      - const: mc
+
+  "#iommu-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#iommu-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mc: memory-controller@70019000 {
+        compatible = "nvidia,tegra210-mc";
+        reg = <0x70019000 0x1000>;
+        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA210_CLK_MC>;
+        clock-names = "mc";
+
+        #iommu-cells = <1>;
+        #reset-cells = <1>;
+    };
-- 
2.34.1

[PATCH 3/5] dt-bindings: memory: Add Tegra114 memory controller bindings

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Document the bindings for the memory controller found on Tegra114 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../nvidia,tegra114-mc.yaml                   | 85 +++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml
new file mode 100644
index 000000000000..2fa50eb3aadb
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra114-mc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra114 SoC Memory Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+  The Tegra114 Memory Controller architecturally consists of the following parts:
+
+    Arbitration Domains, which can handle a single request or response per
+    clock from a group of clients. Typically, a system has a single Arbitration
+    Domain, but an implementation may divide the client space into multiple
+    Arbitration Domains to increase the effective system bandwidth.
+
+    Protocol Arbiter, which manage a related pool of memory devices. A system
+    may have a single Protocol Arbiter or multiple Protocol Arbiters.
+
+    Memory Crossbar, which routes request and responses between Arbitration
+    Domains and Protocol Arbiters. In the simplest version of the system, the
+    Memory Crossbar is just a pass through between a single Arbitration Domain
+    and a single Protocol Arbiter.
+
+    Global Resources, which include things like configuration registers which
+    are shared across the Memory Subsystem.
+
+  The Tegra114 Memory Controller handles memory requests from internal clients
+  and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
+  SDRAMs.
+
+properties:
+  compatible:
+    const: nvidia,tegra114-mc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: mc
+
+  interrupts:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+  "#iommu-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#reset-cells"
+  - "#iommu-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra114-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    memory-controller@70019000 {
+      compatible = "nvidia,tegra114-mc";
+      reg = <0x70019000 0x1000>;
+      interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+      clocks = <&tegra_car TEGRA114_CLK_MC>;
+      clock-names = "mc";
+
+      #reset-cells = <1>;
+      #iommu-cells = <1>;
+    };
-- 
2.34.1

[PATCH 4/5] dt-bindings: memory: tegra: Fix Tegra132 compatible string

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

While the memory controller found on Tegra132 is largely compatible with
the one found on Tegra124, there are some differences that may require
more specific matching on a Tegra132 compatible string, so add one to
the list of compatible strings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/memory-controllers/nvidia,tegra124-emc.yaml    | 6 +++++-
 .../bindings/memory-controllers/nvidia,tegra124-mc.yaml     | 4 +++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
index 9163c3f12a85..90666e8d2de7 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
@@ -16,7 +16,11 @@ description: |
 
 properties:
   compatible:
-    const: nvidia,tegra124-emc
+    oneOf:
+      - const: nvidia,tegra124-emc
+      - items:
+          - const: nvidia,tegra132-emc
+          - const: nvidia,tegra124-emc
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
index 7b18b4d11e0a..887917e02bfa 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
@@ -19,7 +19,9 @@ description: |
 
 properties:
   compatible:
-    const: nvidia,tegra124-mc
+    enum:
+      - nvidia,tegra124-mc
+      - nvidia,tegra132-mc
 
   reg:
     maxItems: 1
-- 
2.34.1

[PATCH 5/5] dt-bindings: memory: tegra210: Mark EMC as cooling device

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The external memory controller found on Tegra210 can use throttling of
the EMC frequency in order to reduce the memory chip temperature. Mark
the memory controller as a cooling device to take advantage of this
functionality.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/memory-controllers/nvidia,tegra210-emc.yaml  | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
index bc8477e7ab19..95c14deb8941 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
@@ -44,6 +44,11 @@ properties:
     description:
       phandle of the memory controller node
 
+allOf:
+  - $ref: ../thermal/thermal-cooling-devices.yaml
+
+unevaluatedProperties: false
+
 required:
   - compatible
   - reg
@@ -51,8 +56,6 @@ required:
   - clock-names
   - nvidia,memory-controller
 
-additionalProperties: false
-
 examples:
   - |
     #include <dt-bindings/clock/tegra210-car.h>
@@ -79,4 +82,5 @@ examples:
         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
         memory-region = <&emc_table>;
         nvidia,memory-controller = <&mc>;
+        #cooling-cells = <2>;
     };
-- 
2.34.1

Re: [PATCH 2/5] dt-bindings: memory: Add Tegra210 memory controller bindings

[Krzysztof Kozlowski]

On 17/12/2021 17:59, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Document the bindings for the memory controller found on Tegra210 SoCs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../nvidia,tegra210-mc.yaml                   | 77 +++++++++++++++++++
>  1 file changed, 77 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
> new file mode 100644
> index 000000000000..ef21c11052e3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra210 SoC Memory Controller
> +
> +maintainers:
> +  - Thierry Reding <thierry.reding@gmail.com>
> +  - Jon Hunter <jonathanh@nvidia.com>
> +
> +description: |
> +  The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split into two 32 bit
> +  channels to support LPDDR3 and LPDDR4 with x16 subpartitions. The MC handles memory requests for
> +  34-bit virtual addresses from internal clients and arbitrates among them to allocate memory
> +  bandwidth.
> +
> +  Up to 8 GiB of physical memory can be supported. Security features such as encryption of traffic
> +  to and from DRAM via general security apertures are available for video and other secure
> +  applications.
> +
> +properties:
> +  $nodename:
> +    pattern: "^memory-controller@[0-9a-f]+$"
> +
> +  compatible:
> +    items:
> +      - enum:
> +          - nvidia,tegra210-mc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: module clock
> +
> +  clock-names:
> +    items:
> +      - const: mc
> +
> +  "#iommu-cells":
> +    const: 1
> +
> +  "#reset-cells":
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - "#iommu-cells"
> +  - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/tegra210-car.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    mc: memory-controller@70019000 {

If there is going to be resubmit, please skip the alias. It just adds
noise. Without resubmit, I can fix it when applying.


Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: memory: Add Tegra114 memory controller bindings

[Krzysztof Kozlowski]

On 17/12/2021 17:59, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Document the bindings for the memory controller found on Tegra114 SoCs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../nvidia,tegra114-mc.yaml                   | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml
> new file mode 100644
> index 000000000000..2fa50eb3aadb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra114-mc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra114 SoC Memory Controller
> +
> +maintainers:
> +  - Thierry Reding <thierry.reding@gmail.com>
> +  - Jon Hunter <jonathanh@nvidia.com>
> +
> +description: |
> +  The Tegra114 Memory Controller architecturally consists of the following parts:
> +
> +    Arbitration Domains, which can handle a single request or response per
> +    clock from a group of clients. Typically, a system has a single Arbitration
> +    Domain, but an implementation may divide the client space into multiple
> +    Arbitration Domains to increase the effective system bandwidth.
> +
> +    Protocol Arbiter, which manage a related pool of memory devices. A system
> +    may have a single Protocol Arbiter or multiple Protocol Arbiters.
> +
> +    Memory Crossbar, which routes request and responses between Arbitration
> +    Domains and Protocol Arbiters. In the simplest version of the system, the
> +    Memory Crossbar is just a pass through between a single Arbitration Domain
> +    and a single Protocol Arbiter.
> +
> +    Global Resources, which include things like configuration registers which
> +    are shared across the Memory Subsystem.
> +
> +  The Tegra114 Memory Controller handles memory requests from internal clients
> +  and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
> +  SDRAMs.
> +
> +properties:
> +  compatible:
> +    const: nvidia,tegra114-mc
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: mc
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  "#reset-cells":
> +    const: 1
> +
> +  "#iommu-cells":
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - "#reset-cells"
> +  - "#iommu-cells"
> +
> +additionalProperties: false

The binding looks the same as Tegra210, Tegra 20 MC. What is the point
of having three separate binding documents which are exactly the same?


Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: memory: Add Tegra114 memory controller bindings

[Rob Herring]

On Fri, 17 Dec 2021 17:59:17 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Document the bindings for the memory controller found on Tegra114 SoCs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../nvidia,tegra114-mc.yaml                   | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1570202


memory-controller@70019000: '#reset-cells' is a required property
	arch/arm/boot/dts/tegra114-dalmore.dt.yaml
	arch/arm/boot/dts/tegra114-roth.dt.yaml
	arch/arm/boot/dts/tegra114-tn7.dt.yaml

Re: [PATCH 4/5] dt-bindings: memory: tegra: Fix Tegra132 compatible string

[Rob Herring]

On Fri, 17 Dec 2021 17:59:18 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> While the memory controller found on Tegra132 is largely compatible with
> the one found on Tegra124, there are some differences that may require
> more specific matching on a Tegra132 compatible string, so add one to
> the list of compatible strings.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/memory-controllers/nvidia,tegra124-emc.yaml    | 6 +++++-
>  .../bindings/memory-controllers/nvidia,tegra124-mc.yaml     | 4 +++-
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1570204


external-memory-controller@7001b000: compatible: 'oneOf' conditional failed, one must be fixed:
	arch/arm64/boot/dts/nvidia/tegra132-norrin.dt.yaml

external-memory-controller@7001b000: '#interconnect-cells' is a required property
	arch/arm64/boot/dts/nvidia/tegra132-norrin.dt.yaml

external-memory-controller@7001b000: 'operating-points-v2' is a required property
	arch/arm64/boot/dts/nvidia/tegra132-norrin.dt.yaml

memory-controller@70019000: '#interconnect-cells' is a required property
	arch/arm64/boot/dts/nvidia/tegra132-norrin.dt.yaml

memory-controller@70019000: '#reset-cells' is a required property
	arch/arm64/boot/dts/nvidia/tegra132-norrin.dt.yaml

Re: [PATCH 5/5] dt-bindings: memory: tegra210: Mark EMC as cooling device

[Rob Herring]

On Fri, Dec 17, 2021 at 05:59:19PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The external memory controller found on Tegra210 can use throttling of
> the EMC frequency in order to reduce the memory chip temperature. Mark
> the memory controller as a cooling device to take advantage of this
> functionality.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/memory-controllers/nvidia,tegra210-emc.yaml  | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> index bc8477e7ab19..95c14deb8941 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> @@ -44,6 +44,11 @@ properties:
>      description:
>        phandle of the memory controller node
>  
> +allOf:
> +  - $ref: ../thermal/thermal-cooling-devices.yaml

/schemas/thermal/...

With that,

Reviewed-by: Rob Herring <robh@kernel.org>

> +
> +unevaluatedProperties: false
> +
>  required:
>    - compatible
>    - reg
> @@ -51,8 +56,6 @@ required:
>    - clock-names
>    - nvidia,memory-controller
>  
> -additionalProperties: false
> -
>  examples:
>    - |
>      #include <dt-bindings/clock/tegra210-car.h>
> @@ -79,4 +82,5 @@ examples:
>          interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>          memory-region = <&emc_table>;
>          nvidia,memory-controller = <&mc>;
> +        #cooling-cells = <2>;
>      };
> -- 
> 2.34.1
> 
> 

Re: [PATCH 4/5] dt-bindings: memory: tegra: Fix Tegra132 compatible string

[Rob Herring]

On Fri, 17 Dec 2021 17:59:18 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> While the memory controller found on Tegra132 is largely compatible with
> the one found on Tegra124, there are some differences that may require
> more specific matching on a Tegra132 compatible string, so add one to
> the list of compatible strings.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/memory-controllers/nvidia,tegra124-emc.yaml    | 6 +++++-
>  .../bindings/memory-controllers/nvidia,tegra124-mc.yaml     | 4 +++-
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/5] dt-bindings: memory: Document Tegra210 EMC table

[Rob Herring]

On Fri, 17 Dec 2021 17:59:15 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add device tree bindings for the Tegra210 EMC table that is passed via a
> reserved-memory device tree node.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../nvidia,tegra210-emc-table.yaml            | 31 +++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra210-emc-table.yaml
> 

This one appears to stand on its own, so applied, thanks!