Re: Test Patch: 2.5.69 Interrupt Latency

[Paul Fulghum <paulkf@microgate.com>]

I think I found the key to this whole problem:

Note:I mistakenly referred to the chipset as PIIX3
in previous messages, in fact it is the PIIX4 (BX)

The PIIX4 errata states that false resume indications
can be generated if CLK48 is active during an
overcondition indication (OC[1..0]).

Sure enough, the USBPORTSC[12] registers constantly
report a status of 0C80 which shows that both
ports are showing overcurrent condition (which
disables the associated port).

My guess is that HP deliberately tied the OC[1..0]
inputs active to force the ports to a disabled state.

So checking for the case of both ports constantly
in OC condition and disabled may be a reasonable
way to either disable the controller altogether or 
at least not do the wakeup/suspend shuffle.

Any comments?

-- 
Paul Fulghum, paulkf@microgate.com
Microgate Corporation, http://www.microgate.com