Re: [PATCH 1/4] glibc: Perform rseq(2) registration at C startup and thread creation (v7)

From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
To: Paul Burton <paul.burton@mips.com>
Cc: Carlos O'Donell <codonell@redhat.com>,
	Will Deacon <will.deacon@arm.com>,
	Boqun Feng <boqun.feng@gmail.com>,
	heiko carstens <heiko.carstens@de.ibm.com>,
	gor <gor@linux.ibm.com>, schwidefsky <schwidefsky@de.ibm.com>,
	"Russell King, ARM Linux" <linux@armlinux.org.uk>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Paul Mackerras <paulus@samba.org>,
	Michael Ellerman <mpe@ellerman.id.au>, carlos <carlos@redhat.com>,
	Florian Weimer <fweimer@redhat.com>,
	Joseph Myers <joseph@codesourcery.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	libc-alpha <libc-alpha@sourceware.org>,
	Thomas Gleixner <tglx@linutronix.de>, Ben Maurer <bmaurer@fb.com>,
	Peter Zijlstra <peterz@infradead.org>,
	"Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
	Dave Watson <davejwatson@fb.com>, Paul Turner <pjt@google.com>,
	Rich Felker <dalias@libc.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	linux-api <linux-api@vger.kernel.org>
Subject: Re: [PATCH 1/4] glibc: Perform rseq(2) registration at C startup and thread creation (v7)
Date: Wed, 24 Apr 2019 11:05:42 -0400 (EDT)	[thread overview]
Message-ID: <1103046939.521.1556118342613.JavaMail.zimbra@efficios.com> (raw)
In-Reply-To: <1031613720.1496.1555613900993.JavaMail.zimbra@efficios.com>

----- On Apr 18, 2019, at 2:58 PM, Mathieu Desnoyers mathieu.desnoyers@efficios.com wrote:

> ----- On Apr 4, 2019, at 5:41 PM, Paul Burton paul.burton@mips.com wrote:
> [...]
> 
>>> 2a. A uncommon TRAP hopefully with some immediate data encoded (maybe uncommon)
>> 
>> Our break instruction has a 19b immediate in nanoMIPS (20b for microMIPS
>> & classic MIPS) so that could be something like:
>> 
>>  break 0x7273       # ASCII 'rs'
>> 
> 
> Hi Paul,
> 
> I like this uncommon break instruction as signature choice.
> 
> However, if I try to compile assembler with a break 0x7273 instruction
> with mips64 and mips32 toolchains (gcc version 8.2.0 (Ubuntu
> 8.2.0-1ubuntu2~18.04))
> I get:
> 
> /tmp/ccVh9F7T.s: Assembler messages:
> /tmp/ccVh9F7T.s:24: Error: operand 1 out of range `break 0x7273'
> 
> It works up to the value 0x3FF, which seems to use the top 10
> code bits:
> 
>   a:	03ff 0007 	break	0x3ff
> 
> Would a "break 0x350" be a good choice as well ?
> 
> Any idea why 0x7273 is not accepted by my assembler ?
> 
> I also tried crafting the assembler with values between 0x3FF and 0x7273
> in the 20 code bits. It seems fine from an objdump perspective:
> 
> ".long 0x03FFFC7\n\t"
> 
> generates:
> 
>  10:	003f ffc7 	break	0x3f,0x3ff
> 
> What I don't understand is why the instruction generated by my
> toolchain ends with the last 6 bits "000111", whereas the mips32
> instruction set specifies break as ending with "001101" [1].
> What am I missing ?
> 
> Also, the nanomips break code [2] has a completely different
> instruction layout. Should we use a different signature when
> compiling for nanomips ? What #ifdef should we use ? Do I
> need a special toolchain to generate nanomips binaries ?

Hi Paul, I'm still waiting for feedback on the MIPS front.

Meanwhile, I plan to use #define RSEQ_SIG 0x0350000d which maps to:

   0350000d 	break	0x350

and use RSEQ_SIG in assembly with:

   ".word " __rseq_str(RSEQ_SIG) "\n\t"

on big and little endian MIPS, for MIPS32 and MIPS64, based on
code generated with gcc version 8.2.0 (Ubuntu 8.2.0-1ubuntu2~18.04).

Let me know if it needs to be tweaked.

Thanks,

Mathieu

> 
> Thanks,
> 
> Mathieu
> 
> [1]
> http://hades.mech.northwestern.edu/images/1/16/MIPS32_Architecture_Volume_II-A_Instruction_Set.pdf
> [2]
> https://s3-eu-west-1.amazonaws.com/downloads-mips/I7200/I7200+product+launch/MIPS_nanomips32_ISA_TRM_01_01_MD01247.pdf
> 
> --
> Mathieu Desnoyers
> EfficiOS Inc.
> http://www.efficios.com

-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com