From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Paul Burton <paul.burton@mips.com>
Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
Carlos O'Donell <codonell@redhat.com>,
Will Deacon <will.deacon@arm.com>,
Boqun Feng <boqun.feng@gmail.com>,
heiko carstens <heiko.carstens@de.ibm.com>,
gor <gor@linux.ibm.com>, schwidefsky <schwidefsky@de.ibm.com>,
"Russell King, ARM Linux" <linux@armlinux.org.uk>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>, carlos <carlos@redhat.com>,
Florian Weimer <fweimer@redhat.com>,
Joseph Myers <joseph@codesourcery.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
libc-alpha <libc-alpha@sourceware.org>,
Thomas Gleixner <tglx@linutronix.de>, Ben Maurer <bmaurer@fb.com>,
Peter Zijlstra <peterz@infradead.org>,
"Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
Dave Watson <davejwatson@fb.com>, Paul Turner <pjt@google.com>,
Rich Felker <dalias@libc.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-api <linux-api@vger.kernel.org>
Subject: Re: [PATCH 1/4] glibc: Perform rseq(2) registration at C startup and thread creation (v7)
Date: Thu, 25 Apr 2019 01:41:30 +0100 (BST) [thread overview]
Message-ID: <alpine.LFD.2.21.1904250022240.18194@eddie.linux-mips.org> (raw)
In-Reply-To: <20190424231303.zu2irxd5g3v7yqey@pburton-laptop>
On Wed, 24 Apr 2019, Paul Burton wrote:
> > > Any idea why 0x7273 is not accepted by my assembler ?
>
> I don't know why the assembler wants a smaller immediate than the
> instruction encoding allows... There's a comment in the binutils file
> include/opcode/mips.h that reads:
>
> > A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
> > breakpoint instruction are not defined; Kane says the breakpoint code
> > field in BREAK is 20 bits; yet MIPS assemblers and debuggers only use
> > ten bits). An optional two-operand form of break/sdbbp allows the
> > lower ten bits to be set too, and MIPS32 and later architectures allow
> > 20 bits to be set with a signal operand (using CODE20).
>
> I suspect there's some history here that predates my involvement (or
> possibly just predates me).
A useful explanation is in the Linux kernel (always good to look there),
in arch/mips/kernel/traps.c:
/*
* There is the ancient bug in the MIPS assemblers that the break
* code starts left to bit 16 instead to bit 6 in the opcode.
* Gas is bug-compatible, but not always, grrr...
* We handle both cases with a simple heuristics. --macro
*/
Unfortunately the bug has been carried over to the microMIPS instruction
encoding in libopcodes for no reason (i.e. likely by copying the table
mechanically without analysing it) and I didn't catch it when upstreaming.
We should have permitted setting all bits in the 20-bit code field in the
microMIPS encoding with a single operand, but you need two, like with the
regular MIPS instruction set.
The note on the MIPS32 assembly ISA permitting to set all the 20 bits
with a single operand is a stale comment referring to the situation before
binutils commit 1586d91e32ea ("/ 0 should send SIGFPE not SIGTRAP..."),
<https://sourceware.org/ml/binutils/2004-07/msg00260.html>, which
addressed a user ABI compatibility issue as discussed upthread here:
<https://sourceware.org/ml/binutils/2004-06/msg00188.html> and previously:
<https://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=40C9F5A4.2050606%40avtrex.com>.
As this is my mistake with the stale note, I have applied a fix to
binutils now, commit cd0923370be1 ("MIPS/include: opcode/mips.h: Update
stale comment for CODE20 operand"), so that it is clear that it is only
SDBBP that accepts a single 20-bit operand for the code field (for the
MIPS32 and later ISAs).
FWIW,
Maciej
next prev parent reply other threads:[~2019-04-25 0:41 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190212194253.1951-1-mathieu.desnoyers@efficios.com>
2019-02-12 19:42 ` [PATCH 1/4] glibc: Perform rseq(2) registration at C startup and thread creation (v7) Mathieu Desnoyers
2019-03-22 20:09 ` Carlos O'Donell
2019-03-25 15:54 ` Mathieu Desnoyers
2019-03-27 9:16 ` Martin Schwidefsky
2019-03-27 20:01 ` Mathieu Desnoyers
2019-03-27 20:38 ` Carlos O'Donell
2019-03-28 7:49 ` Martin Schwidefsky
2019-03-28 15:42 ` Mathieu Desnoyers
2019-04-02 6:02 ` Michael Ellerman
2019-04-02 7:08 ` Florian Weimer
2019-04-04 20:32 ` Carlos O'Donell
2019-04-05 9:16 ` Florian Weimer
2019-04-05 15:40 ` Carlos O'Donell
2019-04-08 19:20 ` Tulio Magno Quites Machado Filho
2019-04-08 21:45 ` Carlos O'Donell
2019-04-09 4:23 ` Michael Ellerman
2019-04-09 9:29 ` Alan Modra
[not found] ` <871s2bp9f9.fsf@linux.ibm.com>
2019-04-09 14:13 ` Carlos O'Donell
2019-04-09 15:45 ` Mathieu Desnoyers
2019-04-18 15:31 ` Mathieu Desnoyers
2019-04-09 16:33 ` Mathieu Desnoyers
2019-04-04 20:15 ` Carlos O'Donell
2019-04-04 20:50 ` Carlos O'Donell
2019-04-04 21:41 ` Paul Burton
2019-04-09 16:40 ` Mathieu Desnoyers
2019-04-18 18:58 ` Mathieu Desnoyers
2019-04-24 15:05 ` Mathieu Desnoyers
2019-04-24 23:13 ` Paul Burton
2019-04-25 0:41 ` Maciej W. Rozycki [this message]
2019-02-12 19:42 ` [PATCH 2/4] glibc: sched_getcpu(): use rseq cpu_id TLS on Linux Mathieu Desnoyers
2019-03-22 20:13 ` Carlos O'Donell
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