* [v4, PATCH 0/3] fix some bugs in stmmac
@ 2019-05-24 6:26 Biao Huang
2019-05-24 6:26 ` [v4, PATCH 1/3] net: stmmac: update rx tail pointer register to fix rx dma hang issue Biao Huang
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Biao Huang @ 2019-05-24 6:26 UTC (permalink / raw)
To: Jose Abreu
Cc: Giuseppe Cavallaro, Alexandre Torgue, Maxime Coquelin,
Matthias Brugger, netdev, linux-stm32, linux-arm-kernel,
linux-kernel, linux-mediatek, yt.shen, biao.huang, jianguo.zhang,
boon.leong.ong
changes in v4:
since MTL_OPERATION_MODE write back issue has be fixed in the latest driver,
remove original patch#3
changes in v3:
add a Fixes:tag for each patch
changes in v2:
1. update rx_tail_addr as Jose's comment
2. changes clk_csr condition as Alex's proposition
3. remove init lines in dwmac-mediatek, get clk_csr from dts instead.
v1:
This series fix some bugs in stmmac driver
3 patches are for common stmmac or dwmac4:
1. update rx tail pointer to fix rx dma hang issue.
2. change condition for mdc clock to fix csr_clk can't be zero issue.
3. write the modified value back to MTL_OPERATION_MODE.
1 patch is for dwmac-mediatek:
modify csr_clk value to fix mdio read/write fail issue for dwmac-mediatek
Biao Huang (3):
net: stmmac: update rx tail pointer register to fix rx dma hang
issue.
net: stmmac: fix csr_clk can't be zero issue
net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio
read/write fail
.../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 --
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++++---
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 ++++-
3 files changed, 8 insertions(+), 6 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 6+ messages in thread
* [v4, PATCH 1/3] net: stmmac: update rx tail pointer register to fix rx dma hang issue.
2019-05-24 6:26 [v4, PATCH 0/3] fix some bugs in stmmac Biao Huang
@ 2019-05-24 6:26 ` Biao Huang
2019-05-24 6:26 ` [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue Biao Huang
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Biao Huang @ 2019-05-24 6:26 UTC (permalink / raw)
To: Jose Abreu
Cc: Giuseppe Cavallaro, Alexandre Torgue, Maxime Coquelin,
Matthias Brugger, netdev, linux-stm32, linux-arm-kernel,
linux-kernel, linux-mediatek, yt.shen, biao.huang, jianguo.zhang,
boon.leong.ong
Currently we will not update the receive descriptor tail pointer in
stmmac_rx_refill. Rx dma will think no available descriptors and stop
once received packets exceed DMA_RX_SIZE, so that the rx only test will fail.
Update the receive tail pointer in stmmac_rx_refill to add more descriptors
to the rx channel, so packets can be received continually
Fixes: 54139cf3bb33 ("net: stmmac: adding multiple buffers for rx")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 5678b86..06487a6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3338,6 +3338,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
}
rx_q->dirty_rx = entry;
+ stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
}
/**
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue
2019-05-24 6:26 [v4, PATCH 0/3] fix some bugs in stmmac Biao Huang
2019-05-24 6:26 ` [v4, PATCH 1/3] net: stmmac: update rx tail pointer register to fix rx dma hang issue Biao Huang
@ 2019-05-24 6:26 ` Biao Huang
2019-05-24 7:07 ` Alexandre Torgue
2019-05-24 6:26 ` [v4, PATCH 3/3] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Biao Huang
2019-05-25 18:02 ` [v4, PATCH 0/3] fix some bugs in stmmac David Miller
3 siblings, 1 reply; 6+ messages in thread
From: Biao Huang @ 2019-05-24 6:26 UTC (permalink / raw)
To: Jose Abreu
Cc: Giuseppe Cavallaro, Alexandre Torgue, Maxime Coquelin,
Matthias Brugger, netdev, linux-stm32, linux-arm-kernel,
linux-kernel, linux-mediatek, yt.shen, biao.huang, jianguo.zhang,
boon.leong.ong
The specific clk_csr value can be zero, and
stmmac_clk is necessary for MDC clock which can be set dynamically.
So, change the condition from plat->clk_csr to plat->stmmac_clk to
fix clk_csr can't be zero issue.
Fixes: cd7201f477b9 ("stmmac: MDC clock dynamically based on the csr clock input")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++---
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 ++++-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 06487a6..b2feb6c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -4380,10 +4380,10 @@ int stmmac_dvr_probe(struct device *device,
* set the MDC clock dynamically according to the csr actual
* clock input.
*/
- if (!priv->plat->clk_csr)
- stmmac_clk_csr_set(priv);
- else
+ if (priv->plat->clk_csr >= 0)
priv->clk_csr = priv->plat->clk_csr;
+ else
+ stmmac_clk_csr_set(priv);
stmmac_check_pcs_mode(priv);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 3031f2b..f45bfbe 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -408,7 +408,10 @@ struct plat_stmmacenet_data *
/* Default to phy auto-detection */
plat->phy_addr = -1;
- /* Get clk_csr from device tree */
+ /* Default to get clk_csr from stmmac_clk_crs_set(),
+ * or get clk_csr from device tree.
+ */
+ plat->clk_csr = -1;
of_property_read_u32(np, "clk_csr", &plat->clk_csr);
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [v4, PATCH 3/3] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail
2019-05-24 6:26 [v4, PATCH 0/3] fix some bugs in stmmac Biao Huang
2019-05-24 6:26 ` [v4, PATCH 1/3] net: stmmac: update rx tail pointer register to fix rx dma hang issue Biao Huang
2019-05-24 6:26 ` [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue Biao Huang
@ 2019-05-24 6:26 ` Biao Huang
2019-05-25 18:02 ` [v4, PATCH 0/3] fix some bugs in stmmac David Miller
3 siblings, 0 replies; 6+ messages in thread
From: Biao Huang @ 2019-05-24 6:26 UTC (permalink / raw)
To: Jose Abreu
Cc: Giuseppe Cavallaro, Alexandre Torgue, Maxime Coquelin,
Matthias Brugger, netdev, linux-stm32, linux-arm-kernel,
linux-kernel, linux-mediatek, yt.shen, biao.huang, jianguo.zhang,
boon.leong.ong
1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.
Fixes: 9992f37e346b ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index bf25629..126b66b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
@@ -346,8 +346,6 @@ static int mediatek_dwmac_probe(struct platform_device *pdev)
return PTR_ERR(plat_dat);
plat_dat->interface = priv_plat->phy_mode;
- /* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */
- plat_dat->clk_csr = 5;
plat_dat->has_gmac4 = 1;
plat_dat->has_gmac = 0;
plat_dat->pmt = 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue
2019-05-24 6:26 ` [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue Biao Huang
@ 2019-05-24 7:07 ` Alexandre Torgue
0 siblings, 0 replies; 6+ messages in thread
From: Alexandre Torgue @ 2019-05-24 7:07 UTC (permalink / raw)
To: Biao Huang, Jose Abreu
Cc: Giuseppe Cavallaro, Maxime Coquelin, Matthias Brugger, netdev,
linux-stm32, linux-arm-kernel, linux-kernel, linux-mediatek,
yt.shen, jianguo.zhang, boon.leong.ong
Hi Biao
On 5/24/19 8:26 AM, Biao Huang wrote:
> The specific clk_csr value can be zero, and
> stmmac_clk is necessary for MDC clock which can be set dynamically.
> So, change the condition from plat->clk_csr to plat->stmmac_clk to
> fix clk_csr can't be zero issue.
>
> Fixes: cd7201f477b9 ("stmmac: MDC clock dynamically based on the csr clock input")
> Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++---
> .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 ++++-
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 06487a6..b2feb6c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -4380,10 +4380,10 @@ int stmmac_dvr_probe(struct device *device,
> * set the MDC clock dynamically according to the csr actual
> * clock input.
> */
> - if (!priv->plat->clk_csr)
> - stmmac_clk_csr_set(priv);
> - else
> + if (priv->plat->clk_csr >= 0)
> priv->clk_csr = priv->plat->clk_csr;
> + else
> + stmmac_clk_csr_set(priv);
>
> stmmac_check_pcs_mode(priv);
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> index 3031f2b..f45bfbe 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> @@ -408,7 +408,10 @@ struct plat_stmmacenet_data *
> /* Default to phy auto-detection */
> plat->phy_addr = -1;
>
> - /* Get clk_csr from device tree */
> + /* Default to get clk_csr from stmmac_clk_crs_set(),
> + * or get clk_csr from device tree.
> + */
> + plat->clk_csr = -1;
> of_property_read_u32(np, "clk_csr", &plat->clk_csr);
>
> /* "snps,phy-addr" is not a standard property. Mark it as deprecated
>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
thanks
Alex
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [v4, PATCH 0/3] fix some bugs in stmmac
2019-05-24 6:26 [v4, PATCH 0/3] fix some bugs in stmmac Biao Huang
` (2 preceding siblings ...)
2019-05-24 6:26 ` [v4, PATCH 3/3] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Biao Huang
@ 2019-05-25 18:02 ` David Miller
3 siblings, 0 replies; 6+ messages in thread
From: David Miller @ 2019-05-25 18:02 UTC (permalink / raw)
To: biao.huang
Cc: joabreu, peppe.cavallaro, alexandre.torgue, mcoquelin.stm32,
matthias.bgg, netdev, linux-stm32, linux-arm-kernel,
linux-kernel, linux-mediatek, yt.shen, jianguo.zhang,
boon.leong.ong
From: Biao Huang <biao.huang@mediatek.com>
Date: Fri, 24 May 2019 14:26:06 +0800
> changes in v4:
> since MTL_OPERATION_MODE write back issue has be fixed in the latest driver,
> remove original patch#3
>
> changes in v3:
> add a Fixes:tag for each patch
>
> changes in v2:
> 1. update rx_tail_addr as Jose's comment
> 2. changes clk_csr condition as Alex's proposition
> 3. remove init lines in dwmac-mediatek, get clk_csr from dts instead.
>
> v1:
> This series fix some bugs in stmmac driver
> 3 patches are for common stmmac or dwmac4:
> 1. update rx tail pointer to fix rx dma hang issue.
> 2. change condition for mdc clock to fix csr_clk can't be zero issue.
> 3. write the modified value back to MTL_OPERATION_MODE.
> 1 patch is for dwmac-mediatek:
> modify csr_clk value to fix mdio read/write fail issue for dwmac-mediatek
Series applied, thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-05-25 18:02 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2019-05-24 6:26 [v4, PATCH 0/3] fix some bugs in stmmac Biao Huang
2019-05-24 6:26 ` [v4, PATCH 1/3] net: stmmac: update rx tail pointer register to fix rx dma hang issue Biao Huang
2019-05-24 6:26 ` [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue Biao Huang
2019-05-24 7:07 ` Alexandre Torgue
2019-05-24 6:26 ` [v4, PATCH 3/3] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Biao Huang
2019-05-25 18:02 ` [v4, PATCH 0/3] fix some bugs in stmmac David Miller
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