[PATCH 0/6] Add support for the Intel CE4100

[PATCH 0/6] Add support for the Intel CE4100

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch set adds support for the Intel CE4100 SOC.  The CE4100 is an SOC 
specialized for media applications.  The CE4100 development platform does
not have a traditionial PC BIOS.  The early setup of the platform uses
the same method as the Moorestown platform.


Dirk Brandewie (5):
  ce4100: add PCI register emulation for CE4100
  serial/ce4100: Add PCI UART support for the ce4100
  ce4100: Add errata fixes for UART on CE4100
  x86: ce4100: Add reboot_fixup() for CE4100
  ce4100: Add support for CE4100 EHCI IP block to EHCI driver

Thomas Gleixner (1):
  x86: Add CE4100 platform support

 Documentation/x86/boot.txt         |    1 +
 arch/x86/Kconfig                   |   12 ++
 arch/x86/include/asm/bootparam.h   |    1 +
 arch/x86/include/asm/setup.h       |    6 +
 arch/x86/kernel/Makefile           |    2 +
 arch/x86/kernel/ce4100.c           |  132 ++++++++++++++
 arch/x86/kernel/head32.c           |    3 +
 arch/x86/kernel/reboot_fixups_32.c |   11 ++
 arch/x86/pci/Makefile              |    1 +
 arch/x86/pci/ce4100.c              |  333 ++++++++++++++++++++++++++++++++++++
 drivers/serial/8250_pci.c          |   35 ++++
 drivers/usb/host/ehci-pci.c        |    4 +
 include/linux/pci_ids.h            |    3 +
 13 files changed, 544 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/kernel/ce4100.c
 create mode 100644 arch/x86/pci/ce4100.c

-- 
1.7.2.3

[PATCH 1/6] x86: Add CE4100 platform support

[dirk.brandewie]

From: Thomas Gleixner <tglx@linutronix.de>

Add CE4100 platform support. CE4100 needs early setup like
moorestown.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
---
 Documentation/x86/boot.txt       |    1 +
 arch/x86/Kconfig                 |   11 +++++++++
 arch/x86/include/asm/bootparam.h |    1 +
 arch/x86/include/asm/setup.h     |    6 +++++
 arch/x86/kernel/Makefile         |    2 +
 arch/x86/kernel/ce4100.c         |   46 ++++++++++++++++++++++++++++++++++++++
 arch/x86/kernel/head32.c         |    3 ++
 7 files changed, 70 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/kernel/ce4100.c

diff --git a/Documentation/x86/boot.txt b/Documentation/x86/boot.txt
index 30b43e1..bdeb81c 100644
--- a/Documentation/x86/boot.txt
+++ b/Documentation/x86/boot.txt
@@ -600,6 +600,7 @@ Protocol:	2.07+
   0x00000001	lguest
   0x00000002	Xen
   0x00000003	Moorestown MID
+  0x00000004	CE4100 TV Platform
 
 Field name:	hardware_subarch_data
 Type:		write (subarch-dependent)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e832768..84236c9 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -377,6 +377,17 @@ config X86_ELAN
 
 	  If unsure, choose "PC-compatible" instead.
 
+config X86_INTEL_CE
+	bool "CE4100 TV platform"
+	depends on PCI
+	depends on PCI_GODIRECT
+	depends on X86_32
+	depends on X86_EXTENDED_PLATFORM
+	---help---
+	  Select for the Intel CE media processor (CE4100) SOC.
+	  This option compiles in support for the CE4100 SOC for settop
+	  boxes and media devices.
+
 config X86_MRST
        bool "Moorestown MID platform"
 	depends on PCI
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index 8e62185..c8bfe63 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -124,6 +124,7 @@ enum {
 	X86_SUBARCH_LGUEST,
 	X86_SUBARCH_XEN,
 	X86_SUBARCH_MRST,
+	X86_SUBARCH_CE4100,
 	X86_NR_SUBARCHS,
 };
 
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index d6763b1..db8aa19 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -53,6 +53,12 @@ extern void x86_mrst_early_setup(void);
 static inline void x86_mrst_early_setup(void) { }
 #endif
 
+#ifdef CONFIG_X86_INTEL_CE
+extern void x86_ce4100_early_setup(void);
+#else
+static inline void x86_ce4100_early_setup(void) { }
+#endif
+
 #ifndef _SETUP
 
 /*
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 9e13763..3cb25ab 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -101,6 +101,8 @@ obj-$(CONFIG_PARAVIRT_CLOCK)	+= pvclock.o
 
 obj-$(CONFIG_PCSPKR_PLATFORM)	+= pcspeaker.o
 
+obj-$(CONFIG_X86_INTEL_CE)	+= ce4100.o
+
 microcode-y				:= microcode_core.o
 microcode-$(CONFIG_MICROCODE_INTEL)	+= microcode_intel.o
 microcode-$(CONFIG_MICROCODE_AMD)	+= microcode_amd.o
diff --git a/arch/x86/kernel/ce4100.c b/arch/x86/kernel/ce4100.c
new file mode 100644
index 0000000..b8f1c48
--- /dev/null
+++ b/arch/x86/kernel/ce4100.c
@@ -0,0 +1,46 @@
+/*
+ * Intel CE4100  platform specific setup code
+ *
+ * (C) Copyright 2010 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+
+#include <asm/setup.h>
+
+
+static int ce4100_i8042_detect(void)
+{
+	return 0;
+}
+
+static void __init sdv_arch_setup(void)
+{
+
+}
+
+
+static void __init sdv_find_smp_config(void)
+{
+}
+
+
+/*
+ * CE4100 specific x86_init function overrides and early setup
+ * calls.
+ */
+void __init x86_ce4100_early_setup(void)
+{
+	x86_init.oem.arch_setup = sdv_arch_setup;
+	x86_platform.i8042_detect = ce4100_i8042_detect;
+	x86_init.resources.probe_roms = x86_init_noop;
+	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
+	x86_init.mpparse.find_smp_config = sdv_find_smp_config;
+}
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index 7633101..7f138b3 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -61,6 +61,9 @@ void __init i386_start_kernel(void)
 	case X86_SUBARCH_MRST:
 		x86_mrst_early_setup();
 		break;
+	case X86_SUBARCH_CE4100:
+		x86_ce4100_early_setup();
+		break;
 	default:
 		i386_default_early_setup();
 		break;
-- 
1.7.2.3

[PATCH 2/6] ce4100: add PCI register emulation for CE4100

[dirk.brandewie]

From: Dirk Brandewie <dirk.j.brandewie@intel.com>

This patch access methods for PCI registers that mis-behave on
the CE4100. Each register can be assigned a private init, read and
write routine. The exception to this is the bridge device.  The
bridge device is the only device on bus zero (0) that requires any
fixup so it is a special case.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
---
 arch/x86/pci/Makefile |    1 +
 arch/x86/pci/ce4100.c |  333 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 334 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/pci/ce4100.c

diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index effd96e..6b8759f 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_OLPC)		+= olpc.o
 obj-$(CONFIG_PCI_XEN)		+= xen.o
 
 obj-y				+= fixup.o
+obj-$(CONFIG_X86_INTEL_CE)      += ce4100.o
 obj-$(CONFIG_ACPI)		+= acpi.o
 obj-y				+= legacy.o irq.o
 
diff --git a/arch/x86/pci/ce4100.c b/arch/x86/pci/ce4100.c
new file mode 100644
index 0000000..5801b15
--- /dev/null
+++ b/arch/x86/pci/ce4100.c
@@ -0,0 +1,333 @@
+/*
+ *  GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2010 Intel Corporation. All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *  The full GNU General Public License is included in this distribution
+ *  in the file called LICENSE.GPL.
+ *
+ *  Contact Information:
+ *    Intel Corporation
+ *    2200 Mission College Blvd.
+ *    Santa Clara, CA  97052
+ *
+ */
+
+/*
+* This provides access methods for PCI registers that mis-behave on
+* the CE4100. Each register can be assigned a private init, read and
+* write routine. The exception to this is the bridge device.  The
+* bridge device is the only device on bus zero (0) that requires any
+* fixup so it is a special case ATM
+*/
+
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <asm/pci_x86.h>
+
+struct sim_reg {
+	u32 value;
+	u32 mask;
+};
+
+struct sim_dev_reg {
+	int dev_func;
+	int reg;
+	void (*init)(struct sim_dev_reg *reg);
+	void (*read)(struct sim_dev_reg *reg, u32 *value);
+	void (*write)(struct sim_dev_reg *reg, u32 value);
+	struct sim_reg sim_reg;
+};
+
+struct sim_reg_op {
+	void (*init)(struct sim_dev_reg *reg);
+	void (*read)(struct sim_dev_reg *reg, u32 value);
+	void (*write)(struct sim_dev_reg *reg, u32 value);
+};
+
+
+#define MB (1024 * 1024)
+#define KB (1024)
+#define SIZE_TO_MASK(size) (~(size - 1))
+
+#define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\
+{ PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\
+	{0, SIZE_TO_MASK(size)} },
+
+static void reg_init(struct sim_dev_reg *reg)
+{
+	pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,
+			&reg->sim_reg.value);
+}
+
+static void reg_read(struct sim_dev_reg *reg, u32 *value)
+{
+	unsigned long flags;
+	raw_spin_lock_irqsave(&pci_config_lock, flags);
+	*value = reg->sim_reg.value;
+	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+}
+
+static void reg_write(struct sim_dev_reg *reg, u32 value)
+{
+	unsigned long flags;
+	raw_spin_lock_irqsave(&pci_config_lock, flags);
+	reg->sim_reg.value = (value & reg->sim_reg.mask) |
+		(reg->sim_reg.value & ~reg->sim_reg.mask);
+	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+}
+
+static void sata_reg_init(struct sim_dev_reg *reg)
+{
+	pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,
+			&reg->sim_reg.value);
+	reg->sim_reg.value += 0x400;
+}
+
+static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value)
+{
+	reg_read(reg, value);
+	if (*value != reg->sim_reg.mask)
+		*value |= 0x100;
+}
+
+void sata_revid_init(struct sim_dev_reg *reg)
+{
+	reg->sim_reg.value = 0x01060100;
+	reg->sim_reg.mask = 0;
+}
+
+static void sata_revid_read(struct sim_dev_reg *reg, u32 *value)
+{
+	reg_read(reg, value);
+}
+
+static struct sim_dev_reg bus1_fixups[] = {
+	DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
+	DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
+	DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
+	DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
+	DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
+	DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
+	DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
+	DEFINE_REG(14, 0, 0x8,  0, sata_revid_init, sata_revid_read, 0)
+	DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write)
+	DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write)
+	DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write)
+	DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write)
+	DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write)
+	DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write)
+	DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
+	DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
+	DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
+	DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
+};
+
+static const int num_bus1_fixups = sizeof(bus1_fixups) / sizeof(bus1_fixups[0]);
+
+static void init_sim_regs(void)
+{
+	int i;
+
+	for (i = 0; i < num_bus1_fixups; i++) {
+		if (bus1_fixups[i].init)
+			bus1_fixups[i].init(&bus1_fixups[i]);
+	}
+}
+
+
+static inline void extract_bytes(u32 *value, int reg, int len)
+{
+	uint32_t mask;
+
+	*value >>= ((reg & 3) * 8);
+	mask = 0xFFFFFFFF >> ((4 - len) * 8);
+	*value &= mask;
+}
+
+int bridge_read(unsigned int devfn, int reg, int len, u32 *value)
+{
+	int retval = 0;
+	u32 av_bridge_base, av_bridge_limit;
+
+	switch (reg) {
+	/* Make BARs appear to not request any memory. */
+	case PCI_BASE_ADDRESS_0:
+	case PCI_BASE_ADDRESS_0 + 1:
+	case PCI_BASE_ADDRESS_0 + 2:
+	case PCI_BASE_ADDRESS_0 + 3:
+		*value = 0;
+		break;
+
+		/* Since subordinate bus number register is hardwired
+		 * to zero and read only, so do the simulation.
+		 */
+	case PCI_PRIMARY_BUS:
+		if (len == 4)
+			*value = 0x00010100;
+		break;
+
+	case PCI_SUBORDINATE_BUS:
+		*value = 1;
+		break;
+
+	case PCI_MEMORY_BASE:
+	case PCI_MEMORY_LIMIT:
+		/* Get the A/V bridge base address. */
+		pci_direct_conf1.read(0, 0, devfn,
+				PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
+
+		av_bridge_limit = av_bridge_base + (512*MB - 1);
+		av_bridge_limit >>= 16;
+		av_bridge_limit &= 0xFFF0;
+
+		av_bridge_base >>= 16;
+		av_bridge_base &= 0xFFF0;
+
+		if (reg == PCI_MEMORY_LIMIT)
+			*value = av_bridge_limit;
+		else if (len == 2)
+			*value = av_bridge_base;
+		else
+			*value = (av_bridge_limit << 16) | av_bridge_base;
+		break;
+		/* Make prefetchable memory limit smaller than prefetchable
+		 * memory base, so not claim prefetchable memory space.
+		 */
+	case PCI_PREF_MEMORY_BASE:
+		*value = 0xFFF0;
+		break;
+	case PCI_PREF_MEMORY_LIMIT:
+		*value = 0x0;
+		break;
+		/* Make IO limit smaller than IO base, so not claim IO space. */
+	case PCI_IO_BASE:
+		*value = 0xF0;
+		break;
+	case PCI_IO_LIMIT:
+		*value = 0;
+		break;
+	default:
+		retval = 1;
+	}
+	return retval;
+}
+
+
+
+
+static int ce4100_conf_read(unsigned int seg, unsigned int bus,
+			  unsigned int devfn, int reg, int len, u32 *value)
+{
+	int retval = 1;
+	int i;
+
+	if (bus == 0 && (PCI_DEVFN(1, 0) == devfn))
+		retval = bridge_read(devfn, reg, len, value);
+
+	if (bus == 1) {
+		for (i = 0; i < num_bus1_fixups; i++) {
+			if (bus1_fixups[i].dev_func == devfn &&
+				bus1_fixups[i].reg == (reg & ~3) &&
+				bus1_fixups[i].read) {
+				bus1_fixups[i].read(&(bus1_fixups[i]),
+					value);
+				extract_bytes(value, reg, len);
+				retval = 0;
+			}
+		}
+	}
+	if (retval)
+		retval = pci_direct_conf1.read(seg, bus, devfn, reg,
+					len, value);
+	return retval;
+}
+
+
+static int ce4100_conf_write(unsigned int seg, unsigned int bus,
+			   unsigned int devfn, int reg, int len, u32 value)
+{
+	int retval = 1;
+	int i;
+
+	if (bus == 1) {
+		for (i = 0; i < num_bus1_fixups; i++) {
+			if (bus1_fixups[i].dev_func == devfn &&
+				bus1_fixups[i].reg == (reg & ~3) &&
+				bus1_fixups[i].write) {
+				bus1_fixups[i].write(&(bus1_fixups[i]),
+					value);
+				retval = 0;
+			}
+		}
+	}
+
+	/* Discard writes to A/V bridge BAR. */
+	if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
+		((reg & ~3) == PCI_BASE_ADDRESS_0))
+		retval = 0;
+
+	if (retval)
+		retval = pci_direct_conf1.write(seg, bus, devfn, reg,
+						len, value);
+	return retval;
+}
+
+
+struct pci_raw_ops ce4100_pci_conf = {
+	.read =	ce4100_conf_read,
+	.write = ce4100_conf_write,
+};
+
+static int __init ce4100_pci_init(void)
+{
+	init_sim_regs();
+	raw_pci_ops = &ce4100_pci_conf;
+	return 0;
+}
+
+
+subsys_initcall(ce4100_pci_init);
-- 
1.7.2.3

[PATCH 3/6] serial/ce4100: Add PCI UART support for the ce4100

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch adds support for the PCI UART on the ce4100.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
CC: linux-serial@vger.kernel.org
---
 drivers/serial/8250_pci.c |   35 +++++++++++++++++++++++++++++++++++
 include/linux/pci_ids.h   |    1 +
 2 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 53be4d3..f98da48 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -957,6 +957,22 @@ pci_default_setup(struct serial_private *priv,
 	return setup_port(priv, port, bar, offset, board->reg_shift);
 }
 
+static int
+ce4100_serial_setup(struct serial_private *priv,
+		  const struct pciserial_board *board,
+		  struct uart_port *port, int idx)
+{
+	int ret;
+
+	ret = setup_port(priv, port, 0, 0, board->reg_shift);
+	port->iotype = UPIO_MEM32;
+	port->type = PORT_XSCALE;
+	port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
+	port->regshift = 2;
+
+	return ret;
+}
+
 static int skip_tx_en_setup(struct serial_private *priv,
 			const struct pciserial_board *board,
 			struct uart_port *port, int idx)
@@ -1072,6 +1088,13 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 		.subdevice	= PCI_ANY_ID,
 		.setup		= skip_tx_en_setup,
 	},
+	{
+		.vendor		= PCI_VENDOR_ID_INTEL,
+		.device		= PCI_DEVICE_ID_INTEL_CE4100_UART,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= ce4100_serial_setup,
+	},
 	/*
 	 * ITE
 	 */
@@ -1592,6 +1615,7 @@ enum pci_board_num_t {
 	pbn_ADDIDATA_PCIe_2_3906250,
 	pbn_ADDIDATA_PCIe_4_3906250,
 	pbn_ADDIDATA_PCIe_8_3906250,
+	pbn_ce4100_1_115200,
 };
 
 /*
@@ -2281,6 +2305,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
 		.uart_offset	= 0x200,
 		.first_offset	= 0x1000,
 	},
+	[pbn_ce4100_1_115200] = {
+		.flags		= FL_BASE0,
+		.num_ports	= 1,
+		.base_baud	= 921600,
+		.reg_shift      = 2,
+	},
 };
 
 static const struct pci_device_id softmodem_blacklist[] = {
@@ -3760,6 +3790,11 @@ static struct pci_device_id serial_pci_tbl[] = {
 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
 		0xA000, 0x3004,
 		0, 0, pbn_b0_bt_4_115200 },
+	/* Intel CE4100 */
+	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
+		PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
+		pbn_ce4100_1_115200 },
+
 
 	/*
 	 * These entries match devices with class COMMUNICATION_SERIAL,
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index c6bcfe9..8fc40b6 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2629,6 +2629,7 @@
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2  0x2db1
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2  0x2db2
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2    0x2db3
+#define PCI_DEVICE_ID_INTEL_CE4100_UART	0x2e66
 #define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG4	0x3429
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG5	0x342a
-- 
1.7.2.3

[PATCH 4/6] ce4100: Add errata fixes for UART on CE4100

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch enables the UART on the CE4100.  The UART has a couple of
issues that need to be worked around.  First the UART is mostly PC
compatible except that it is clocked eight times faster than a
standard PC so the default configuration provided in
arch/x86/include/asm/serial.h needs to be overridden. Second the TX
interrupt may not be set correctly all the time. Lastly accessing the
UART via I/O space for early_prink() hangs the chip when the IOAPIC is
enabled.

A custom mem_serial_in() is provided to work around the TX interrupt
issue. The configuration issues are dealt with in the call back
registered with the 8250 driver via serial8250_set_isa_configurator()

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
---
 arch/x86/kernel/ce4100.c |   92 ++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 89 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/ce4100.c b/arch/x86/kernel/ce4100.c
index b8f1c48..d2c0d51 100644
--- a/arch/x86/kernel/ce4100.c
+++ b/arch/x86/kernel/ce4100.c
@@ -12,25 +12,111 @@
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <linux/module.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
 
 #include <asm/setup.h>
-
+#include <asm/io.h>
 
 static int ce4100_i8042_detect(void)
 {
 	return 0;
 }
 
-static void __init sdv_arch_setup(void)
+static void __init sdv_find_smp_config(void)
 {
+}
+
+#ifdef CONFIG_SERIAL_8250
+
 
+static unsigned int mem_serial_in(struct uart_port *p, int offset)
+{
+	offset = offset << p->regshift;
+	return readl(p->membase + offset);
 }
 
+/*
+ * The UART Tx interrupts are not set under some conditions and therefore serial
+ * transmission hangs. This is a silicon issue and has not been root caused. The
+ * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
+ * bit of LSR register in interrupt handler to see whether at least one of these
+ * two bits is set, if so then process the transmit request. If this workaround
+ * is not applied, then the serial transmission may hang. This workaround is for
+ * errata number 9 in Errata - B step.
+*/
 
-static void __init sdv_find_smp_config(void)
+static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
+{
+	unsigned int ret, ier, lsr;
+
+	if (offset == UART_IIR) {
+		offset = offset << p->regshift;
+		ret = readl(p->membase + offset);
+		if (ret & UART_IIR_NO_INT) {
+			/* see if the TX interrupt should have really set */
+			ier = mem_serial_in(p, UART_IER);
+			/* see if the UART's XMIT interrupt is enabled */
+			if (ier & UART_IER_THRI) {
+				lsr = mem_serial_in(p, UART_LSR);
+				/* now check to see if the UART should be
+				   generating an interrupt (but isn't) */
+				if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
+					ret &= ~UART_IIR_NO_INT;
+			}
+		}
+	} else
+		ret =  mem_serial_in(p, offset);
+	return ret;
+}
+
+static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
+{
+	offset = offset << p->regshift;
+	writel(value, p->membase + offset);
+}
+
+static void ce4100_serial_fixup(int port, struct uart_port *up,
+	unsigned short *capabilites)
+{
+#ifdef CONFIG_EARLY_PRINTK
+	/*
+	 * Over ride the legacy port configuration that comes from
+	 * asm/serial.h. Using the ioport driver then switching to the
+	 * PCI memmaped driver hangs the IOAPIC
+	 */
+	if (up->iotype !=  UPIO_MEM32) {
+		up->uartclk  = 14745600;
+		up->mapbase = 0xdffe0200;
+		set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
+				up->mapbase & PAGE_MASK);
+		up->membase =
+			(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
+		up->membase += up->mapbase & ~PAGE_MASK;
+		up->iotype   = UPIO_MEM32;
+		up->regshift = 2;
+	}
+#endif
+	up->iobase = 0;
+	up->serial_in = ce4100_mem_serial_in;
+	up->serial_out = ce4100_mem_serial_out;
+
+	*capabilites |= (1 << 12);
+}
+
+static __init void sdv_serial_fixup(void)
 {
+	serial8250_set_isa_configurator(ce4100_serial_fixup);
 }
 
+#else
+static inline void sdv_serial_fixup(void);
+#endif
+
+static void __init sdv_arch_setup(void)
+{
+	sdv_serial_fixup();
+}
 
 /*
  * CE4100 specific x86_init function overrides and early setup
-- 
1.7.2.3

[PATCH 5/6] x86: ce4100: Add reboot_fixup() for CE4100

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch adds the CE4100 reboot fixup to reboot_fixups_32.c

Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
---
 arch/x86/Kconfig                   |    1 +
 arch/x86/kernel/reboot_fixups_32.c |   11 +++++++++++
 include/linux/pci_ids.h            |    1 +
 3 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 84236c9..d9f3fcf 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -383,6 +383,7 @@ config X86_INTEL_CE
 	depends on PCI_GODIRECT
 	depends on X86_32
 	depends on X86_EXTENDED_PLATFORM
+	select X86_REBOOTFIXUPS
 	---help---
 	  Select for the Intel CE media processor (CE4100) SOC.
 	  This option compiles in support for the CE4100 SOC for settop
diff --git a/arch/x86/kernel/reboot_fixups_32.c b/arch/x86/kernel/reboot_fixups_32.c
index fda313e..1bb5531 100644
--- a/arch/x86/kernel/reboot_fixups_32.c
+++ b/arch/x86/kernel/reboot_fixups_32.c
@@ -43,6 +43,16 @@ static void rdc321x_reset(struct pci_dev *dev)
 	outb(1, 0x92);
 }
 
+static void ce4100_reset(struct pci_dev *dev)
+{
+	int i;
+
+	for (i = 0; i < 10; i++) {
+		outb(0x2, 0xcf9);
+		udelay(50);
+	}
+}
+
 struct device_fixup {
 	unsigned int vendor;
 	unsigned int device;
@@ -54,6 +64,7 @@ static const struct device_fixup fixups_table[] = {
 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, cs5536_warm_reset },
 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE, cs5530a_warm_reset },
 { PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030, rdc321x_reset },
+{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100, ce4100_reset },
 };
 
 /*
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 8fc40b6..84f7130 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2434,6 +2434,7 @@
 #define PCI_DEVICE_ID_INTEL_82375	0x0482
 #define PCI_DEVICE_ID_INTEL_82424	0x0483
 #define PCI_DEVICE_ID_INTEL_82378	0x0484
+#define PCI_DEVICE_ID_INTEL_CE4100	0x0708
 #define PCI_DEVICE_ID_INTEL_MRST_SD0	0x0807
 #define PCI_DEVICE_ID_INTEL_MRST_SD1	0x0808
 #define PCI_DEVICE_ID_INTEL_MFD_SD	0x0820
-- 
1.7.2.3

[PATCH 6/6] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch adds support for the EHCI IP block present on the Intel
CE4100.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
CC: linux-usb@vger.kernel.org
CC: David Brownell <dbrownell@users.sourceforge.net>
---
 drivers/usb/host/ehci-pci.c |    4 ++++
 include/linux/pci_ids.h     |    1 +
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index a1e8d27..724da36 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -124,6 +124,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
 			ehci_info(ehci, "disable lpm for langwell/penwell\n");
 			ehci->has_lpm = 0;
 		}
+		if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
+			hcd->has_tt = 1;
+			tdi_reset(ehci);
+		}
 		break;
 	case PCI_VENDOR_ID_TDI:
 		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 84f7130..7790f40 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2631,6 +2631,7 @@
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2  0x2db2
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2    0x2db3
 #define PCI_DEVICE_ID_INTEL_CE4100_UART	0x2e66
+#define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70
 #define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG4	0x3429
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG5	0x342a
-- 
1.7.2.3

Re: [PATCH 3/6] serial/ce4100: Add PCI UART support for the ce4100

[Greg KH]

On Tue, Nov 09, 2010 at 12:08:06PM -0800, dirk.brandewie@gmail.com wrote:
> From: Dirk Brandewie <dirk.brandewie@gmail.com>
> 
> This patch adds support for the PCI UART on the ce4100.
> 
> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
> CC: linux-serial@vger.kernel.org
> ---
>  drivers/serial/8250_pci.c |   35 +++++++++++++++++++++++++++++++++++
>  include/linux/pci_ids.h   |    1 +

You did read the top of pci_ids.h right?  Why are you adding new ids
that are only used by one file?

Please don't do that.

thanks,

greg k-h

Re: [PATCH 3/6] serial/ce4100: Add PCI UART support for the ce4100

[Dirk Brandewie]

On 11/09/2010 01:14 PM, Greg KH wrote:
> On Tue, Nov 09, 2010 at 12:08:06PM -0800, dirk.brandewie@gmail.com wrote:
>> From: Dirk Brandewie<dirk.brandewie@gmail.com>
>>
>> This patch adds support for the PCI UART on the ce4100.
>>
>> Signed-off-by: Dirk Brandewie<dirk.brandewie@gmail.com>
>> CC: linux-serial@vger.kernel.org
>> ---
>>   drivers/serial/8250_pci.c |   35 +++++++++++++++++++++++++++++++++++
>>   include/linux/pci_ids.h   |    1 +
> 
> You did read the top of pci_ids.h right?  Why are you adding new ids
> that are only used by one file?
> 
I have now. Here is a replacement patch for the UART. I will update the 
USB patch as well.

--Dirk

Subject: [PATCH] serial/ce4100: Add PCI UART support for the ce4100

This patch adds support for the PCI UART on the ce4100.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
CC: linux-serial@vger.kernel.org
---
 drivers/serial/8250_pci.c |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 53be4d3..12e6f81 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -957,6 +957,22 @@ pci_default_setup(struct serial_private *priv,
 	return setup_port(priv, port, bar, offset, board->reg_shift);
 }
 
+static int
+ce4100_serial_setup(struct serial_private *priv,
+		  const struct pciserial_board *board,
+		  struct uart_port *port, int idx)
+{
+	int ret;
+
+	ret = setup_port(priv, port, 0, 0, board->reg_shift);
+	port->iotype = UPIO_MEM32;
+	port->type = PORT_XSCALE;
+	port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
+	port->regshift = 2;
+
+	return ret;
+}
+
 static int skip_tx_en_setup(struct serial_private *priv,
 			const struct pciserial_board *board,
 			struct uart_port *port, int idx)
@@ -1072,6 +1088,13 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 		.subdevice	= PCI_ANY_ID,
 		.setup		= skip_tx_en_setup,
 	},
+	{
+		.vendor		= PCI_VENDOR_ID_INTEL,
+		.device		= 0x2e66,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= ce4100_serial_setup,
+	},
 	/*
 	 * ITE
 	 */
@@ -1592,6 +1615,7 @@ enum pci_board_num_t {
 	pbn_ADDIDATA_PCIe_2_3906250,
 	pbn_ADDIDATA_PCIe_4_3906250,
 	pbn_ADDIDATA_PCIe_8_3906250,
+	pbn_ce4100_1_115200,
 };
 
 /*
@@ -2281,6 +2305,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
 		.uart_offset	= 0x200,
 		.first_offset	= 0x1000,
 	},
+	[pbn_ce4100_1_115200] = {
+		.flags		= FL_BASE0,
+		.num_ports	= 1,
+		.base_baud	= 921600,
+		.reg_shift      = 2,
+	},
 };
 
 static const struct pci_device_id softmodem_blacklist[] = {
@@ -3760,6 +3790,11 @@ static struct pci_device_id serial_pci_tbl[] = {
 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
 		0xA000, 0x3004,
 		0, 0, pbn_b0_bt_4_115200 },
+	/* Intel CE4100 */
+	{	PCI_VENDOR_ID_INTEL, 0x2e66,
+		PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
+		pbn_ce4100_1_115200 },
+
 
 	/*
 	 * These entries match devices with class COMMUNICATION_SERIAL,
-- 
1.7.2.3

Re: [PATCH 6/6] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

[Dirk Brandewie]

In a previous patch in this series GregKH asked that the PCI ID not be added 
to pci_ids.h for ID's that are only used by a single file.  
Here is an updated version of the EHCI controller patch.

Subject: [PATCH] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

This patch adds support for the EHCI IP block present on the Intel
CE4100.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
CC: linux-usb@vger.kernel.org
CC: David Brownell <dbrownell@users.sourceforge.net>
---
 drivers/usb/host/ehci-pci.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index a1e8d27..da2b196 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -124,6 +124,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
 			ehci_info(ehci, "disable lpm for langwell/penwell\n");
 			ehci->has_lpm = 0;
 		}
+		if (pdev->device == 0x2e70) {
+			hcd->has_tt = 1;
+			tdi_reset(ehci);
+		}
 		break;
 	case PCI_VENDOR_ID_TDI:
 		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
-- 
1.7.2.3

 

Re: [PATCH 6/6] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

[Alan Stern]

On Tue, 9 Nov 2010, Dirk Brandewie wrote:

> In a previous patch in this series GregKH asked that the PCI ID not be added 
> to pci_ids.h for ID's that are only used by a single file.  
> Here is an updated version of the EHCI controller patch.
> 
> Subject: [PATCH] ce4100: Add support for CE4100 EHCI IP block to EHCI driver
> 
> This patch adds support for the EHCI IP block present on the Intel
> CE4100.
> 
> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
> CC: linux-usb@vger.kernel.org
> CC: David Brownell <dbrownell@users.sourceforge.net>
> ---
>  drivers/usb/host/ehci-pci.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
> index a1e8d27..da2b196 100644
> --- a/drivers/usb/host/ehci-pci.c
> +++ b/drivers/usb/host/ehci-pci.c
> @@ -124,6 +124,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
>  			ehci_info(ehci, "disable lpm for langwell/penwell\n");
>  			ehci->has_lpm = 0;
>  		}
> +		if (pdev->device == 0x2e70) {
> +			hcd->has_tt = 1;
> +			tdi_reset(ehci);
> +		}

I think Greg meant that it's okay to use a symbolic constant for the
PCI ID (it helps tell people what hardware is being handled).  Just
don't add that constant to the pci_ids.h file.

Alan Stern

Re: [PATCH 6/6] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

[Sergei Shtylyov]

Hello.

On 10-11-2010 5:36, Alan Stern wrote:

>> In a previous patch in this series GregKH asked that the PCI ID not be added
>> to pci_ids.h for ID's that are only used by a single file.
>> Here is an updated version of the EHCI controller patch.

>> Subject: [PATCH] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

>> This patch adds support for the EHCI IP block present on the Intel
>> CE4100.

>> Signed-off-by: Dirk Brandewie<dirk.brandewie@gmail.com>
>> CC: linux-usb@vger.kernel.org
>> CC: David Brownell<dbrownell@users.sourceforge.net>
>> ---
>>   drivers/usb/host/ehci-pci.c |    4 ++++
>>   1 files changed, 4 insertions(+), 0 deletions(-)

>> diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
>> index a1e8d27..da2b196 100644
>> --- a/drivers/usb/host/ehci-pci.c
>> +++ b/drivers/usb/host/ehci-pci.c
>> @@ -124,6 +124,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
>>   			ehci_info(ehci, "disable lpm for langwell/penwell\n");
>>   			ehci->has_lpm = 0;
>>   		}
>> +		if (pdev->device == 0x2e70) {
>> +			hcd->has_tt = 1;
>> +			tdi_reset(ehci);
>> +		}

> I think Greg meant that it's okay to use a symbolic constant for the
> PCI ID (it helps tell people what hardware is being handled).  Just
> don't add that constant to the pci_ids.h file.

    Or at least you need a comment naming the hardware that this ID belongs to.

> Alan Stern

WBR, Sergei

Re: [PATCH 4/6] ce4100: Add errata fixes for UART on CE4100

[Thomas Gleixner]

On Tue, 9 Nov 2010, dirk.brandewie@gmail.com wrote:

> From: Dirk Brandewie <dirk.brandewie@gmail.com>
> 
> This patch enables the UART on the CE4100.  The UART has a couple of
> issues that need to be worked around.  First the UART is mostly PC
> compatible except that it is clocked eight times faster than a
> standard PC so the default configuration provided in
> arch/x86/include/asm/serial.h needs to be overridden. Second the TX
> interrupt may not be set correctly all the time. Lastly accessing the
> UART via I/O space for early_prink() hangs the chip when the IOAPIC is
> enabled.
> 
> A custom mem_serial_in() is provided to work around the TX interrupt
> issue. The configuration issues are dealt with in the call back
> registered with the 8250 driver via serial8250_set_isa_configurator()
> 
> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
> ---
>  arch/x86/kernel/ce4100.c |   92 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 89 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/ce4100.c b/arch/x86/kernel/ce4100.c
> index b8f1c48..d2c0d51 100644
> --- a/arch/x86/kernel/ce4100.c
> +++ b/arch/x86/kernel/ce4100.c
> @@ -12,25 +12,111 @@
>  #include <linux/kernel.h>
>  #include <linux/irq.h>
>  #include <linux/module.h>
> +#include <linux/serial_reg.h>
> +#include <linux/serial_8250.h>
>  
>  #include <asm/setup.h>
> -
> +#include <asm/io.h>
>  
>  static int ce4100_i8042_detect(void)
>  {
>  	return 0;
>  }
>  
> -static void __init sdv_arch_setup(void)
> +static void __init sdv_find_smp_config(void)
>  {
> +}
> +
> +#ifdef CONFIG_SERIAL_8250
> +
>  
> +static unsigned int mem_serial_in(struct uart_port *p, int offset)
> +{
> +	offset = offset << p->regshift;
> +	return readl(p->membase + offset);
>  }
>  
> +/*
> + * The UART Tx interrupts are not set under some conditions and therefore serial
> + * transmission hangs. This is a silicon issue and has not been root caused. The
> + * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
> + * bit of LSR register in interrupt handler to see whether at least one of these
> + * two bits is set, if so then process the transmit request. If this workaround
> + * is not applied, then the serial transmission may hang. This workaround is for
> + * errata number 9 in Errata - B step.
> +*/
>  
> -static void __init sdv_find_smp_config(void)
> +static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
> +{
> +	unsigned int ret, ier, lsr;
> +
> +	if (offset == UART_IIR) {
> +		offset = offset << p->regshift;
> +		ret = readl(p->membase + offset);
> +		if (ret & UART_IIR_NO_INT) {
> +			/* see if the TX interrupt should have really set */
> +			ier = mem_serial_in(p, UART_IER);
> +			/* see if the UART's XMIT interrupt is enabled */
> +			if (ier & UART_IER_THRI) {
> +				lsr = mem_serial_in(p, UART_LSR);
> +				/* now check to see if the UART should be
> +				   generating an interrupt (but isn't) */
> +				if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
> +					ret &= ~UART_IIR_NO_INT;
> +			}
> +		}
> +	} else
> +		ret =  mem_serial_in(p, offset);
> +	return ret;
> +}
> +
> +static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
> +{
> +	offset = offset << p->regshift;
> +	writel(value, p->membase + offset);
> +}
> +
> +static void ce4100_serial_fixup(int port, struct uart_port *up,
> +	unsigned short *capabilites)
> +{
> +#ifdef CONFIG_EARLY_PRINTK
> +	/*
> +	 * Over ride the legacy port configuration that comes from
> +	 * asm/serial.h. Using the ioport driver then switching to the
> +	 * PCI memmaped driver hangs the IOAPIC
> +	 */
> +	if (up->iotype !=  UPIO_MEM32) {
> +		up->uartclk  = 14745600;
> +		up->mapbase = 0xdffe0200;

  What does the uartclk, mapbase fixups in the CONFIG_EARLY_PRINTK=n case ?

> +		set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
> +				up->mapbase & PAGE_MASK);
> +		up->membase =
> +			(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
> +		up->membase += up->mapbase & ~PAGE_MASK;
> +		up->iotype   = UPIO_MEM32;
> +		up->regshift = 2;
> +	}
> +#endif
> +	up->iobase = 0;
> +	up->serial_in = ce4100_mem_serial_in;
> +	up->serial_out = ce4100_mem_serial_out;
> +
> +	*capabilites |= (1 << 12);
> +}

Thanks,

	tglx

Re: [PATCH 4/6] ce4100: Add errata fixes for UART on CE4100

[Thomas Gleixner]

On Thu, 11 Nov 2010, Dirk Brandewie wrote:

> On 11/11/2010 03:34 AM, Thomas Gleixner wrote:
> > 
> > 
> > > +	 * Over ride the legacy port configuration that comes from
> > > +	 * asm/serial.h. Using the ioport driver then switching to the
> > > +	 * PCI memmaped driver hangs the IOAPIC
> > > +	 */
> > > +	if (up->iotype !=  UPIO_MEM32) {
> > > +		up->uartclk  = 14745600;
> > > +		up->mapbase = 0xdffe0200;
> > 
> >    What does the uartclk, mapbase fixups in the CONFIG_EARLY_PRINTK=n case ?
> > 
> This is setup in the PCI driver patch #3 in the series

I just can't find it there, that's why I'm asking :)

Thanks,

	tglx

Re: [PATCH 2/6] ce4100: add PCI register emulation for CE4100

[Thomas Gleixner]

On Tue, 9 Nov 2010, dirk.brandewie@gmail.com wrote:
> +
> +static int ce4100_conf_read(unsigned int seg, unsigned int bus,
> +			  unsigned int devfn, int reg, int len, u32 *value)
> +{
> +	int retval = 1;
> +	int i;
> +
> +	if (bus == 0 && (PCI_DEVFN(1, 0) == devfn))
> +		retval = bridge_read(devfn, reg, len, value);
> +
> +	if (bus == 1) {
> +		for (i = 0; i < num_bus1_fixups; i++) {
> +			if (bus1_fixups[i].dev_func == devfn &&
> +				bus1_fixups[i].reg == (reg & ~3) &&
> +				bus1_fixups[i].read) {
> +				bus1_fixups[i].read(&(bus1_fixups[i]),
> +					value);
> +				extract_bytes(value, reg, len);
> +				retval = 0;

  Shouldn't we return 0 here and be done ?

> +			}
> +		}
> +	}
> +	if (retval)
> +		retval = pci_direct_conf1.read(seg, bus, devfn, reg,
> +					len, value);
> +	return retval;
> +}
> +
> +
> +static int ce4100_conf_write(unsigned int seg, unsigned int bus,
> +			   unsigned int devfn, int reg, int len, u32 value)
> +{
> +	int retval = 1;
> +	int i;
> +
> +	if (bus == 1) {
> +		for (i = 0; i < num_bus1_fixups; i++) {
> +			if (bus1_fixups[i].dev_func == devfn &&
> +				bus1_fixups[i].reg == (reg & ~3) &&
> +				bus1_fixups[i].write) {
> +				bus1_fixups[i].write(&(bus1_fixups[i]),
> +					value);
> +				retval = 0;

  Ditto

> +			}
> +		}
> +	}
> +
> +	/* Discard writes to A/V bridge BAR. */
> +	if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
> +		((reg & ~3) == PCI_BASE_ADDRESS_0))
> +		retval = 0;

  Ditto

> +
> +	if (retval)
> +		retval = pci_direct_conf1.write(seg, bus, devfn, reg,
> +						len, value);
> +	return retval;
> +}

It took me some time to grok the above retval magic. I'd rather write
it this way:

+static int ce4100_conf_read(unsigned int seg, unsigned int bus,
+			    unsigned int devfn, int reg, int len, u32 *value)
+{
+	int i;
+
+	if (bus == 1) {
+		for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
+			if (bus1_fixups[i].dev_func == devfn &&
+			    bus1_fixups[i].reg == (reg & ~3) &&
+			    bus1_fixups[i].read) {
+				bus1_fixups[i].read(&(bus1_fixups[i]),
+						    value);
+				extract_bytes(value, reg, len);
+				return 0;
+			}
+		}
+	}
+
+	if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&
+	    !bridge_read(devfn, reg, len, value))
+		return 0;
+
+	return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
+}
+
+static int ce4100_conf_write(unsigned int seg, unsigned int bus,
+			     unsigned int devfn, int reg, int len, u32 value)
+{
+	int i;
+
+	if (bus == 1) {
+		for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
+			if (bus1_fixups[i].dev_func == devfn &&
+			    bus1_fixups[i].reg == (reg & ~3) &&
+			    bus1_fixups[i].write) {
+				bus1_fixups[i].write(&(bus1_fixups[i]),
+						     value);
+				return 0;
+			}
+		}
+	}
+
+	/* Discard writes to A/V bridge BAR. */
+	if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
+	    ((reg & ~3) == PCI_BASE_ADDRESS_0))
+		return 0;
+
+	return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
+}

Thanks,

	tglx

Re: [PATCH 4/6] ce4100: Add errata fixes for UART on CE4100

[Dirk Brandewie]

On 11/11/2010 03:34 AM, Thomas Gleixner wrote:
>
>
>> +	 * Over ride the legacy port configuration that comes from
>> +	 * asm/serial.h. Using the ioport driver then switching to the
>> +	 * PCI memmaped driver hangs the IOAPIC
>> +	 */
>> +	if (up->iotype !=  UPIO_MEM32) {
>> +		up->uartclk  = 14745600;
>> +		up->mapbase = 0xdffe0200;
>
>    What does the uartclk, mapbase fixups in the CONFIG_EARLY_PRINTK=n case ?
>
This is setup in the PCI driver patch #3 in the series

>> +		set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
>> +				up->mapbase&  PAGE_MASK);
>> +		up->membase =
>> +			(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
>> +		up->membase += up->mapbase&  ~PAGE_MASK;
>> +		up->iotype   = UPIO_MEM32;
>> +		up->regshift = 2;
>> +	}
>> +#endif
>> +	up->iobase = 0;
>> +	up->serial_in = ce4100_mem_serial_in;
>> +	up->serial_out = ce4100_mem_serial_out;
>> +
>> +	*capabilites |= (1<<  12);
>> +}
>
> Thanks,
>
> 	tglx

Re: [PATCH 4/6] ce4100: Add errata fixes for UART on CE4100

[Thomas Gleixner]

On Thu, 11 Nov 2010, Dirk Brandewie wrote:

> On 11/11/2010 03:47 AM, Thomas Gleixner wrote:
> > On Thu, 11 Nov 2010, Dirk Brandewie wrote:
> > 
> > > On 11/11/2010 03:34 AM, Thomas Gleixner wrote:
> > > > 
> > > > 
> > > > > +	 * Over ride the legacy port configuration that comes from
> > > > > +	 * asm/serial.h. Using the ioport driver then switching to the
> > > > > +	 * PCI memmaped driver hangs the IOAPIC
> > > > > +	 */
> > > > > +	if (up->iotype !=  UPIO_MEM32) {
> > > > > +		up->uartclk  = 14745600;
> > > > > +		up->mapbase = 0xdffe0200;
> > > > 
> > > >     What does the uartclk, mapbase fixups in the CONFIG_EARLY_PRINTK=n
> > > > case ?
> > > > 
> > > This is setup in the PCI driver patch #3 in the series
> > 
> > I just can't find it there, that's why I'm asking :)
> The weird clock is dealt with in:
> +	[pbn_ce4100_1_115200] = {
> +		.flags		= FL_BASE0,
> +		.num_ports	= 1,
> +		.base_baud	= 921600,
> +		.reg_shift      = 2,
> +	},
> 
> That map base is setup in the generic pci driver in setup_port(). I didn't
> need to do anything special.

Thanks for the clarification.

       tglx

Re: [PATCH 4/6] ce4100: Add errata fixes for UART on CE4100

[Dirk Brandewie]

On 11/11/2010 03:47 AM, Thomas Gleixner wrote:
> On Thu, 11 Nov 2010, Dirk Brandewie wrote:
>
>> On 11/11/2010 03:34 AM, Thomas Gleixner wrote:
>>>
>>>
>>>> +	 * Over ride the legacy port configuration that comes from
>>>> +	 * asm/serial.h. Using the ioport driver then switching to the
>>>> +	 * PCI memmaped driver hangs the IOAPIC
>>>> +	 */
>>>> +	if (up->iotype !=  UPIO_MEM32) {
>>>> +		up->uartclk  = 14745600;
>>>> +		up->mapbase = 0xdffe0200;
>>>
>>>     What does the uartclk, mapbase fixups in the CONFIG_EARLY_PRINTK=n case ?
>>>
>> This is setup in the PCI driver patch #3 in the series
>
> I just can't find it there, that's why I'm asking :)
The weird clock is dealt with in:
+	[pbn_ce4100_1_115200] = {
+		.flags		= FL_BASE0,
+		.num_ports	= 1,
+		.base_baud	= 921600,
+		.reg_shift      = 2,
+	},

That map base is setup in the generic pci driver in setup_port(). I didn't need 
to do anything special.
--Dirk
>
> Thanks,
>
> 	tglx

Re: [PATCH 6/6] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

[Greg KH]

On Wed, Nov 10, 2010 at 01:51:17PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 10-11-2010 5:36, Alan Stern wrote:
> 
> >>In a previous patch in this series GregKH asked that the PCI ID not be added
> >>to pci_ids.h for ID's that are only used by a single file.
> >>Here is an updated version of the EHCI controller patch.
> 
> >>Subject: [PATCH] ce4100: Add support for CE4100 EHCI IP block to EHCI driver
> 
> >>This patch adds support for the EHCI IP block present on the Intel
> >>CE4100.
> 
> >>Signed-off-by: Dirk Brandewie<dirk.brandewie@gmail.com>
> >>CC: linux-usb@vger.kernel.org
> >>CC: David Brownell<dbrownell@users.sourceforge.net>
> >>---
> >>  drivers/usb/host/ehci-pci.c |    4 ++++
> >>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> >>diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
> >>index a1e8d27..da2b196 100644
> >>--- a/drivers/usb/host/ehci-pci.c
> >>+++ b/drivers/usb/host/ehci-pci.c
> >>@@ -124,6 +124,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
> >>  			ehci_info(ehci, "disable lpm for langwell/penwell\n");
> >>  			ehci->has_lpm = 0;
> >>  		}
> >>+		if (pdev->device == 0x2e70) {
> >>+			hcd->has_tt = 1;
> >>+			tdi_reset(ehci);
> >>+		}
> 
> >I think Greg meant that it's okay to use a symbolic constant for the
> >PCI ID (it helps tell people what hardware is being handled).  Just
> >don't add that constant to the pci_ids.h file.
> 
>    Or at least you need a comment naming the hardware that this ID belongs to.

I agree, something a bit better than just the device id might be nice
here.

Dirk, care to redo this one and your serial one, with that idea?

thanks,

greg k-h

Re: [PATCH 6/6] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

[Dirk Brandewie]

On 11/16/2010 01:46 PM, Greg KH wrote:
> On Wed, Nov 10, 2010 at 01:51:17PM +0300, Sergei Shtylyov wrote:
>> Hello.
>>
>> On 10-11-2010 5:36, Alan Stern wrote:
>>
>>>> In a previous patch in this series GregKH asked that the PCI ID not be added
>>>> to pci_ids.h for ID's that are only used by a single file.
>>>> Here is an updated version of the EHCI controller patch.
>>
>>>> Subject: [PATCH] ce4100: Add support for CE4100 EHCI IP block to EHCI driver
>>
>>>> This patch adds support for the EHCI IP block present on the Intel
>>>> CE4100.
>>
>>>> Signed-off-by: Dirk Brandewie<dirk.brandewie@gmail.com>
>>>> CC: linux-usb@vger.kernel.org
>>>> CC: David Brownell<dbrownell@users.sourceforge.net>
>>>> ---
>>>>   drivers/usb/host/ehci-pci.c |    4 ++++
>>>>   1 files changed, 4 insertions(+), 0 deletions(-)
>>
>>>> diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
>>>> index a1e8d27..da2b196 100644
>>>> --- a/drivers/usb/host/ehci-pci.c
>>>> +++ b/drivers/usb/host/ehci-pci.c
>>>> @@ -124,6 +124,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
>>>>   			ehci_info(ehci, "disable lpm for langwell/penwell\n");
>>>>   			ehci->has_lpm = 0;
>>>>   		}
>>>> +		if (pdev->device == 0x2e70) {
>>>> +			hcd->has_tt = 1;
>>>> +			tdi_reset(ehci);
>>>> +		}
>>
>>> I think Greg meant that it's okay to use a symbolic constant for the
>>> PCI ID (it helps tell people what hardware is being handled).  Just
>>> don't add that constant to the pci_ids.h file.
>>
>>     Or at least you need a comment naming the hardware that this ID belongs to.
>
> I agree, something a bit better than just the device id might be nice
> here.
>
> Dirk, care to redo this one and your serial one, with that idea?
>
Yes, sorry for slow turn around been pulled in other random directions the last 
few days

--Dirk

[PATCH] serial/ce4100: Add PCI UART support for the ce4100

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch adds support for the PCI UART on the ce4100.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
CC: linux-serial@vger.kernel.org
---
 drivers/serial/8250_pci.c |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 53be4d3..e30356d 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -957,6 +957,22 @@ pci_default_setup(struct serial_private *priv,
 	return setup_port(priv, port, bar, offset, board->reg_shift);
 }
 
+static int
+ce4100_serial_setup(struct serial_private *priv,
+		  const struct pciserial_board *board,
+		  struct uart_port *port, int idx)
+{
+	int ret;
+
+	ret = setup_port(priv, port, 0, 0, board->reg_shift);
+	port->iotype = UPIO_MEM32;
+	port->type = PORT_XSCALE;
+	port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
+	port->regshift = 2;
+
+	return ret;
+}
+
 static int skip_tx_en_setup(struct serial_private *priv,
 			const struct pciserial_board *board,
 			struct uart_port *port, int idx)
@@ -981,6 +997,7 @@ static int skip_tx_en_setup(struct serial_private *priv,
 #define PCI_SUBDEVICE_ID_POCTAL232	0x0308
 #define PCI_SUBDEVICE_ID_POCTAL422	0x0408
 #define PCI_VENDOR_ID_ADVANTECH		0x13fe
+#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
 #define PCI_DEVICE_ID_ADVANTECH_PCI3620	0x3620
 #define PCI_DEVICE_ID_TITAN_200I	0x8028
 #define PCI_DEVICE_ID_TITAN_400I	0x8048
@@ -1072,6 +1089,13 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 		.subdevice	= PCI_ANY_ID,
 		.setup		= skip_tx_en_setup,
 	},
+	{
+		.vendor		= PCI_VENDOR_ID_INTEL,
+		.device		= PCI_DEVICE_ID_INTEL_CE4100_UART,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= ce4100_serial_setup,
+	},
 	/*
 	 * ITE
 	 */
@@ -1592,6 +1616,7 @@ enum pci_board_num_t {
 	pbn_ADDIDATA_PCIe_2_3906250,
 	pbn_ADDIDATA_PCIe_4_3906250,
 	pbn_ADDIDATA_PCIe_8_3906250,
+	pbn_ce4100_1_115200,
 };
 
 /*
@@ -2281,6 +2306,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
 		.uart_offset	= 0x200,
 		.first_offset	= 0x1000,
 	},
+	[pbn_ce4100_1_115200] = {
+		.flags		= FL_BASE0,
+		.num_ports	= 1,
+		.base_baud	= 921600,
+		.reg_shift      = 2,
+	},
 };
 
 static const struct pci_device_id softmodem_blacklist[] = {
@@ -3760,6 +3791,11 @@ static struct pci_device_id serial_pci_tbl[] = {
 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
 		0xA000, 0x3004,
 		0, 0, pbn_b0_bt_4_115200 },
+	/* Intel CE4100 */
+	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
+		PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
+		pbn_ce4100_1_115200 },
+
 
 	/*
 	 * These entries match devices with class COMMUNICATION_SERIAL,
-- 
1.7.2.3

[PATCH] ce4100: Add support for CE4100 EHCI IP block to EHCI driver

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch adds support for the EHCI IP block present on the Intel
CE4100.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
CC: linux-usb@vger.kernel.org
CC: David Brownell <dbrownell@users.sourceforge.net>
---
 drivers/usb/host/ehci-pci.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index a1e8d27..56c78e9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,6 +22,9 @@
 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
 #endif
 
+/* defined here to avoid adding to pci_ids.h for single instance use */
+#define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70
+
 /*-------------------------------------------------------------------------*/
 
 /* called after powerup, by probe or system-pm "wakeup" */
@@ -124,6 +127,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
 			ehci_info(ehci, "disable lpm for langwell/penwell\n");
 			ehci->has_lpm = 0;
 		}
+		if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
+			hcd->has_tt = 1;
+			tdi_reset(ehci);
+		}
 		break;
 	case PCI_VENDOR_ID_TDI:
 		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
-- 
1.7.2.3

[PATCH] ce4100: Add errata fixes for UART on CE4100

[dirk.brandewie]

From: Dirk Brandewie <dirk.brandewie@gmail.com>

This patch enables the UART on the CE4100.  The UART has a couple of
issues that need to be worked around.  First the UART is mostly PC
compatible except that it is clocked eight times faster than a
standard PC so the default configuration provided in
arch/x86/include/asm/serial.h needs to be overridden. Second the TX
interrupt may not be set correctly all the time. Lastly accessing the
UART via I/O space for early_prink() hangs the chip when the IOAPIC is
enabled.

A custom mem_serial_in() is provided to work around the TX interrupt
issue. The configuration issues are dealt with in the call back
registered with the 8250 driver via serial8250_set_isa_configurator()

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
---
 arch/x86/platform/ce4100/ce4100.c |   92 +++++++++++++++++++++++++++++++++++-
 1 files changed, 89 insertions(+), 3 deletions(-)

diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c
index b8f1c48..d2c0d51 100644
--- a/arch/x86/platform/ce4100/ce4100.c
+++ b/arch/x86/platform/ce4100/ce4100.c
@@ -12,25 +12,111 @@
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <linux/module.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
 
 #include <asm/setup.h>
-
+#include <asm/io.h>
 
 static int ce4100_i8042_detect(void)
 {
 	return 0;
 }
 
-static void __init sdv_arch_setup(void)
+static void __init sdv_find_smp_config(void)
 {
+}
+
+#ifdef CONFIG_SERIAL_8250
+
 
+static unsigned int mem_serial_in(struct uart_port *p, int offset)
+{
+	offset = offset << p->regshift;
+	return readl(p->membase + offset);
 }
 
+/*
+ * The UART Tx interrupts are not set under some conditions and therefore serial
+ * transmission hangs. This is a silicon issue and has not been root caused. The
+ * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
+ * bit of LSR register in interrupt handler to see whether at least one of these
+ * two bits is set, if so then process the transmit request. If this workaround
+ * is not applied, then the serial transmission may hang. This workaround is for
+ * errata number 9 in Errata - B step.
+*/
 
-static void __init sdv_find_smp_config(void)
+static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
+{
+	unsigned int ret, ier, lsr;
+
+	if (offset == UART_IIR) {
+		offset = offset << p->regshift;
+		ret = readl(p->membase + offset);
+		if (ret & UART_IIR_NO_INT) {
+			/* see if the TX interrupt should have really set */
+			ier = mem_serial_in(p, UART_IER);
+			/* see if the UART's XMIT interrupt is enabled */
+			if (ier & UART_IER_THRI) {
+				lsr = mem_serial_in(p, UART_LSR);
+				/* now check to see if the UART should be
+				   generating an interrupt (but isn't) */
+				if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
+					ret &= ~UART_IIR_NO_INT;
+			}
+		}
+	} else
+		ret =  mem_serial_in(p, offset);
+	return ret;
+}
+
+static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
+{
+	offset = offset << p->regshift;
+	writel(value, p->membase + offset);
+}
+
+static void ce4100_serial_fixup(int port, struct uart_port *up,
+	unsigned short *capabilites)
+{
+#ifdef CONFIG_EARLY_PRINTK
+	/*
+	 * Over ride the legacy port configuration that comes from
+	 * asm/serial.h. Using the ioport driver then switching to the
+	 * PCI memmaped driver hangs the IOAPIC
+	 */
+	if (up->iotype !=  UPIO_MEM32) {
+		up->uartclk  = 14745600;
+		up->mapbase = 0xdffe0200;
+		set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
+				up->mapbase & PAGE_MASK);
+		up->membase =
+			(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
+		up->membase += up->mapbase & ~PAGE_MASK;
+		up->iotype   = UPIO_MEM32;
+		up->regshift = 2;
+	}
+#endif
+	up->iobase = 0;
+	up->serial_in = ce4100_mem_serial_in;
+	up->serial_out = ce4100_mem_serial_out;
+
+	*capabilites |= (1 << 12);
+}
+
+static __init void sdv_serial_fixup(void)
 {
+	serial8250_set_isa_configurator(ce4100_serial_fixup);
 }
 
+#else
+static inline void sdv_serial_fixup(void);
+#endif
+
+static void __init sdv_arch_setup(void)
+{
+	sdv_serial_fixup();
+}
 
 /*
  * CE4100 specific x86_init function overrides and early setup
-- 
1.7.2.3

[tip:x86/platform] ce4100: Add errata fixes for UART on CE4100

[tip-bot for Dirk Brandewie]

Commit-ID:  5ec6960f6f0c7be9cc6e5506fdf0070add3b6e08
Gitweb:     http://git.kernel.org/tip/5ec6960f6f0c7be9cc6e5506fdf0070add3b6e08
Author:     Dirk Brandewie <dirk.brandewie@gmail.com>
AuthorDate: Mon, 22 Nov 2010 06:28:48 -0800
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 6 Dec 2010 15:58:26 +0100

ce4100: Add errata fixes for UART on CE4100

This patch enables the UART on the CE4100. The UART has a couple of
issues that need to be worked around. First the UART is mostly PC
compatible except that it is clocked eight times faster than a
standard PC so the default configuration provided in
arch/x86/include/asm/serial.h needs to be overridden. Second the TX
interrupt may not be set correctly all the time. Lastly accessing the
UART via I/O space for early_prink() hangs the chip when the IOAPIC is
enabled.

A custom mem_serial_in() is provided to work around the TX interrupt
issue. The configuration issues are dealt with in the call back
registered with the 8250 driver via serial8250_set_isa_configurator()

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
LKML-Reference: <1290436128-17958-1-git-send-email-dirk.brandewie@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/platform/ce4100/ce4100.c |   94 ++++++++++++++++++++++++++++++++++++-
 1 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c
index 0ede12b..d2c0d51 100644
--- a/arch/x86/platform/ce4100/ce4100.c
+++ b/arch/x86/platform/ce4100/ce4100.c
@@ -12,20 +12,110 @@
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <linux/module.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
 
 #include <asm/setup.h>
+#include <asm/io.h>
 
 static int ce4100_i8042_detect(void)
 {
 	return 0;
 }
 
-static void __init sdv_arch_setup(void)
+static void __init sdv_find_smp_config(void)
 {
 }
 
-static void __init sdv_find_smp_config(void)
+#ifdef CONFIG_SERIAL_8250
+
+
+static unsigned int mem_serial_in(struct uart_port *p, int offset)
+{
+	offset = offset << p->regshift;
+	return readl(p->membase + offset);
+}
+
+/*
+ * The UART Tx interrupts are not set under some conditions and therefore serial
+ * transmission hangs. This is a silicon issue and has not been root caused. The
+ * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
+ * bit of LSR register in interrupt handler to see whether at least one of these
+ * two bits is set, if so then process the transmit request. If this workaround
+ * is not applied, then the serial transmission may hang. This workaround is for
+ * errata number 9 in Errata - B step.
+*/
+
+static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
+{
+	unsigned int ret, ier, lsr;
+
+	if (offset == UART_IIR) {
+		offset = offset << p->regshift;
+		ret = readl(p->membase + offset);
+		if (ret & UART_IIR_NO_INT) {
+			/* see if the TX interrupt should have really set */
+			ier = mem_serial_in(p, UART_IER);
+			/* see if the UART's XMIT interrupt is enabled */
+			if (ier & UART_IER_THRI) {
+				lsr = mem_serial_in(p, UART_LSR);
+				/* now check to see if the UART should be
+				   generating an interrupt (but isn't) */
+				if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
+					ret &= ~UART_IIR_NO_INT;
+			}
+		}
+	} else
+		ret =  mem_serial_in(p, offset);
+	return ret;
+}
+
+static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
+{
+	offset = offset << p->regshift;
+	writel(value, p->membase + offset);
+}
+
+static void ce4100_serial_fixup(int port, struct uart_port *up,
+	unsigned short *capabilites)
+{
+#ifdef CONFIG_EARLY_PRINTK
+	/*
+	 * Over ride the legacy port configuration that comes from
+	 * asm/serial.h. Using the ioport driver then switching to the
+	 * PCI memmaped driver hangs the IOAPIC
+	 */
+	if (up->iotype !=  UPIO_MEM32) {
+		up->uartclk  = 14745600;
+		up->mapbase = 0xdffe0200;
+		set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
+				up->mapbase & PAGE_MASK);
+		up->membase =
+			(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
+		up->membase += up->mapbase & ~PAGE_MASK;
+		up->iotype   = UPIO_MEM32;
+		up->regshift = 2;
+	}
+#endif
+	up->iobase = 0;
+	up->serial_in = ce4100_mem_serial_in;
+	up->serial_out = ce4100_mem_serial_out;
+
+	*capabilites |= (1 << 12);
+}
+
+static __init void sdv_serial_fixup(void)
+{
+	serial8250_set_isa_configurator(ce4100_serial_fixup);
+}
+
+#else
+static inline void sdv_serial_fixup(void);
+#endif
+
+static void __init sdv_arch_setup(void)
 {
+	sdv_serial_fixup();
 }
 
 /*