* [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver @ 2012-01-05 7:11 Hiroshi DOYU 2012-01-05 7:11 ` [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Hiroshi DOYU ` (2 more replies) 0 siblings, 3 replies; 25+ messages in thread From: Hiroshi DOYU @ 2012-01-05 7:11 UTC (permalink / raw) To: Hiroshi DOYU Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces This patchset adds support for IOMMU API for Tegra20(GART) and Tegra30(SMMU). "struct iommu_ops" are implemented for both H/W IOMMU modules. Tested with "Ion memory manager" and "DMA mapping API"(*1). This was originally developed with Tegra specific IOMMU API(tegra_iovmm_*()) in: git://nv-tegra.nvidia.com/linux-2.6.git. v2: https://lkml.org/lkml/2011/12/15/203 v1: https://lkml.org/lkml/2011/11/17/111 *1: Reworking the DMA mapping code (especially on ARM) http://lwn.net/Articles/467509/ Hiroshi DOYU (2): ARM: IOMMU: Tegra20: Add iommu_ops for GART driver ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver arch/arm/mach-tegra/include/mach/smmu.h | 63 ++ drivers/iommu/Kconfig | 22 + drivers/iommu/Makefile | 2 + drivers/iommu/tegra-gart.c | 436 +++++++++++++ drivers/iommu/tegra-smmu.c | 1026 +++++++++++++++++++++++++++++++ 5 files changed, 1549 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-tegra/include/mach/smmu.h create mode 100644 drivers/iommu/tegra-gart.c create mode 100644 drivers/iommu/tegra-smmu.c -- 1.7.5.4 ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver 2012-01-05 7:11 [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi DOYU @ 2012-01-05 7:11 ` Hiroshi DOYU 2012-01-23 15:00 ` Joerg Roedel 2012-01-05 7:11 ` [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Hiroshi DOYU 2012-01-05 7:17 ` [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi Doyu 2 siblings, 1 reply; 25+ messages in thread From: Hiroshi DOYU @ 2012-01-05 7:11 UTC (permalink / raw) To: Hiroshi DOYU Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This patch implements struct iommu_ops for GART for the upper IOMMU API. This H/W module supports only single virtual address space(domain), and manages a single level 1-to-1 mapping H/W translation page table. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> --- drivers/iommu/Kconfig | 11 + drivers/iommu/Makefile | 1 + drivers/iommu/tegra-gart.c | 436 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 448 insertions(+), 0 deletions(-) create mode 100644 drivers/iommu/tegra-gart.c diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 6bea696..4562698 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -142,4 +142,15 @@ config OMAP_IOMMU_DEBUG Say N unless you know you need this. +config TEGRA_IOMMU_GART + bool "Tegra GART IOMMU Support" + depends on ARCH_TEGRA_2x_SOC + default y + select IOMMU_API + help + Enables support for remapping discontiguous physical memory + shared with the operating system into contiguous I/O virtual + space through the GART (Graphics Address Relocation Table) + hardware included on Tegra SoCs. + endif # IOMMU_SUPPORT diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 0e36b49..3238a31 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o +obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c new file mode 100644 index 0000000..feaccd4 --- /dev/null +++ b/drivers/iommu/tegra-gart.c @@ -0,0 +1,436 @@ +/* + * IOMMU API for GART in Tegra20 + * + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define pr_fmt(fmt) "%s(): " fmt, __func__ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/mm.h> +#include <linux/list.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/iommu.h> + +#include <asm/cacheflush.h> + +/* bitmap of the page sizes currently supported */ +#define GART_IOMMU_PGSIZES (SZ_4K) + +#define GART_CONFIG 0x24 +#define GART_ENTRY_ADDR 0x28 +#define GART_ENTRY_DATA 0x2c +#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31) + +#define GART_PAGE_SHIFT 12 +#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT) +#define GART_PAGE_MASK \ + (~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID) + +struct gart_client { + struct device *dev; + struct list_head list; +}; + +struct gart_device { + void __iomem *regs; + u32 *savedata; + u32 page_count; /* total remappable size */ + dma_addr_t iovmm_base; /* offset to apply to vmm_area */ + spinlock_t pte_lock; /* for pagetable */ + struct list_head client; + spinlock_t client_lock; /* for client list */ + struct device *dev; +}; + +#define GART_PTE(_pfn) \ + (GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT)) + +/* + * Any interaction between any block on PPSB and a block on APB or AHB + * must have these read-back to ensure the APB/AHB bus transaction is + * complete before initiating activity on the PPSB block. + */ +#define FLUSH_GART_REGS(gart) ((void)readl((gart)->regs + GART_CONFIG)) + +#define for_each_gart_pte(gart, iova) \ + for (iova = gart->iovmm_base; \ + iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \ + iova += GART_PAGE_SIZE) + +static inline void gart_set_pte(struct gart_device *gart, + unsigned long offs, u32 pte) +{ + writel(offs, gart->regs + GART_ENTRY_ADDR); + writel(pte, gart->regs + GART_ENTRY_DATA); + + dev_dbg(gart->dev, "%s %08lx:%08x\n", + pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK); +} + +static inline unsigned long gart_read_pte(struct gart_device *gart, + unsigned long offs) +{ + unsigned long pte; + + writel(offs, gart->regs + GART_ENTRY_ADDR); + pte = readl(gart->regs + GART_ENTRY_DATA); + + return pte; +} + +static void do_gart_setup(struct gart_device *gart, const u32 *data) +{ + unsigned long iova; + + for_each_gart_pte(gart, iova) + gart_set_pte(gart, iova, data ? *(data++) : 0); + + writel(1, gart->regs + GART_CONFIG); + FLUSH_GART_REGS(gart); +} + +#ifdef DEBUG +static void gart_dump_table(struct gart_device *gart) +{ + unsigned long iova; + unsigned long flags; + + spin_lock_irqsave(&gart->pte_lock, flags); + for_each_gart_pte(gart, iova) { + unsigned long pte; + + pte = gart_read_pte(gart, iova); + + dev_dbg(gart->dev, "%s %08lx:%08lx\n", + (GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ", + iova, pte & GART_PAGE_MASK); + } + spin_unlock_irqrestore(&gart->pte_lock, flags); +} +#else +static inline void gart_dump_table(struct gart_device *gart) +{ +} +#endif + +static inline bool gart_iova_range_valid(struct gart_device *gart, + unsigned long iova, size_t bytes) +{ + unsigned long iova_start, iova_end, gart_start, gart_end; + + iova_start = iova; + iova_end = iova_start + bytes - 1; + gart_start = gart->iovmm_base; + gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1; + + if (iova_start < gart_start) + return false; + if (iova_end > gart_end) + return false; + return true; +} + +static int gart_iommu_domain_init(struct iommu_domain *domain) +{ + return 0; +} + +static void gart_iommu_domain_destroy(struct iommu_domain *domain) +{ + struct gart_device *gart = domain->priv; + + spin_lock(&gart->client_lock); + if (!list_empty(&gart->client)) { + struct gart_client *c; + + list_for_each_entry(c, &gart->client, list) + dev_err(gart->dev, + "%s is still attached\n", dev_name(c->dev)); + } + spin_unlock(&gart->client_lock); + domain->priv = NULL; +} + +static int gart_iommu_attach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct gart_device *gart; + struct gart_client *client, *c; + int err = 0; + + gart = dev_get_drvdata(dev->parent); + if (!gart) + return -EINVAL; + domain->priv = gart; + client = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL); + if (!client) + return -ENOMEM; + client->dev = dev; + + spin_lock(&gart->client_lock); + list_for_each_entry(c, &gart->client, list) { + if (c->dev == dev) { + dev_err(gart->dev, + "%s is already attached\n", dev_name(dev)); + err = -EINVAL; + goto fail; + } + } + list_add(&client->list, &gart->client); + spin_unlock(&gart->client_lock); + dev_dbg(gart->dev, "Attached %s\n", dev_name(dev)); + return 0; + +fail: + devm_kfree(dev, client); + spin_unlock(&gart->client_lock); + return err; +} + +static void gart_iommu_detach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct gart_device *gart = domain->priv; + struct gart_client *c; + + spin_lock(&gart->client_lock); + + list_for_each_entry(c, &gart->client, list) { + if (c->dev == dev) { + list_del(&c->list); + devm_kfree(dev, c); + dev_dbg(gart->dev, "Detached %s\n", dev_name(dev)); + goto out; + } + } + dev_err(gart->dev, "Couldn't find\n"); +out: + spin_unlock(&gart->client_lock); +} + +static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t pa, size_t bytes, int prot) +{ + struct gart_device *gart = domain->priv; + unsigned long flags; + unsigned long pfn; + + if (!gart_iova_range_valid(gart, iova, bytes)) + return -EINVAL; + + spin_lock_irqsave(&gart->pte_lock, flags); + pfn = __phys_to_pfn(pa); + if (!pfn_valid(pfn)) { + dev_err(gart->dev, "Invalid page: %08x\n", pa); + spin_unlock(&gart->pte_lock); + return -EINVAL; + } + gart_set_pte(gart, iova, GART_PTE(pfn)); + FLUSH_GART_REGS(gart); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova, + size_t bytes) +{ + struct gart_device *gart = domain->priv; + unsigned long flags; + + if (!gart_iova_range_valid(gart, iova, bytes)) + return -EINVAL; + + spin_lock_irqsave(&gart->pte_lock, flags); + gart_set_pte(gart, iova, 0); + FLUSH_GART_REGS(gart); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain, + unsigned long iova) +{ + struct gart_device *gart = domain->priv; + unsigned long pte; + phys_addr_t pa; + unsigned long flags; + + if (!gart_iova_range_valid(gart, iova, 0)) + return -EINVAL; + + spin_lock_irqsave(&gart->pte_lock, flags); + pte = gart_read_pte(gart, iova); + spin_unlock_irqrestore(&gart->pte_lock, flags); + + pa = (pte & GART_PAGE_MASK); + if (!pfn_valid(__phys_to_pfn(pa))) { + dev_err(gart->dev, "No entry for %08lx:%08x\n", iova, pa); + gart_dump_table(gart); + return -EINVAL; + } + return pa; +} + +static int gart_iommu_domain_has_cap(struct iommu_domain *domain, + unsigned long cap) +{ + return 0; +} + +static struct iommu_ops gart_iommu_ops = { + .domain_init = gart_iommu_domain_init, + .domain_destroy = gart_iommu_domain_destroy, + .attach_dev = gart_iommu_attach_dev, + .detach_dev = gart_iommu_detach_dev, + .map = gart_iommu_map, + .unmap = gart_iommu_unmap, + .iova_to_phys = gart_iommu_iova_to_phys, + .domain_has_cap = gart_iommu_domain_has_cap, + .pgsize_bitmap = GART_IOMMU_PGSIZES, +}; + +static int tegra_gart_suspend(struct device *dev) +{ + struct gart_device *gart = dev_get_drvdata(dev); + unsigned long iova; + u32 *data = gart->savedata; + unsigned long flags; + + spin_lock_irqsave(&gart->pte_lock, flags); + for_each_gart_pte(gart, iova) + *(data++) = gart_read_pte(gart, iova); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static int tegra_gart_resume(struct device *dev) +{ + struct gart_device *gart = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&gart->pte_lock, flags); + do_gart_setup(gart, gart->savedata); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static int tegra_gart_probe(struct platform_device *pdev) +{ + struct gart_device *gart; + struct resource *res, *res_remap; + void __iomem *gart_regs; + int err; + struct device *dev = &pdev->dev; + + BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT); + + /* the GART memory aperture is required */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res || !res_remap) { + dev_err(dev, "GART memory aperture expected\n"); + return -ENXIO; + } + + gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL); + if (!gart) { + dev_err(dev, "failed to allocate gart_device\n"); + return -ENOMEM; + } + + gart_regs = devm_ioremap(dev, res->start, resource_size(res)); + if (!gart_regs) { + dev_err(dev, "failed to remap GART registers\n"); + err = -ENXIO; + goto fail; + } + + gart->dev = &pdev->dev; + spin_lock_init(&gart->pte_lock); + spin_lock_init(&gart->client_lock); + INIT_LIST_HEAD(&gart->client); + gart->regs = gart_regs; + gart->iovmm_base = (dma_addr_t)res_remap->start; + gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT); + + gart->savedata = vmalloc(sizeof(u32) * gart->page_count); + if (!gart->savedata) { + dev_err(dev, "failed to allocate context save area\n"); + err = -ENOMEM; + goto fail; + } + + platform_set_drvdata(pdev, gart); + do_gart_setup(gart, NULL); + return 0; + +fail: + if (gart_regs) + devm_iounmap(dev, gart_regs); + if (gart && gart->savedata) + vfree(gart->savedata); + devm_kfree(dev, gart); + return err; +} + +static int tegra_gart_remove(struct platform_device *pdev) +{ + struct gart_device *gart = platform_get_drvdata(pdev); + struct device *dev = gart->dev; + + writel(0, gart->regs + GART_CONFIG); + if (gart->savedata) + vfree(gart->savedata); + if (gart->regs) + devm_iounmap(dev, gart->regs); + devm_kfree(dev, gart); + return 0; +} + +const struct dev_pm_ops tegra_gart_pm_ops = { + .suspend = tegra_gart_suspend, + .resume = tegra_gart_resume, +}; + +static struct platform_driver tegra_gart_driver = { + .probe = tegra_gart_probe, + .remove = tegra_gart_remove, + .driver = { + .owner = THIS_MODULE, + .name = "tegra-gart", + .pm = &tegra_gart_pm_ops, + }, +}; + +static int __devinit tegra_gart_init(void) +{ + bus_set_iommu(&platform_bus_type, &gart_iommu_ops); + return platform_driver_register(&tegra_gart_driver); +} + +static void __exit tegra_gart_exit(void) +{ + platform_driver_unregister(&tegra_gart_driver); +} + +subsys_initcall(tegra_gart_init); +module_exit(tegra_gart_exit); -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver 2012-01-05 7:11 ` [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Hiroshi DOYU @ 2012-01-23 15:00 ` Joerg Roedel 2012-01-25 7:40 ` Hiroshi Doyu 0 siblings, 1 reply; 25+ messages in thread From: Joerg Roedel @ 2012-01-23 15:00 UTC (permalink / raw) To: Hiroshi DOYU Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces Hi, first, some questions about the GART on your platform. 1) How many GARTs are usually implemented? One GART per device or is there a single GART covering all devices, or a mix of both? 2) Are devices allowed to DMA outside of the remappable range or will this fail? Besides that I think IOMMU-API is not yet fully ready for GART-like drivers like this one. But I will merge it anyway to get things moving. But please answer or fix my objections first. On Thu, Jan 05, 2012 at 09:11:48AM +0200, Hiroshi DOYU wrote: > +static void gart_iommu_domain_destroy(struct iommu_domain *domain) > +{ > + struct gart_device *gart = domain->priv; > + > + spin_lock(&gart->client_lock); > + if (!list_empty(&gart->client)) { > + struct gart_client *c; > + > + list_for_each_entry(c, &gart->client, list) > + dev_err(gart->dev, > + "%s is still attached\n", dev_name(c->dev)); > + } > + spin_unlock(&gart->client_lock); gart needs a NULL check. When you create a domain and immediatly destroy it without ever attaching a device this code will dereference a NULL pointer. As a general improvement I suggest that you introduce a gart_domain structure and store it in domain->priv (assigned in domain_init) instead of using the hardware descriptor. > +static int gart_iommu_attach_dev(struct iommu_domain *domain, > + struct device *dev) > +{ > + struct gart_device *gart; > + struct gart_client *client, *c; > + int err = 0; > + > + gart = dev_get_drvdata(dev->parent); > + if (!gart) > + return -EINVAL; > + domain->priv = gart; What happens when devices behind different GARTs are assigned to the same domain? domain->priv can only hold a pointer to one hardware GART. This can be solved by a 'struct gart_domain' holding a linked list to all gart_devices in this domain. Joerg ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver 2012-01-23 15:00 ` Joerg Roedel @ 2012-01-25 7:40 ` Hiroshi Doyu 2012-01-26 11:58 ` joro 0 siblings, 1 reply; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-25 7:40 UTC (permalink / raw) To: joro Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces [-- Attachment #1: Type: text/plain, Size: 2375 bytes --] Hi Joerg, From: Joerg Roedel <joro@8bytes.org> Subject: Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Date: Mon, 23 Jan 2012 16:00:48 +0100 Message-ID: <20120123150048.GB6269@8bytes.org> > Hi, > > first, some questions about the GART on your platform. > > 1) How many GARTs are usually implemented? One GART per device or is > there a single GART covering all devices, or a mix of both? There's a single GART in the system which takes care of all devices. > 2) Are devices allowed to DMA outside of the remappable range or will > this fail? Fail. > > Besides that I think IOMMU-API is not yet fully ready for GART-like > drivers like this one. But I will merge it anyway to get things moving. > But please answer or fix my objections first. > > On Thu, Jan 05, 2012 at 09:11:48AM +0200, Hiroshi DOYU wrote: > > +static void gart_iommu_domain_destroy(struct iommu_domain *domain) > > +{ > > + struct gart_device *gart = domain->priv; > > + > > + spin_lock(&gart->client_lock); > > + if (!list_empty(&gart->client)) { > > + struct gart_client *c; > > + > > + list_for_each_entry(c, &gart->client, list) > > + dev_err(gart->dev, > > + "%s is still attached\n", dev_name(c->dev)); > > + } > > + spin_unlock(&gart->client_lock); > > gart needs a NULL check. When you create a domain and immediatly destroy > it without ever attaching a device this code will dereference a NULL > pointer. Fixed. > As a general improvement I suggest that you introduce a gart_domain > structure and store it in domain->priv (assigned in domain_init) instead > of using the hardware descriptor. > > > +static int gart_iommu_attach_dev(struct iommu_domain *domain, > > + struct device *dev) > > +{ > > + struct gart_device *gart; > > + struct gart_client *client, *c; > > + int err = 0; > > + > > + gart = dev_get_drvdata(dev->parent); > > + if (!gart) > > + return -EINVAL; > > + domain->priv = gart; > > What happens when devices behind different GARTs are assigned to the > same domain? domain->priv can only hold a pointer to one hardware GART. > This can be solved by a 'struct gart_domain' holding a linked list to > all gart_devices in this domain. As discussed in SMMU thread, I'll revisit the above multiple iommu device support later. Attached the update patch. [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #2: 0001-ARM-IOMMU-Tegra20-Add-iommu_ops-for-GART-driver.patch --] [-- Type: text/x-patch; name="0001-ARM-IOMMU-Tegra20-Add-iommu_ops-for-GART-driver.patch", Size: 14203 bytes --] From f4c1dbb0dfee79ecb4443777780470f6698044e9 Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU <hdoyu@nvidia.com> Date: Wed, 16 Nov 2011 17:36:37 +0200 Subject: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This patch implements struct iommu_ops for GART for the upper IOMMU API. This H/W module supports only single virtual address space(domain), and manages a single level 1-to-1 mapping H/W translation page table. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> --- drivers/iommu/Kconfig | 11 + drivers/iommu/Makefile | 1 + drivers/iommu/tegra-gart.c | 451 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 463 insertions(+), 0 deletions(-) create mode 100644 drivers/iommu/tegra-gart.c diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 6bea696..4562698 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -142,4 +142,15 @@ config OMAP_IOMMU_DEBUG Say N unless you know you need this. +config TEGRA_IOMMU_GART + bool "Tegra GART IOMMU Support" + depends on ARCH_TEGRA_2x_SOC + default y + select IOMMU_API + help + Enables support for remapping discontiguous physical memory + shared with the operating system into contiguous I/O virtual + space through the GART (Graphics Address Relocation Table) + hardware included on Tegra SoCs. + endif # IOMMU_SUPPORT diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 0e36b49..3238a31 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o +obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c new file mode 100644 index 0000000..f6be902 --- /dev/null +++ b/drivers/iommu/tegra-gart.c @@ -0,0 +1,451 @@ +/* + * IOMMU API for GART in Tegra20 + * + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define pr_fmt(fmt) "%s(): " fmt, __func__ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/mm.h> +#include <linux/list.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/iommu.h> + +#include <asm/cacheflush.h> + +/* bitmap of the page sizes currently supported */ +#define GART_IOMMU_PGSIZES (SZ_4K) + +#define GART_CONFIG 0x24 +#define GART_ENTRY_ADDR 0x28 +#define GART_ENTRY_DATA 0x2c +#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31) + +#define GART_PAGE_SHIFT 12 +#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT) +#define GART_PAGE_MASK \ + (~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID) + +struct gart_client { + struct device *dev; + struct list_head list; +}; + +struct gart_device { + void __iomem *regs; + u32 *savedata; + u32 page_count; /* total remappable size */ + dma_addr_t iovmm_base; /* offset to vmm_area */ + spinlock_t pte_lock; /* for pagetable */ + struct list_head client; + spinlock_t client_lock; /* for client list */ + struct device *dev; +}; + +static struct gart_device *gart_handle; /* unique for a system */ + +#define GART_PTE(_pfn) \ + (GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT)) + +/* + * Any interaction between any block on PPSB and a block on APB or AHB + * must have these read-back to ensure the APB/AHB bus transaction is + * complete before initiating activity on the PPSB block. + */ +#define FLUSH_GART_REGS(gart) ((void)readl((gart)->regs + GART_CONFIG)) + +#define for_each_gart_pte(gart, iova) \ + for (iova = gart->iovmm_base; \ + iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \ + iova += GART_PAGE_SIZE) + +static inline void gart_set_pte(struct gart_device *gart, + unsigned long offs, u32 pte) +{ + writel(offs, gart->regs + GART_ENTRY_ADDR); + writel(pte, gart->regs + GART_ENTRY_DATA); + + dev_dbg(gart->dev, "%s %08lx:%08x\n", + pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK); +} + +static inline unsigned long gart_read_pte(struct gart_device *gart, + unsigned long offs) +{ + unsigned long pte; + + writel(offs, gart->regs + GART_ENTRY_ADDR); + pte = readl(gart->regs + GART_ENTRY_DATA); + + return pte; +} + +static void do_gart_setup(struct gart_device *gart, const u32 *data) +{ + unsigned long iova; + + for_each_gart_pte(gart, iova) + gart_set_pte(gart, iova, data ? *(data++) : 0); + + writel(1, gart->regs + GART_CONFIG); + FLUSH_GART_REGS(gart); +} + +#ifdef DEBUG +static void gart_dump_table(struct gart_device *gart) +{ + unsigned long iova; + unsigned long flags; + + spin_lock_irqsave(&gart->pte_lock, flags); + for_each_gart_pte(gart, iova) { + unsigned long pte; + + pte = gart_read_pte(gart, iova); + + dev_dbg(gart->dev, "%s %08lx:%08lx\n", + (GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ", + iova, pte & GART_PAGE_MASK); + } + spin_unlock_irqrestore(&gart->pte_lock, flags); +} +#else +static inline void gart_dump_table(struct gart_device *gart) +{ +} +#endif + +static inline bool gart_iova_range_valid(struct gart_device *gart, + unsigned long iova, size_t bytes) +{ + unsigned long iova_start, iova_end, gart_start, gart_end; + + iova_start = iova; + iova_end = iova_start + bytes - 1; + gart_start = gart->iovmm_base; + gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1; + + if (iova_start < gart_start) + return false; + if (iova_end > gart_end) + return false; + return true; +} + +static int gart_iommu_attach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct gart_device *gart; + struct gart_client *client, *c; + int err = 0; + + gart = dev_get_drvdata(dev->parent); + if (!gart) + return -EINVAL; + domain->priv = gart; + + client = devm_kzalloc(gart->dev, sizeof(*c), GFP_KERNEL); + if (!client) + return -ENOMEM; + client->dev = dev; + + spin_lock(&gart->client_lock); + list_for_each_entry(c, &gart->client, list) { + if (c->dev == dev) { + dev_err(gart->dev, + "%s is already attached\n", dev_name(dev)); + err = -EINVAL; + goto fail; + } + } + list_add(&client->list, &gart->client); + spin_unlock(&gart->client_lock); + dev_dbg(gart->dev, "Attached %s\n", dev_name(dev)); + return 0; + +fail: + devm_kfree(gart->dev, client); + spin_unlock(&gart->client_lock); + return err; +} + +static void gart_iommu_detach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct gart_device *gart = domain->priv; + struct gart_client *c; + + spin_lock(&gart->client_lock); + + list_for_each_entry(c, &gart->client, list) { + if (c->dev == dev) { + list_del(&c->list); + devm_kfree(gart->dev, c); + dev_dbg(gart->dev, "Detached %s\n", dev_name(dev)); + goto out; + } + } + dev_err(gart->dev, "Couldn't find\n"); +out: + spin_unlock(&gart->client_lock); +} + +static int gart_iommu_domain_init(struct iommu_domain *domain) +{ + return 0; +} + +static void gart_iommu_domain_destroy(struct iommu_domain *domain) +{ + struct gart_device *gart = domain->priv; + + if (!gart) + return; + + spin_lock(&gart->client_lock); + if (!list_empty(&gart->client)) { + struct gart_client *c; + + list_for_each_entry(c, &gart->client, list) + gart_iommu_detach_dev(domain, c->dev); + } + spin_unlock(&gart->client_lock); + domain->priv = NULL; +} + +static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t pa, size_t bytes, int prot) +{ + struct gart_device *gart = domain->priv; + unsigned long flags; + unsigned long pfn; + + if (!gart_iova_range_valid(gart, iova, bytes)) + return -EINVAL; + + spin_lock_irqsave(&gart->pte_lock, flags); + pfn = __phys_to_pfn(pa); + if (!pfn_valid(pfn)) { + dev_err(gart->dev, "Invalid page: %08x\n", pa); + spin_unlock(&gart->pte_lock); + return -EINVAL; + } + gart_set_pte(gart, iova, GART_PTE(pfn)); + FLUSH_GART_REGS(gart); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova, + size_t bytes) +{ + struct gart_device *gart = domain->priv; + unsigned long flags; + + if (!gart_iova_range_valid(gart, iova, bytes)) + return -EINVAL; + + spin_lock_irqsave(&gart->pte_lock, flags); + gart_set_pte(gart, iova, 0); + FLUSH_GART_REGS(gart); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain, + unsigned long iova) +{ + struct gart_device *gart = domain->priv; + unsigned long pte; + phys_addr_t pa; + unsigned long flags; + + if (!gart_iova_range_valid(gart, iova, 0)) + return -EINVAL; + + spin_lock_irqsave(&gart->pte_lock, flags); + pte = gart_read_pte(gart, iova); + spin_unlock_irqrestore(&gart->pte_lock, flags); + + pa = (pte & GART_PAGE_MASK); + if (!pfn_valid(__phys_to_pfn(pa))) { + dev_err(gart->dev, "No entry for %08lx:%08x\n", iova, pa); + gart_dump_table(gart); + return -EINVAL; + } + return pa; +} + +static int gart_iommu_domain_has_cap(struct iommu_domain *domain, + unsigned long cap) +{ + return 0; +} + +static struct iommu_ops gart_iommu_ops = { + .domain_init = gart_iommu_domain_init, + .domain_destroy = gart_iommu_domain_destroy, + .attach_dev = gart_iommu_attach_dev, + .detach_dev = gart_iommu_detach_dev, + .map = gart_iommu_map, + .unmap = gart_iommu_unmap, + .iova_to_phys = gart_iommu_iova_to_phys, + .domain_has_cap = gart_iommu_domain_has_cap, + .pgsize_bitmap = GART_IOMMU_PGSIZES, +}; + +static int tegra_gart_suspend(struct device *dev) +{ + struct gart_device *gart = dev_get_drvdata(dev); + unsigned long iova; + u32 *data = gart->savedata; + unsigned long flags; + + spin_lock_irqsave(&gart->pte_lock, flags); + for_each_gart_pte(gart, iova) + *(data++) = gart_read_pte(gart, iova); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static int tegra_gart_resume(struct device *dev) +{ + struct gart_device *gart = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&gart->pte_lock, flags); + do_gart_setup(gart, gart->savedata); + spin_unlock_irqrestore(&gart->pte_lock, flags); + return 0; +} + +static int tegra_gart_probe(struct platform_device *pdev) +{ + struct gart_device *gart; + struct resource *res, *res_remap; + void __iomem *gart_regs; + int err; + struct device *dev = &pdev->dev; + + if (gart_handle) + return -EIO; + + BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT); + + /* the GART memory aperture is required */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res || !res_remap) { + dev_err(dev, "GART memory aperture expected\n"); + return -ENXIO; + } + + gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL); + if (!gart) { + dev_err(dev, "failed to allocate gart_device\n"); + return -ENOMEM; + } + + gart_regs = devm_ioremap(dev, res->start, resource_size(res)); + if (!gart_regs) { + dev_err(dev, "failed to remap GART registers\n"); + err = -ENXIO; + goto fail; + } + + gart->dev = &pdev->dev; + spin_lock_init(&gart->pte_lock); + spin_lock_init(&gart->client_lock); + INIT_LIST_HEAD(&gart->client); + gart->regs = gart_regs; + gart->iovmm_base = (dma_addr_t)res_remap->start; + gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT); + + gart->savedata = vmalloc(sizeof(u32) * gart->page_count); + if (!gart->savedata) { + dev_err(dev, "failed to allocate context save area\n"); + err = -ENOMEM; + goto fail; + } + + platform_set_drvdata(pdev, gart); + do_gart_setup(gart, NULL); + + gart_handle = gart; + return 0; + +fail: + if (gart_regs) + devm_iounmap(dev, gart_regs); + if (gart && gart->savedata) + vfree(gart->savedata); + devm_kfree(dev, gart); + return err; +} + +static int tegra_gart_remove(struct platform_device *pdev) +{ + struct gart_device *gart = platform_get_drvdata(pdev); + struct device *dev = gart->dev; + + writel(0, gart->regs + GART_CONFIG); + if (gart->savedata) + vfree(gart->savedata); + if (gart->regs) + devm_iounmap(dev, gart->regs); + devm_kfree(dev, gart); + gart_handle = NULL; + return 0; +} + +const struct dev_pm_ops tegra_gart_pm_ops = { + .suspend = tegra_gart_suspend, + .resume = tegra_gart_resume, +}; + +static struct platform_driver tegra_gart_driver = { + .probe = tegra_gart_probe, + .remove = tegra_gart_remove, + .driver = { + .owner = THIS_MODULE, + .name = "tegra-gart", + .pm = &tegra_gart_pm_ops, + }, +}; + +static int __devinit tegra_gart_init(void) +{ + bus_set_iommu(&platform_bus_type, &gart_iommu_ops); + return platform_driver_register(&tegra_gart_driver); +} + +static void __exit tegra_gart_exit(void) +{ + platform_driver_unregister(&tegra_gart_driver); +} + +subsys_initcall(tegra_gart_init); +module_exit(tegra_gart_exit); + +MODULE_DESCRIPTION("IOMMU API for GART in Tegra20"); +MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); +MODULE_LICENSE("GPL v2"); -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver 2012-01-25 7:40 ` Hiroshi Doyu @ 2012-01-26 11:58 ` joro 2012-01-26 14:45 ` Hiroshi Doyu 0 siblings, 1 reply; 25+ messages in thread From: joro @ 2012-01-26 11:58 UTC (permalink / raw) To: Hiroshi Doyu Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces On Wed, Jan 25, 2012 at 08:40:20AM +0100, Hiroshi Doyu wrote: > From: Hiroshi DOYU <hdoyu@nvidia.com> > Date: Wed, 16 Nov 2011 17:36:37 +0200 > Subject: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver > > Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This > patch implements struct iommu_ops for GART for the upper IOMMU API. > > This H/W module supports only single virtual address space(domain), > and manages a single level 1-to-1 mapping H/W translation page table. Thanks. Applied with a few minor changes and fixes. Please see below. > +config TEGRA_IOMMU_GART > + bool "Tegra GART IOMMU Support" > + depends on ARCH_TEGRA_2x_SOC > + default y I removed 'default y'. New drivers shouldn't be selected by default. > +static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova, > + phys_addr_t pa, size_t bytes, int prot) > +{ > + struct gart_device *gart = domain->priv; > + unsigned long flags; > + unsigned long pfn; > + > + if (!gart_iova_range_valid(gart, iova, bytes)) > + return -EINVAL; > + > + spin_lock_irqsave(&gart->pte_lock, flags); > + pfn = __phys_to_pfn(pa); > + if (!pfn_valid(pfn)) { > + dev_err(gart->dev, "Invalid page: %08x\n", pa); > + spin_unlock(&gart->pte_lock); Changed this to spin_unlock_irqrestore(). > + return -EINVAL; > + } > + gart_set_pte(gart, iova, GART_PTE(pfn)); > + FLUSH_GART_REGS(gart); > + spin_unlock_irqrestore(&gart->pte_lock, flags); > + return 0; > +} > + > +static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova, > + size_t bytes) > +{ > + struct gart_device *gart = domain->priv; > + unsigned long flags; > + > + if (!gart_iova_range_valid(gart, iova, bytes)) > + return -EINVAL; Return 0 here instead of -EINVAL. Size_t is unsigned and the unmap path returns 0 on failure. ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver 2012-01-26 11:58 ` joro @ 2012-01-26 14:45 ` Hiroshi Doyu 0 siblings, 0 replies; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-26 14:45 UTC (permalink / raw) To: joro Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces On Thu, 26 Jan 2012 12:58:13 +0100 "joro@8bytes.org" <joro@8bytes.org> wrote: > On Wed, Jan 25, 2012 at 08:40:20AM +0100, Hiroshi Doyu wrote: > > From: Hiroshi DOYU <hdoyu@nvidia.com> > > Date: Wed, 16 Nov 2011 17:36:37 +0200 > > Subject: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver > > > > Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This > > patch implements struct iommu_ops for GART for the upper IOMMU API. > > > > This H/W module supports only single virtual address space(domain), > > and manages a single level 1-to-1 mapping H/W translation page table. > > Thanks. Applied with a few minor changes and fixes. Please see below. All fixes are valid. Thanks. > > +config TEGRA_IOMMU_GART > > + bool "Tegra GART IOMMU Support" > > + depends on ARCH_TEGRA_2x_SOC > > + default y > > I removed 'default y'. New drivers shouldn't be selected by default. > > > +static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova, > > + phys_addr_t pa, size_t bytes, int prot) > > +{ > > + struct gart_device *gart = domain->priv; > > + unsigned long flags; > > + unsigned long pfn; > > + > > + if (!gart_iova_range_valid(gart, iova, bytes)) > > + return -EINVAL; > > + > > + spin_lock_irqsave(&gart->pte_lock, flags); > > + pfn = __phys_to_pfn(pa); > > + if (!pfn_valid(pfn)) { > > + dev_err(gart->dev, "Invalid page: %08x\n", pa); > > + spin_unlock(&gart->pte_lock); > > Changed this to spin_unlock_irqrestore(). > > > + return -EINVAL; > > + } > > + gart_set_pte(gart, iova, GART_PTE(pfn)); > > + FLUSH_GART_REGS(gart); > > + spin_unlock_irqrestore(&gart->pte_lock, flags); > > + return 0; > > +} > > + > > +static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova, > > + size_t bytes) > > +{ > > + struct gart_device *gart = domain->priv; > > + unsigned long flags; > > + > > + if (!gart_iova_range_valid(gart, iova, bytes)) > > + return -EINVAL; > > Return 0 here instead of -EINVAL. Size_t is unsigned and the unmap path > returns 0 on failure. > ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-05 7:11 [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi DOYU 2012-01-05 7:11 ` [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Hiroshi DOYU @ 2012-01-05 7:11 ` Hiroshi DOYU 2012-01-23 15:43 ` Joerg Roedel 2012-01-05 7:17 ` [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi Doyu 2 siblings, 1 reply; 25+ messages in thread From: Hiroshi DOYU @ 2012-01-05 7:11 UTC (permalink / raw) To: Hiroshi DOYU Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit). This patch implements struct iommu_ops for SMMU for the upper IOMMU API. This H/W module supports multiple virtual address spaces(domain x4), and manages 2 level H/W translation pagetable. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> --- arch/arm/mach-tegra/include/mach/smmu.h | 63 ++ drivers/iommu/Kconfig | 11 + drivers/iommu/Makefile | 1 + drivers/iommu/tegra-smmu.c | 1026 +++++++++++++++++++++++++++++++ 4 files changed, 1101 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-tegra/include/mach/smmu.h create mode 100644 drivers/iommu/tegra-smmu.c diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h new file mode 100644 index 0000000..dad403a --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/smmu.h @@ -0,0 +1,63 @@ +/* + * IOMMU API for SMMU in Tegra30 + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef MACH_SMMU_H +#define MACH_SMMU_H + +enum smmu_hwgrp { + HWGRP_AFI, + HWGRP_AVPC, + HWGRP_DC, + HWGRP_DCB, + HWGRP_EPP, + HWGRP_G2, + HWGRP_HC, + HWGRP_HDA, + HWGRP_ISP, + HWGRP_MPE, + HWGRP_NV, + HWGRP_NV2, + HWGRP_PPCS, + HWGRP_SATA, + HWGRP_VDE, + HWGRP_VI, + + HWGRP_COUNT, + + HWGRP_END = ~0, +}; + +#define HWG_AFI (1 << HWGRP_AFI) +#define HWG_AVPC (1 << HWGRP_AVPC) +#define HWG_DC (1 << HWGRP_DC) +#define HWG_DCB (1 << HWGRP_DCB) +#define HWG_EPP (1 << HWGRP_EPP) +#define HWG_G2 (1 << HWGRP_G2) +#define HWG_HC (1 << HWGRP_HC) +#define HWG_HDA (1 << HWGRP_HDA) +#define HWG_ISP (1 << HWGRP_ISP) +#define HWG_MPE (1 << HWGRP_MPE) +#define HWG_NV (1 << HWGRP_NV) +#define HWG_NV2 (1 << HWGRP_NV2) +#define HWG_PPCS (1 << HWGRP_PPCS) +#define HWG_SATA (1 << HWGRP_SATA) +#define HWG_VDE (1 << HWGRP_VDE) +#define HWG_VI (1 << HWGRP_VI) + +#endif /* MACH_SMMU_H */ diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 4562698..4b3d616 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -153,4 +153,15 @@ config TEGRA_IOMMU_GART space through the GART (Graphics Address Relocation Table) hardware included on Tegra SoCs. +config TEGRA_IOMMU_SMMU + bool "Tegra SMMU IOMMU Support" + depends on ARCH_TEGRA_3x_SOC + default y + select IOMMU_API + help + Enables support for remapping discontiguous physical memory + shared with the operating system into contiguous I/O virtual + space through the SMMU (System Memory Management Unit) + hardware included on Tegra SoCs. + endif # IOMMU_SUPPORT diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 3238a31..7ad7a3b 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o +obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c new file mode 100644 index 0000000..7deea32 --- /dev/null +++ b/drivers/iommu/tegra-smmu.c @@ -0,0 +1,1026 @@ +/* + * IOMMU API for SMMU in Tegra30 + * + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define pr_fmt(fmt) "%s(): " fmt, __func__ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/mm.h> +#include <linux/pagemap.h> +#include <linux/device.h> +#include <linux/sched.h> +#include <linux/iommu.h> +#include <linux/io.h> + +#include <asm/page.h> +#include <asm/cacheflush.h> + +#include <mach/iomap.h> +#include <mach/smmu.h> + +/* bitmap of the page sizes currently supported */ +#define SMMU_IOMMU_PGSIZES (SZ_4K | SZ_4M) + +#define SMMU_CONFIG 0x10 +#define SMMU_CONFIG_DISABLE 0 +#define SMMU_CONFIG_ENABLE 1 + +#define SMMU_TLB_CONFIG 0x14 +#define SMMU_TLB_CONFIG_STATS__MASK (1 << 31) +#define SMMU_TLB_CONFIG_STATS__ENABLE (1 << 31) +#define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29) +#define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10 +#define SMMU_TLB_CONFIG_RESET_VAL 0x20000010 + +#define SMMU_PTC_CONFIG 0x18 +#define SMMU_PTC_CONFIG_STATS__MASK (1 << 31) +#define SMMU_PTC_CONFIG_STATS__ENABLE (1 << 31) +#define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29) +#define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f +#define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f + +#define SMMU_PTB_ASID 0x1c +#define SMMU_PTB_ASID_CURRENT_SHIFT 0 + +#define SMMU_PTB_DATA 0x20 +#define SMMU_PTB_DATA_RESET_VAL 0 +#define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29 +#define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30 +#define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31 + +#define SMMU_TLB_FLUSH 0x30 +#define SMMU_TLB_FLUSH_VA_MATCH_ALL 0 +#define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2 +#define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3 +#define SMMU_TLB_FLUSH_ASID_SHIFT 29 +#define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0 +#define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1 +#define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31 + +#define SMMU_PTC_FLUSH 0x34 +#define SMMU_PTC_FLUSH_TYPE_ALL 0 +#define SMMU_PTC_FLUSH_TYPE_ADR 1 +#define SMMU_PTC_FLUSH_ADR_SHIFT 4 + +#define SMMU_ASID_SECURITY 0x38 + +#define SMMU_STATS_TLB_HIT_COUNT 0x1f0 +#define SMMU_STATS_TLB_MISS_COUNT 0x1f4 +#define SMMU_STATS_PTC_HIT_COUNT 0x1f8 +#define SMMU_STATS_PTC_MISS_COUNT 0x1fc + +#define SMMU_TRANSLATION_ENABLE_0 0x228 +#define SMMU_TRANSLATION_ENABLE_1 0x22c +#define SMMU_TRANSLATION_ENABLE_2 0x230 + +#define SMMU_AFI_ASID 0x238 /* PCIE */ +#define SMMU_AVPC_ASID 0x23c /* AVP */ +#define SMMU_DC_ASID 0x240 /* Display controller */ +#define SMMU_DCB_ASID 0x244 /* Display controller B */ +#define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */ +#define SMMU_G2_ASID 0x24c /* 2D engine */ +#define SMMU_HC_ASID 0x250 /* Host1x */ +#define SMMU_HDA_ASID 0x254 /* High-def audio */ +#define SMMU_ISP_ASID 0x258 /* Image signal processor */ +#define SMMU_MPE_ASID 0x264 /* MPEG encoder */ +#define SMMU_NV_ASID 0x268 /* (3D) */ +#define SMMU_NV2_ASID 0x26c /* (3D) */ +#define SMMU_PPCS_ASID 0x270 /* AHB */ +#define SMMU_SATA_ASID 0x278 /* SATA */ +#define SMMU_VDE_ASID 0x27c /* Video decoder */ +#define SMMU_VI_ASID 0x280 /* Video input */ + +#define SMMU_PDE_NEXT_SHIFT 28 + +/* AHB Arbiter Registers */ +#define AHB_XBAR_CTRL 0xe0 +#define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE 1 +#define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT 17 + +#define SMMU_NUM_ASIDS 4 +#define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000 +#define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */ +#define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000 +#define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */ +#define SMMU_TLB_FLUSH_VA(iova, which) \ + ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \ + SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \ + SMMU_TLB_FLUSH_VA_MATCH_##which) +#define SMMU_PTB_ASID_CUR(n) \ + ((n) << SMMU_PTB_ASID_CURRENT_SHIFT) +#define SMMU_TLB_FLUSH_ASID_MATCH_disable \ + (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \ + SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) +#define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \ + (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \ + SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) + +#define SMMU_PAGE_SHIFT 12 +#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT) + +#define SMMU_PDIR_COUNT 1024 +#define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT) +#define SMMU_PTBL_COUNT 1024 +#define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT) +#define SMMU_PDIR_SHIFT 12 +#define SMMU_PDE_SHIFT 12 +#define SMMU_PTE_SHIFT 12 +#define SMMU_PFN_MASK 0x000fffff + +#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12) +#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22) +#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22) + +#define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT) +#define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT) +#define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT) +#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT) +#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE) + +#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE) + +#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE) +#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT) +#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR) + +#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE) +#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR) + +#define SMMU_MK_PDIR(page, attr) \ + ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr)) +#define SMMU_MK_PDE(page, attr) \ + (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr)) +#define SMMU_EX_PTBL_PAGE(pde) \ + pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK) +#define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr)) + +#define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31)) +#define SMMU_ASID_DISABLE 0 +#define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0)) + +#define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1) +#define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0) +#define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1) +#define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0) + +#define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID + +static const u32 smmu_hwgrp_asid_reg[] = { + HWGRP_INIT(AFI), + HWGRP_INIT(AVPC), + HWGRP_INIT(DC), + HWGRP_INIT(DCB), + HWGRP_INIT(EPP), + HWGRP_INIT(G2), + HWGRP_INIT(HC), + HWGRP_INIT(HDA), + HWGRP_INIT(ISP), + HWGRP_INIT(MPE), + HWGRP_INIT(NV), + HWGRP_INIT(NV2), + HWGRP_INIT(PPCS), + HWGRP_INIT(SATA), + HWGRP_INIT(VDE), + HWGRP_INIT(VI), +}; +#define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x]) + +/* + * Per client for address space + */ +struct smmu_client { + struct device *dev; + struct list_head list; + struct smmu_as *as; + u32 hwgrp; +}; + +/* + * Per address space + */ +struct smmu_as { + struct smmu_device *smmu; /* back pointer to container */ + unsigned int asid; + spinlock_t lock; /* for pagetable */ + struct page *pdir_page; + unsigned long pdir_attr; + unsigned long pde_attr; + unsigned long pte_attr; + unsigned int *pte_count; + + struct list_head client; + spinlock_t client_lock; /* for client list */ +}; + +/* + * Per SMMU device - IOMMU device + */ +struct smmu_device { + void __iomem *regs, *regs_ahbarb; + unsigned long iovmm_base; /* remappable base address */ + unsigned long page_count; /* total remappable size */ + spinlock_t lock; + char *name; + struct device *dev; + int num_as; + struct smmu_as *as; /* Run-time allocated array */ + struct page *avp_vector_page; /* dummy page shared by all AS's */ + + /* + * Register image savers for suspend/resume + */ + unsigned long translation_enable_0; + unsigned long translation_enable_1; + unsigned long translation_enable_2; + unsigned long asid_security; +}; + +static struct smmu_device *smmu_handle; /* unique for a system */ + +/* + * SMMU/AHB register accessors + */ +static inline u32 smmu_read(struct smmu_device *smmu, size_t offs) +{ + return readl(smmu->regs + offs); +} +static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) +{ + writel(val, smmu->regs + offs); +} + +static inline u32 ahb_read(struct smmu_device *smmu, size_t offs) +{ + return readl(smmu->regs_ahbarb + offs); +} +static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs) +{ + writel(val, smmu->regs_ahbarb + offs); +} + +#define VA_PAGE_TO_PA(va, page) \ + (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK)) + +#define FLUSH_CPU_DCACHE(va, page, size) \ + do { \ + unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \ + __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \ + outer_flush_range(_pa_, _pa_+(size_t)(size)); \ + } while (0) + +/* + * Any interaction between any block on PPSB and a block on APB or AHB + * must have these read-back barriers to ensure the APB/AHB bus + * transaction is complete before initiating activity on the PPSB + * block. + */ +#define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) + +#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data) + +static int __smmu_client_set_hwgrp(struct smmu_client *c, + unsigned long map, int on) +{ + int i; + struct smmu_as *as = c->as; + u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid); + struct smmu_device *smmu = as->smmu; + + WARN_ON(!on && map); + if (on && !map) + return -EINVAL; + if (!on) + map = smmu_client_hwgrp(c); + + for_each_set_bit(i, &map, HWGRP_COUNT) { + offs = HWGRP_ASID_REG(i); + val = smmu_read(smmu, offs); + if (on) { + if (WARN_ON(val & mask)) + goto err_hw_busy; + val |= mask; + } else { + WARN_ON((val & mask) == mask); + val &= ~mask; + } + smmu_write(smmu, val, offs); + } + FLUSH_SMMU_REGS(smmu); + c->hwgrp = map; + return 0; + +err_hw_busy: + for_each_set_bit(i, &map, HWGRP_COUNT) { + offs = HWGRP_ASID_REG(i); + val = smmu_read(smmu, offs); + val &= ~mask; + smmu_write(smmu, val, offs); + } + return -EBUSY; +} + +static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on) +{ + u32 val; + unsigned long flags; + struct smmu_as *as = c->as; + struct smmu_device *smmu = as->smmu; + + spin_lock_irqsave(&smmu->lock, flags); + val = __smmu_client_set_hwgrp(c, map, on); + spin_unlock_irqrestore(&smmu->lock, flags); + return val; +} + +/* + * Flush all TLB entries and all PTC entries + * Caller must lock smmu + */ +static void smmu_flush_regs(struct smmu_device *smmu, int enable) +{ + u32 val; + + smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); + FLUSH_SMMU_REGS(smmu); + val = SMMU_TLB_FLUSH_VA_MATCH_ALL | + SMMU_TLB_FLUSH_ASID_MATCH_disable; + smmu_write(smmu, val, SMMU_TLB_FLUSH); + + if (enable) + smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); + FLUSH_SMMU_REGS(smmu); +} + +static void smmu_setup_regs(struct smmu_device *smmu) +{ + int i; + u32 val; + + for (i = 0; i < smmu->num_as; i++) { + struct smmu_as *as = &smmu->as[i]; + struct smmu_client *c; + + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); + val = as->pdir_page ? + SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) : + SMMU_PTB_DATA_RESET_VAL; + smmu_write(smmu, val, SMMU_PTB_DATA); + + list_for_each_entry(c, &as->client, list) + __smmu_client_set_hwgrp(c, c->hwgrp, 1); + } + + smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0); + smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1); + smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2); + smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY); + smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_TLB_CONFIG); + smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_PTC_CONFIG); + + smmu_flush_regs(smmu, 1); + + val = ahb_read(smmu, AHB_XBAR_CTRL); + val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE << + AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT; + ahb_write(smmu, val, AHB_XBAR_CTRL); +} + +static void flush_ptc_and_tlb(struct smmu_device *smmu, + struct smmu_as *as, dma_addr_t iova, + unsigned long *pte, struct page *page, int is_pde) +{ + u32 val; + unsigned long tlb_flush_va = is_pde + ? SMMU_TLB_FLUSH_VA(iova, SECTION) + : SMMU_TLB_FLUSH_VA(iova, GROUP); + + val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page); + smmu_write(smmu, val, SMMU_PTC_FLUSH); + FLUSH_SMMU_REGS(smmu); + val = tlb_flush_va | + SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + smmu_write(smmu, val, SMMU_TLB_FLUSH); + FLUSH_SMMU_REGS(smmu); +} + +static void free_ptbl(struct smmu_as *as, dma_addr_t iova) +{ + unsigned long pdn = SMMU_ADDR_TO_PDN(iova); + unsigned long *pdir = (unsigned long *)page_address(as->pdir_page); + + if (pdir[pdn] != _PDE_VACANT(pdn)) { + dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn); + + ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn])); + __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn])); + pdir[pdn] = _PDE_VACANT(pdn); + FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); + flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], + as->pdir_page, 1); + } +} + +static void free_pdir(struct smmu_as *as) +{ + unsigned addr; + int count; + struct device *dev = as->smmu->dev; + + if (!as->pdir_page) + return; + + addr = as->smmu->iovmm_base; + count = as->smmu->page_count; + while (count-- > 0) { + free_ptbl(as, addr); + addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT; + } + ClearPageReserved(as->pdir_page); + __free_page(as->pdir_page); + as->pdir_page = NULL; + devm_kfree(dev, as->pte_count); + as->pte_count = NULL; +} + +/* + * Maps PTBL for given iova and returns the PTE address + * Caller must unmap the mapped PTBL returned in *ptbl_page_p + */ +static unsigned long *locate_pte(struct smmu_as *as, + dma_addr_t iova, bool allocate, + struct page **ptbl_page_p, + unsigned int **count) +{ + unsigned long ptn = SMMU_ADDR_TO_PFN(iova); + unsigned long pdn = SMMU_ADDR_TO_PDN(iova); + unsigned long *pdir = page_address(as->pdir_page); + unsigned long *ptbl; + + if (pdir[pdn] != _PDE_VACANT(pdn)) { + /* Mapped entry table already exists */ + *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]); + ptbl = page_address(*ptbl_page_p); + } else if (!allocate) { + return NULL; + } else { + int pn; + unsigned long addr = SMMU_PDN_TO_ADDR(pdn); + + /* Vacant - allocate a new page table */ + dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn); + + *ptbl_page_p = alloc_page(GFP_ATOMIC); + if (!*ptbl_page_p) { + dev_err(as->smmu->dev, + "failed to allocate smmu_device page table\n"); + return NULL; + } + SetPageReserved(*ptbl_page_p); + ptbl = (unsigned long *)page_address(*ptbl_page_p); + for (pn = 0; pn < SMMU_PTBL_COUNT; + pn++, addr += SMMU_PAGE_SIZE) { + ptbl[pn] = _PTE_VACANT(addr); + } + FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE); + pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p, + as->pde_attr | _PDE_NEXT); + FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); + flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], + as->pdir_page, 1); + } + *count = &as->pte_count[pdn]; + + return &ptbl[ptn % SMMU_PTBL_COUNT]; +} + +#ifdef CONFIG_SMMU_SIG_DEBUG +static void put_signature(struct smmu_as *as, + dma_addr_t iova, unsigned long pfn) +{ + struct page *page; + unsigned long *vaddr; + + page = pfn_to_page(pfn); + vaddr = page_address(page); + if (!vaddr) + return; + + vaddr[0] = iova; + vaddr[1] = pfn << PAGE_SHIFT; + FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2); +} +#else +static inline void put_signature(struct smmu_as *as, + unsigned long addr, unsigned long pfn) +{ +} +#endif + +/* + * Caller must lock/unlock as + */ +static int alloc_pdir(struct smmu_as *as) +{ + unsigned long *pdir; + int pdn; + u32 val; + struct smmu_device *smmu = as->smmu; + + if (as->pdir_page) + return 0; + + as->pte_count = devm_kzalloc(smmu->dev, + sizeof(as->pte_count[0]) * SMMU_PDIR_COUNT, GFP_KERNEL); + if (!as->pte_count) { + dev_err(smmu->dev, + "failed to allocate smmu_device PTE cunters\n"); + return -ENOMEM; + } + as->pdir_page = alloc_page(GFP_KERNEL | __GFP_DMA); + if (!as->pdir_page) { + dev_err(smmu->dev, + "failed to allocate smmu_device page directory\n"); + devm_kfree(smmu->dev, as->pte_count); + as->pte_count = NULL; + return -ENOMEM; + } + SetPageReserved(as->pdir_page); + pdir = page_address(as->pdir_page); + + for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) + pdir[pdn] = _PDE_VACANT(pdn); + FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE); + val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page); + smmu_write(smmu, val, SMMU_PTC_FLUSH); + FLUSH_SMMU_REGS(as->smmu); + val = SMMU_TLB_FLUSH_VA_MATCH_ALL | + SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + smmu_write(smmu, val, SMMU_TLB_FLUSH); + FLUSH_SMMU_REGS(as->smmu); + + return 0; +} + +static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova) +{ + unsigned long *pte; + struct page *page; + unsigned int *count; + + pte = locate_pte(as, iova, false, &page, &count); + if (WARN_ON(!pte)) + return; + + if (WARN_ON(*pte == _PTE_VACANT(iova))) + return; + + *pte = _PTE_VACANT(iova); + FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); + flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0); + if (!--(*count)) { + free_ptbl(as, iova); + smmu_flush_regs(as->smmu, 0); + } +} + +static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova, + unsigned long pfn) +{ + struct smmu_device *smmu = as->smmu; + unsigned long *pte; + unsigned int *count; + struct page *page; + + pte = locate_pte(as, iova, true, &page, &count); + if (WARN_ON(!pte)) + return; + + if (*pte == _PTE_VACANT(iova)) + (*count)++; + *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr); + if (unlikely((*pte == _PTE_VACANT(iova)))) + (*count)--; + FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); + flush_ptc_and_tlb(smmu, as, iova, pte, page, 0); + put_signature(as, iova, pfn); +} + +static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t pa, size_t bytes, int prot) +{ + struct smmu_as *as = domain->priv; + unsigned long pfn = __phys_to_pfn(pa); + unsigned long flags; + + dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa); + + if (!pfn_valid(pfn)) + return -ENOMEM; + + spin_lock_irqsave(&as->lock, flags); + __smmu_iommu_map_pfn(as, iova, pfn); + spin_unlock_irqrestore(&as->lock, flags); + return 0; +} + +static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova, + size_t bytes) +{ + struct smmu_as *as = domain->priv; + unsigned long flags; + + dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova); + + spin_lock_irqsave(&as->lock, flags); + __smmu_iommu_unmap(as, iova); + spin_unlock_irqrestore(&as->lock, flags); + return SMMU_PAGE_SIZE; +} + +static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain, + unsigned long iova) +{ + struct smmu_as *as = domain->priv; + unsigned long *pte; + unsigned int *count; + struct page *page; + unsigned long pfn; + unsigned long flags; + + spin_lock_irqsave(&as->lock, flags); + + pte = locate_pte(as, iova, true, &page, &count); + pfn = *pte & SMMU_PFN_MASK; + WARN_ON(!pfn_valid(pfn)); + dev_dbg(as->smmu->dev, + "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid); + + spin_unlock_irqrestore(&as->lock, flags); + return PFN_PHYS(pfn); +} + +static int smmu_iommu_domain_has_cap(struct iommu_domain *domain, + unsigned long cap) +{ + return 0; +} + +static int smmu_iommu_domain_init(struct iommu_domain *domain) +{ + int i; + unsigned long flags; + struct smmu_as *as; + struct smmu_device *smmu = smmu_handle; + + /* Look for a free AS with lock held */ + for (i = 0; i < smmu->num_as; i++) { + struct smmu_as *tmp = &smmu->as[i]; + + spin_lock_irqsave(&tmp->lock, flags); + if (!tmp->pdir_page) { + as = tmp; + goto found; + } + spin_unlock_irqrestore(&tmp->lock, flags); + } + dev_err(smmu->dev, "no free AS\n"); + return -ENODEV; + +found: + if (alloc_pdir(as) < 0) + goto err_alloc_pdir; + + spin_lock(&smmu->lock); + + /* Update PDIR register */ + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); + smmu_write(smmu, + SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA); + FLUSH_SMMU_REGS(smmu); + + spin_unlock(&smmu->lock); + + spin_unlock_irqrestore(&as->lock, flags); + domain->priv = as; + dev_dbg(smmu->dev, "smmu_as@%p\n", as); + return 0; + +err_alloc_pdir: + spin_unlock_irqrestore(&as->lock, flags); + return -ENODEV; +} + +static void smmu_iommu_domain_destroy(struct iommu_domain *domain) +{ + struct smmu_as *as = domain->priv; + struct smmu_device *smmu = as->smmu; + unsigned long flags; + + spin_lock_irqsave(&as->lock, flags); + + if (as->pdir_page) { + spin_lock(&smmu->lock); + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); + smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA); + FLUSH_SMMU_REGS(smmu); + spin_unlock(&smmu->lock); + + free_pdir(as); + } + + if (!list_empty(&as->client)) { + struct smmu_client *c; + + list_for_each_entry(c, &as->client, list) + dev_err(smmu->dev, + "%s is still attached\n", dev_name(c->dev)); + } + + spin_unlock_irqrestore(&as->lock, flags); + + domain->priv = NULL; + dev_dbg(smmu->dev, "smmu_as@%p\n", as); +} + +static int smmu_iommu_attach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct smmu_as *as = domain->priv; + struct smmu_device *smmu = as->smmu; + struct smmu_client *client, *c; + u32 map; + int err; + + client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL); + if (!client) + return -ENOMEM; + client->dev = dev; + client->as = as; + map = (unsigned long)dev->platform_data; + if (!map) + return -EINVAL; + + err = smmu_client_enable_hwgrp(client, map); + if (err) + goto err_hwgrp; + + spin_lock(&as->client_lock); + list_for_each_entry(c, &as->client, list) { + if (c->dev == dev) { + dev_err(smmu->dev, + "%s is already attached\n", dev_name(c->dev)); + err = -EINVAL; + goto err_client; + } + } + list_add(&client->list, &as->client); + spin_unlock(&as->client_lock); + + /* + * Reserve "page zero" for AVP vectors using a common dummy + * page. + */ + if (map & HWG_AVPC) { + struct page *page; + + page = as->smmu->avp_vector_page; + __smmu_iommu_map_pfn(as, 0, page_to_pfn(page)); + + pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n"); + } + + dev_dbg(smmu->dev, "%s is attached\n", dev_name(c->dev)); + return 0; + +err_client: + smmu_client_disable_hwgrp(client); + spin_unlock(&as->client_lock); +err_hwgrp: + devm_kfree(smmu->dev, client); + return err; +} + +static void smmu_iommu_detach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct smmu_as *as = domain->priv; + struct smmu_device *smmu = as->smmu; + struct smmu_client *c; + + spin_lock(&as->client_lock); + + list_for_each_entry(c, &as->client, list) { + if (c->dev == dev) { + smmu_client_disable_hwgrp(c); + list_del(&c->list); + devm_kfree(smmu->dev, c); + c->as = NULL; + dev_dbg(smmu->dev, + "%s is detached\n", dev_name(c->dev)); + goto out; + } + } + dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev)); +out: + spin_unlock(&as->client_lock); +} + +static struct iommu_ops smmu_iommu_ops = { + .domain_init = smmu_iommu_domain_init, + .domain_destroy = smmu_iommu_domain_destroy, + .attach_dev = smmu_iommu_attach_dev, + .detach_dev = smmu_iommu_detach_dev, + .map = smmu_iommu_map, + .unmap = smmu_iommu_unmap, + .iova_to_phys = smmu_iommu_iova_to_phys, + .domain_has_cap = smmu_iommu_domain_has_cap, + .pgsize_bitmap = SMMU_IOMMU_PGSIZES, +}; + +static int tegra_smmu_suspend(struct device *dev) +{ + struct smmu_device *smmu = dev_get_drvdata(dev); + + smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0); + smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1); + smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2); + smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY); + return 0; +} + +static int tegra_smmu_resume(struct device *dev) +{ + struct smmu_device *smmu = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&smmu->lock, flags); + smmu_setup_regs(smmu); + spin_unlock_irqrestore(&smmu->lock, flags); + return 0; +} + +static int tegra_smmu_probe(struct platform_device *pdev) +{ + struct smmu_device *smmu; + struct resource *regs, *regs2, *window; + struct device *dev = &pdev->dev; + int i, err = 0; + + BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT); + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); + window = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!regs || !regs2 || !window) { + dev_err(dev, "No SMMU resources\n"); + return -ENODEV; + } + + smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); + if (!smmu) { + dev_err(dev, "failed to allocate smmu_device\n"); + return -ENOMEM; + } + + smmu->dev = dev; + smmu->num_as = SMMU_NUM_ASIDS; + smmu->iovmm_base = (unsigned long)window->start; + smmu->page_count = resource_size(window) >> SMMU_PAGE_SHIFT; + smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs)); + smmu->regs_ahbarb = devm_ioremap(dev, regs2->start, + resource_size(regs2)); + if (!smmu->regs || !smmu->regs_ahbarb) { + dev_err(dev, "failed to remap SMMU registers\n"); + err = -ENXIO; + goto fail; + } + + smmu->translation_enable_0 = ~0; + smmu->translation_enable_1 = ~0; + smmu->translation_enable_2 = ~0; + smmu->asid_security = 0; + + smmu->as = devm_kzalloc(dev, + sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL); + if (!smmu->as) { + dev_err(dev, "failed to allocate smmu_as\n"); + err = -ENOMEM; + goto fail; + } + + for (i = 0; i < smmu->num_as; i++) { + struct smmu_as *as = &smmu->as[i]; + + as->smmu = smmu; + as->asid = i; + as->pdir_attr = _PDIR_ATTR; + as->pde_attr = _PDE_ATTR; + as->pte_attr = _PTE_ATTR; + + spin_lock_init(&as->lock); + INIT_LIST_HEAD(&as->client); + } + spin_lock_init(&smmu->lock); + smmu_setup_regs(smmu); + platform_set_drvdata(pdev, smmu); + smmu_handle = smmu; + + smmu->avp_vector_page = alloc_page(GFP_KERNEL); + if (!smmu->avp_vector_page) + goto fail; + return 0; + +fail: + if (smmu->avp_vector_page) + __free_page(smmu->avp_vector_page); + if (smmu->regs) + devm_iounmap(dev, smmu->regs); + if (smmu->regs_ahbarb) + devm_iounmap(dev, smmu->regs_ahbarb); + if (smmu && smmu->as) { + for (i = 0; i < smmu->num_as; i++) { + if (smmu->as[i].pdir_page) { + ClearPageReserved(smmu->as[i].pdir_page); + __free_page(smmu->as[i].pdir_page); + } + } + devm_kfree(dev, smmu->as); + } + devm_kfree(dev, smmu); + return err; +} + +static int tegra_smmu_remove(struct platform_device *pdev) +{ + struct smmu_device *smmu = platform_get_drvdata(pdev); + struct device *dev = smmu->dev; + + smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG); + platform_set_drvdata(pdev, NULL); + if (smmu->as) { + int i; + + for (i = 0; i < smmu->num_as; i++) + free_pdir(&smmu->as[i]); + devm_kfree(dev, smmu->as); + } + if (smmu->avp_vector_page) + __free_page(smmu->avp_vector_page); + if (smmu->regs) + devm_iounmap(dev, smmu->regs); + if (smmu->regs_ahbarb) + devm_iounmap(dev, smmu->regs_ahbarb); + devm_kfree(dev, smmu); + smmu_handle = NULL; + return 0; +} + +const struct dev_pm_ops tegra_smmu_pm_ops = { + .suspend = tegra_smmu_suspend, + .resume = tegra_smmu_resume, +}; + +static struct platform_driver tegra_smmu_driver = { + .probe = tegra_smmu_probe, + .remove = tegra_smmu_remove, + .driver = { + .owner = THIS_MODULE, + .name = "tegra-smmu", + .pm = &tegra_smmu_pm_ops, + }, +}; + +static int __devinit tegra_smmu_init(void) +{ + bus_set_iommu(&platform_bus_type, &smmu_iommu_ops); + return platform_driver_register(&tegra_smmu_driver); +} + +static void __exit tegra_smmu_exit(void) +{ + platform_driver_unregister(&tegra_smmu_driver); +} + +subsys_initcall(tegra_smmu_init); +module_exit(tegra_smmu_exit); -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-05 7:11 ` [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Hiroshi DOYU @ 2012-01-23 15:43 ` Joerg Roedel 2012-01-24 9:57 ` Hiroshi Doyu 2012-01-24 13:41 ` Hiroshi Doyu 0 siblings, 2 replies; 25+ messages in thread From: Joerg Roedel @ 2012-01-23 15:43 UTC (permalink / raw) To: Hiroshi DOYU Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces Hi, please see my comments inline. When you fix these issues I think the driver is ready for merging. On Thu, Jan 05, 2012 at 09:11:49AM +0200, Hiroshi DOYU wrote: > +static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova, > + phys_addr_t pa, size_t bytes, int prot) > +{ > + struct smmu_as *as = domain->priv; > + unsigned long pfn = __phys_to_pfn(pa); > + unsigned long flags; > + > + dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa); > + > + if (!pfn_valid(pfn)) > + return -ENOMEM; > + > + spin_lock_irqsave(&as->lock, flags); > + __smmu_iommu_map_pfn(as, iova, pfn); > + spin_unlock_irqrestore(&as->lock, flags); > + return 0; Why do you completly ignore the size parameter in this function (and in the unmap part below)? According to the page-sizes you export to the generic layer size can be 4k or 4M. You need to take care of that in this function. > +static void smmu_iommu_domain_destroy(struct iommu_domain *domain) > +{ > + struct smmu_as *as = domain->priv; > + struct smmu_device *smmu = as->smmu; > + unsigned long flags; > + > + spin_lock_irqsave(&as->lock, flags); > + > + if (as->pdir_page) { > + spin_lock(&smmu->lock); > + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); > + smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA); > + FLUSH_SMMU_REGS(smmu); > + spin_unlock(&smmu->lock); > + > + free_pdir(as); > + } > + > + if (!list_empty(&as->client)) { > + struct smmu_client *c; > + > + list_for_each_entry(c, &as->client, list) > + dev_err(smmu->dev, > + "%s is still attached\n", dev_name(c->dev)); This is not an error. Just detach the devices when they are still attached to the domain. > + } > + > + spin_unlock_irqrestore(&as->lock, flags); > + > + domain->priv = NULL; > + dev_dbg(smmu->dev, "smmu_as@%p\n", as); > +} > + > +static int smmu_iommu_attach_dev(struct iommu_domain *domain, > + struct device *dev) > +{ > + struct smmu_as *as = domain->priv; > + struct smmu_device *smmu = as->smmu; Hmm, this looks like there is a 1-1 mapping between hardware SMMU devices and domains. This is not consistent with IOMMU-API semantics where a domain can contain devices behind different SMMUs. Please fix that. Thanks, Joerg ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-23 15:43 ` Joerg Roedel @ 2012-01-24 9:57 ` Hiroshi Doyu 2012-01-24 11:04 ` Joerg Roedel 2012-01-24 13:41 ` Hiroshi Doyu 1 sibling, 1 reply; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-24 9:57 UTC (permalink / raw) To: joro Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces Hi Joerg, From: Joerg Roedel <joro@8bytes.org> Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Date: Mon, 23 Jan 2012 16:43:10 +0100 Message-ID: <20120123154310.GC6269@8bytes.org> > Hi, > > please see my comments inline. When you fix these issues I think the > driver is ready for merging. > > On Thu, Jan 05, 2012 at 09:11:49AM +0200, Hiroshi DOYU wrote: > > +static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova, > > + phys_addr_t pa, size_t bytes, int prot) > > +{ > > + struct smmu_as *as = domain->priv; > > + unsigned long pfn = __phys_to_pfn(pa); > > + unsigned long flags; > > + > > + dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa); > > + > > + if (!pfn_valid(pfn)) > > + return -ENOMEM; > > + > > + spin_lock_irqsave(&as->lock, flags); > > + __smmu_iommu_map_pfn(as, iova, pfn); > > + spin_unlock_irqrestore(&as->lock, flags); > > + return 0; > > Why do you completly ignore the size parameter in this function (and > in the unmap part below)? > According to the page-sizes you export to the generic layer size can be > 4k or 4M. You need to take care of that in this function. I'll drop 4MB support here once. I'll make another patch for 4MB page support later. > > +static void smmu_iommu_domain_destroy(struct iommu_domain *domain) > > +{ > > + struct smmu_as *as = domain->priv; > > + struct smmu_device *smmu = as->smmu; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&as->lock, flags); > > + > > + if (as->pdir_page) { > > + spin_lock(&smmu->lock); > > + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); > > + smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA); > > + FLUSH_SMMU_REGS(smmu); > > + spin_unlock(&smmu->lock); > > + > > + free_pdir(as); > > + } > > + > > + if (!list_empty(&as->client)) { > > + struct smmu_client *c; > > + > > + list_for_each_entry(c, &as->client, list) > > + dev_err(smmu->dev, > > + "%s is still attached\n", dev_name(c->dev)); > > This is not an error. Just detach the devices when they are still > attached to the domain. Ok > > + } > > + > > + spin_unlock_irqrestore(&as->lock, flags); > > + > > + domain->priv = NULL; > > + dev_dbg(smmu->dev, "smmu_as@%p\n", as); > > +} > > + > > +static int smmu_iommu_attach_dev(struct iommu_domain *domain, > > + struct device *dev) > > +{ > > + struct smmu_as *as = domain->priv; > > + struct smmu_device *smmu = as->smmu; > > Hmm, this looks like there is a 1-1 mapping between hardware SMMU > devices and domains. This is not consistent with IOMMU-API semantics > where a domain can contain devices behind different SMMUs. Please fix > that. I'm a bit confused with the concept of "domain". I thought that "domain" is equivalent to a "virtual address space". Usually a IOMMU device provides a virtual address space for multiple client devices. IOW, a IOMMU device provides a virtual address space, which can be shared with multiple client devices. Actually Tegra SMMU case, a single IOMMU device has 4 different virtual address speace("smmu_as"). Each "smmu_as" has its own virtual address space. "smmu_as[i]" has mutiple "smmu_client" devices. smmu_as[i] == domain[i] I don't understand why "a domain can contain devices behind different SMMUs" because those client devices belong to different virtual address spaces, and they should belong to different "domains". Could you please explain a bit more about "domain"? > > > Thanks, > > Joerg > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-24 9:57 ` Hiroshi Doyu @ 2012-01-24 11:04 ` Joerg Roedel 2012-01-24 11:36 ` Hiroshi Doyu 0 siblings, 1 reply; 25+ messages in thread From: Joerg Roedel @ 2012-01-24 11:04 UTC (permalink / raw) To: Hiroshi Doyu Cc: joro, linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel On Tue, Jan 24, 2012 at 10:57:01AM +0100, Hiroshi Doyu wrote: > > Why do you completly ignore the size parameter in this function (and > > in the unmap part below)? > > According to the page-sizes you export to the generic layer size can be > > 4k or 4M. You need to take care of that in this function. > > I'll drop 4MB support here once. I'll make another patch for 4MB page > support later. Okay, so when you only export 4k everything should be fine. > > Hmm, this looks like there is a 1-1 mapping between hardware SMMU > > devices and domains. This is not consistent with IOMMU-API semantics > > where a domain can contain devices behind different SMMUs. Please fix > > that. > > I'm a bit confused with the concept of "domain". I thought that > "domain" is equivalent to a "virtual address space". Usually a IOMMU > device provides a virtual address space for multiple client > devices. IOW, a IOMMU device provides a virtual address space, which > can be shared with multiple client devices. > > Actually Tegra SMMU case, a single IOMMU device has 4 different > virtual address speace("smmu_as"). Each "smmu_as" has its own virtual > address space. "smmu_as[i]" has mutiple "smmu_client" devices. > > smmu_as[i] == domain[i] > > I don't understand why "a domain can contain devices behind different > SMMUs" because those client devices belong to different virtual > address spaces, and they should belong to different "domains". > > Could you please explain a bit more about "domain"? A domain is, as you said, a virtual address space for IO devices. But the important point is, an arbitrary number of devices can be part of a domain. This also means that the devices can be behind different hardware SMMUs. In this case your driver needs to program the page-table pointer into more than one SMMU to give devices behind different SMMUs the same address space. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-24 11:04 ` Joerg Roedel @ 2012-01-24 11:36 ` Hiroshi Doyu 2012-01-24 11:57 ` joerg.roedel 0 siblings, 1 reply; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-24 11:36 UTC (permalink / raw) To: joerg.roedel Cc: joro, linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel From: Joerg Roedel <joerg.roedel@amd.com> Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Date: Tue, 24 Jan 2012 12:04:44 +0100 Message-ID: <20120124110444.GB19255@amd.com> > > > Hmm, this looks like there is a 1-1 mapping between hardware SMMU > > > devices and domains. This is not consistent with IOMMU-API semantics > > > where a domain can contain devices behind different SMMUs. Please fix > > > that. > > > > I'm a bit confused with the concept of "domain". I thought that > > "domain" is equivalent to a "virtual address space". Usually a IOMMU > > device provides a virtual address space for multiple client > > devices. IOW, a IOMMU device provides a virtual address space, which > > can be shared with multiple client devices. > > > > Actually Tegra SMMU case, a single IOMMU device has 4 different > > virtual address speace("smmu_as"). Each "smmu_as" has its own virtual > > address space. "smmu_as[i]" has mutiple "smmu_client" devices. > > > > smmu_as[i] == domain[i] > > > > I don't understand why "a domain can contain devices behind different > > SMMUs" because those client devices belong to different virtual > > address spaces, and they should belong to different "domains". > > > > Could you please explain a bit more about "domain"? > > A domain is, as you said, a virtual address space for IO devices. But > the important point is, an arbitrary number of devices can be part of a > domain. This also means that the devices can be behind different > hardware SMMUs. In this case your driver needs to program the page-table > pointer into more than one SMMU to give devices behind different SMMUs > the same address space. Thank you for explaining. Does the above mean that a buffer can be shared with different devices which belong to different IOMMU devices(virtual address spaces)? For example, assuming the following: - We have "struct iommu_domain *domain1". - "domain1" has iommu device "iommu_dev1" and "iommu_dev2". - "iommu_dev1" has "client_dev1" and "client_dev2". - "iommu_dev2" has "client_dev3" and "client_dev4". "iommu_map(domain1, iova, pa, ...)" will create the following mapping ___at once___: - (iova)-(pa) mapping in iommu_dev1(iommmu_dev1's virtual address space) - (iova)-(pa) mapping in iommu_dev2(iommmu_dev2's virtual address space) Is the above correct? It seems that the same (iova) is used for different virtual address spaces. What kind of case is this beneficial most in? ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-24 11:36 ` Hiroshi Doyu @ 2012-01-24 11:57 ` joerg.roedel 2012-01-24 12:07 ` Hiroshi Doyu 0 siblings, 1 reply; 25+ messages in thread From: joerg.roedel @ 2012-01-24 11:57 UTC (permalink / raw) To: Hiroshi Doyu Cc: joro, linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel On Tue, Jan 24, 2012 at 12:36:14PM +0100, Hiroshi Doyu wrote: > > A domain is, as you said, a virtual address space for IO devices. But > > the important point is, an arbitrary number of devices can be part of a > > domain. This also means that the devices can be behind different > > hardware SMMUs. In this case your driver needs to program the page-table > > pointer into more than one SMMU to give devices behind different SMMUs > > the same address space. > > Thank you for explaining. > > Does the above mean that a buffer can be shared with different devices > which belong to different IOMMU devices(virtual address spaces)? > > For example, assuming the following: > > - We have "struct iommu_domain *domain1". > - "domain1" has iommu device "iommu_dev1" and "iommu_dev2". > - "iommu_dev1" has "client_dev1" and "client_dev2". > - "iommu_dev2" has "client_dev3" and "client_dev4". > > "iommu_map(domain1, iova, pa, ...)" will create the following mapping > ___at once___: > > - (iova)-(pa) mapping in iommu_dev1(iommmu_dev1's virtual address space) > - (iova)-(pa) mapping in iommu_dev2(iommmu_dev2's virtual address space) > > Is the above correct? Yes, this is correct. > It seems that the same (iova) is used for different virtual address > spaces. What kind of case is this beneficial most in? It is actually the _same_ virtual address space which is used by iommu_dev1 and iommu_dev2. Think of it like multiple threads of a single process. They also share the address space. This is a requirement of the iommu-api which is beneficial for virtualization and simplifies the usage of the api in general. The user does not need to care which devices can be assigned to which domain because of underlying hardware constraints. The goal of the iommu-api is to hide such contraints. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-24 11:57 ` joerg.roedel @ 2012-01-24 12:07 ` Hiroshi Doyu 0 siblings, 0 replies; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-24 12:07 UTC (permalink / raw) To: joerg.roedel Cc: joro, linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel From: "joerg.roedel@amd.com" <joerg.roedel@amd.com> Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Date: Tue, 24 Jan 2012 12:57:23 +0100 Message-ID: <20120124115723.GC19255@amd.com> > On Tue, Jan 24, 2012 at 12:36:14PM +0100, Hiroshi Doyu wrote: > > > A domain is, as you said, a virtual address space for IO devices. But > > > the important point is, an arbitrary number of devices can be part of a > > > domain. This also means that the devices can be behind different > > > hardware SMMUs. In this case your driver needs to program the page-table > > > pointer into more than one SMMU to give devices behind different SMMUs > > > the same address space. > > > > Thank you for explaining. > > > > Does the above mean that a buffer can be shared with different devices > > which belong to different IOMMU devices(virtual address spaces)? > > > > For example, assuming the following: > > > > - We have "struct iommu_domain *domain1". > > - "domain1" has iommu device "iommu_dev1" and "iommu_dev2". > > - "iommu_dev1" has "client_dev1" and "client_dev2". > > - "iommu_dev2" has "client_dev3" and "client_dev4". > > > > "iommu_map(domain1, iova, pa, ...)" will create the following mapping > > ___at once___: > > > > - (iova)-(pa) mapping in iommu_dev1(iommmu_dev1's virtual address space) > > - (iova)-(pa) mapping in iommu_dev2(iommmu_dev2's virtual address space) > > > > Is the above correct? > > Yes, this is correct. > > > It seems that the same (iova) is used for different virtual address > > spaces. What kind of case is this beneficial most in? > > It is actually the _same_ virtual address space which is used by > iommu_dev1 and iommu_dev2. Think of it like multiple threads of a single > process. They also share the address space. I see. The above makes more sense. > This is a requirement of the iommu-api which is beneficial for > virtualization and simplifies the usage of the api in general. The user > does not need to care which devices can be assigned to which domain > because of underlying hardware constraints. The goal of the iommu-api is > to hide such contraints. Now it's clear to me. I'll send the update patch soon. Thank you for explaining all of this. > > > Joerg > > -- > AMD Operating System Research Center > > Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach > General Managers: Alberto Bozzo > Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-23 15:43 ` Joerg Roedel 2012-01-24 9:57 ` Hiroshi Doyu @ 2012-01-24 13:41 ` Hiroshi Doyu 2012-01-24 13:46 ` Felipe Balbi 1 sibling, 1 reply; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-24 13:41 UTC (permalink / raw) To: joro Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces From: Joerg Roedel <joro@8bytes.org> Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Date: Mon, 23 Jan 2012 16:43:10 +0100 Message-ID: <20120123154310.GC6269@8bytes.org> > > + } > > + > > + spin_unlock_irqrestore(&as->lock, flags); > > + > > + domain->priv = NULL; > > + dev_dbg(smmu->dev, "smmu_as@%p\n", as); > > +} > > + > > +static int smmu_iommu_attach_dev(struct iommu_domain *domain, > > + struct device *dev) > > +{ > > + struct smmu_as *as = domain->priv; > > + struct smmu_device *smmu = as->smmu; > > Hmm, this looks like there is a 1-1 mapping between hardware SMMU > devices and domains. This is not consistent with IOMMU-API semantics > where a domain can contain devices behind different SMMUs. Please fix > that. Actually I really like the concept of this "domain" now, which hides the H/W hierarchy from users. But in Tegra SMMU/GART case, there's a single one IOMMU device in the system. Keeping a iommu device list in a domain and iterating iommu device list in each iommu_ops seem to be so nice, but I'm afraid that this may be a bit too much when one already knows that there's only one IOMMU device in the system. If there's no actual problem for 1-1 mapping between IOMMU H/Ws and domains, I think that it may not so bad to keep the original code(1-1) for GART and SMMU. What do you think? ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-24 13:41 ` Hiroshi Doyu @ 2012-01-24 13:46 ` Felipe Balbi 2012-01-24 14:25 ` joro 0 siblings, 1 reply; 25+ messages in thread From: Felipe Balbi @ 2012-01-24 13:46 UTC (permalink / raw) To: Hiroshi Doyu Cc: joro, iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces [-- Attachment #1: Type: text/plain, Size: 1930 bytes --] Hi, On Tue, Jan 24, 2012 at 02:41:21PM +0100, Hiroshi Doyu wrote: > From: Joerg Roedel <joro@8bytes.org> > Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver > Date: Mon, 23 Jan 2012 16:43:10 +0100 > Message-ID: <20120123154310.GC6269@8bytes.org> > > > > + } > > > + > > > + spin_unlock_irqrestore(&as->lock, flags); > > > + > > > + domain->priv = NULL; > > > + dev_dbg(smmu->dev, "smmu_as@%p\n", as); > > > +} > > > + > > > +static int smmu_iommu_attach_dev(struct iommu_domain *domain, > > > + struct device *dev) > > > +{ > > > + struct smmu_as *as = domain->priv; > > > + struct smmu_device *smmu = as->smmu; > > > > Hmm, this looks like there is a 1-1 mapping between hardware SMMU > > devices and domains. This is not consistent with IOMMU-API semantics > > where a domain can contain devices behind different SMMUs. Please fix > > that. > > Actually I really like the concept of this "domain" now, which hides > the H/W hierarchy from users. > > But in Tegra SMMU/GART case, there's a single one IOMMU device in the > system. Keeping a iommu device list in a domain and iterating iommu > device list in each iommu_ops seem to be so nice, but I'm afraid that > this may be a bit too much when one already knows that there's only > one IOMMU device in the system. > > If there's no actual problem for 1-1 mapping between IOMMU H/Ws and > domains, I think that it may not so bad to keep the original code(1-1) > for GART and SMMU. What do you think? I think it boils down to "extensability". If you can truly/fully guarantee that there will *always* be a single IOMMU on all upcoming Tegras, then it's really overkill. But if there's even a remote possibility of the HW being changed and you end up with more IOMMUs, things start to feel necessary for the sake of making it easy to extend. my 2 cents, feel free to ignore ;-) -- balbi [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-24 13:46 ` Felipe Balbi @ 2012-01-24 14:25 ` joro 2012-01-25 7:39 ` Hiroshi Doyu 0 siblings, 1 reply; 25+ messages in thread From: joro @ 2012-01-24 14:25 UTC (permalink / raw) To: Felipe Balbi Cc: Hiroshi Doyu, iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces On Tue, Jan 24, 2012 at 03:46:01PM +0200, Felipe Balbi wrote: > On Tue, Jan 24, 2012 at 02:41:21PM +0100, Hiroshi Doyu wrote: > > Actually I really like the concept of this "domain" now, which hides > > the H/W hierarchy from users. > > > > But in Tegra SMMU/GART case, there's a single one IOMMU device in the > > system. Keeping a iommu device list in a domain and iterating iommu > > device list in each iommu_ops seem to be so nice, but I'm afraid that > > this may be a bit too much when one already knows that there's only > > one IOMMU device in the system. > > > > If there's no actual problem for 1-1 mapping between IOMMU H/Ws and > > domains, I think that it may not so bad to keep the original code(1-1) > > for GART and SMMU. What do you think? > > I think it boils down to "extensability". If you can truly/fully > guarantee that there will *always* be a single IOMMU on all upcoming > Tegras, then it's really overkill. > > But if there's even a remote possibility of the HW being changed and you > end up with more IOMMUs, things start to feel necessary for the sake of > making it easy to extend. Right. But I am fine with the logic as-is when there is only one SMMU in the system. But please also change the IOMMU driver so that it really only initializes a single SMMU. When boards pop up with more than one you we notice that assumption in the code again and are reminded to change it. Joerg ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-24 14:25 ` joro @ 2012-01-25 7:39 ` Hiroshi Doyu 2012-01-26 14:59 ` joro 0 siblings, 1 reply; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-25 7:39 UTC (permalink / raw) To: joro Cc: balbi, iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig [-- Attachment #1: Type: text/plain, Size: 1844 bytes --] From: "joro@8bytes.org" <joro@8bytes.org> Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Date: Tue, 24 Jan 2012 15:25:21 +0100 Message-ID: <20120124142521.GE6269@8bytes.org> > On Tue, Jan 24, 2012 at 03:46:01PM +0200, Felipe Balbi wrote: > > On Tue, Jan 24, 2012 at 02:41:21PM +0100, Hiroshi Doyu wrote: > > > Actually I really like the concept of this "domain" now, which hides > > > the H/W hierarchy from users. > > > > > > But in Tegra SMMU/GART case, there's a single one IOMMU device in the > > > system. Keeping a iommu device list in a domain and iterating iommu > > > device list in each iommu_ops seem to be so nice, but I'm afraid that > > > this may be a bit too much when one already knows that there's only > > > one IOMMU device in the system. > > > > > > If there's no actual problem for 1-1 mapping between IOMMU H/Ws and > > > domains, I think that it may not so bad to keep the original code(1-1) > > > for GART and SMMU. What do you think? > > > > I think it boils down to "extensability". If you can truly/fully > > guarantee that there will *always* be a single IOMMU on all upcoming > > Tegras, then it's really overkill. > > > > But if there's even a remote possibility of the HW being changed and you > > end up with more IOMMUs, things start to feel necessary for the sake of > > making it easy to extend. > > Right. But I am fine with the logic as-is when there is only one SMMU in > the system. But please also change the IOMMU driver so that it really > only initializes a single SMMU. When boards pop up with more than one > you we notice that assumption in the code again and are reminded to > change it. Fixed. I'll revisit 4MB pagesize support and the above multiple iommu device support in a domain later. Attached the update patch. [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #2: 0002-ARM-IOMMU-Tegra30-Add-iommu_ops-for-SMMU-driver.patch --] [-- Type: text/x-patch; name="0002-ARM-IOMMU-Tegra30-Add-iommu_ops-for-SMMU-driver.patch", Size: 33838 bytes --] From 18448424ce1f8ae554cd3b801d61b6a064e4bcd8 Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU <hdoyu@nvidia.com> Date: Thu, 17 Nov 2011 07:31:31 +0200 Subject: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit). This patch implements struct iommu_ops for SMMU for the upper IOMMU API. This H/W module supports multiple virtual address spaces(domain x4), and manages 2 level H/W translation pagetable. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> --- arch/arm/mach-tegra/include/mach/smmu.h | 63 ++ drivers/iommu/Kconfig | 11 + drivers/iommu/Makefile | 1 + drivers/iommu/tegra-smmu.c | 1034 +++++++++++++++++++++++++++++++ 4 files changed, 1109 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-tegra/include/mach/smmu.h create mode 100644 drivers/iommu/tegra-smmu.c diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h new file mode 100644 index 0000000..dad403a --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/smmu.h @@ -0,0 +1,63 @@ +/* + * IOMMU API for SMMU in Tegra30 + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef MACH_SMMU_H +#define MACH_SMMU_H + +enum smmu_hwgrp { + HWGRP_AFI, + HWGRP_AVPC, + HWGRP_DC, + HWGRP_DCB, + HWGRP_EPP, + HWGRP_G2, + HWGRP_HC, + HWGRP_HDA, + HWGRP_ISP, + HWGRP_MPE, + HWGRP_NV, + HWGRP_NV2, + HWGRP_PPCS, + HWGRP_SATA, + HWGRP_VDE, + HWGRP_VI, + + HWGRP_COUNT, + + HWGRP_END = ~0, +}; + +#define HWG_AFI (1 << HWGRP_AFI) +#define HWG_AVPC (1 << HWGRP_AVPC) +#define HWG_DC (1 << HWGRP_DC) +#define HWG_DCB (1 << HWGRP_DCB) +#define HWG_EPP (1 << HWGRP_EPP) +#define HWG_G2 (1 << HWGRP_G2) +#define HWG_HC (1 << HWGRP_HC) +#define HWG_HDA (1 << HWGRP_HDA) +#define HWG_ISP (1 << HWGRP_ISP) +#define HWG_MPE (1 << HWGRP_MPE) +#define HWG_NV (1 << HWGRP_NV) +#define HWG_NV2 (1 << HWGRP_NV2) +#define HWG_PPCS (1 << HWGRP_PPCS) +#define HWG_SATA (1 << HWGRP_SATA) +#define HWG_VDE (1 << HWGRP_VDE) +#define HWG_VI (1 << HWGRP_VI) + +#endif /* MACH_SMMU_H */ diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 4562698..4b3d616 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -153,4 +153,15 @@ config TEGRA_IOMMU_GART space through the GART (Graphics Address Relocation Table) hardware included on Tegra SoCs. +config TEGRA_IOMMU_SMMU + bool "Tegra SMMU IOMMU Support" + depends on ARCH_TEGRA_3x_SOC + default y + select IOMMU_API + help + Enables support for remapping discontiguous physical memory + shared with the operating system into contiguous I/O virtual + space through the SMMU (System Memory Management Unit) + hardware included on Tegra SoCs. + endif # IOMMU_SUPPORT diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 3238a31..7ad7a3b 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o +obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c new file mode 100644 index 0000000..eb93c82 --- /dev/null +++ b/drivers/iommu/tegra-smmu.c @@ -0,0 +1,1034 @@ +/* + * IOMMU API for SMMU in Tegra30 + * + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define pr_fmt(fmt) "%s(): " fmt, __func__ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/mm.h> +#include <linux/pagemap.h> +#include <linux/device.h> +#include <linux/sched.h> +#include <linux/iommu.h> +#include <linux/io.h> + +#include <asm/page.h> +#include <asm/cacheflush.h> + +#include <mach/iomap.h> +#include <mach/smmu.h> + +/* bitmap of the page sizes currently supported */ +#define SMMU_IOMMU_PGSIZES (SZ_4K) + +#define SMMU_CONFIG 0x10 +#define SMMU_CONFIG_DISABLE 0 +#define SMMU_CONFIG_ENABLE 1 + +#define SMMU_TLB_CONFIG 0x14 +#define SMMU_TLB_CONFIG_STATS__MASK (1 << 31) +#define SMMU_TLB_CONFIG_STATS__ENABLE (1 << 31) +#define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29) +#define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10 +#define SMMU_TLB_CONFIG_RESET_VAL 0x20000010 + +#define SMMU_PTC_CONFIG 0x18 +#define SMMU_PTC_CONFIG_STATS__MASK (1 << 31) +#define SMMU_PTC_CONFIG_STATS__ENABLE (1 << 31) +#define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29) +#define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f +#define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f + +#define SMMU_PTB_ASID 0x1c +#define SMMU_PTB_ASID_CURRENT_SHIFT 0 + +#define SMMU_PTB_DATA 0x20 +#define SMMU_PTB_DATA_RESET_VAL 0 +#define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29 +#define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30 +#define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31 + +#define SMMU_TLB_FLUSH 0x30 +#define SMMU_TLB_FLUSH_VA_MATCH_ALL 0 +#define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2 +#define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3 +#define SMMU_TLB_FLUSH_ASID_SHIFT 29 +#define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0 +#define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1 +#define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31 + +#define SMMU_PTC_FLUSH 0x34 +#define SMMU_PTC_FLUSH_TYPE_ALL 0 +#define SMMU_PTC_FLUSH_TYPE_ADR 1 +#define SMMU_PTC_FLUSH_ADR_SHIFT 4 + +#define SMMU_ASID_SECURITY 0x38 + +#define SMMU_STATS_TLB_HIT_COUNT 0x1f0 +#define SMMU_STATS_TLB_MISS_COUNT 0x1f4 +#define SMMU_STATS_PTC_HIT_COUNT 0x1f8 +#define SMMU_STATS_PTC_MISS_COUNT 0x1fc + +#define SMMU_TRANSLATION_ENABLE_0 0x228 +#define SMMU_TRANSLATION_ENABLE_1 0x22c +#define SMMU_TRANSLATION_ENABLE_2 0x230 + +#define SMMU_AFI_ASID 0x238 /* PCIE */ +#define SMMU_AVPC_ASID 0x23c /* AVP */ +#define SMMU_DC_ASID 0x240 /* Display controller */ +#define SMMU_DCB_ASID 0x244 /* Display controller B */ +#define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */ +#define SMMU_G2_ASID 0x24c /* 2D engine */ +#define SMMU_HC_ASID 0x250 /* Host1x */ +#define SMMU_HDA_ASID 0x254 /* High-def audio */ +#define SMMU_ISP_ASID 0x258 /* Image signal processor */ +#define SMMU_MPE_ASID 0x264 /* MPEG encoder */ +#define SMMU_NV_ASID 0x268 /* (3D) */ +#define SMMU_NV2_ASID 0x26c /* (3D) */ +#define SMMU_PPCS_ASID 0x270 /* AHB */ +#define SMMU_SATA_ASID 0x278 /* SATA */ +#define SMMU_VDE_ASID 0x27c /* Video decoder */ +#define SMMU_VI_ASID 0x280 /* Video input */ + +#define SMMU_PDE_NEXT_SHIFT 28 + +/* AHB Arbiter Registers */ +#define AHB_XBAR_CTRL 0xe0 +#define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE 1 +#define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT 17 + +#define SMMU_NUM_ASIDS 4 +#define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000 +#define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */ +#define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000 +#define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */ +#define SMMU_TLB_FLUSH_VA(iova, which) \ + ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \ + SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \ + SMMU_TLB_FLUSH_VA_MATCH_##which) +#define SMMU_PTB_ASID_CUR(n) \ + ((n) << SMMU_PTB_ASID_CURRENT_SHIFT) +#define SMMU_TLB_FLUSH_ASID_MATCH_disable \ + (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \ + SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) +#define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \ + (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \ + SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) + +#define SMMU_PAGE_SHIFT 12 +#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT) + +#define SMMU_PDIR_COUNT 1024 +#define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT) +#define SMMU_PTBL_COUNT 1024 +#define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT) +#define SMMU_PDIR_SHIFT 12 +#define SMMU_PDE_SHIFT 12 +#define SMMU_PTE_SHIFT 12 +#define SMMU_PFN_MASK 0x000fffff + +#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12) +#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22) +#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22) + +#define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT) +#define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT) +#define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT) +#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT) +#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE) + +#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE) + +#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE) +#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT) +#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR) + +#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE) +#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR) + +#define SMMU_MK_PDIR(page, attr) \ + ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr)) +#define SMMU_MK_PDE(page, attr) \ + (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr)) +#define SMMU_EX_PTBL_PAGE(pde) \ + pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK) +#define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr)) + +#define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31)) +#define SMMU_ASID_DISABLE 0 +#define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0)) + +#define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1) +#define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0) +#define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1) +#define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0) + +#define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID + +static const u32 smmu_hwgrp_asid_reg[] = { + HWGRP_INIT(AFI), + HWGRP_INIT(AVPC), + HWGRP_INIT(DC), + HWGRP_INIT(DCB), + HWGRP_INIT(EPP), + HWGRP_INIT(G2), + HWGRP_INIT(HC), + HWGRP_INIT(HDA), + HWGRP_INIT(ISP), + HWGRP_INIT(MPE), + HWGRP_INIT(NV), + HWGRP_INIT(NV2), + HWGRP_INIT(PPCS), + HWGRP_INIT(SATA), + HWGRP_INIT(VDE), + HWGRP_INIT(VI), +}; +#define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x]) + +/* + * Per client for address space + */ +struct smmu_client { + struct device *dev; + struct list_head list; + struct smmu_as *as; + u32 hwgrp; +}; + +/* + * Per address space + */ +struct smmu_as { + struct smmu_device *smmu; /* back pointer to container */ + unsigned int asid; + spinlock_t lock; /* for pagetable */ + struct page *pdir_page; + unsigned long pdir_attr; + unsigned long pde_attr; + unsigned long pte_attr; + unsigned int *pte_count; + + struct list_head client; + spinlock_t client_lock; /* for client list */ +}; + +/* + * Per SMMU device - IOMMU device + */ +struct smmu_device { + void __iomem *regs, *regs_ahbarb; + unsigned long iovmm_base; /* remappable base address */ + unsigned long page_count; /* total remappable size */ + spinlock_t lock; + char *name; + struct device *dev; + int num_as; + struct smmu_as *as; /* Run-time allocated array */ + struct page *avp_vector_page; /* dummy page shared by all AS's */ + + /* + * Register image savers for suspend/resume + */ + unsigned long translation_enable_0; + unsigned long translation_enable_1; + unsigned long translation_enable_2; + unsigned long asid_security; +}; + +static struct smmu_device *smmu_handle; /* unique for a system */ + +/* + * SMMU/AHB register accessors + */ +static inline u32 smmu_read(struct smmu_device *smmu, size_t offs) +{ + return readl(smmu->regs + offs); +} +static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) +{ + writel(val, smmu->regs + offs); +} + +static inline u32 ahb_read(struct smmu_device *smmu, size_t offs) +{ + return readl(smmu->regs_ahbarb + offs); +} +static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs) +{ + writel(val, smmu->regs_ahbarb + offs); +} + +#define VA_PAGE_TO_PA(va, page) \ + (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK)) + +#define FLUSH_CPU_DCACHE(va, page, size) \ + do { \ + unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \ + __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \ + outer_flush_range(_pa_, _pa_+(size_t)(size)); \ + } while (0) + +/* + * Any interaction between any block on PPSB and a block on APB or AHB + * must have these read-back barriers to ensure the APB/AHB bus + * transaction is complete before initiating activity on the PPSB + * block. + */ +#define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) + +#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data) + +static int __smmu_client_set_hwgrp(struct smmu_client *c, + unsigned long map, int on) +{ + int i; + struct smmu_as *as = c->as; + u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid); + struct smmu_device *smmu = as->smmu; + + WARN_ON(!on && map); + if (on && !map) + return -EINVAL; + if (!on) + map = smmu_client_hwgrp(c); + + for_each_set_bit(i, &map, HWGRP_COUNT) { + offs = HWGRP_ASID_REG(i); + val = smmu_read(smmu, offs); + if (on) { + if (WARN_ON(val & mask)) + goto err_hw_busy; + val |= mask; + } else { + WARN_ON((val & mask) == mask); + val &= ~mask; + } + smmu_write(smmu, val, offs); + } + FLUSH_SMMU_REGS(smmu); + c->hwgrp = map; + return 0; + +err_hw_busy: + for_each_set_bit(i, &map, HWGRP_COUNT) { + offs = HWGRP_ASID_REG(i); + val = smmu_read(smmu, offs); + val &= ~mask; + smmu_write(smmu, val, offs); + } + return -EBUSY; +} + +static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on) +{ + u32 val; + unsigned long flags; + struct smmu_as *as = c->as; + struct smmu_device *smmu = as->smmu; + + spin_lock_irqsave(&smmu->lock, flags); + val = __smmu_client_set_hwgrp(c, map, on); + spin_unlock_irqrestore(&smmu->lock, flags); + return val; +} + +/* + * Flush all TLB entries and all PTC entries + * Caller must lock smmu + */ +static void smmu_flush_regs(struct smmu_device *smmu, int enable) +{ + u32 val; + + smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); + FLUSH_SMMU_REGS(smmu); + val = SMMU_TLB_FLUSH_VA_MATCH_ALL | + SMMU_TLB_FLUSH_ASID_MATCH_disable; + smmu_write(smmu, val, SMMU_TLB_FLUSH); + + if (enable) + smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); + FLUSH_SMMU_REGS(smmu); +} + +static void smmu_setup_regs(struct smmu_device *smmu) +{ + int i; + u32 val; + + for (i = 0; i < smmu->num_as; i++) { + struct smmu_as *as = &smmu->as[i]; + struct smmu_client *c; + + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); + val = as->pdir_page ? + SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) : + SMMU_PTB_DATA_RESET_VAL; + smmu_write(smmu, val, SMMU_PTB_DATA); + + list_for_each_entry(c, &as->client, list) + __smmu_client_set_hwgrp(c, c->hwgrp, 1); + } + + smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0); + smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1); + smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2); + smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY); + smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_TLB_CONFIG); + smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_PTC_CONFIG); + + smmu_flush_regs(smmu, 1); + + val = ahb_read(smmu, AHB_XBAR_CTRL); + val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE << + AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT; + ahb_write(smmu, val, AHB_XBAR_CTRL); +} + +static void flush_ptc_and_tlb(struct smmu_device *smmu, + struct smmu_as *as, dma_addr_t iova, + unsigned long *pte, struct page *page, int is_pde) +{ + u32 val; + unsigned long tlb_flush_va = is_pde + ? SMMU_TLB_FLUSH_VA(iova, SECTION) + : SMMU_TLB_FLUSH_VA(iova, GROUP); + + val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page); + smmu_write(smmu, val, SMMU_PTC_FLUSH); + FLUSH_SMMU_REGS(smmu); + val = tlb_flush_va | + SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + smmu_write(smmu, val, SMMU_TLB_FLUSH); + FLUSH_SMMU_REGS(smmu); +} + +static void free_ptbl(struct smmu_as *as, dma_addr_t iova) +{ + unsigned long pdn = SMMU_ADDR_TO_PDN(iova); + unsigned long *pdir = (unsigned long *)page_address(as->pdir_page); + + if (pdir[pdn] != _PDE_VACANT(pdn)) { + dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn); + + ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn])); + __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn])); + pdir[pdn] = _PDE_VACANT(pdn); + FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); + flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], + as->pdir_page, 1); + } +} + +static void free_pdir(struct smmu_as *as) +{ + unsigned addr; + int count; + struct device *dev = as->smmu->dev; + + if (!as->pdir_page) + return; + + addr = as->smmu->iovmm_base; + count = as->smmu->page_count; + while (count-- > 0) { + free_ptbl(as, addr); + addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT; + } + ClearPageReserved(as->pdir_page); + __free_page(as->pdir_page); + as->pdir_page = NULL; + devm_kfree(dev, as->pte_count); + as->pte_count = NULL; +} + +/* + * Maps PTBL for given iova and returns the PTE address + * Caller must unmap the mapped PTBL returned in *ptbl_page_p + */ +static unsigned long *locate_pte(struct smmu_as *as, + dma_addr_t iova, bool allocate, + struct page **ptbl_page_p, + unsigned int **count) +{ + unsigned long ptn = SMMU_ADDR_TO_PFN(iova); + unsigned long pdn = SMMU_ADDR_TO_PDN(iova); + unsigned long *pdir = page_address(as->pdir_page); + unsigned long *ptbl; + + if (pdir[pdn] != _PDE_VACANT(pdn)) { + /* Mapped entry table already exists */ + *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]); + ptbl = page_address(*ptbl_page_p); + } else if (!allocate) { + return NULL; + } else { + int pn; + unsigned long addr = SMMU_PDN_TO_ADDR(pdn); + + /* Vacant - allocate a new page table */ + dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn); + + *ptbl_page_p = alloc_page(GFP_ATOMIC); + if (!*ptbl_page_p) { + dev_err(as->smmu->dev, + "failed to allocate smmu_device page table\n"); + return NULL; + } + SetPageReserved(*ptbl_page_p); + ptbl = (unsigned long *)page_address(*ptbl_page_p); + for (pn = 0; pn < SMMU_PTBL_COUNT; + pn++, addr += SMMU_PAGE_SIZE) { + ptbl[pn] = _PTE_VACANT(addr); + } + FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE); + pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p, + as->pde_attr | _PDE_NEXT); + FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); + flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], + as->pdir_page, 1); + } + *count = &as->pte_count[pdn]; + + return &ptbl[ptn % SMMU_PTBL_COUNT]; +} + +#ifdef CONFIG_SMMU_SIG_DEBUG +static void put_signature(struct smmu_as *as, + dma_addr_t iova, unsigned long pfn) +{ + struct page *page; + unsigned long *vaddr; + + page = pfn_to_page(pfn); + vaddr = page_address(page); + if (!vaddr) + return; + + vaddr[0] = iova; + vaddr[1] = pfn << PAGE_SHIFT; + FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2); +} +#else +static inline void put_signature(struct smmu_as *as, + unsigned long addr, unsigned long pfn) +{ +} +#endif + +/* + * Caller must lock/unlock as + */ +static int alloc_pdir(struct smmu_as *as) +{ + unsigned long *pdir; + int pdn; + u32 val; + struct smmu_device *smmu = as->smmu; + + if (as->pdir_page) + return 0; + + as->pte_count = devm_kzalloc(smmu->dev, + sizeof(as->pte_count[0]) * SMMU_PDIR_COUNT, GFP_KERNEL); + if (!as->pte_count) { + dev_err(smmu->dev, + "failed to allocate smmu_device PTE cunters\n"); + return -ENOMEM; + } + as->pdir_page = alloc_page(GFP_KERNEL | __GFP_DMA); + if (!as->pdir_page) { + dev_err(smmu->dev, + "failed to allocate smmu_device page directory\n"); + devm_kfree(smmu->dev, as->pte_count); + as->pte_count = NULL; + return -ENOMEM; + } + SetPageReserved(as->pdir_page); + pdir = page_address(as->pdir_page); + + for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) + pdir[pdn] = _PDE_VACANT(pdn); + FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE); + val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page); + smmu_write(smmu, val, SMMU_PTC_FLUSH); + FLUSH_SMMU_REGS(as->smmu); + val = SMMU_TLB_FLUSH_VA_MATCH_ALL | + SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + smmu_write(smmu, val, SMMU_TLB_FLUSH); + FLUSH_SMMU_REGS(as->smmu); + + return 0; +} + +static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova) +{ + unsigned long *pte; + struct page *page; + unsigned int *count; + + pte = locate_pte(as, iova, false, &page, &count); + if (WARN_ON(!pte)) + return; + + if (WARN_ON(*pte == _PTE_VACANT(iova))) + return; + + *pte = _PTE_VACANT(iova); + FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); + flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0); + if (!--(*count)) { + free_ptbl(as, iova); + smmu_flush_regs(as->smmu, 0); + } +} + +static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova, + unsigned long pfn) +{ + struct smmu_device *smmu = as->smmu; + unsigned long *pte; + unsigned int *count; + struct page *page; + + pte = locate_pte(as, iova, true, &page, &count); + if (WARN_ON(!pte)) + return; + + if (*pte == _PTE_VACANT(iova)) + (*count)++; + *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr); + if (unlikely((*pte == _PTE_VACANT(iova)))) + (*count)--; + FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); + flush_ptc_and_tlb(smmu, as, iova, pte, page, 0); + put_signature(as, iova, pfn); +} + +static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t pa, size_t bytes, int prot) +{ + struct smmu_as *as = domain->priv; + unsigned long pfn = __phys_to_pfn(pa); + unsigned long flags; + + dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa); + + if (!pfn_valid(pfn)) + return -ENOMEM; + + spin_lock_irqsave(&as->lock, flags); + __smmu_iommu_map_pfn(as, iova, pfn); + spin_unlock_irqrestore(&as->lock, flags); + return 0; +} + +static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova, + size_t bytes) +{ + struct smmu_as *as = domain->priv; + unsigned long flags; + + dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova); + + spin_lock_irqsave(&as->lock, flags); + __smmu_iommu_unmap(as, iova); + spin_unlock_irqrestore(&as->lock, flags); + return SMMU_PAGE_SIZE; +} + +static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain, + unsigned long iova) +{ + struct smmu_as *as = domain->priv; + unsigned long *pte; + unsigned int *count; + struct page *page; + unsigned long pfn; + unsigned long flags; + + spin_lock_irqsave(&as->lock, flags); + + pte = locate_pte(as, iova, true, &page, &count); + pfn = *pte & SMMU_PFN_MASK; + WARN_ON(!pfn_valid(pfn)); + dev_dbg(as->smmu->dev, + "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid); + + spin_unlock_irqrestore(&as->lock, flags); + return PFN_PHYS(pfn); +} + +static int smmu_iommu_domain_has_cap(struct iommu_domain *domain, + unsigned long cap) +{ + return 0; +} + +static int smmu_iommu_attach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct smmu_as *as = domain->priv; + struct smmu_device *smmu = as->smmu; + struct smmu_client *client, *c; + u32 map; + int err; + + client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL); + if (!client) + return -ENOMEM; + client->dev = dev; + client->as = as; + map = (unsigned long)dev->platform_data; + if (!map) + return -EINVAL; + + err = smmu_client_enable_hwgrp(client, map); + if (err) + goto err_hwgrp; + + spin_lock(&as->client_lock); + list_for_each_entry(c, &as->client, list) { + if (c->dev == dev) { + dev_err(smmu->dev, + "%s is already attached\n", dev_name(c->dev)); + err = -EINVAL; + goto err_client; + } + } + list_add(&client->list, &as->client); + spin_unlock(&as->client_lock); + + /* + * Reserve "page zero" for AVP vectors using a common dummy + * page. + */ + if (map & HWG_AVPC) { + struct page *page; + + page = as->smmu->avp_vector_page; + __smmu_iommu_map_pfn(as, 0, page_to_pfn(page)); + + pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n"); + } + + dev_dbg(smmu->dev, "%s is attached\n", dev_name(c->dev)); + return 0; + +err_client: + smmu_client_disable_hwgrp(client); + spin_unlock(&as->client_lock); +err_hwgrp: + devm_kfree(smmu->dev, client); + return err; +} + +static void smmu_iommu_detach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct smmu_as *as = domain->priv; + struct smmu_device *smmu = as->smmu; + struct smmu_client *c; + + spin_lock(&as->client_lock); + + list_for_each_entry(c, &as->client, list) { + if (c->dev == dev) { + smmu_client_disable_hwgrp(c); + list_del(&c->list); + devm_kfree(smmu->dev, c); + c->as = NULL; + dev_dbg(smmu->dev, + "%s is detached\n", dev_name(c->dev)); + goto out; + } + } + dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev)); +out: + spin_unlock(&as->client_lock); +} + +static int smmu_iommu_domain_init(struct iommu_domain *domain) +{ + int i; + unsigned long flags; + struct smmu_as *as; + struct smmu_device *smmu = smmu_handle; + + /* Look for a free AS with lock held */ + for (i = 0; i < smmu->num_as; i++) { + struct smmu_as *tmp = &smmu->as[i]; + + spin_lock_irqsave(&tmp->lock, flags); + if (!tmp->pdir_page) { + as = tmp; + goto found; + } + spin_unlock_irqrestore(&tmp->lock, flags); + } + dev_err(smmu->dev, "no free AS\n"); + return -ENODEV; + +found: + if (alloc_pdir(as) < 0) + goto err_alloc_pdir; + + spin_lock(&smmu->lock); + + /* Update PDIR register */ + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); + smmu_write(smmu, + SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA); + FLUSH_SMMU_REGS(smmu); + + spin_unlock(&smmu->lock); + + spin_unlock_irqrestore(&as->lock, flags); + domain->priv = as; + + dev_dbg(smmu->dev, "smmu_as@%p\n", as); + return 0; + +err_alloc_pdir: + spin_unlock_irqrestore(&as->lock, flags); + return -ENODEV; +} + +static void smmu_iommu_domain_destroy(struct iommu_domain *domain) +{ + struct smmu_as *as = domain->priv; + struct smmu_device *smmu = as->smmu; + unsigned long flags; + + spin_lock_irqsave(&as->lock, flags); + + if (as->pdir_page) { + spin_lock(&smmu->lock); + smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); + smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA); + FLUSH_SMMU_REGS(smmu); + spin_unlock(&smmu->lock); + + free_pdir(as); + } + + if (!list_empty(&as->client)) { + struct smmu_client *c; + + list_for_each_entry(c, &as->client, list) + smmu_iommu_detach_dev(domain, c->dev); + } + + spin_unlock_irqrestore(&as->lock, flags); + + domain->priv = NULL; + dev_dbg(smmu->dev, "smmu_as@%p\n", as); +} + +static struct iommu_ops smmu_iommu_ops = { + .domain_init = smmu_iommu_domain_init, + .domain_destroy = smmu_iommu_domain_destroy, + .attach_dev = smmu_iommu_attach_dev, + .detach_dev = smmu_iommu_detach_dev, + .map = smmu_iommu_map, + .unmap = smmu_iommu_unmap, + .iova_to_phys = smmu_iommu_iova_to_phys, + .domain_has_cap = smmu_iommu_domain_has_cap, + .pgsize_bitmap = SMMU_IOMMU_PGSIZES, +}; + +static int tegra_smmu_suspend(struct device *dev) +{ + struct smmu_device *smmu = dev_get_drvdata(dev); + + smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0); + smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1); + smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2); + smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY); + return 0; +} + +static int tegra_smmu_resume(struct device *dev) +{ + struct smmu_device *smmu = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&smmu->lock, flags); + smmu_setup_regs(smmu); + spin_unlock_irqrestore(&smmu->lock, flags); + return 0; +} + +static int tegra_smmu_probe(struct platform_device *pdev) +{ + struct smmu_device *smmu; + struct resource *regs, *regs2, *window; + struct device *dev = &pdev->dev; + int i, err = 0; + + if (smmu_handle) + return -EIO; + + BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT); + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); + window = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!regs || !regs2 || !window) { + dev_err(dev, "No SMMU resources\n"); + return -ENODEV; + } + + smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); + if (!smmu) { + dev_err(dev, "failed to allocate smmu_device\n"); + return -ENOMEM; + } + + smmu->dev = dev; + smmu->num_as = SMMU_NUM_ASIDS; + smmu->iovmm_base = (unsigned long)window->start; + smmu->page_count = resource_size(window) >> SMMU_PAGE_SHIFT; + smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs)); + smmu->regs_ahbarb = devm_ioremap(dev, regs2->start, + resource_size(regs2)); + if (!smmu->regs || !smmu->regs_ahbarb) { + dev_err(dev, "failed to remap SMMU registers\n"); + err = -ENXIO; + goto fail; + } + + smmu->translation_enable_0 = ~0; + smmu->translation_enable_1 = ~0; + smmu->translation_enable_2 = ~0; + smmu->asid_security = 0; + + smmu->as = devm_kzalloc(dev, + sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL); + if (!smmu->as) { + dev_err(dev, "failed to allocate smmu_as\n"); + err = -ENOMEM; + goto fail; + } + + for (i = 0; i < smmu->num_as; i++) { + struct smmu_as *as = &smmu->as[i]; + + as->smmu = smmu; + as->asid = i; + as->pdir_attr = _PDIR_ATTR; + as->pde_attr = _PDE_ATTR; + as->pte_attr = _PTE_ATTR; + + spin_lock_init(&as->lock); + INIT_LIST_HEAD(&as->client); + } + spin_lock_init(&smmu->lock); + smmu_setup_regs(smmu); + platform_set_drvdata(pdev, smmu); + + smmu->avp_vector_page = alloc_page(GFP_KERNEL); + if (!smmu->avp_vector_page) + goto fail; + + smmu_handle = smmu; + return 0; + +fail: + if (smmu->avp_vector_page) + __free_page(smmu->avp_vector_page); + if (smmu->regs) + devm_iounmap(dev, smmu->regs); + if (smmu->regs_ahbarb) + devm_iounmap(dev, smmu->regs_ahbarb); + if (smmu && smmu->as) { + for (i = 0; i < smmu->num_as; i++) { + if (smmu->as[i].pdir_page) { + ClearPageReserved(smmu->as[i].pdir_page); + __free_page(smmu->as[i].pdir_page); + } + } + devm_kfree(dev, smmu->as); + } + devm_kfree(dev, smmu); + return err; +} + +static int tegra_smmu_remove(struct platform_device *pdev) +{ + struct smmu_device *smmu = platform_get_drvdata(pdev); + struct device *dev = smmu->dev; + + smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG); + platform_set_drvdata(pdev, NULL); + if (smmu->as) { + int i; + + for (i = 0; i < smmu->num_as; i++) + free_pdir(&smmu->as[i]); + devm_kfree(dev, smmu->as); + } + if (smmu->avp_vector_page) + __free_page(smmu->avp_vector_page); + if (smmu->regs) + devm_iounmap(dev, smmu->regs); + if (smmu->regs_ahbarb) + devm_iounmap(dev, smmu->regs_ahbarb); + devm_kfree(dev, smmu); + smmu_handle = NULL; + return 0; +} + +const struct dev_pm_ops tegra_smmu_pm_ops = { + .suspend = tegra_smmu_suspend, + .resume = tegra_smmu_resume, +}; + +static struct platform_driver tegra_smmu_driver = { + .probe = tegra_smmu_probe, + .remove = tegra_smmu_remove, + .driver = { + .owner = THIS_MODULE, + .name = "tegra-smmu", + .pm = &tegra_smmu_pm_ops, + }, +}; + +static int __devinit tegra_smmu_init(void) +{ + bus_set_iommu(&platform_bus_type, &smmu_iommu_ops); + return platform_driver_register(&tegra_smmu_driver); +} + +static void __exit tegra_smmu_exit(void) +{ + platform_driver_unregister(&tegra_smmu_driver); +} + +subsys_initcall(tegra_smmu_init); +module_exit(tegra_smmu_exit); + +MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30"); +MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); +MODULE_LICENSE("GPL v2"); -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 2012-01-25 7:39 ` Hiroshi Doyu @ 2012-01-26 14:59 ` joro 0 siblings, 0 replies; 25+ messages in thread From: joro @ 2012-01-26 14:59 UTC (permalink / raw) To: Hiroshi Doyu Cc: balbi, iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig On Wed, Jan 25, 2012 at 08:39:32AM +0100, Hiroshi Doyu wrote: > From: Hiroshi DOYU <hdoyu@nvidia.com> > Date: Thu, 17 Nov 2011 07:31:31 +0200 > Subject: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver > > Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit). This patch > implements struct iommu_ops for SMMU for the upper IOMMU API. > > This H/W module supports multiple virtual address spaces(domain x4), > and manages 2 level H/W translation pagetable. > > Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> > --- > arch/arm/mach-tegra/include/mach/smmu.h | 63 ++ > drivers/iommu/Kconfig | 11 + > drivers/iommu/Makefile | 1 + > drivers/iommu/tegra-smmu.c | 1034 +++++++++++++++++++++++++++++++ > 4 files changed, 1109 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-tegra/include/mach/smmu.h > create mode 100644 drivers/iommu/tegra-smmu.c Removed 'default y' and applied to arm/tegra as well. Thanks. Joerg ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver 2012-01-05 7:11 [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi DOYU 2012-01-05 7:11 ` [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Hiroshi DOYU 2012-01-05 7:11 ` [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Hiroshi DOYU @ 2012-01-05 7:17 ` Hiroshi Doyu 2012-01-05 12:53 ` Russell King - ARM Linux 2 siblings, 1 reply; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-05 7:17 UTC (permalink / raw) To: Hiroshi Doyu Cc: iommu, linux-arm-kernel, linux-tegra, linux-kernel, linaro-mm-sig-bounces On Thu, 5 Jan 2012 08:11:47 +0100 Hiroshi Doyu <hdoyu@nvidia.com> wrote: > This patchset adds support for IOMMU API for Tegra20(GART) and > Tegra30(SMMU). "struct iommu_ops" are implemented for both H/W IOMMU > modules. > > Tested with "Ion memory manager" and "DMA mapping API"(*1). Just for DMA mapping test from MPU side, the following one is used. >From a7a163c29694c056e020ba9200648120498e1764 Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU <hdoyu@nvidia.com> Date: Thu, 15 Dec 2011 13:24:24 +0200 Subject: [PATCH 1/1] [NOT-FOR-MERGE] TEST: Simple dma-iommu-mapping API TEST module This is not posted to merge but this is necessary to understand how SMMU/GART works with DMA(-iommu-mapping-)API. This is a test to verify DMA API(DMA iommu mapping API), where SoC specific iommu_ops is used internally. This does alloc/(un)map/free, but there's no actual access from device side since it requires device specific communications. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> --- drivers/iommu/dmaapi-test.c | 193 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 193 insertions(+), 0 deletions(-) create mode 100644 drivers/iommu/dmaapi-test.c diff --git a/drivers/iommu/dmaapi-test.c b/drivers/iommu/dmaapi-test.c new file mode 100644 index 0000000..f386249 --- /dev/null +++ b/drivers/iommu/dmaapi-test.c @@ -0,0 +1,193 @@ +/* + * DMA IOMMU mapping API test module + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Author: Krishna Reddy <vdumpa@nvidia.com>, + * Hiroshi DOYU <hdoyu@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define DEBUG +#define pr_fmt(fmt) KBUILD_MODNAME ":" fmt + +#include <linux/module.h> +#include <linux/dma-mapping.h> +#include <linux/kthread.h> +#include <linux/delay.h> +#include <linux/highmem.h> +#include <linux/pfn.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> + +#include <mach/iomap.h> +#include <mach/smmu.h> + +#include <asm/dma-iommu.h> + +#include "devices.h" + +/* FIXME: 2x and 3x should be supported at once */ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#define IOVA_START TEGRA_GART_BASE +#define IOVA_SIZE TEGRA_GART_SIZE +static struct platform_device *tegra_iommu_device = &tegra_gart_device; +#elif CONFIG_ARCH_TEGRA_3x_SOC +#define IOVA_START TEGRA_SMMU_BASE +#define IOVA_SIZE TEGRA_SMMU_SIZE +static struct platform_device *tegra_iommu_device = &tegra_smmu_device; +#else +#error Unsupported device +#endif + +#define NUM_TEST 3 +#define MAP_SIZE (4 * PAGE_SIZE) + +struct dmaapi_test_case { + char *name; + void (*fn)(struct device *); +}; + +static void dmaapi_test_map_page(struct device *dev) +{ + struct page *page; + dma_addr_t dma_addr; + void *cpu_addr; + + page = alloc_page(GFP_KERNEL); + BUG_ON(!page); + + dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); + BUG_ON(!dma_addr); + + cpu_addr = kmap(page); + BUG_ON(!cpu_addr); + memset(cpu_addr, 0xa5, PAGE_SIZE); + kunmap(cpu_addr); + + pr_debug("pid:%d,%s mapped\t%08x:%08x\n", + current->pid, dev_name(dev), dma_addr, page_to_phys(page)); + + dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_TO_DEVICE); + __free_page(page); +} + +static void dmaapi_test_alloc_coherent(struct device *dev) +{ + dma_addr_t da[NUM_TEST]; + void *va[NUM_TEST]; + int i; + + for (i = 0; i < NUM_TEST; i++) { + void *cpu_addr; + dma_addr_t dma_addr; + + cpu_addr = dma_alloc_coherent(dev, MAP_SIZE, + &dma_addr, GFP_KERNEL); + BUG_ON(!cpu_addr); + memset(cpu_addr, 0xa5, MAP_SIZE); + + pr_debug("pid:%d,%s,[%d] mapped\t%08x:%08x\n", + current->pid, dev_name(dev), i, + dma_addr, virt_to_phys(cpu_addr)); + + da[i] = dma_addr; + va[i] = cpu_addr; + } + + while (--i >= 0) { + pr_debug("pid:%d,%s,[%d] unmapping\t%08x:%08x\n", + current->pid, dev_name(dev), i, + da[i], virt_to_phys(va[i])); + dma_free_coherent(dev, MAP_SIZE, va[i], da[i]); + } +} + +static struct dmaapi_test_case test[] = { + { + .name = "dmaapi/map page", + .fn = dmaapi_test_map_page, + }, + { + .name = "dmaapi/alloc coherent", + .fn = dmaapi_test_alloc_coherent, + }, +}; + +static u32 dummy_hwgrp_map[] = { + HWG_DC | HWG_AFI | HWG_AVPC | HWG_DCB, + HWG_EPP | HWG_HC | HWG_G2 | HWG_MPE | HWG_HDA | HWG_ISP, + HWG_NV | HWG_PPCS | HWG_SATA | HWG_NV2 | HWG_VI | HWG_VDE, +}; + +/* FIXME: Need driver for iommu context? */ +static struct platform_device dmaapi_dummy_device[] = { + { .name = "hwgrp@a", .id = -1, }, + { .name = "hwgrp@b", .id = -1, }, + { .name = "hwgrp@c", .id = -1, }, +}; + +static int dmaapi_test_thread(void *data) +{ + int i; + struct dmaapi_test_case *c = data; + + for (i = 0; true; i++) { + struct device *dev; + int interval[] = {7, 3, 5,}; + int n; + + n = i % ARRAY_SIZE(dmaapi_dummy_device); + ssleep(interval[n]); + dev = &dmaapi_dummy_device[n].dev; + c->fn(dev); + } + return 0; +} + +static int __init dmaapi_test_init(void) +{ + int i; + struct dma_iommu_mapping *map; + + map = arm_iommu_create_mapping(IOVA_START, IOVA_SIZE, 0); + BUG_ON(!map); + pr_debug("Allocate IOVA: %08x-%08x\n", map->base, map->base + IOVA_SIZE); + + for (i = 0; i < ARRAY_SIZE(dmaapi_dummy_device); i++) { + int err; + struct platform_device *pdev = &dmaapi_dummy_device[i]; + + pdev->dev.platform_data = (void *)dummy_hwgrp_map[i]; + pdev->dev.parent = &tegra_iommu_device->dev; + err = platform_device_register(pdev); + BUG_ON(err); + + err = arm_iommu_attach_device(&pdev->dev, map); + BUG_ON(err); + pr_debug("IOMMU API: Attached to %s\n", dev_name(&pdev->dev)); + } + + for (i = 0; i < ARRAY_SIZE(test); i++) + kthread_run(dmaapi_test_thread, &test[i], test[i].name); + + return 0; +} +module_init(dmaapi_test_init); + +MODULE_AUTHOR("Krishna Reddy <vdumpa@nvidia.com>"); +MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); +MODULE_DESCRIPTION("DMA IOMMU mapping API test"); +MODULE_LICENSE("GPL v2"); -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver 2012-01-05 7:17 ` [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi Doyu @ 2012-01-05 12:53 ` Russell King - ARM Linux 2012-01-05 14:29 ` Hiroshi Doyu 2012-01-09 0:39 ` KyongHo Cho 0 siblings, 2 replies; 25+ messages in thread From: Russell King - ARM Linux @ 2012-01-05 12:53 UTC (permalink / raw) To: Hiroshi Doyu Cc: linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel On Thu, Jan 05, 2012 at 09:17:18AM +0200, Hiroshi Doyu wrote: > Just for DMA mapping test from MPU side, the following one is used. This patch is buggy. > +static void dmaapi_test_map_page(struct device *dev) > +{ > + struct page *page; > + dma_addr_t dma_addr; > + void *cpu_addr; > + > + page = alloc_page(GFP_KERNEL); > + BUG_ON(!page); > + > + dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); > + BUG_ON(!dma_addr); > + > + cpu_addr = kmap(page); > + BUG_ON(!cpu_addr); > + memset(cpu_addr, 0xa5, PAGE_SIZE); > + kunmap(cpu_addr); The DMA API works like this: - The CPU owns the page or buffer and can access it. - You map the page or buffer. - The device owns the page or buffer; the CPU must explicitly access it. - You unmap the page or buffer. - The CPU again owns the page/buffer and can access it. Please respect the DMA API rules. So. Once dma_map_page() has returned, you must not kmap() or otherwise access the data contained in that page until after you have unmapped it. ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver 2012-01-05 12:53 ` Russell King - ARM Linux @ 2012-01-05 14:29 ` Hiroshi Doyu 2012-01-05 14:46 ` Russell King - ARM Linux 2012-01-09 0:39 ` KyongHo Cho 1 sibling, 1 reply; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-05 14:29 UTC (permalink / raw) To: linux Cc: linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel Hi Russell, From: Russell King - ARM Linux <linux@arm.linux.org.uk> Subject: Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Date: Thu, 5 Jan 2012 13:53:26 +0100 Message-ID: <20120105125326.GT11810@n2100.arm.linux.org.uk> > On Thu, Jan 05, 2012 at 09:17:18AM +0200, Hiroshi Doyu wrote: > > Just for DMA mapping test from MPU side, the following one is used. > > This patch is buggy. > > > +static void dmaapi_test_map_page(struct device *dev) > > +{ > > + struct page *page; > > + dma_addr_t dma_addr; > > + void *cpu_addr; > > + > > + page = alloc_page(GFP_KERNEL); > > + BUG_ON(!page); > > + > > + dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); > > + BUG_ON(!dma_addr); > > + > > + cpu_addr = kmap(page); > > + BUG_ON(!cpu_addr); > > + memset(cpu_addr, 0xa5, PAGE_SIZE); > > + kunmap(cpu_addr); > > The DMA API works like this: > > - The CPU owns the page or buffer and can access it. > - You map the page or buffer. > - The device owns the page or buffer; the CPU must explicitly access it. > - You unmap the page or buffer. > - The CPU again owns the page/buffer and can access it. > > Please respect the DMA API rules. Right, I do. > So. Once dma_map_page() has returned, you must not kmap() or otherwise > access the data contained in that page until after you have unmapped it. Ok, the above function order should be as below? page = alloc_page(GFP_KERNEL); cpu_addr = kmap(page); memset(cpu_addr, 0xa5, PAGE_SIZE); dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); < expect GPU does something > dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_TO_DEVICE); < CPU can access data here again> kunmap(cpu_addr); __free_page(page); ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver 2012-01-05 14:29 ` Hiroshi Doyu @ 2012-01-05 14:46 ` Russell King - ARM Linux 2012-01-11 14:24 ` Hiroshi Doyu 0 siblings, 1 reply; 25+ messages in thread From: Russell King - ARM Linux @ 2012-01-05 14:46 UTC (permalink / raw) To: Hiroshi Doyu Cc: linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel On Thu, Jan 05, 2012 at 03:29:30PM +0100, Hiroshi Doyu wrote: > Ok, the above function order should be as below? > > page = alloc_page(GFP_KERNEL); > cpu_addr = kmap(page); > memset(cpu_addr, 0xa5, PAGE_SIZE); > dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); > < expect GPU does something > > dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_TO_DEVICE); > < CPU can access data here again> > kunmap(cpu_addr); > __free_page(page); That should work, but it's not particularly nice to wrap kmap around the DMA API. Bear in mind that alloc_page(GFP_KERNEL) will always give you a lowmem page. So, you might as well do: page = alloc_page(GFP_KERNEL); cpu_addr = page_address(page); memset() dma_addr = dma_map_single(dev, cpu_addr, PAGE_SIZE, DMA_TO_DEVICE); < GPU access > dma_unmap_single(dev, dma_ddr, PAGE_SIZE, DMA_TO_DEVICE); < CPU access > __free_page(page); and this doesn't raise any issues with kmap vs DMA API. ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver 2012-01-05 14:46 ` Russell King - ARM Linux @ 2012-01-11 14:24 ` Hiroshi Doyu 0 siblings, 0 replies; 25+ messages in thread From: Hiroshi Doyu @ 2012-01-11 14:24 UTC (permalink / raw) To: linux Cc: linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 1397 bytes --] From: Russell King - ARM Linux <linux@arm.linux.org.uk> Subject: Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Date: Thu, 5 Jan 2012 15:46:31 +0100 Message-ID: <20120105144631.GV11810@n2100.arm.linux.org.uk> > On Thu, Jan 05, 2012 at 03:29:30PM +0100, Hiroshi Doyu wrote: > > Ok, the above function order should be as below? > > > > page = alloc_page(GFP_KERNEL); > > cpu_addr = kmap(page); > > memset(cpu_addr, 0xa5, PAGE_SIZE); > > dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); > > < expect GPU does something > > > dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_TO_DEVICE); > > < CPU can access data here again> > > kunmap(cpu_addr); > > __free_page(page); > > That should work, but it's not particularly nice to wrap kmap around > the DMA API. > > Bear in mind that alloc_page(GFP_KERNEL) will always give you a lowmem > page. So, you might as well do: > > page = alloc_page(GFP_KERNEL); > cpu_addr = page_address(page); > memset() > dma_addr = dma_map_single(dev, cpu_addr, PAGE_SIZE, DMA_TO_DEVICE); > < GPU access > > dma_unmap_single(dev, dma_ddr, PAGE_SIZE, DMA_TO_DEVICE); > < CPU access > > __free_page(page); > > and this doesn't raise any issues with kmap vs DMA API. Attached the update one just in case that someone wants to use it for theirs. [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #2: 0001-NOT-FOR-MERGE-TEST-Simple-dma-iommu-mapping-API-TEST.patch --] [-- Type: text/x-patch; name="0001-NOT-FOR-MERGE-TEST-Simple-dma-iommu-mapping-API-TEST.patch", Size: 6451 bytes --] From 76aefea1c7ad004590295dbe63c27f0c6f482f7a Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU <hdoyu@nvidia.com> Date: Thu, 15 Dec 2011 13:24:24 +0200 Subject: [PATCH 1/1] [NOT-FOR-MERGE] TEST: Simple dma-iommu-mapping API TEST module This is not posted to merge but this is necessary to understand how SMMU/GART works with DMA(-iommu-mapping-)API. This is a test to verify DMA API(DMA iommu mapping API), where SoC specific iommu_ops is used internally. This does alloc/(un)map/free, but there's no actual access from device side since it requires device specific communications. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> --- drivers/iommu/dmaapi-test.c | 202 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 202 insertions(+), 0 deletions(-) create mode 100644 drivers/iommu/dmaapi-test.c diff --git a/drivers/iommu/dmaapi-test.c b/drivers/iommu/dmaapi-test.c new file mode 100644 index 0000000..3199386 --- /dev/null +++ b/drivers/iommu/dmaapi-test.c @@ -0,0 +1,202 @@ +/* + * DMA IOMMU mapping API test module + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Author: Krishna Reddy <vdumpa@nvidia.com>, + * Hiroshi DOYU <hdoyu@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define DEBUG +#define pr_fmt(fmt) KBUILD_MODNAME ":" fmt + +#include <linux/module.h> +#include <linux/dma-mapping.h> +#include <linux/kthread.h> +#include <linux/delay.h> +#include <linux/highmem.h> +#include <linux/pfn.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> + +#include <mach/iomap.h> +#include <mach/smmu.h> + +#include <asm/dma-iommu.h> + +#include "devices.h" + +/* FIXME: 2x and 3x should be supported at once */ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#define IOVA_START TEGRA_GART_BASE +#define IOVA_SIZE TEGRA_GART_SIZE +static struct platform_device *tegra_iommu_device = &tegra_gart_device; +#elif CONFIG_ARCH_TEGRA_3x_SOC +#define IOVA_START TEGRA_SMMU_BASE +#define IOVA_SIZE TEGRA_SMMU_SIZE +static struct platform_device *tegra_iommu_device = &tegra_smmu_device; +#else +#error Unsupported device +#endif + +#define NUM_TEST 3 +#define MAP_SIZE (4 * PAGE_SIZE) + +struct dmaapi_test_case { + char *name; + void (*fn)(struct device *); +}; + +static void dmaapi_test_map_page(struct device *dev) +{ + struct page *page; + dma_addr_t dma_addr; + void *cpu_addr; + + page = alloc_page(GFP_KERNEL); + BUG_ON(!page); + + cpu_addr = page_address(page); + BUG_ON(!cpu_addr); + memset(cpu_addr, 0xa5, PAGE_SIZE); + + dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); + BUG_ON(!dma_addr); + + pr_debug("pid:%d,%s mapped\t%08x:%08x\n", + current->pid, dev_name(dev), dma_addr, page_to_phys(page)); + + /* + * Expect GPU access + */ + + dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_TO_DEVICE); + + /* + * CPU access + */ + BUG_ON(*(char *)cpu_addr != 0xa5); + + __free_page(page); +} + +static void dmaapi_test_alloc_coherent(struct device *dev) +{ + dma_addr_t da[NUM_TEST]; + void *va[NUM_TEST]; + int i; + + for (i = 0; i < NUM_TEST; i++) { + void *cpu_addr; + dma_addr_t dma_addr; + + cpu_addr = dma_alloc_coherent(dev, MAP_SIZE, + &dma_addr, GFP_KERNEL); + BUG_ON(!cpu_addr); + memset(cpu_addr, 0xa5, MAP_SIZE); + + pr_debug("pid:%d,%s,[%d] mapped\t%08x:%08x\n", + current->pid, dev_name(dev), i, + dma_addr, virt_to_phys(cpu_addr)); + + da[i] = dma_addr; + va[i] = cpu_addr; + } + + while (--i >= 0) { + pr_debug("pid:%d,%s,[%d] unmapping\t%08x:%08x\n", + current->pid, dev_name(dev), i, + da[i], virt_to_phys(va[i])); + dma_free_coherent(dev, MAP_SIZE, va[i], da[i]); + } +} + +static struct dmaapi_test_case test[] = { + { + .name = "dmaapi/map page", + .fn = dmaapi_test_map_page, + }, + { + .name = "dmaapi/alloc coherent", + .fn = dmaapi_test_alloc_coherent, + }, +}; + +static u32 dummy_hwgrp_map[] = { + HWG_DC | HWG_AFI | HWG_AVPC | HWG_DCB, + HWG_EPP | HWG_HC | HWG_G2 | HWG_MPE | HWG_HDA | HWG_ISP, + HWG_NV | HWG_PPCS | HWG_SATA | HWG_NV2 | HWG_VI | HWG_VDE, +}; + +/* FIXME: Need driver for iommu context? */ +static struct platform_device dmaapi_dummy_device[] = { + { .name = "hwgrp@a", .id = -1, }, + { .name = "hwgrp@b", .id = -1, }, + { .name = "hwgrp@c", .id = -1, }, +}; + +static int dmaapi_test_thread(void *data) +{ + int i; + struct dmaapi_test_case *c = data; + + for (i = 0; true; i++) { + struct device *dev; + int interval[] = {7, 3, 5,}; + int n; + + n = i % ARRAY_SIZE(dmaapi_dummy_device); + ssleep(interval[n]); + dev = &dmaapi_dummy_device[n].dev; + c->fn(dev); + } + return 0; +} + +static int __init dmaapi_test_init(void) +{ + int i; + struct dma_iommu_mapping *map; + + map = arm_iommu_create_mapping(IOVA_START, IOVA_SIZE, 0); + BUG_ON(!map); + pr_debug("Allocate IOVA: %08x-%08x\n", map->base, map->base + IOVA_SIZE); + + for (i = 0; i < ARRAY_SIZE(dmaapi_dummy_device); i++) { + int err; + struct platform_device *pdev = &dmaapi_dummy_device[i]; + + pdev->dev.platform_data = (void *)dummy_hwgrp_map[i]; + pdev->dev.parent = &tegra_iommu_device->dev; + err = platform_device_register(pdev); + BUG_ON(err); + + err = arm_iommu_attach_device(&pdev->dev, map); + BUG_ON(err); + pr_debug("IOMMU API: Attached to %s\n", dev_name(&pdev->dev)); + } + + for (i = 0; i < ARRAY_SIZE(test); i++) + kthread_run(dmaapi_test_thread, &test[i], test[i].name); + + return 0; +} +module_init(dmaapi_test_init); + +MODULE_AUTHOR("Krishna Reddy <vdumpa@nvidia.com>"); +MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); +MODULE_DESCRIPTION("DMA IOMMU mapping API test"); +MODULE_LICENSE("GPL v2"); -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver 2012-01-05 12:53 ` Russell King - ARM Linux 2012-01-05 14:29 ` Hiroshi Doyu @ 2012-01-09 0:39 ` KyongHo Cho 2012-01-09 11:45 ` Russell King - ARM Linux 1 sibling, 1 reply; 25+ messages in thread From: KyongHo Cho @ 2012-01-09 0:39 UTC (permalink / raw) To: Russell King - ARM Linux Cc: Hiroshi Doyu, linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel On Thu, Jan 5, 2012 at 9:53 PM, Russell King - ARM Linux <linux@arm.linux.org.uk> wrote: > On Thu, Jan 05, 2012 at 09:17:18AM +0200, Hiroshi Doyu wrote: >> Just for DMA mapping test from MPU side, the following one is used. > > This patch is buggy. > >> +static void dmaapi_test_map_page(struct device *dev) >> +{ >> + struct page *page; >> + dma_addr_t dma_addr; >> + void *cpu_addr; >> + >> + page = alloc_page(GFP_KERNEL); >> + BUG_ON(!page); >> + >> + dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); >> + BUG_ON(!dma_addr); >> + >> + cpu_addr = kmap(page); >> + BUG_ON(!cpu_addr); >> + memset(cpu_addr, 0xa5, PAGE_SIZE); >> + kunmap(cpu_addr); > > The DMA API works like this: > > - The CPU owns the page or buffer and can access it. > - You map the page or buffer. > - The device owns the page or buffer; the CPU must explicitly access it. I don't understand what "CPU must __explicitly__ access it" means. Do you mean that CPU must access the mapped buffer when it __explicitly__ knows that the access does not cause any side effect? > - You unmap the page or buffer. > - The CPU again owns the page/buffer and can access it. > > Please respect the DMA API rules. > > So. Once dma_map_page() has returned, you must not kmap() or otherwise > access the data contained in that page until after you have unmapped it. > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver 2012-01-09 0:39 ` KyongHo Cho @ 2012-01-09 11:45 ` Russell King - ARM Linux 0 siblings, 0 replies; 25+ messages in thread From: Russell King - ARM Linux @ 2012-01-09 11:45 UTC (permalink / raw) To: KyongHo Cho Cc: Hiroshi Doyu, linux-tegra, linaro-mm-sig-bounces, iommu, linux-kernel, linux-arm-kernel On Mon, Jan 09, 2012 at 09:39:48AM +0900, KyongHo Cho wrote: > On Thu, Jan 5, 2012 at 9:53 PM, Russell King - ARM Linux > <linux@arm.linux.org.uk> wrote: > > On Thu, Jan 05, 2012 at 09:17:18AM +0200, Hiroshi Doyu wrote: > >> Just for DMA mapping test from MPU side, the following one is used. > > > > This patch is buggy. > > > >> +static void dmaapi_test_map_page(struct device *dev) > >> +{ > >> + struct page *page; > >> + dma_addr_t dma_addr; > >> + void *cpu_addr; > >> + > >> + page = alloc_page(GFP_KERNEL); > >> + BUG_ON(!page); > >> + > >> + dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_TO_DEVICE); > >> + BUG_ON(!dma_addr); > >> + > >> + cpu_addr = kmap(page); > >> + BUG_ON(!cpu_addr); > >> + memset(cpu_addr, 0xa5, PAGE_SIZE); > >> + kunmap(cpu_addr); > > > > The DMA API works like this: > > > > - The CPU owns the page or buffer and can access it. > > - You map the page or buffer. > > - The device owns the page or buffer; the CPU must explicitly access it. Sorry, that 'must' should have been a 'must not'. > I don't understand what "CPU must __explicitly__ access it" means. > > Do you mean that CPU must access the mapped buffer when > it __explicitly__ knows that the access does not cause any side effect? No - I mean that the program must not attempt to read or write the buffer. ^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2012-01-26 14:59 UTC | newest] Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-01-05 7:11 [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi DOYU 2012-01-05 7:11 ` [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Hiroshi DOYU 2012-01-23 15:00 ` Joerg Roedel 2012-01-25 7:40 ` Hiroshi Doyu 2012-01-26 11:58 ` joro 2012-01-26 14:45 ` Hiroshi Doyu 2012-01-05 7:11 ` [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Hiroshi DOYU 2012-01-23 15:43 ` Joerg Roedel 2012-01-24 9:57 ` Hiroshi Doyu 2012-01-24 11:04 ` Joerg Roedel 2012-01-24 11:36 ` Hiroshi Doyu 2012-01-24 11:57 ` joerg.roedel 2012-01-24 12:07 ` Hiroshi Doyu 2012-01-24 13:41 ` Hiroshi Doyu 2012-01-24 13:46 ` Felipe Balbi 2012-01-24 14:25 ` joro 2012-01-25 7:39 ` Hiroshi Doyu 2012-01-26 14:59 ` joro 2012-01-05 7:17 ` [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi Doyu 2012-01-05 12:53 ` Russell King - ARM Linux 2012-01-05 14:29 ` Hiroshi Doyu 2012-01-05 14:46 ` Russell King - ARM Linux 2012-01-11 14:24 ` Hiroshi Doyu 2012-01-09 0:39 ` KyongHo Cho 2012-01-09 11:45 ` Russell King - ARM Linux
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).