* [PATCH] x86: cache_info: Fix setup of l2/l3 ids
@ 2012-04-06 12:38 Ido Yariv
2012-04-19 22:09 ` [PATCH RESEND] " Ido Yariv
0 siblings, 1 reply; 4+ messages in thread
From: Ido Yariv @ 2012-04-06 12:38 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner, Ingo Molnar, H. Peter Anvin
Cc: Shai Fultheim, Ido Yariv
From: Shai Fultheim <shai@scalemp.com>
On some architectures (such as vSMP), it is possible to have CPUs with a
different number of cores sharing the same cache.
The current implementation implicitly assumes that all CPUs will have
the same number of cores sharing caches, and as a result, different CPUs
can end up with the same l2/l3 ids.
Fix this by masking out the shared cache bits, instead of shifting the
APICID. By doing so, it is guaranteed that the generated cache ids are
always unique.
Signed-off-by: Shai Fultheim <shai@scalemp.com>
[ido@wizery.com: rebased, simplified, and reworded the commit message]
Signed-off-by: Ido Yariv <ido@wizery.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 73d08ed..caa6cb0 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -615,14 +615,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
new_l2 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(num_threads_sharing);
- l2_id = c->apicid >> index_msb;
+ l2_id = c->apicid & ~((1 << index_msb) - 1);
break;
case 3:
new_l3 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(
num_threads_sharing);
- l3_id = c->apicid >> index_msb;
+ l3_id = c->apicid & ~((1 << index_msb) - 1);
break;
default:
break;
--
1.7.7.6
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH RESEND] x86: cache_info: Fix setup of l2/l3 ids
2012-04-06 12:38 [PATCH] x86: cache_info: Fix setup of l2/l3 ids Ido Yariv
@ 2012-04-19 22:09 ` Ido Yariv
2012-05-05 23:46 ` Ido Yariv
2012-05-08 4:24 ` [tip:x86/cpu] x86/cache_info: " tip-bot for Shai Fultheim
0 siblings, 2 replies; 4+ messages in thread
From: Ido Yariv @ 2012-04-19 22:09 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner, Ingo Molnar, H. Peter Anvin
Cc: Shai Fultheim, Ido Yariv
From: Shai Fultheim <shai@scalemp.com>
On some architectures (such as vSMP), it is possible to have CPUs with a
different number of cores sharing the same cache.
The current implementation implicitly assumes that all CPUs will have
the same number of cores sharing caches, and as a result, different CPUs
can end up with the same l2/l3 ids.
Fix this by masking out the shared cache bits, instead of shifting the
APICID. By doing so, it is guaranteed that the generated cache ids are
always unique.
Signed-off-by: Shai Fultheim <shai@scalemp.com>
[ido@wizery.com: rebased, simplified, and reworded the commit message]
Signed-off-by: Ido Yariv <ido@wizery.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 73d08ed..caa6cb0 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -615,14 +615,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
new_l2 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(num_threads_sharing);
- l2_id = c->apicid >> index_msb;
+ l2_id = c->apicid & ~((1 << index_msb) - 1);
break;
case 3:
new_l3 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(
num_threads_sharing);
- l3_id = c->apicid >> index_msb;
+ l3_id = c->apicid & ~((1 << index_msb) - 1);
break;
default:
break;
--
1.7.7.6
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH RESEND] x86: cache_info: Fix setup of l2/l3 ids
2012-04-19 22:09 ` [PATCH RESEND] " Ido Yariv
@ 2012-05-05 23:46 ` Ido Yariv
2012-05-08 4:24 ` [tip:x86/cpu] x86/cache_info: " tip-bot for Shai Fultheim
1 sibling, 0 replies; 4+ messages in thread
From: Ido Yariv @ 2012-05-05 23:46 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner, Ingo Molnar, H. Peter Anvin
Cc: Shai Fultheim, Ido Yariv
On Fri, Apr 20, 2012 at 1:09 AM, Ido Yariv <ido@wizery.com> wrote:
> From: Shai Fultheim <shai@scalemp.com>
>
> On some architectures (such as vSMP), it is possible to have CPUs with a
> different number of cores sharing the same cache.
>
> The current implementation implicitly assumes that all CPUs will have
> the same number of cores sharing caches, and as a result, different CPUs
> can end up with the same l2/l3 ids.
>
> Fix this by masking out the shared cache bits, instead of shifting the
> APICID. By doing so, it is guaranteed that the generated cache ids are
> always unique.
>
> Signed-off-by: Shai Fultheim <shai@scalemp.com>
> [ido@wizery.com: rebased, simplified, and reworded the commit message]
> Signed-off-by: Ido Yariv <ido@wizery.com>
Ping?
^ permalink raw reply [flat|nested] 4+ messages in thread
* [tip:x86/cpu] x86/cache_info: Fix setup of l2/l3 ids
2012-04-19 22:09 ` [PATCH RESEND] " Ido Yariv
2012-05-05 23:46 ` Ido Yariv
@ 2012-05-08 4:24 ` tip-bot for Shai Fultheim
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot for Shai Fultheim @ 2012-05-08 4:24 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, travis, andreas.herrmann3, davej, shai,
tglx, ido, borislav.petkov
Commit-ID: ddc5681ed33a279fdc188e98e71f0c539f08c6e6
Gitweb: http://git.kernel.org/tip/ddc5681ed33a279fdc188e98e71f0c539f08c6e6
Author: Shai Fultheim <shai@scalemp.com>
AuthorDate: Fri, 20 Apr 2012 01:09:11 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 7 May 2012 15:27:37 +0200
x86/cache_info: Fix setup of l2/l3 ids
On some architectures (such as vSMP), it is possible to have
CPUs with a different number of cores sharing the same cache.
The current implementation implicitly assumes that all CPUs will
have the same number of cores sharing caches, and as a result,
different CPUs can end up with the same l2/l3 ids.
Fix this by masking out the shared cache bits, instead of
shifting the APICID. By doing so, it is guaranteed that the
generated cache ids are always unique.
Signed-off-by: Shai Fultheim <shai@scalemp.com>
[ rebased, simplified, and reworded the commit message]
Signed-off-by: Ido Yariv <ido@wizery.com>
Cc: Borislav Petkov <borislav.petkov@amd.com>
Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Mike Travis <travis@sgi.com>
Cc: Dave Jones <davej@redhat.com>
Link: http://lkml.kernel.org/r/1334873351-31142-1-git-send-email-ido@wizery.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index b8f3653..9a7c90d 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -615,14 +615,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
new_l2 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(num_threads_sharing);
- l2_id = c->apicid >> index_msb;
+ l2_id = c->apicid & ~((1 << index_msb) - 1);
break;
case 3:
new_l3 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(
num_threads_sharing);
- l3_id = c->apicid >> index_msb;
+ l3_id = c->apicid & ~((1 << index_msb) - 1);
break;
default:
break;
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2012-04-06 12:38 [PATCH] x86: cache_info: Fix setup of l2/l3 ids Ido Yariv
2012-04-19 22:09 ` [PATCH RESEND] " Ido Yariv
2012-05-05 23:46 ` Ido Yariv
2012-05-08 4:24 ` [tip:x86/cpu] x86/cache_info: " tip-bot for Shai Fultheim
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