From: Jiang Liu <liuj97@gmail.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Don Dutile <ddutile@redhat.com>,
Jeff Kirsher <jeffrey.t.kirsher@intel.com>,
Jesse Brandeburg <jesse.brandeburg@intel.com>,
Bruce Allan <bruce.w.allan@intel.com>,
Carolyn Wyborny <carolyn.wyborny@intel.com>,
Don Skidmore <donald.c.skidmore@intel.com>,
Greg Rose <gregory.v.rose@intel.com>,
Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>,
Alex Duyck <alexander.h.duyck@intel.com>,
John Ronciak <john.ronciak@intel.com>
Cc: Jiang Liu <jiang.liu@huawei.com>, Yinghai Lu <yinghai@kernel.org>,
Taku Izumi <izumi.taku@jp.fujitsu.com>,
"Rafael J . Wysocki" <rjw@sisk.pl>,
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>,
Yijing Wang <wangyijing@huawei.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
Jiang Liu <liuj97@gmail.com>
Subject: [PATCH v3 17/32] PCI/igb: use PCIe capabilities access functions to simplify implementation
Date: Wed, 1 Aug 2012 23:54:22 +0800 [thread overview]
Message-ID: <1343836477-7287-18-git-send-email-jiang.liu@huawei.com> (raw)
In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
From: Jiang Liu <jiang.liu@huawei.com>
Use PCIe capabilities access functions to simplify Intel ethernet drivers'
implementation.
Signed-off-by: Jiang Liu <liuj97@gmail.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
drivers/net/ethernet/intel/e1000e/netdev.c | 27 ++++++++-------------------
drivers/net/ethernet/intel/igb/igb_main.c | 12 ++----------
2 files changed, 10 insertions(+), 29 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index a4b0435..30b647f 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -5582,16 +5582,15 @@ static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
*/
if (adapter->flags & FLAG_IS_QUAD_PORT) {
struct pci_dev *us_dev = pdev->bus->self;
- int pos = pci_pcie_cap(us_dev);
u16 devctl;
- pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
- pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
- (devctl & ~PCI_EXP_DEVCTL_CERE));
+ pci_pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
+ pci_pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
+ (devctl & ~PCI_EXP_DEVCTL_CERE));
e1000_power_off(pdev, sleep, wake);
- pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
+ pci_pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
} else {
e1000_power_off(pdev, sleep, wake);
}
@@ -5605,25 +5604,15 @@ static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
#else
static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
{
- int pos;
- u16 reg16;
-
/*
* Both device and parent should have the same ASPM setting.
* Disable ASPM in downstream component first and then upstream.
*/
- pos = pci_pcie_cap(pdev);
- pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
- reg16 &= ~state;
- pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
-
- if (!pdev->bus->self)
- return;
+ pci_pcie_capability_change_word(pdev, PCI_EXP_LNKCTL, 0, state);
- pos = pci_pcie_cap(pdev->bus->self);
- pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, ®16);
- reg16 &= ~state;
- pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
+ if (pdev->bus->self)
+ pci_pcie_capability_change_word(pdev->bus->self, PCI_EXP_LNKCTL,
+ 0, state);
}
#endif
static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index dd3bfe8..3d46830 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -6446,28 +6446,20 @@ static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
{
struct igb_adapter *adapter = hw->back;
- u16 cap_offset;
- cap_offset = adapter->pdev->pcie_cap;
- if (!cap_offset)
+ if (pci_pcie_capability_read_word(adapter->pdev, reg, value))
return -E1000_ERR_CONFIG;
- pci_read_config_word(adapter->pdev, cap_offset + reg, value);
-
return 0;
}
s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
{
struct igb_adapter *adapter = hw->back;
- u16 cap_offset;
- cap_offset = adapter->pdev->pcie_cap;
- if (!cap_offset)
+ if (pci_pcie_capability_write_word(adapter->pdev, reg, *value))
return -E1000_ERR_CONFIG;
- pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
-
return 0;
}
--
1.7.9.5
next prev parent reply other threads:[~2012-08-01 15:58 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-01 15:54 [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers Jiang Liu
2012-08-01 15:54 ` [PATCH v3 01/32] PCI: add pcie_flags_reg into struct pci_dev to cache PCIe capabilities register Jiang Liu
2012-08-01 15:54 ` [PATCH v3 02/32] PCI: introduce pci_pcie_type(dev) to replace pci_dev->pcie_type Jiang Liu
2012-08-01 15:54 ` [PATCH v3 03/32] PCI: remove unused field pcie_type from struct pci_dev Jiang Liu
2012-08-01 15:54 ` [PATCH v3 04/32] PCI: add PCIe capabilities access functions to hide differences among PCIe specs Jiang Liu
2012-08-01 15:54 ` [PATCH v3 05/32] PCI/core: use PCIe capabilities access functions to simplify implementation Jiang Liu
2012-08-01 15:54 ` [PATCH v3 06/32] PCI/hotplug: " Jiang Liu
2012-08-02 1:30 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 07/32] PCI/portdrv: " Jiang Liu
2012-08-02 1:33 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 08/32] PCI/pciehp: " Jiang Liu
2012-08-02 1:37 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 09/32] PCI/PME: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 10/32] PCI/AER: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 11/32] PCI/ASPM: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 12/32] PCI/ARM: " Jiang Liu
2012-08-01 17:20 ` Stephen Warren
2012-08-02 5:58 ` Thierry Reding
2012-08-03 18:05 ` Stephen Warren
2012-08-01 15:54 ` [PATCH v3 13/32] PCI/MIPS: " Jiang Liu
2012-08-13 21:40 ` David Daney
2012-08-01 15:54 ` [PATCH v3 14/32] PCI/tile: " Jiang Liu
2012-08-01 21:07 ` Chris Metcalf
2012-08-01 15:54 ` [PATCH v3 15/32] PCI/r8169: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 16/32] PCI/broadcom: " Jiang Liu
2012-08-01 15:54 ` Jiang Liu [this message]
2012-08-02 22:12 ` [PATCH v3 17/32] PCI/igb: " Jeff Kirsher
2012-08-01 15:54 ` [PATCH v3 18/32] PCI/vxge: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 19/32] PCI/mlx4: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 20/32] PCI/niu: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 21/32] PCI/myri10ge: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 22/32] PCI/chelsio: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 23/32] PCI/atl1c: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 24/32] PCI/ath9k: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 25/32] PCI/iwl: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 26/32] PCI/mthca: " Jiang Liu
2012-08-02 21:46 ` Roland Dreier
2012-08-01 15:54 ` [PATCH v3 27/32] PCI/qib: " Jiang Liu
2012-08-01 17:30 ` Marciniszyn, Mike
2012-08-01 15:54 ` [PATCH v3 28/32] PCI/qla: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 29/32] PCI/radeon: " Jiang Liu
2012-08-01 16:04 ` Deucher, Alexander
2012-08-01 15:54 ` [PATCH v3 30/32] PCI/tsi721: " Jiang Liu
2012-08-09 14:16 ` Bounine, Alexandre
2012-08-01 15:54 ` [PATCH v3 31/32] PCI/et131x: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 32/32] PCI/rtl8192e: " Jiang Liu
2012-08-14 4:25 ` [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers Bjorn Helgaas
2012-08-14 15:46 ` Jiang Liu
2012-08-20 15:26 ` Jiang Liu
2012-08-20 15:35 ` Bjorn Helgaas
2012-08-20 15:47 ` Jiang Liu
2012-08-20 16:10 ` Bjorn Helgaas
2012-08-20 22:13 ` Bjorn Helgaas
2012-08-21 4:40 ` Cui, Dexuan
2012-08-22 16:28 ` Bjorn Helgaas
2012-08-23 1:00 ` Cui, Dexuan
2012-08-23 1:51 ` Don Dutile
2012-08-21 15:59 ` Jiang Liu
2012-08-22 17:08 ` Bjorn Helgaas
2012-08-24 18:52 ` Bjorn Helgaas
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