[PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[Fengguang Wu]

Sorry I have no compilers for build testing these changes, however the
risk looks low and it's much better than to leave the arch broken,
considering that Eric will do atomic64_t in the core fs/namespace.c code.

CC: "Eric W. Biederman" <ebiederm@xmission.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---

Andrew: the arch maintainers have been CCed. Best is the maintainers
respond, test and perhaps take the corresponding change. Let's see how
this will work out..


 arch/c6x/Kconfig       |    1 +
 arch/score/Kconfig     |    1 +
 arch/unicore32/Kconfig |    1 +
 3 files changed, 3 insertions(+)

--- linux.orig/arch/c6x/Kconfig	2012-06-14 22:29:58.187502107 +0800
+++ linux/arch/c6x/Kconfig	2012-08-14 23:23:18.147838692 +0800
@@ -16,6 +16,7 @@ config C6X
 	select OF
 	select OF_EARLY_FLATTREE
 	select GENERIC_CLOCKEVENTS
+	select GENERIC_ATOMIC64
 
 config MMU
 	def_bool n
--- linux.orig/arch/score/Kconfig	2012-06-14 22:29:58.219502109 +0800
+++ linux/arch/score/Kconfig	2012-08-14 23:23:37.691839156 +0800
@@ -10,6 +10,7 @@ config SCORE
        select ARCH_DISCARD_MEMBLOCK
        select GENERIC_CPU_DEVICES
        select GENERIC_CLOCKEVENTS
+       select GENERIC_ATOMIC64
 
 choice
 	prompt "System type"
--- linux.orig/arch/unicore32/Kconfig	2012-07-25 19:09:37.671358715 +0800
+++ linux/arch/unicore32/Kconfig	2012-08-14 23:23:52.351839505 +0800
@@ -14,6 +14,7 @@ config UNICORE32
 	select GENERIC_IRQ_SHOW
 	select ARCH_WANT_FRAME_POINTERS
 	select GENERIC_IOMAP
+	select GENERIC_ATOMIC64
 	help
 	  UniCore-32 is 32-bit Instruction Set Architecture,
 	  including a series of low-power-consumption RISC chip

Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[Mark Salter]

On Tue, 2012-08-14 at 23:34 +0800, Fengguang Wu wrote:
> Sorry I have no compilers for build testing these changes, however the
> risk looks low and it's much better than to leave the arch broken,
> considering that Eric will do atomic64_t in the core fs/namespace.c
> code.
> 
> CC: "Eric W. Biederman" <ebiederm@xmission.com>
> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
> ---
> 
> Andrew: the arch maintainers have been CCed. Best is the maintainers
> respond, test and perhaps take the corresponding change. Let's see how
> this will work out..
> 
> 
>  arch/c6x/Kconfig       |    1 +

The c6x port also needs this:

C6X: add L*_CACHE_SHIFT defines
    
C6X currently lacks L*_CACHE_SHIFT defines which are used in a few
places in the generic kernel. This patch adds those missing defines.
    
Signed-off-by: Mark Salter <msalter@redhat.com>
---

diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
index 6d521d9..feff1d7 100644
--- a/arch/c6x/include/asm/cache.h
+++ b/arch/c6x/include/asm/cache.h
@@ -1,7 +1,7 @@
 /*
  *  Port on Texas Instruments TMS320C6x architecture
  *
- *  Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
+ *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -16,9 +16,14 @@
 /*
  * Cache line size
  */
-#define L1D_CACHE_BYTES   64
-#define L1P_CACHE_BYTES   32
-#define L2_CACHE_BYTES   128
+#define L1D_CACHE_SHIFT   6
+#define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)
+
+#define L1P_CACHE_SHIFT   5
+#define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)
+
+#define L2_CACHE_SHIFT    7
+#define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)
 
 /*
  * L2 used as cache
@@ -29,7 +34,8 @@
  * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
  * the L2 line size
  */
-#define L1_CACHE_BYTES        L2_CACHE_BYTES
+#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
+#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)
 
 #define L2_CACHE_ALIGN_LOW(x) \
        (((x) & ~(L2_CACHE_BYTES - 1)))

Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[Fengguang Wu]

On Tue, Aug 14, 2012 at 12:22:49PM -0400, Mark Salter wrote:
> On Tue, 2012-08-14 at 23:34 +0800, Fengguang Wu wrote:
> > Sorry I have no compilers for build testing these changes, however the
> > risk looks low and it's much better than to leave the arch broken,
> > considering that Eric will do atomic64_t in the core fs/namespace.c
> > code.
> > 
> > CC: "Eric W. Biederman" <ebiederm@xmission.com>
> > Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
> > ---
> > 
> > Andrew: the arch maintainers have been CCed. Best is the maintainers
> > respond, test and perhaps take the corresponding change. Let's see how
> > this will work out..
> > 
> > 
> >  arch/c6x/Kconfig       |    1 +
> 
> The c6x port also needs this:
> 
> C6X: add L*_CACHE_SHIFT defines
>     
> C6X currently lacks L*_CACHE_SHIFT defines which are used in a few
> places in the generic kernel. This patch adds those missing defines.
>     
> Signed-off-by: Mark Salter <msalter@redhat.com>

Thanks for the quick fix! git grep shows this:

        lib/atomic64.c: addr >>= L1_CACHE_SHIFT;

So this patch is a prerequisite for the GENERIC_ATOMIC64 patch.

git grep also shows

        arch/score/include/asm/cache.h:#define L1_CACHE_SHIFT           4

        arch/unicore32/include/asm/cache.h:#define L1_CACHE_SHIFT (5)

So the other two archs are fine.

Thanks,
Fengguang

Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[Fengguang Wu]

> -#define L1_CACHE_BYTES        L2_CACHE_BYTES
> +#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
> +#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)

Nitpick: the last line could better be:

+#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)

Reviewed-by: Fengguang Wu <fengguang.wu@intel.com>

Thanks!

Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[guanxuetao]

> Sorry I have no compilers for build testing these changes, however the
> risk looks low and it's much better than to leave the arch broken,
> considering that Eric will do atomic64_t in the core fs/namespace.c code.
>
> CC: "Eric W. Biederman" <ebiederm@xmission.com>
> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
It looks ok for unicore32.

Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>

Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[Mark Salter]

On Wed, 2012-08-15 at 10:36 +0800, Fengguang Wu wrote:
> > -#define L1_CACHE_BYTES        L2_CACHE_BYTES
> > +#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
> > +#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)
> 
> Nitpick: the last line could better be:
> 
> +#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
> 
> Reviewed-by: Fengguang Wu <fengguang.wu@intel.com>

Yes, I noticed that after sending the patch.

Should I push this through the c6x tree?

--Mark

Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[Fengguang Wu]

On Wed, Aug 15, 2012 at 09:42:58AM -0400, Mark Salter wrote:
> On Wed, 2012-08-15 at 10:36 +0800, Fengguang Wu wrote:
> > > -#define L1_CACHE_BYTES        L2_CACHE_BYTES
> > > +#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
> > > +#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)
> > 
> > Nitpick: the last line could better be:
> > 
> > +#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
> > 
> > Reviewed-by: Fengguang Wu <fengguang.wu@intel.com>
> 
> Yes, I noticed that after sending the patch.
> 
> Should I push this through the c6x tree?

That'd be good. For consistency, will you also include the
GENERIC_ATOMIC64 chunk in the titled patch?

I can send Andrew an updated series (reducing the c6x changes, and
possibly the score/unicore32 bits) later on.

Thanks,
Fengguang

Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

[Mark Salter]

On Wed, 2012-08-15 at 22:12 +0800, Fengguang Wu wrote:
> > Should I push this through the c6x tree?
> 
> That'd be good. For consistency, will you also include the
> GENERIC_ATOMIC64 chunk in the titled patch?
> 
> I can send Andrew an updated series (reducing the c6x changes, and
> possibly the score/unicore32 bits) later on.

Ok. Will do.