linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
@ 2012-11-20  0:57 Jonghwan Choi
  2012-11-20  1:39 ` Kyungmin Park
  2012-11-22  2:18 ` Zhang Rui
  0 siblings, 2 replies; 8+ messages in thread
From: Jonghwan Choi @ 2012-11-20  0:57 UTC (permalink / raw)
  To: 'Jonghwan Choi', 'open list'
  Cc: 'Amit Daniel Kachhap', 'Sachin Kamat',
	'Zhang Rui'

[0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.

Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
---
 drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/thermal/exynos_thermal.c
b/drivers/thermal/exynos_thermal.c
index 6dd29e4..129e827 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -52,9 +52,12 @@

 #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
 #define EXYNOS_TMU_GAIN_SHIFT          8
+#define EXYNOS_TMU_GAIN_MASK           (0xF << EXYNOS_TMU_GAIN_SHIFT)
 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
-#define EXYNOS_TMU_CORE_ON             3
-#define EXYNOS_TMU_CORE_OFF            2
+#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
EXYNOS_TMU_REF_VOLTAGE_SHIFT)
+#define EXYNOS_TMU_CORE_ON             BIT(0)
+#define EXYNOS_TMU_CORE_ON_SHIFT       0
+#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
EXYNOS_TMU_CORE_ON_SHIFT)
 #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50

 /* Exynos4210 specific registers */
@@ -85,7 +88,9 @@
 #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
 #define EXYNOS_MUX_ADDR_VALUE          6
 #define EXYNOS_MUX_ADDR_SHIFT          20
+#define EXYNOS_MUX_ADDR_MASK           (0x7 << EXYNOS_MUX_ADDR_SHIFT)
 #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
+#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 << EXYNOS_TMU_TRIP_MODE_SHIFT)

 #define EFUSE_MIN_VALUE 40
 #define EFUSE_MAX_VALUE 100
@@ -650,10 +655,14 @@ static void exynos_tmu_control(struct platform_device
*pdev, bool on)
        mutex_lock(&data->lock);
        clk_enable(data->clk);

-       con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
+       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
+       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
+               EXYNOS_TMU_CORE_ON_MASK);
+       con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
                pdata->gain << EXYNOS_TMU_GAIN_SHIFT;

        if (data->soc == SOC_ARCH_EXYNOS) {
+               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK | EXYNOS_MUX_ADDR_MASK);
                con |= pdata->noise_cancel_mode <<
EXYNOS_TMU_TRIP_MODE_SHIFT;
                con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
        }
@@ -665,7 +674,6 @@ static void exynos_tmu_control(struct platform_device
*pdev, bool on)
                        pdata->trigger_level1_en << 4 |
                        pdata->trigger_level0_en;
        } else {
-               con |= EXYNOS_TMU_CORE_OFF;
                interrupt_en = 0; /* Disable all interrupts */
        }
        writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
--
1.7.4.1


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
  2012-11-20  0:57 [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core Jonghwan Choi
@ 2012-11-20  1:39 ` Kyungmin Park
  2012-11-20  5:53   ` Zhang Rui
  2012-11-22  2:18 ` Zhang Rui
  1 sibling, 1 reply; 8+ messages in thread
From: Kyungmin Park @ 2012-11-20  1:39 UTC (permalink / raw)
  To: Jonghwan Choi, jonghwa3.lee
  Cc: open list, Amit Daniel Kachhap, Sachin Kamat, Zhang Rui

On 11/20/12, Jonghwan Choi <jhbird.choi@samsung.com> wrote:
> [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
>
> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
>  1 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/thermal/exynos_thermal.c
> b/drivers/thermal/exynos_thermal.c
> index 6dd29e4..129e827 100644
> --- a/drivers/thermal/exynos_thermal.c
> +++ b/drivers/thermal/exynos_thermal.c
> @@ -52,9 +52,12 @@
>
>  #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
>  #define EXYNOS_TMU_GAIN_SHIFT          8
> +#define EXYNOS_TMU_GAIN_MASK           (0xF << EXYNOS_TMU_GAIN_SHIFT)
>  #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
> -#define EXYNOS_TMU_CORE_ON             3
> -#define EXYNOS_TMU_CORE_OFF            2
> +#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
> EXYNOS_TMU_REF_VOLTAGE_SHIFT)
> +#define EXYNOS_TMU_CORE_ON             BIT(0)
> +#define EXYNOS_TMU_CORE_ON_SHIFT       0
> +#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
> EXYNOS_TMU_CORE_ON_SHIFT)
>  #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50
>
>  /* Exynos4210 specific registers */
> @@ -85,7 +88,9 @@
>  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
>  #define EXYNOS_MUX_ADDR_VALUE          6
>  #define EXYNOS_MUX_ADDR_SHIFT          20
> +#define EXYNOS_MUX_ADDR_MASK           (0x7 << EXYNOS_MUX_ADDR_SHIFT)
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
> +#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 << EXYNOS_TMU_TRIP_MODE_SHIFT)
>
>  #define EFUSE_MIN_VALUE 40
>  #define EFUSE_MAX_VALUE 100
> @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct platform_device
> *pdev, bool on)
>         mutex_lock(&data->lock);
>         clk_enable(data->clk);
>
> -       con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
> +       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
> +       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
> +               EXYNOS_TMU_CORE_ON_MASK);
> +       con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
>                 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
>
>         if (data->soc == SOC_ARCH_EXYNOS) {
> +               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK | EXYNOS_MUX_ADDR_MASK);
>                 con |= pdata->noise_cancel_mode <<
> EXYNOS_TMU_TRIP_MODE_SHIFT;
>                 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
>         }
> @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct platform_device
> *pdev, bool on)
>                         pdata->trigger_level1_en << 4 |
>                         pdata->trigger_level0_en;
>         } else {
> -               con |= EXYNOS_TMU_CORE_OFF;
>                 interrupt_en = 0; /* Disable all interrupts */
>         }
>         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
> --
> 1.7.4.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
  2012-11-20  1:39 ` Kyungmin Park
@ 2012-11-20  5:53   ` Zhang Rui
  2012-11-20  6:16     ` Kyungmin Park
  2012-11-21  9:46     ` Amit Kachhap
  0 siblings, 2 replies; 8+ messages in thread
From: Zhang Rui @ 2012-11-20  5:53 UTC (permalink / raw)
  To: Kyungmin Park
  Cc: Jonghwan Choi, jonghwa3.lee, open list, Amit Daniel Kachhap,
	Sachin Kamat, Linux PM list, dg77.kim

On Tue, 2012-11-20 at 10:39 +0900, Kyungmin Park wrote:
> On 11/20/12, Jonghwan Choi <jhbird.choi@samsung.com> wrote:
> > [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
> >
> > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>

Amit and Donggeun Kim,

any comments on this patch?

thanks,
rui

> > ---
> >  drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
> >  1 files changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/thermal/exynos_thermal.c
> > b/drivers/thermal/exynos_thermal.c
> > index 6dd29e4..129e827 100644
> > --- a/drivers/thermal/exynos_thermal.c
> > +++ b/drivers/thermal/exynos_thermal.c
> > @@ -52,9 +52,12 @@
> >
> >  #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
> >  #define EXYNOS_TMU_GAIN_SHIFT          8
> > +#define EXYNOS_TMU_GAIN_MASK           (0xF << EXYNOS_TMU_GAIN_SHIFT)
> >  #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
> > -#define EXYNOS_TMU_CORE_ON             3
> > -#define EXYNOS_TMU_CORE_OFF            2
> > +#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
> > EXYNOS_TMU_REF_VOLTAGE_SHIFT)
> > +#define EXYNOS_TMU_CORE_ON             BIT(0)
> > +#define EXYNOS_TMU_CORE_ON_SHIFT       0
> > +#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
> > EXYNOS_TMU_CORE_ON_SHIFT)
> >  #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50
> >
> >  /* Exynos4210 specific registers */
> > @@ -85,7 +88,9 @@
> >  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
> >  #define EXYNOS_MUX_ADDR_VALUE          6
> >  #define EXYNOS_MUX_ADDR_SHIFT          20
> > +#define EXYNOS_MUX_ADDR_MASK           (0x7 << EXYNOS_MUX_ADDR_SHIFT)
> >  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
> > +#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 << EXYNOS_TMU_TRIP_MODE_SHIFT)
> >
> >  #define EFUSE_MIN_VALUE 40
> >  #define EFUSE_MAX_VALUE 100
> > @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct platform_device
> > *pdev, bool on)
> >         mutex_lock(&data->lock);
> >         clk_enable(data->clk);
> >
> > -       con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
> > +       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
> > +       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
> > +               EXYNOS_TMU_CORE_ON_MASK);
> > +       con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
> >                 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
> >
> >         if (data->soc == SOC_ARCH_EXYNOS) {
> > +               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK | EXYNOS_MUX_ADDR_MASK);
> >                 con |= pdata->noise_cancel_mode <<
> > EXYNOS_TMU_TRIP_MODE_SHIFT;
> >                 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
> >         }
> > @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct platform_device
> > *pdev, bool on)
> >                         pdata->trigger_level1_en << 4 |
> >                         pdata->trigger_level0_en;
> >         } else {
> > -               con |= EXYNOS_TMU_CORE_OFF;
> >                 interrupt_en = 0; /* Disable all interrupts */
> >         }
> >         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
> > --
> > 1.7.4.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at  http://www.tux.org/lkml/
> >



^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
  2012-11-20  5:53   ` Zhang Rui
@ 2012-11-20  6:16     ` Kyungmin Park
  2012-11-20  6:32       ` Zhang Rui
  2012-11-21  9:46     ` Amit Kachhap
  1 sibling, 1 reply; 8+ messages in thread
From: Kyungmin Park @ 2012-11-20  6:16 UTC (permalink / raw)
  To: Zhang Rui
  Cc: Jonghwan Choi, jonghwa3.lee, open list, Amit Daniel Kachhap,
	Sachin Kamat, Linux PM list, dg77.kim

On 11/20/12, Zhang Rui <rui.zhang@intel.com> wrote:
> On Tue, 2012-11-20 at 10:39 +0900, Kyungmin Park wrote:
>> On 11/20/12, Jonghwan Choi <jhbird.choi@samsung.com> wrote:
>> > [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
>> >
>> > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>
> Amit and Donggeun Kim,
FYI: Donggeun was working together with me and he left the company an
year ago and now Mr. Lee are take over.
> any comments on this patch?
>
> thanks,
> rui
>
>> > ---
>> >  drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
>> >  1 files changed, 12 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/thermal/exynos_thermal.c
>> > b/drivers/thermal/exynos_thermal.c
>> > index 6dd29e4..129e827 100644
>> > --- a/drivers/thermal/exynos_thermal.c
>> > +++ b/drivers/thermal/exynos_thermal.c
>> > @@ -52,9 +52,12 @@
>> >
>> >  #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
>> >  #define EXYNOS_TMU_GAIN_SHIFT          8
>> > +#define EXYNOS_TMU_GAIN_MASK           (0xF << EXYNOS_TMU_GAIN_SHIFT)
>> >  #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
>> > -#define EXYNOS_TMU_CORE_ON             3
>> > -#define EXYNOS_TMU_CORE_OFF            2
>> > +#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
>> > EXYNOS_TMU_REF_VOLTAGE_SHIFT)
>> > +#define EXYNOS_TMU_CORE_ON             BIT(0)
>> > +#define EXYNOS_TMU_CORE_ON_SHIFT       0
>> > +#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
>> > EXYNOS_TMU_CORE_ON_SHIFT)
>> >  #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50
>> >
>> >  /* Exynos4210 specific registers */
>> > @@ -85,7 +88,9 @@
>> >  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
>> >  #define EXYNOS_MUX_ADDR_VALUE          6
>> >  #define EXYNOS_MUX_ADDR_SHIFT          20
>> > +#define EXYNOS_MUX_ADDR_MASK           (0x7 << EXYNOS_MUX_ADDR_SHIFT)
>> >  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>> > +#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 <<
>> > EXYNOS_TMU_TRIP_MODE_SHIFT)
>> >
>> >  #define EFUSE_MIN_VALUE 40
>> >  #define EFUSE_MAX_VALUE 100
>> > @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct
>> > platform_device
>> > *pdev, bool on)
>> >         mutex_lock(&data->lock);
>> >         clk_enable(data->clk);
>> >
>> > -       con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT
>> > |
>> > +       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
>> > +       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
>> > +               EXYNOS_TMU_CORE_ON_MASK);
>> > +       con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT
>> > |
>> >                 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
>> >
>> >         if (data->soc == SOC_ARCH_EXYNOS) {
>> > +               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK |
>> > EXYNOS_MUX_ADDR_MASK);
>> >                 con |= pdata->noise_cancel_mode <<
>> > EXYNOS_TMU_TRIP_MODE_SHIFT;
>> >                 con |= (EXYNOS_MUX_ADDR_VALUE <<
>> > EXYNOS_MUX_ADDR_SHIFT);
>> >         }
>> > @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct
>> > platform_device
>> > *pdev, bool on)
>> >                         pdata->trigger_level1_en << 4 |
>> >                         pdata->trigger_level0_en;
>> >         } else {
>> > -               con |= EXYNOS_TMU_CORE_OFF;
>> >                 interrupt_en = 0; /* Disable all interrupts */
>> >         }
>> >         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
>> > --
>> > 1.7.4.1
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe linux-kernel"
>> > in
>> > the body of a message to majordomo@vger.kernel.org
>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> > Please read the FAQ at  http://www.tux.org/lkml/
>> >
>
>
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
  2012-11-20  6:16     ` Kyungmin Park
@ 2012-11-20  6:32       ` Zhang Rui
  2012-11-20  7:06         ` Kyungmin Park
  0 siblings, 1 reply; 8+ messages in thread
From: Zhang Rui @ 2012-11-20  6:32 UTC (permalink / raw)
  To: Kyungmin Park
  Cc: Jonghwan Choi, jonghwa3.lee, open list, Amit Daniel Kachhap,
	Sachin Kamat, Linux PM list, dg77.kim

On Tue, 2012-11-20 at 15:16 +0900, Kyungmin Park wrote:
> On 11/20/12, Zhang Rui <rui.zhang@intel.com> wrote:
> > On Tue, 2012-11-20 at 10:39 +0900, Kyungmin Park wrote:
> >> On 11/20/12, Jonghwan Choi <jhbird.choi@samsung.com> wrote:
> >> > [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
> >> >
> >> > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> >> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
> >
> > Amit and Donggeun Kim,
> FYI: Donggeun was working together with me and he left the company an
> year ago and now Mr. Lee are take over.

I see.

so Amit and Lee,
will any of you be the maintainer of this driver?

I'd like to see your comments for the changes, as you know more about
the hardware details.

thanks,
rui
> > any comments on this patch?
> >
> > thanks,
> > rui
> >
> >> > ---
> >> >  drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
> >> >  1 files changed, 12 insertions(+), 4 deletions(-)
> >> >
> >> > diff --git a/drivers/thermal/exynos_thermal.c
> >> > b/drivers/thermal/exynos_thermal.c
> >> > index 6dd29e4..129e827 100644
> >> > --- a/drivers/thermal/exynos_thermal.c
> >> > +++ b/drivers/thermal/exynos_thermal.c
> >> > @@ -52,9 +52,12 @@
> >> >
> >> >  #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
> >> >  #define EXYNOS_TMU_GAIN_SHIFT          8
> >> > +#define EXYNOS_TMU_GAIN_MASK           (0xF << EXYNOS_TMU_GAIN_SHIFT)
> >> >  #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
> >> > -#define EXYNOS_TMU_CORE_ON             3
> >> > -#define EXYNOS_TMU_CORE_OFF            2
> >> > +#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
> >> > EXYNOS_TMU_REF_VOLTAGE_SHIFT)
> >> > +#define EXYNOS_TMU_CORE_ON             BIT(0)
> >> > +#define EXYNOS_TMU_CORE_ON_SHIFT       0
> >> > +#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
> >> > EXYNOS_TMU_CORE_ON_SHIFT)
> >> >  #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50
> >> >
> >> >  /* Exynos4210 specific registers */
> >> > @@ -85,7 +88,9 @@
> >> >  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
> >> >  #define EXYNOS_MUX_ADDR_VALUE          6
> >> >  #define EXYNOS_MUX_ADDR_SHIFT          20
> >> > +#define EXYNOS_MUX_ADDR_MASK           (0x7 << EXYNOS_MUX_ADDR_SHIFT)
> >> >  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
> >> > +#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 <<
> >> > EXYNOS_TMU_TRIP_MODE_SHIFT)
> >> >
> >> >  #define EFUSE_MIN_VALUE 40
> >> >  #define EFUSE_MAX_VALUE 100
> >> > @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct
> >> > platform_device
> >> > *pdev, bool on)
> >> >         mutex_lock(&data->lock);
> >> >         clk_enable(data->clk);
> >> >
> >> > -       con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT
> >> > |
> >> > +       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
> >> > +       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
> >> > +               EXYNOS_TMU_CORE_ON_MASK);
> >> > +       con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT
> >> > |
> >> >                 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
> >> >
> >> >         if (data->soc == SOC_ARCH_EXYNOS) {
> >> > +               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK |
> >> > EXYNOS_MUX_ADDR_MASK);
> >> >                 con |= pdata->noise_cancel_mode <<
> >> > EXYNOS_TMU_TRIP_MODE_SHIFT;
> >> >                 con |= (EXYNOS_MUX_ADDR_VALUE <<
> >> > EXYNOS_MUX_ADDR_SHIFT);
> >> >         }
> >> > @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct
> >> > platform_device
> >> > *pdev, bool on)
> >> >                         pdata->trigger_level1_en << 4 |
> >> >                         pdata->trigger_level0_en;
> >> >         } else {
> >> > -               con |= EXYNOS_TMU_CORE_OFF;
> >> >                 interrupt_en = 0; /* Disable all interrupts */
> >> >         }
> >> >         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
> >> > --
> >> > 1.7.4.1
> >> >
> >> > --
> >> > To unsubscribe from this list: send the line "unsubscribe linux-kernel"
> >> > in
> >> > the body of a message to majordomo@vger.kernel.org
> >> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >> > Please read the FAQ at  http://www.tux.org/lkml/
> >> >
> >
> >
> >
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
  2012-11-20  6:32       ` Zhang Rui
@ 2012-11-20  7:06         ` Kyungmin Park
  0 siblings, 0 replies; 8+ messages in thread
From: Kyungmin Park @ 2012-11-20  7:06 UTC (permalink / raw)
  To: Zhang Rui
  Cc: Jonghwan Choi, jonghwa3.lee, open list, Amit Daniel Kachhap,
	Sachin Kamat, Linux PM list

On 11/20/12, Zhang Rui <rui.zhang@intel.com> wrote:
> On Tue, 2012-11-20 at 15:16 +0900, Kyungmin Park wrote:
>> On 11/20/12, Zhang Rui <rui.zhang@intel.com> wrote:
>> > On Tue, 2012-11-20 at 10:39 +0900, Kyungmin Park wrote:
>> >> On 11/20/12, Jonghwan Choi <jhbird.choi@samsung.com> wrote:
>> >> > [0]bit is used to enable/disable tmu core. [1] bit is a reserved
>> >> > bit.
>> >> >
>> >> > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
>> >> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>> >
>> > Amit and Donggeun Kim,
>> FYI: Donggeun was working together with me and he left the company an
>> year ago and now Mr. Lee are take over.
>
> I see.
>
> so Amit and Lee,
> will any of you be the maintainer of this driver?
Okay, after discussing it with Amit and Mr. Lee. let you know.
basically Mr. Lee want to maintain thermal task and he's working on it now.

Thank you,
Kyungmin Park
>
> I'd like to see your comments for the changes, as you know more about
> the hardware details.
>
> thanks,
> rui
>> > any comments on this patch?
>> >
>> > thanks,
>> > rui
>> >
>> >> > ---
>> >> >  drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
>> >> >  1 files changed, 12 insertions(+), 4 deletions(-)
>> >> >
>> >> > diff --git a/drivers/thermal/exynos_thermal.c
>> >> > b/drivers/thermal/exynos_thermal.c
>> >> > index 6dd29e4..129e827 100644
>> >> > --- a/drivers/thermal/exynos_thermal.c
>> >> > +++ b/drivers/thermal/exynos_thermal.c
>> >> > @@ -52,9 +52,12 @@
>> >> >
>> >> >  #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
>> >> >  #define EXYNOS_TMU_GAIN_SHIFT          8
>> >> > +#define EXYNOS_TMU_GAIN_MASK           (0xF <<
>> >> > EXYNOS_TMU_GAIN_SHIFT)
>> >> >  #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
>> >> > -#define EXYNOS_TMU_CORE_ON             3
>> >> > -#define EXYNOS_TMU_CORE_OFF            2
>> >> > +#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
>> >> > EXYNOS_TMU_REF_VOLTAGE_SHIFT)
>> >> > +#define EXYNOS_TMU_CORE_ON             BIT(0)
>> >> > +#define EXYNOS_TMU_CORE_ON_SHIFT       0
>> >> > +#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
>> >> > EXYNOS_TMU_CORE_ON_SHIFT)
>> >> >  #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50
>> >> >
>> >> >  /* Exynos4210 specific registers */
>> >> > @@ -85,7 +88,9 @@
>> >> >  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
>> >> >  #define EXYNOS_MUX_ADDR_VALUE          6
>> >> >  #define EXYNOS_MUX_ADDR_SHIFT          20
>> >> > +#define EXYNOS_MUX_ADDR_MASK           (0x7 <<
>> >> > EXYNOS_MUX_ADDR_SHIFT)
>> >> >  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>> >> > +#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 <<
>> >> > EXYNOS_TMU_TRIP_MODE_SHIFT)
>> >> >
>> >> >  #define EFUSE_MIN_VALUE 40
>> >> >  #define EFUSE_MAX_VALUE 100
>> >> > @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct
>> >> > platform_device
>> >> > *pdev, bool on)
>> >> >         mutex_lock(&data->lock);
>> >> >         clk_enable(data->clk);
>> >> >
>> >> > -       con = pdata->reference_voltage <<
>> >> > EXYNOS_TMU_REF_VOLTAGE_SHIFT
>> >> > |
>> >> > +       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
>> >> > +       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK
>> >> > |
>> >> > +               EXYNOS_TMU_CORE_ON_MASK);
>> >> > +       con |= pdata->reference_voltage <<
>> >> > EXYNOS_TMU_REF_VOLTAGE_SHIFT
>> >> > |
>> >> >                 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
>> >> >
>> >> >         if (data->soc == SOC_ARCH_EXYNOS) {
>> >> > +               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK |
>> >> > EXYNOS_MUX_ADDR_MASK);
>> >> >                 con |= pdata->noise_cancel_mode <<
>> >> > EXYNOS_TMU_TRIP_MODE_SHIFT;
>> >> >                 con |= (EXYNOS_MUX_ADDR_VALUE <<
>> >> > EXYNOS_MUX_ADDR_SHIFT);
>> >> >         }
>> >> > @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct
>> >> > platform_device
>> >> > *pdev, bool on)
>> >> >                         pdata->trigger_level1_en << 4 |
>> >> >                         pdata->trigger_level0_en;
>> >> >         } else {
>> >> > -               con |= EXYNOS_TMU_CORE_OFF;
>> >> >                 interrupt_en = 0; /* Disable all interrupts */
>> >> >         }
>> >> >         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
>> >> > --
>> >> > 1.7.4.1
>> >> >
>> >> > --
>> >> > To unsubscribe from this list: send the line "unsubscribe
>> >> > linux-kernel"
>> >> > in
>> >> > the body of a message to majordomo@vger.kernel.org
>> >> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> >> > Please read the FAQ at  http://www.tux.org/lkml/
>> >> >
>> >
>> >
>> >
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
  2012-11-20  5:53   ` Zhang Rui
  2012-11-20  6:16     ` Kyungmin Park
@ 2012-11-21  9:46     ` Amit Kachhap
  1 sibling, 0 replies; 8+ messages in thread
From: Amit Kachhap @ 2012-11-21  9:46 UTC (permalink / raw)
  To: Zhang Rui
  Cc: Kyungmin Park, Jonghwan Choi, jonghwa3.lee, open list,
	Sachin Kamat, Linux PM list, dg77.kim

On 20 November 2012 11:23, Zhang Rui <rui.zhang@intel.com> wrote:
> On Tue, 2012-11-20 at 10:39 +0900, Kyungmin Park wrote:
>> On 11/20/12, Jonghwan Choi <jhbird.choi@samsung.com> wrote:
>> > [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
>> >
>> > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>
> Amit and Donggeun Kim,
>
> any comments on this patch?
>
> thanks,
> rui
Hi Riu,

This patch is according to the suggestion I made earlier and looks fine.
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>

Thanks,
Amit Daniel
>
>> > ---
>> >  drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
>> >  1 files changed, 12 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/thermal/exynos_thermal.c
>> > b/drivers/thermal/exynos_thermal.c
>> > index 6dd29e4..129e827 100644
>> > --- a/drivers/thermal/exynos_thermal.c
>> > +++ b/drivers/thermal/exynos_thermal.c
>> > @@ -52,9 +52,12 @@
>> >
>> >  #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
>> >  #define EXYNOS_TMU_GAIN_SHIFT          8
>> > +#define EXYNOS_TMU_GAIN_MASK           (0xF << EXYNOS_TMU_GAIN_SHIFT)
>> >  #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
>> > -#define EXYNOS_TMU_CORE_ON             3
>> > -#define EXYNOS_TMU_CORE_OFF            2
>> > +#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
>> > EXYNOS_TMU_REF_VOLTAGE_SHIFT)
>> > +#define EXYNOS_TMU_CORE_ON             BIT(0)
>> > +#define EXYNOS_TMU_CORE_ON_SHIFT       0
>> > +#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
>> > EXYNOS_TMU_CORE_ON_SHIFT)
>> >  #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50
>> >
>> >  /* Exynos4210 specific registers */
>> > @@ -85,7 +88,9 @@
>> >  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
>> >  #define EXYNOS_MUX_ADDR_VALUE          6
>> >  #define EXYNOS_MUX_ADDR_SHIFT          20
>> > +#define EXYNOS_MUX_ADDR_MASK           (0x7 << EXYNOS_MUX_ADDR_SHIFT)
>> >  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>> > +#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 << EXYNOS_TMU_TRIP_MODE_SHIFT)
>> >
>> >  #define EFUSE_MIN_VALUE 40
>> >  #define EFUSE_MAX_VALUE 100
>> > @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct platform_device
>> > *pdev, bool on)
>> >         mutex_lock(&data->lock);
>> >         clk_enable(data->clk);
>> >
>> > -       con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
>> > +       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
>> > +       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
>> > +               EXYNOS_TMU_CORE_ON_MASK);
>> > +       con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
>> >                 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
>> >
>> >         if (data->soc == SOC_ARCH_EXYNOS) {
>> > +               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK | EXYNOS_MUX_ADDR_MASK);
>> >                 con |= pdata->noise_cancel_mode <<
>> > EXYNOS_TMU_TRIP_MODE_SHIFT;
>> >                 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
>> >         }
>> > @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct platform_device
>> > *pdev, bool on)
>> >                         pdata->trigger_level1_en << 4 |
>> >                         pdata->trigger_level0_en;
>> >         } else {
>> > -               con |= EXYNOS_TMU_CORE_OFF;
>> >                 interrupt_en = 0; /* Disable all interrupts */
>> >         }
>> >         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
>> > --
>> > 1.7.4.1
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> > the body of a message to majordomo@vger.kernel.org
>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> > Please read the FAQ at  http://www.tux.org/lkml/
>> >
>
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core
  2012-11-20  0:57 [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core Jonghwan Choi
  2012-11-20  1:39 ` Kyungmin Park
@ 2012-11-22  2:18 ` Zhang Rui
  1 sibling, 0 replies; 8+ messages in thread
From: Zhang Rui @ 2012-11-22  2:18 UTC (permalink / raw)
  To: Jonghwan Choi
  Cc: 'open list', 'Amit Daniel Kachhap',
	'Sachin Kamat'

On Tue, 2012-11-20 at 09:57 +0900, Jonghwan Choi wrote:
> [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
> 
> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>

I don't know why but the patch format seems to be a mess.
please resend the patch.

thanks,
rui
> ---
>  drivers/thermal/exynos_thermal.c |   16 ++++++++++++----
>  1 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/thermal/exynos_thermal.c
> b/drivers/thermal/exynos_thermal.c
> index 6dd29e4..129e827 100644
> --- a/drivers/thermal/exynos_thermal.c
> +++ b/drivers/thermal/exynos_thermal.c
> @@ -52,9 +52,12 @@
> 
>  #define EXYNOS_TMU_TRIM_TEMP_MASK      0xff
>  #define EXYNOS_TMU_GAIN_SHIFT          8
> +#define EXYNOS_TMU_GAIN_MASK           (0xF << EXYNOS_TMU_GAIN_SHIFT)
>  #define EXYNOS_TMU_REF_VOLTAGE_SHIFT   24
> -#define EXYNOS_TMU_CORE_ON             3
> -#define EXYNOS_TMU_CORE_OFF            2
> +#define EXYNOS_TMU_REF_VOLTAGE_MASK    (0x1F <<
> EXYNOS_TMU_REF_VOLTAGE_SHIFT)
> +#define EXYNOS_TMU_CORE_ON             BIT(0)
> +#define EXYNOS_TMU_CORE_ON_SHIFT       0
> +#define EXYNOS_TMU_CORE_ON_MASK                (0x1 <<
> EXYNOS_TMU_CORE_ON_SHIFT)
>  #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET     50
> 
>  /* Exynos4210 specific registers */
> @@ -85,7 +88,9 @@
>  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 16)
>  #define EXYNOS_MUX_ADDR_VALUE          6
>  #define EXYNOS_MUX_ADDR_SHIFT          20
> +#define EXYNOS_MUX_ADDR_MASK           (0x7 << EXYNOS_MUX_ADDR_SHIFT)
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
> +#define EXYNOS_TMU_TRIP_MODE_MASK      (0x7 << EXYNOS_TMU_TRIP_MODE_SHIFT)
> 
>  #define EFUSE_MIN_VALUE 40
>  #define EFUSE_MAX_VALUE 100
> @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct platform_device
> *pdev, bool on)
>         mutex_lock(&data->lock);
>         clk_enable(data->clk);
> 
> -       con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
> +       con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
> +       con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
> +               EXYNOS_TMU_CORE_ON_MASK);
> +       con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
>                 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
> 
>         if (data->soc == SOC_ARCH_EXYNOS) {
> +               con &= ~(EXYNOS_TMU_TRIP_MODE_MASK | EXYNOS_MUX_ADDR_MASK);
>                 con |= pdata->noise_cancel_mode <<
> EXYNOS_TMU_TRIP_MODE_SHIFT;
>                 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
>         }
> @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct platform_device
> *pdev, bool on)
>                         pdata->trigger_level1_en << 4 |
>                         pdata->trigger_level0_en;
>         } else {
> -               con |= EXYNOS_TMU_CORE_OFF;
>                 interrupt_en = 0; /* Disable all interrupts */
>         }
>         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
> --
> 1.7.4.1
> 



^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2012-11-22 18:44 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-11-20  0:57 [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu core Jonghwan Choi
2012-11-20  1:39 ` Kyungmin Park
2012-11-20  5:53   ` Zhang Rui
2012-11-20  6:16     ` Kyungmin Park
2012-11-20  6:32       ` Zhang Rui
2012-11-20  7:06         ` Kyungmin Park
2012-11-21  9:46     ` Amit Kachhap
2012-11-22  2:18 ` Zhang Rui

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).