* [PATCH v2 0/8] enable support for AMBA drivers under x86
@ 2012-11-23 15:08 Davide Ciminaghi
2012-11-23 15:08 ` [PATCH 1/8] DMA: PL330: use prefix in reg names to build " Davide Ciminaghi
` (7 more replies)
0 siblings, 8 replies; 34+ messages in thread
From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw)
To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely,
linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux,
viresh.linux, rajeev-dlh.kumar
Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi
Hi,
this is v2 of a patchset submitted on Sep 14th
(see https://lkml.org/lkml/2012/9/14/412).
The only changes are:
* Rebased to next-20121115.
* "gpio: pl061 depends on ARM" : changelog fixed as per Sergei Shtylyov's
comments (see https://lkml.org/lkml/2012/9/14/471).
* "drivers/amba: add support for a PCI bridge" : pci_amba_probe(), avoided
unnecessary double return statement.
Acked by situation:
"DMA: PL330: use prefix in reg names to build under x86" has already been
acked by Vinod Koul (see https://lkml.org/lkml/2012/9/16/271) and
Linus Walleij (see https://lkml.org/lkml/2012/9/16/93).
"mmc: use the new <linux/sizes.h>" has already been acked by David Brown
(see https://lkml.org/lkml/2012/9/14/613)
"pl080.h: moved from arm/include/asm/hardware to include/linux/amba/" has
already been acked by Linus Walleij (see https://lkml.org/lkml/2012/9/16/92).
Regards
Davide
Alessandro Rubini (7):
DMA: PL330: use prefix in reg names to build under x86
gpio: pl061 depends on ARM
pl080.h: moved from arm/include/asm/hardware to include/linux/amba/
watchdog: sp805_wdt depends on ARM
mmc: use the new <linux/sizes.h>
drivers/amba: add support for a PCI bridge
x86: add CONFIG_ARM_AMBA, selected by STA2X11
Davide Ciminaghi (1):
mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep
arch/arm/include/asm/hardware/pl080.h | 146 ---------
arch/arm/mach-s3c64xx/dma.c | 2 +-
arch/arm/mach-spear3xx/spear3xx.c | 2 +-
arch/arm/mach-spear6xx/spear6xx.c | 2 +-
arch/x86/Kconfig | 4 +
drivers/Kconfig | 2 +
drivers/amba/Kconfig | 10 +
drivers/amba/Makefile | 1 +
drivers/amba/pci-amba.c | 93 ++++++
drivers/dma/amba-pl08x.c | 2 +-
drivers/dma/pl330.c | 581 +++++++++++++++++----------------
drivers/gpio/Kconfig | 2 +-
drivers/mmc/host/mmci.c | 10 +-
drivers/mmc/host/msm_sdcc.c | 2 +-
drivers/mmc/host/mvsdio.c | 2 +-
drivers/mmc/host/mxcmmc.c | 2 +-
drivers/mmc/host/pxamci.c | 3 +-
drivers/watchdog/Kconfig | 2 +-
include/linux/amba/pl080.h | 146 +++++++++
19 files changed, 563 insertions(+), 451 deletions(-)
delete mode 100644 arch/arm/include/asm/hardware/pl080.h
create mode 100644 drivers/amba/Kconfig
create mode 100644 drivers/amba/pci-amba.c
create mode 100644 include/linux/amba/pl080.h
--
1.7.10.4
^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 1/8] DMA: PL330: use prefix in reg names to build under x86 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 2012-11-23 15:51 ` viresh kumar 2012-11-23 15:08 ` [PATCH 2/8] gpio: pl061 depends on ARM Davide Ciminaghi ` (6 subsequent siblings) 7 siblings, 1 reply; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> This driver would not compile if ARM_AMBA is selected under x86, because "CS" and "DS" are already defined there. But AMBA is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. The patch adds the "PL330_" prefix to all register and bit fields, so it can be built by randomconfig after ARM_AMBA appears within x86. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- drivers/dma/pl330.c | 581 ++++++++++++++++++++++++++------------------------- 1 file changed, 292 insertions(+), 289 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 665668b..6de6de3 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -69,129 +69,129 @@ enum pl330_reqtype { }; /* Register and Bit field Definitions */ -#define DS 0x0 -#define DS_ST_STOP 0x0 -#define DS_ST_EXEC 0x1 -#define DS_ST_CMISS 0x2 -#define DS_ST_UPDTPC 0x3 -#define DS_ST_WFE 0x4 -#define DS_ST_ATBRR 0x5 -#define DS_ST_QBUSY 0x6 -#define DS_ST_WFP 0x7 -#define DS_ST_KILL 0x8 -#define DS_ST_CMPLT 0x9 -#define DS_ST_FLTCMP 0xe -#define DS_ST_FAULT 0xf - -#define DPC 0x4 -#define INTEN 0x20 -#define ES 0x24 -#define INTSTATUS 0x28 -#define INTCLR 0x2c -#define FSM 0x30 -#define FSC 0x34 -#define FTM 0x38 - -#define _FTC 0x40 -#define FTC(n) (_FTC + (n)*0x4) - -#define _CS 0x100 -#define CS(n) (_CS + (n)*0x8) -#define CS_CNS (1 << 21) - -#define _CPC 0x104 -#define CPC(n) (_CPC + (n)*0x8) - -#define _SA 0x400 -#define SA(n) (_SA + (n)*0x20) - -#define _DA 0x404 -#define DA(n) (_DA + (n)*0x20) - -#define _CC 0x408 -#define CC(n) (_CC + (n)*0x20) - -#define CC_SRCINC (1 << 0) -#define CC_DSTINC (1 << 14) -#define CC_SRCPRI (1 << 8) -#define CC_DSTPRI (1 << 22) -#define CC_SRCNS (1 << 9) -#define CC_DSTNS (1 << 23) -#define CC_SRCIA (1 << 10) -#define CC_DSTIA (1 << 24) -#define CC_SRCBRSTLEN_SHFT 4 -#define CC_DSTBRSTLEN_SHFT 18 -#define CC_SRCBRSTSIZE_SHFT 1 -#define CC_DSTBRSTSIZE_SHFT 15 -#define CC_SRCCCTRL_SHFT 11 -#define CC_SRCCCTRL_MASK 0x7 -#define CC_DSTCCTRL_SHFT 25 -#define CC_DRCCCTRL_MASK 0x7 -#define CC_SWAP_SHFT 28 - -#define _LC0 0x40c -#define LC0(n) (_LC0 + (n)*0x20) - -#define _LC1 0x410 -#define LC1(n) (_LC1 + (n)*0x20) - -#define DBGSTATUS 0xd00 -#define DBG_BUSY (1 << 0) - -#define DBGCMD 0xd04 -#define DBGINST0 0xd08 -#define DBGINST1 0xd0c - -#define CR0 0xe00 -#define CR1 0xe04 -#define CR2 0xe08 -#define CR3 0xe0c -#define CR4 0xe10 -#define CRD 0xe14 - -#define PERIPH_ID 0xfe0 -#define PERIPH_REV_SHIFT 20 -#define PERIPH_REV_MASK 0xf -#define PERIPH_REV_R0P0 0 -#define PERIPH_REV_R1P0 1 -#define PERIPH_REV_R1P1 2 -#define PCELL_ID 0xff0 - -#define CR0_PERIPH_REQ_SET (1 << 0) -#define CR0_BOOT_EN_SET (1 << 1) -#define CR0_BOOT_MAN_NS (1 << 2) -#define CR0_NUM_CHANS_SHIFT 4 -#define CR0_NUM_CHANS_MASK 0x7 -#define CR0_NUM_PERIPH_SHIFT 12 -#define CR0_NUM_PERIPH_MASK 0x1f -#define CR0_NUM_EVENTS_SHIFT 17 -#define CR0_NUM_EVENTS_MASK 0x1f - -#define CR1_ICACHE_LEN_SHIFT 0 -#define CR1_ICACHE_LEN_MASK 0x7 -#define CR1_NUM_ICACHELINES_SHIFT 4 -#define CR1_NUM_ICACHELINES_MASK 0xf - -#define CRD_DATA_WIDTH_SHIFT 0 -#define CRD_DATA_WIDTH_MASK 0x7 -#define CRD_WR_CAP_SHIFT 4 -#define CRD_WR_CAP_MASK 0x7 -#define CRD_WR_Q_DEP_SHIFT 8 -#define CRD_WR_Q_DEP_MASK 0xf -#define CRD_RD_CAP_SHIFT 12 -#define CRD_RD_CAP_MASK 0x7 -#define CRD_RD_Q_DEP_SHIFT 16 -#define CRD_RD_Q_DEP_MASK 0xf -#define CRD_DATA_BUFF_SHIFT 20 -#define CRD_DATA_BUFF_MASK 0x3ff - -#define PART 0x330 -#define DESIGNER 0x41 -#define REVISION 0x0 -#define INTEG_CFG 0x0 -#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) - -#define PCELL_ID_VAL 0xb105f00d +#define PL330_DS 0x0 +#define PL330_DS_ST_STOP 0x0 +#define PL330_DS_ST_EXEC 0x1 +#define PL330_DS_ST_CMISS 0x2 +#define PL330_DS_ST_UPDTPC 0x3 +#define PL330_DS_ST_WFE 0x4 +#define PL330_DS_ST_ATBRR 0x5 +#define PL330_DS_ST_QBUSY 0x6 +#define PL330_DS_ST_WFP 0x7 +#define PL330_DS_ST_KILL 0x8 +#define PL330_DS_ST_CMPLT 0x9 +#define PL330_DS_ST_FLTCMP 0xe +#define PL330_DS_ST_FAULT 0xf + +#define PL330_DPC 0x4 +#define PL330_INTEN 0x20 +#define PL330_ES 0x24 +#define PL330_INTSTATUS 0x28 +#define PL330_INTCLR 0x2c +#define PL330_FSM 0x30 +#define PL330_FSC 0x34 +#define PL330_FTM 0x38 + +#define _FTC 0x40 +#define PL330_FTC(n) (_FTC + (n)*0x4) + +#define _CS 0x100 +#define PL330_CS(n) (_CS + (n)*0x8) +#define PL330_CS_CNS (1 << 21) + +#define _CPC 0x104 +#define PL330_CPC(n) (_CPC + (n)*0x8) + +#define _SA 0x400 +#define PL330_SA(n) (_SA + (n)*0x20) + +#define _DA 0x404 +#define PL330_DA(n) (_DA + (n)*0x20) + +#define _CC 0x408 +#define PL330_CC(n) (_CC + (n)*0x20) + +#define PL330_CC_SRCINC (1 << 0) +#define PL330_CC_DSTINC (1 << 14) +#define PL330_CC_SRCPRI (1 << 8) +#define PL330_CC_DSTPRI (1 << 22) +#define PL330_CC_SRCNS (1 << 9) +#define PL330_CC_DSTNS (1 << 23) +#define PL330_CC_SRCIA (1 << 10) +#define PL330_CC_DSTIA (1 << 24) +#define PL330_CC_SRCBRSTLEN_SHFT 4 +#define PL330_CC_DSTBRSTLEN_SHFT 18 +#define PL330_CC_SRCBRSTSIZE_SHFT 1 +#define PL330_CC_DSTBRSTSIZE_SHFT 15 +#define PL330_CC_SRCCCTRL_SHFT 11 +#define PL330_CC_SRCCCTRL_MASK 0x7 +#define PL330_CC_DSTCCTRL_SHFT 25 +#define PL330_CC_DRCCCTRL_MASK 0x7 +#define PL330_CC_SWAP_SHFT 28 + +#define _LC0 0x40c +#define PL330_LC0(n) (_LC0 + (n)*0x20) + +#define _LC1 0x410 +#define PL330_LC1(n) (_LC1 + (n)*0x20) + +#define PL330_DBGSTATUS 0xd00 +#define PL330_DBG_BUSY (1 << 0) + +#define PL330_DBGCMD 0xd04 +#define PL330_DBGINST0 0xd08 +#define PL330_DBGINST1 0xd0c + +#define PL330_CR0 0xe00 +#define PL330_CR1 0xe04 +#define PL330_CR2 0xe08 +#define PL330_CR3 0xe0c +#define PL330_CR4 0xe10 +#define PL330_CRD 0xe14 + +#define PL330_PERIPH_ID 0xfe0 +#define PL330_PERIPH_REV_SHIFT 20 +#define PL330_PERIPH_REV_MASK 0xf +#define PL330_PERIPH_REV_R0P0 0 +#define PL330_PERIPH_REV_R1P0 1 +#define PL330_PERIPH_REV_R1P1 2 +#define PL330_PCELL_ID 0xff0 + +#define PL330_CR0_PERIPH_REQ_SET (1 << 0) +#define PL330_CR0_BOOT_EN_SET (1 << 1) +#define PL330_CR0_BOOT_MAN_NS (1 << 2) +#define PL330_CR0_NUM_CHANS_SHIFT 4 +#define PL330_CR0_NUM_CHANS_MASK 0x7 +#define PL330_CR0_NUM_PERIPH_SHIFT 12 +#define PL330_CR0_NUM_PERIPH_MASK 0x1f +#define PL330_CR0_NUM_EVENTS_SHIFT 17 +#define PL330_CR0_NUM_EVENTS_MASK 0x1f + +#define PL330_CR1_ICACHE_LEN_SHIFT 0 +#define PL330_CR1_ICACHE_LEN_MASK 0x7 +#define PL330_CR1_NUM_ICACHELINES_SHIFT 4 +#define PL330_CR1_NUM_ICACHELINES_MASK 0xf + +#define PL330_CRD_DATA_WIDTH_SHIFT 0 +#define PL330_CRD_DATA_WIDTH_MASK 0x7 +#define PL330_CRD_WR_CAP_SHIFT 4 +#define PL330_CRD_WR_CAP_MASK 0x7 +#define PL330_CRD_WR_Q_DEP_SHIFT 8 +#define PL330_CRD_WR_Q_DEP_MASK 0xf +#define PL330_CRD_RD_CAP_SHIFT 12 +#define PL330_CRD_RD_CAP_MASK 0x7 +#define PL330_CRD_RD_Q_DEP_SHIFT 16 +#define PL330_CRD_RD_Q_DEP_MASK 0xf +#define PL330_CRD_DATA_BUFF_SHIFT 20 +#define PL330_CRD_DATA_BUFF_MASK 0x3ff + +#define PL330_PART 0x330 +#define PL330_DESIGNER 0x41 +#define PL330_REVISION 0x0 +#define PL330_INTEG_CFG 0x0 +#define PL330_PERIPH_ID_VAL ((PL330_PART << 0) | (PL330_DESIGNER << 12)) + +#define PL330_PCELL_ID_VAL 0xb105f00d #define PL330_STATE_STOPPED (1 << 0) #define PL330_STATE_EXECUTING (1 << 1) @@ -210,48 +210,48 @@ enum pl330_reqtype { #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | PL330_STATE_WFE | PL330_STATE_FAULTING) -#define CMD_DMAADDH 0x54 -#define CMD_DMAEND 0x00 -#define CMD_DMAFLUSHP 0x35 -#define CMD_DMAGO 0xa0 -#define CMD_DMALD 0x04 -#define CMD_DMALDP 0x25 -#define CMD_DMALP 0x20 -#define CMD_DMALPEND 0x28 -#define CMD_DMAKILL 0x01 -#define CMD_DMAMOV 0xbc -#define CMD_DMANOP 0x18 -#define CMD_DMARMB 0x12 -#define CMD_DMASEV 0x34 -#define CMD_DMAST 0x08 -#define CMD_DMASTP 0x29 -#define CMD_DMASTZ 0x0c -#define CMD_DMAWFE 0x36 -#define CMD_DMAWFP 0x30 -#define CMD_DMAWMB 0x13 - -#define SZ_DMAADDH 3 -#define SZ_DMAEND 1 -#define SZ_DMAFLUSHP 2 -#define SZ_DMALD 1 -#define SZ_DMALDP 2 -#define SZ_DMALP 2 -#define SZ_DMALPEND 2 -#define SZ_DMAKILL 1 -#define SZ_DMAMOV 6 -#define SZ_DMANOP 1 -#define SZ_DMARMB 1 -#define SZ_DMASEV 2 -#define SZ_DMAST 1 -#define SZ_DMASTP 2 -#define SZ_DMASTZ 1 -#define SZ_DMAWFE 2 -#define SZ_DMAWFP 2 -#define SZ_DMAWMB 1 -#define SZ_DMAGO 6 - -#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) -#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) +#define PL330_CMD_DMAADDH 0x54 +#define PL330_CMD_DMAEND 0x00 +#define PL330_CMD_DMAFLUSHP 0x35 +#define PL330_CMD_DMAGO 0xa0 +#define PL330_CMD_DMALD 0x04 +#define PL330_CMD_DMALDP 0x25 +#define PL330_CMD_DMALP 0x20 +#define PL330_CMD_DMALPEND 0x28 +#define PL330_CMD_DMAKILL 0x01 +#define PL330_CMD_DMAMOV 0xbc +#define PL330_CMD_DMANOP 0x18 +#define PL330_CMD_DMARMB 0x12 +#define PL330_CMD_DMASEV 0x34 +#define PL330_CMD_DMAST 0x08 +#define PL330_CMD_DMASTP 0x29 +#define PL330_CMD_DMASTZ 0x0c +#define PL330_CMD_DMAWFE 0x36 +#define PL330_CMD_DMAWFP 0x30 +#define PL330_CMD_DMAWMB 0x13 + +#define PL330_SZ_DMAADDH 3 +#define PL330_SZ_DMAEND 1 +#define PL330_SZ_DMAFLUSHP 2 +#define PL330_SZ_DMALD 1 +#define PL330_SZ_DMALDP 2 +#define PL330_SZ_DMALP 2 +#define PL330_SZ_DMALPEND 2 +#define PL330_SZ_DMAKILL 1 +#define PL330_SZ_DMAMOV 6 +#define PL330_SZ_DMANOP 1 +#define PL330_SZ_DMARMB 1 +#define PL330_SZ_DMASEV 2 +#define PL330_SZ_DMAST 1 +#define PL330_SZ_DMASTP 2 +#define PL330_SZ_DMASTZ 1 +#define PL330_SZ_DMAWFE 2 +#define PL330_SZ_DMAWFP 2 +#define PL330_SZ_DMAWMB 1 +#define PL330_SZ_DMAGO 6 + +#define BRST_LEN(ccr) ((((ccr) >> PL330_CC_SRCBRSTLEN_SHFT) & 0xf) + 1) +#define BRST_SIZE(ccr) (1 << (((ccr) >> PL330_CC_SRCBRSTSIZE_SHFT) & 0x7)) #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) @@ -265,7 +265,7 @@ enum pl330_reqtype { #define MCODE_BUFF_PER_REQ 256 /* If the _pl330_req is available to the client */ -#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) +#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == PL330_CMD_DMAEND) /* Use this _only_ to wait on transient states */ #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); @@ -658,43 +658,43 @@ static inline u32 get_id(struct pl330_info *pi, u32 off) static inline u32 get_revision(u32 periph_id) { - return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; + return (periph_id >> PL330_PERIPH_REV_SHIFT) & PL330_PERIPH_REV_MASK; } static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], enum pl330_dst da, u16 val) { if (dry_run) - return SZ_DMAADDH; + return PL330_SZ_DMAADDH; - buf[0] = CMD_DMAADDH; + buf[0] = PL330_CMD_DMAADDH; buf[0] |= (da << 1); *((u16 *)&buf[1]) = val; - PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", + PL330_DBGCMD_DUMP(PL330_SZ_DMAADDH, "\tDMAADDH %s %u\n", da == 1 ? "DA" : "SA", val); - return SZ_DMAADDH; + return PL330_SZ_DMAADDH; } static inline u32 _emit_END(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMAEND; + return PL330_SZ_DMAEND; - buf[0] = CMD_DMAEND; + buf[0] = PL330_CMD_DMAEND; - PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); + PL330_DBGCMD_DUMP(PL330_SZ_DMAEND, "\tDMAEND\n"); - return SZ_DMAEND; + return PL330_SZ_DMAEND; } static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) { if (dry_run) - return SZ_DMAFLUSHP; + return PL330_SZ_DMAFLUSHP; - buf[0] = CMD_DMAFLUSHP; + buf[0] = PL330_CMD_DMAFLUSHP; peri &= 0x1f; peri <<= 3; @@ -702,15 +702,15 @@ static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); - return SZ_DMAFLUSHP; + return PL330_SZ_DMAFLUSHP; } static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) - return SZ_DMALD; + return PL330_SZ_DMALD; - buf[0] = CMD_DMALD; + buf[0] = PL330_CMD_DMALD; if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); @@ -720,16 +720,16 @@ static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); - return SZ_DMALD; + return PL330_SZ_DMALD; } static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) - return SZ_DMALDP; + return PL330_SZ_DMALDP; - buf[0] = CMD_DMALDP; + buf[0] = PL330_CMD_DMALDP; if (cond == BURST) buf[0] |= (1 << 1); @@ -741,16 +741,16 @@ static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); - return SZ_DMALDP; + return PL330_SZ_DMALDP; } static inline u32 _emit_LP(unsigned dry_run, u8 buf[], unsigned loop, u8 cnt) { if (dry_run) - return SZ_DMALP; + return PL330_SZ_DMALP; - buf[0] = CMD_DMALP; + buf[0] = PL330_CMD_DMALP; if (loop) buf[0] |= (1 << 1); @@ -760,7 +760,7 @@ static inline u32 _emit_LP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); - return SZ_DMALP; + return PL330_SZ_DMALP; } struct _arg_LPEND { @@ -779,9 +779,9 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], u8 bjump = arg->bjump; if (dry_run) - return SZ_DMALPEND; + return PL330_SZ_DMALPEND; - buf[0] = CMD_DMALPEND; + buf[0] = PL330_CMD_DMALPEND; if (loop) buf[0] |= (1 << 2); @@ -802,65 +802,65 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], loop ? '1' : '0', bjump); - return SZ_DMALPEND; + return PL330_SZ_DMALPEND; } static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMAKILL; + return PL330_SZ_DMAKILL; - buf[0] = CMD_DMAKILL; + buf[0] = PL330_CMD_DMAKILL; - return SZ_DMAKILL; + return PL330_SZ_DMAKILL; } static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], enum dmamov_dst dst, u32 val) { if (dry_run) - return SZ_DMAMOV; + return PL330_SZ_DMAMOV; - buf[0] = CMD_DMAMOV; + buf[0] = PL330_CMD_DMAMOV; buf[1] = dst; *((u32 *)&buf[2]) = val; PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); - return SZ_DMAMOV; + return PL330_SZ_DMAMOV; } static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMANOP; + return PL330_SZ_DMANOP; - buf[0] = CMD_DMANOP; + buf[0] = PL330_CMD_DMANOP; PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); - return SZ_DMANOP; + return PL330_SZ_DMANOP; } static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMARMB; + return PL330_SZ_DMARMB; - buf[0] = CMD_DMARMB; + buf[0] = PL330_CMD_DMARMB; PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); - return SZ_DMARMB; + return PL330_SZ_DMARMB; } static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) { if (dry_run) - return SZ_DMASEV; + return PL330_SZ_DMASEV; - buf[0] = CMD_DMASEV; + buf[0] = PL330_CMD_DMASEV; ev &= 0x1f; ev <<= 3; @@ -868,15 +868,15 @@ static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); - return SZ_DMASEV; + return PL330_SZ_DMASEV; } static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) - return SZ_DMAST; + return PL330_SZ_DMAST; - buf[0] = CMD_DMAST; + buf[0] = PL330_CMD_DMAST; if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); @@ -886,16 +886,16 @@ static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); - return SZ_DMAST; + return PL330_SZ_DMAST; } static inline u32 _emit_STP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) - return SZ_DMASTP; + return PL330_SZ_DMASTP; - buf[0] = CMD_DMASTP; + buf[0] = PL330_CMD_DMASTP; if (cond == BURST) buf[0] |= (1 << 1); @@ -907,28 +907,28 @@ static inline u32 _emit_STP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); - return SZ_DMASTP; + return PL330_SZ_DMASTP; } static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMASTZ; + return PL330_SZ_DMASTZ; - buf[0] = CMD_DMASTZ; + buf[0] = PL330_CMD_DMASTZ; PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); - return SZ_DMASTZ; + return PL330_SZ_DMASTZ; } static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, unsigned invalidate) { if (dry_run) - return SZ_DMAWFE; + return PL330_SZ_DMAWFE; - buf[0] = CMD_DMAWFE; + buf[0] = PL330_CMD_DMAWFE; ev &= 0x1f; ev <<= 3; @@ -940,16 +940,16 @@ static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", ev >> 3, invalidate ? ", I" : ""); - return SZ_DMAWFE; + return PL330_SZ_DMAWFE; } static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) - return SZ_DMAWFP; + return PL330_SZ_DMAWFP; - buf[0] = CMD_DMAWFP; + buf[0] = PL330_CMD_DMAWFP; if (cond == SINGLE) buf[0] |= (0 << 1) | (0 << 0); @@ -965,19 +965,19 @@ static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); - return SZ_DMAWFP; + return PL330_SZ_DMAWFP; } static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMAWMB; + return PL330_SZ_DMAWMB; - buf[0] = CMD_DMAWMB; + buf[0] = PL330_CMD_DMAWMB; PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); - return SZ_DMAWMB; + return PL330_SZ_DMAWMB; } struct _arg_GO { @@ -994,16 +994,16 @@ static inline u32 _emit_GO(unsigned dry_run, u8 buf[], unsigned ns = arg->ns; if (dry_run) - return SZ_DMAGO; + return PL330_SZ_DMAGO; - buf[0] = CMD_DMAGO; + buf[0] = PL330_CMD_DMAGO; buf[0] |= (ns << 1); buf[1] = chan & 0x7; *((u32 *)&buf[2]) = addr; - return SZ_DMAGO; + return PL330_SZ_DMAGO; } #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) @@ -1016,7 +1016,7 @@ static bool _until_dmac_idle(struct pl330_thread *thrd) do { /* Until Manager is Idle */ - if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) + if (!(readl(regs + PL330_DBGSTATUS) & PL330_DBG_BUSY)) break; cpu_relax(); @@ -1039,10 +1039,10 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, val |= (1 << 0); val |= (thrd->id << 8); /* Channel Number */ } - writel(val, regs + DBGINST0); + writel(val, regs + PL330_DBGINST0); val = *((u32 *)&insn[2]); - writel(val, regs + DBGINST1); + writel(val, regs + PL330_DBGINST1); /* If timed out due to halted state-machine */ if (_until_dmac_idle(thrd)) { @@ -1051,7 +1051,7 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, } /* Get going */ - writel(0, regs + DBGCMD); + writel(0, regs + PL330_DBGCMD); } /* @@ -1078,47 +1078,47 @@ static inline u32 _state(struct pl330_thread *thrd) if (is_manager(thrd)) val = readl(regs + DS) & 0xf; else - val = readl(regs + CS(thrd->id)) & 0xf; + val = readl(regs + PL330_CS(thrd->id)) & 0xf; switch (val) { - case DS_ST_STOP: + case PL330_DS_ST_STOP: return PL330_STATE_STOPPED; - case DS_ST_EXEC: + case PL330_DS_ST_EXEC: return PL330_STATE_EXECUTING; - case DS_ST_CMISS: + case PL330_DS_ST_CMISS: return PL330_STATE_CACHEMISS; - case DS_ST_UPDTPC: + case PL330_DS_ST_UPDTPC: return PL330_STATE_UPDTPC; - case DS_ST_WFE: + case PL330_DS_ST_WFE: return PL330_STATE_WFE; - case DS_ST_FAULT: + case PL330_DS_ST_FAULT: return PL330_STATE_FAULTING; - case DS_ST_ATBRR: + case PL330_DS_ST_ATBRR: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_ATBARRIER; - case DS_ST_QBUSY: + case PL330_DS_ST_QBUSY: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_QUEUEBUSY; - case DS_ST_WFP: + case PL330_DS_ST_WFP: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_WFP; - case DS_ST_KILL: + case PL330_DS_ST_KILL: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_KILLING; - case DS_ST_CMPLT: + case PL330_DS_ST_CMPLT: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_COMPLETING; - case DS_ST_FLTCMP: + case PL330_DS_ST_FLTCMP: if (is_manager(thrd)) return PL330_STATE_INVALID; else @@ -1145,7 +1145,8 @@ static void _stop(struct pl330_thread *thrd) _emit_KILL(0, insn); /* Stop generating interrupts for SEV */ - writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); + writel(readl(regs + PL330_INTEN) & ~(1 << thrd->ev), + regs + PL330_INTEN); _execute_DBGINSN(thrd, insn, is_manager(thrd)); } @@ -1184,7 +1185,7 @@ static bool _trigger(struct pl330_thread *thrd) if (r->cfg) ns = r->cfg->nonsecure ? 1 : 0; - else if (readl(regs + CS(thrd->id)) & CS_CNS) + else if (readl(regs + PL330_CS(thrd->id)) & PL330_CS_CNS) ns = 1; else ns = 0; @@ -1200,7 +1201,7 @@ static bool _trigger(struct pl330_thread *thrd) _emit_GO(0, insn, &go); /* Set to generate interrupts for SEV */ - writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); + writel(readl(regs + PL330_INTEN) | (1 << thrd->ev), regs + PL330_INTEN); /* Only manager can execute GO */ _execute_DBGINSN(thrd, insn, true); @@ -1250,7 +1251,7 @@ static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], struct pl330_config *pcfg = pxs->r->cfg->pcfg; /* check lock-up free version */ - if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { + if (get_revision(pcfg->periph_id) >= PL330_PERIPH_REV_R1P0) { while (cyc--) { off += _emit_LD(dry_run, &buf[off], ALWAYS); off += _emit_ST(dry_run, &buf[off], ALWAYS); @@ -1475,29 +1476,29 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) u32 ccr = 0; if (rqc->src_inc) - ccr |= CC_SRCINC; + ccr |= PL330_CC_SRCINC; if (rqc->dst_inc) - ccr |= CC_DSTINC; + ccr |= PL330_CC_DSTINC; /* We set same protection levels for Src and DST for now */ if (rqc->privileged) - ccr |= CC_SRCPRI | CC_DSTPRI; + ccr |= PL330_CC_SRCPRI | PL330_CC_DSTPRI; if (rqc->nonsecure) - ccr |= CC_SRCNS | CC_DSTNS; + ccr |= PL330_CC_SRCNS | PL330_CC_DSTNS; if (rqc->insnaccess) - ccr |= CC_SRCIA | CC_DSTIA; + ccr |= PL330_CC_SRCIA | PL330_CC_DSTIA; - ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); - ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); + ccr |= (((rqc->brst_len - 1) & 0xf) << PL330_CC_SRCBRSTLEN_SHFT); + ccr |= (((rqc->brst_len - 1) & 0xf) << PL330_CC_DSTBRSTLEN_SHFT); - ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); - ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); + ccr |= (rqc->brst_size << PL330_CC_SRCBRSTSIZE_SHFT); + ccr |= (rqc->brst_size << PL330_CC_DSTBRSTSIZE_SHFT); - ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); - ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); + ccr |= (rqc->scctl << PL330_CC_SRCCCTRL_SHFT); + ccr |= (rqc->dcctl << PL330_CC_DSTCCTRL_SHFT); - ccr |= (rqc->swap << CC_SWAP_SHFT); + ccr |= (rqc->swap << PL330_CC_SWAP_SHFT); return ccr; } @@ -1507,8 +1508,8 @@ static inline bool _is_valid(u32 ccr) enum pl330_dstcachectrl dcctl; enum pl330_srccachectrl scctl; - dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK; - scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK; + dcctl = (ccr >> PL330_CC_DSTCCTRL_SHFT) & PL330_CC_DRCCCTRL_MASK; + scctl = (ccr >> PL330_CC_SRCCCTRL_SHFT) & PL330_CC_SRCCCTRL_MASK; if (dcctl == DINVALID1 || dcctl == DINVALID2 || scctl == SINVALID1 || scctl == SINVALID2) @@ -1575,7 +1576,7 @@ static int pl330_submit_req(void *ch_id, struct pl330_req *r) ccr = _prepare_ccr(r->cfg); } else { - ccr = readl(regs + CC(thrd->id)); + ccr = readl(regs + PL330_CC(thrd->id)); } /* If this req doesn't have valid xfer settings */ @@ -1652,7 +1653,7 @@ static void pl330_dotask(unsigned long data) _stop(thrd); - if (readl(regs + FSC) & (1 << thrd->id)) + if (readl(regs + PL330_FSC) & (1 << thrd->id)) err = PL330_ERR_FAIL; else err = PL330_ERR_ABORT; @@ -1697,13 +1698,13 @@ static int pl330_update(const struct pl330_info *pi) spin_lock_irqsave(&pl330->lock, flags); - val = readl(regs + FSM) & 0x1; + val = readl(regs + PL330_FSM) & 0x1; if (val) pl330->dmac_tbd.reset_mngr = true; else pl330->dmac_tbd.reset_mngr = false; - val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1); + val = readl(regs + PL330_FSC) & ((1 << pi->pcfg.num_chan) - 1); pl330->dmac_tbd.reset_chan |= val; if (val) { int i = 0; @@ -1711,8 +1712,8 @@ static int pl330_update(const struct pl330_info *pi) if (val & (1 << i)) { dev_info(pi->dev, "Reset Channel-%d\t CS-%x FTC-%x\n", - i, readl(regs + CS(i)), - readl(regs + FTC(i))); + i, readl(regs + PL330_CS(i)), + readl(regs + PL330_FTC(i))); _stop(&pl330->channels[i]); } i++; @@ -1732,12 +1733,12 @@ static int pl330_update(const struct pl330_info *pi) for (ev = 0; ev < pi->pcfg.num_events; ev++) { if (val & (1 << ev)) { /* Event occurred */ struct pl330_thread *thrd; - u32 inten = readl(regs + INTEN); + u32 inten = readl(regs + PL330_INTEN); int active; /* Clear the event */ if (inten & (1 << ev)) - writel(1 << ev, regs + INTCLR); + writel(1 << ev, regs + PL330_INTCLR); ret = 1; @@ -1944,44 +1945,45 @@ static void read_dmac_config(struct pl330_info *pi) void __iomem *regs = pi->base; u32 val; - val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; - val &= CRD_DATA_WIDTH_MASK; + val = readl(regs + PL330_CRD) >> PL330_CRD_DATA_WIDTH_SHIFT; + val &= PL330_CRD_DATA_WIDTH_MASK; pi->pcfg.data_bus_width = 8 * (1 << val); - val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; - val &= CRD_DATA_BUFF_MASK; + val = readl(regs + PL330_CRD) >> PL330_CRD_DATA_BUFF_SHIFT; + val &= PL330_CRD_DATA_BUFF_MASK; pi->pcfg.data_buf_dep = val + 1; - val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; - val &= CR0_NUM_CHANS_MASK; + val = readl(regs + PL330_CR0) >> PL330_CR0_NUM_CHANS_SHIFT; + val &= PL330_CR0_NUM_CHANS_MASK; val += 1; pi->pcfg.num_chan = val; - val = readl(regs + CR0); - if (val & CR0_PERIPH_REQ_SET) { - val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; + val = readl(regs + PL330_CR0); + if (val & PL330_CR0_PERIPH_REQ_SET) { + val = (val >> PL330_CR0_NUM_PERIPH_SHIFT) + & PL330_CR0_NUM_PERIPH_MASK; val += 1; pi->pcfg.num_peri = val; - pi->pcfg.peri_ns = readl(regs + CR4); + pi->pcfg.peri_ns = readl(regs + PL330_CR4); } else { pi->pcfg.num_peri = 0; } - val = readl(regs + CR0); - if (val & CR0_BOOT_MAN_NS) + val = readl(regs + PL330_CR0); + if (val & PL330_CR0_BOOT_MAN_NS) pi->pcfg.mode |= DMAC_MODE_NS; else pi->pcfg.mode &= ~DMAC_MODE_NS; - val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; - val &= CR0_NUM_EVENTS_MASK; + val = readl(regs + PL330_CR0) >> PL330_CR0_NUM_EVENTS_SHIFT; + val &= PL330_CR0_NUM_EVENTS_MASK; val += 1; pi->pcfg.num_events = val; - pi->pcfg.irq_ns = readl(regs + CR3); + pi->pcfg.irq_ns = readl(regs + PL330_CR3); - pi->pcfg.periph_id = get_id(pi, PERIPH_ID); - pi->pcfg.pcell_id = get_id(pi, PCELL_ID); + pi->pcfg.periph_id = get_id(pi, PL330_PERIPH_ID); + pi->pcfg.pcell_id = get_id(pi, PL330_PCELL_ID); } static inline void _reset_thread(struct pl330_thread *thrd) @@ -2091,10 +2093,11 @@ static int pl330_add(struct pl330_info *pi) regs = pi->base; /* Check if we can handle this DMAC */ - if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL - || get_id(pi, PCELL_ID) != PCELL_ID_VAL) { + if ((get_id(pi, PL330_PERIPH_ID) & 0xfffff) != PL330_PERIPH_ID_VAL + || get_id(pi, PL330_PCELL_ID) != PL330_PCELL_ID_VAL) { dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n", - get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID)); + get_id(pi, PL330_PERIPH_ID), + get_id(pi, PL330_PCELL_ID)); return -EINVAL; } -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 1/8] DMA: PL330: use prefix in reg names to build under x86 2012-11-23 15:08 ` [PATCH 1/8] DMA: PL330: use prefix in reg names to build " Davide Ciminaghi @ 2012-11-23 15:51 ` viresh kumar 2012-11-23 17:23 ` Davide Ciminaghi 0 siblings, 1 reply; 34+ messages in thread From: viresh kumar @ 2012-11-23 15:51 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 8:38 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > This driver would not compile if ARM_AMBA is selected under x86, > because "CS" and "DS" are already defined there. But AMBA > is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. > > The patch adds the "PL330_" prefix to all register and bit fields, > so it can be built by randomconfig after ARM_AMBA appears within x86. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Hi Davide, Its impossible to review due to obvious reasons :) Though git provides an option to people to review such stuff easily. git diff HEAD^.. --word-diff and HEAD being the commit in discussion. Problem, is people reviewing it need to apply it and not everybody can do that. Don't know if adding this diff after the three --- line, which form the non-commit log would be the right solution ? -- viresh ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/8] DMA: PL330: use prefix in reg names to build under x86 2012-11-23 15:51 ` viresh kumar @ 2012-11-23 17:23 ` Davide Ciminaghi 2012-11-23 17:28 ` Viresh Kumar 0 siblings, 1 reply; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 17:23 UTC (permalink / raw) To: viresh kumar Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 09:21:44PM +0530, viresh kumar wrote: > On Fri, Nov 23, 2012 at 8:38 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > > From: Alessandro Rubini <rubini@gnudd.com> > > > > This driver would not compile if ARM_AMBA is selected under x86, > > because "CS" and "DS" are already defined there. But AMBA > > is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. > > > > The patch adds the "PL330_" prefix to all register and bit fields, > > so it can be built by randomconfig after ARM_AMBA appears within x86. > > > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> > > Hi Davide, > > Its impossible to review due to obvious reasons :) > > Though git provides an option to people to review such stuff easily. > > git diff HEAD^.. --word-diff > > and HEAD being the commit in discussion. > > Problem, is people reviewing it need to apply it and not everybody > can do that. Don't know if adding this diff after the three --- line, > which form the non-commit log would be the right solution ? > Hi, I tried that, but the resulting patch does not apply: $ git checkout -b pl330_test next-20121115 Switched to a new branch 'pl330_test' $ git format-patch --word-diff 5f1e3c5~..5f1e3c5 $ cat 0001-DMA-PL330-use-prefix-in-reg-names-to-build-under-x86.patch >From 5f1e3c5779a0ad90e95697e23eeb0532e8a4be1a Mon Sep 17 00:00:00 2001 From: Alessandro Rubini <rubini@gnudd.com> Date: Tue, 4 Sep 2012 22:21:00 +0200 Subject: [PATCH] DMA: PL330: use prefix in reg names to build under x86 .... --- drivers/dma/pl330.c | 581 ++++++++++++++++++++++++++------------------------- 1 file changed, 292 insertions(+), 289 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 665668b..6de6de3 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -69,129 +69,129 @@ enum pl330_reqtype { }; /* Register and Bit field Definitions */ #define [-DS-]{+PL330_DS+} 0x0 #define [-DS_ST_STOP-]{+PL330_DS_ST_STOP+} 0x0 #define [-DS_ST_EXEC-]{+PL330_DS_ST_EXEC+} 0x1 $ git am 0001-DMA-PL330-use-prefix-in-reg-names-to-build-under-x86.patch Applying: DMA: PL330: use prefix in reg names to build under x86 fatal: corrupt patch at line 10 Patch failed at 0001 DMA: PL330: use prefix in reg names to build under x86 Did I do anything wrong (sorry, I'm not a git guru at all) ? However, here's the output of git-format-patch with --word-diff: ========================================================================== >From 5f1e3c5779a0ad90e95697e23eeb0532e8a4be1a Mon Sep 17 00:00:00 2001 From: Alessandro Rubini <rubini@gnudd.com> Date: Tue, 4 Sep 2012 22:21:00 +0200 Subject: [PATCH] DMA: PL330: use prefix in reg names to build under x86 This driver would not compile if ARM_AMBA is selected under x86, because "CS" and "DS" are already defined there. But AMBA is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. The patch adds the "PL330_" prefix to all register and bit fields, so it can be built by randomconfig after ARM_AMBA appears within x86. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- drivers/dma/pl330.c | 581 ++++++++++++++++++++++++++------------------------- 1 file changed, 292 insertions(+), 289 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 665668b..6de6de3 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -69,129 +69,129 @@ enum pl330_reqtype { }; /* Register and Bit field Definitions */ #define [-DS-]{+PL330_DS+} 0x0 #define [-DS_ST_STOP-]{+PL330_DS_ST_STOP+} 0x0 #define [-DS_ST_EXEC-]{+PL330_DS_ST_EXEC+} 0x1 #define [-DS_ST_CMISS-]{+PL330_DS_ST_CMISS+} 0x2 #define [-DS_ST_UPDTPC-]{+PL330_DS_ST_UPDTPC+} 0x3 #define [-DS_ST_WFE-]{+PL330_DS_ST_WFE+} 0x4 #define [-DS_ST_ATBRR-]{+PL330_DS_ST_ATBRR+} 0x5 #define [-DS_ST_QBUSY-]{+PL330_DS_ST_QBUSY+} 0x6 #define [-DS_ST_WFP-]{+PL330_DS_ST_WFP+} 0x7 #define [-DS_ST_KILL-]{+PL330_DS_ST_KILL+} 0x8 #define [-DS_ST_CMPLT-]{+PL330_DS_ST_CMPLT+} 0x9 #define [-DS_ST_FLTCMP-]{+PL330_DS_ST_FLTCMP+} 0xe #define [-DS_ST_FAULT-]{+PL330_DS_ST_FAULT+} 0xf #define [-DPC-]{+PL330_DPC+} 0x4 #define [-INTEN-]{+PL330_INTEN+} 0x20 #define [-ES-]{+PL330_ES+} 0x24 #define [-INTSTATUS-]{+PL330_INTSTATUS+} 0x28 #define [-INTCLR-]{+PL330_INTCLR+} 0x2c #define [-FSM-]{+PL330_FSM+} 0x30 #define [-FSC-]{+PL330_FSC+} 0x34 #define [-FTM-]{+PL330_FTM+} 0x38 #define _FTC 0x40 #define [-FTC(n)-]{+PL330_FTC(n)+} (_FTC + (n)*0x4) #define _CS 0x100 #define [-CS(n)-]{+PL330_CS(n)+} (_CS + (n)*0x8) #define [-CS_CNS-]{+PL330_CS_CNS+} (1 << 21) #define _CPC 0x104 #define [-CPC(n)-]{+PL330_CPC(n)+} (_CPC + (n)*0x8) #define _SA 0x400 #define [-SA(n)-]{+PL330_SA(n)+} (_SA + (n)*0x20) #define _DA 0x404 #define [-DA(n)-]{+PL330_DA(n)+} (_DA + (n)*0x20) #define _CC 0x408 #define [-CC(n)-]{+PL330_CC(n)+} (_CC + (n)*0x20) #define [-CC_SRCINC-]{+PL330_CC_SRCINC+} (1 << 0) #define [-CC_DSTINC-]{+PL330_CC_DSTINC+} (1 << 14) #define [-CC_SRCPRI-]{+PL330_CC_SRCPRI+} (1 << 8) #define [-CC_DSTPRI-]{+PL330_CC_DSTPRI+} (1 << 22) #define [-CC_SRCNS-]{+PL330_CC_SRCNS+} (1 << 9) #define [-CC_DSTNS-]{+PL330_CC_DSTNS+} (1 << 23) #define [-CC_SRCIA-]{+PL330_CC_SRCIA+} (1 << 10) #define [-CC_DSTIA-]{+PL330_CC_DSTIA+} (1 << 24) #define [-CC_SRCBRSTLEN_SHFT-]{+PL330_CC_SRCBRSTLEN_SHFT+} 4 #define [-CC_DSTBRSTLEN_SHFT-]{+PL330_CC_DSTBRSTLEN_SHFT+} 18 #define [-CC_SRCBRSTSIZE_SHFT-]{+PL330_CC_SRCBRSTSIZE_SHFT+} 1 #define [-CC_DSTBRSTSIZE_SHFT-]{+PL330_CC_DSTBRSTSIZE_SHFT+} 15 #define [-CC_SRCCCTRL_SHFT-]{+PL330_CC_SRCCCTRL_SHFT+} 11 #define [-CC_SRCCCTRL_MASK-]{+PL330_CC_SRCCCTRL_MASK+} 0x7 #define [-CC_DSTCCTRL_SHFT-]{+PL330_CC_DSTCCTRL_SHFT+} 25 #define [-CC_DRCCCTRL_MASK-]{+PL330_CC_DRCCCTRL_MASK+} 0x7 #define [-CC_SWAP_SHFT-]{+PL330_CC_SWAP_SHFT+} 28 #define _LC0 0x40c #define [-LC0(n)-]{+PL330_LC0(n)+} (_LC0 + (n)*0x20) #define _LC1 0x410 #define [-LC1(n)-]{+PL330_LC1(n)+} (_LC1 + (n)*0x20) #define [-DBGSTATUS-]{+PL330_DBGSTATUS+} 0xd00 #define [-DBG_BUSY-]{+PL330_DBG_BUSY+} (1 << 0) #define [-DBGCMD-]{+PL330_DBGCMD+} 0xd04 #define [-DBGINST0-]{+PL330_DBGINST0+} 0xd08 #define [-DBGINST1-]{+PL330_DBGINST1+} 0xd0c #define [-CR0-]{+PL330_CR0+} 0xe00 #define [-CR1-]{+PL330_CR1+} 0xe04 #define [-CR2-]{+PL330_CR2+} 0xe08 #define [-CR3-]{+PL330_CR3+} 0xe0c #define [-CR4-]{+PL330_CR4+} 0xe10 #define [-CRD-]{+PL330_CRD+} 0xe14 #define [-PERIPH_ID-]{+PL330_PERIPH_ID+} 0xfe0 #define [-PERIPH_REV_SHIFT-]{+PL330_PERIPH_REV_SHIFT+} 20 #define [-PERIPH_REV_MASK-]{+PL330_PERIPH_REV_MASK+} 0xf #define [-PERIPH_REV_R0P0-]{+PL330_PERIPH_REV_R0P0+} 0 #define [-PERIPH_REV_R1P0-]{+PL330_PERIPH_REV_R1P0+} 1 #define [-PERIPH_REV_R1P1-]{+PL330_PERIPH_REV_R1P1+} 2 #define [-PCELL_ID-]{+PL330_PCELL_ID+} 0xff0 #define [-CR0_PERIPH_REQ_SET-]{+PL330_CR0_PERIPH_REQ_SET+} (1 << 0) #define [-CR0_BOOT_EN_SET-]{+PL330_CR0_BOOT_EN_SET+} (1 << 1) #define [-CR0_BOOT_MAN_NS-]{+PL330_CR0_BOOT_MAN_NS+} (1 << 2) #define [-CR0_NUM_CHANS_SHIFT-]{+PL330_CR0_NUM_CHANS_SHIFT+} 4 #define [-CR0_NUM_CHANS_MASK-]{+PL330_CR0_NUM_CHANS_MASK+} 0x7 #define [-CR0_NUM_PERIPH_SHIFT-]{+PL330_CR0_NUM_PERIPH_SHIFT+} 12 #define [-CR0_NUM_PERIPH_MASK-]{+PL330_CR0_NUM_PERIPH_MASK+} 0x1f #define [-CR0_NUM_EVENTS_SHIFT-]{+PL330_CR0_NUM_EVENTS_SHIFT+} 17 #define [-CR0_NUM_EVENTS_MASK-]{+PL330_CR0_NUM_EVENTS_MASK+} 0x1f #define [-CR1_ICACHE_LEN_SHIFT-]{+PL330_CR1_ICACHE_LEN_SHIFT+} 0 #define [-CR1_ICACHE_LEN_MASK-]{+PL330_CR1_ICACHE_LEN_MASK+} 0x7 #define [-CR1_NUM_ICACHELINES_SHIFT-]{+PL330_CR1_NUM_ICACHELINES_SHIFT+} 4 #define [-CR1_NUM_ICACHELINES_MASK-]{+PL330_CR1_NUM_ICACHELINES_MASK+} 0xf #define [-CRD_DATA_WIDTH_SHIFT-]{+PL330_CRD_DATA_WIDTH_SHIFT+} 0 #define [-CRD_DATA_WIDTH_MASK-]{+PL330_CRD_DATA_WIDTH_MASK+} 0x7 #define [-CRD_WR_CAP_SHIFT-]{+PL330_CRD_WR_CAP_SHIFT+} 4 #define [-CRD_WR_CAP_MASK-]{+PL330_CRD_WR_CAP_MASK+} 0x7 #define [-CRD_WR_Q_DEP_SHIFT-]{+PL330_CRD_WR_Q_DEP_SHIFT+} 8 #define [-CRD_WR_Q_DEP_MASK-]{+PL330_CRD_WR_Q_DEP_MASK+} 0xf #define [-CRD_RD_CAP_SHIFT-]{+PL330_CRD_RD_CAP_SHIFT+} 12 #define [-CRD_RD_CAP_MASK-]{+PL330_CRD_RD_CAP_MASK+} 0x7 #define [-CRD_RD_Q_DEP_SHIFT-]{+PL330_CRD_RD_Q_DEP_SHIFT+} 16 #define [-CRD_RD_Q_DEP_MASK-]{+PL330_CRD_RD_Q_DEP_MASK+} 0xf #define [-CRD_DATA_BUFF_SHIFT-]{+PL330_CRD_DATA_BUFF_SHIFT+} 20 #define [-CRD_DATA_BUFF_MASK-]{+PL330_CRD_DATA_BUFF_MASK+} 0x3ff #define [-PART-]{+PL330_PART+} 0x330 #define [-DESIGNER-]{+PL330_DESIGNER+} 0x41 #define [-REVISION-]{+PL330_REVISION+} 0x0 #define [-INTEG_CFG-]{+PL330_INTEG_CFG+} 0x0 #define [-PERIPH_ID_VAL ((PART-]{+PL330_PERIPH_ID_VAL ((PL330_PART+} << 0) | [-(DESIGNER-]{+(PL330_DESIGNER+} << 12)) #define [-PCELL_ID_VAL-]{+PL330_PCELL_ID_VAL+} 0xb105f00d #define PL330_STATE_STOPPED (1 << 0) #define PL330_STATE_EXECUTING (1 << 1) @@ -210,48 +210,48 @@ enum pl330_reqtype { #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | PL330_STATE_WFE | PL330_STATE_FAULTING) #define [-CMD_DMAADDH-]{+PL330_CMD_DMAADDH+} 0x54 #define [-CMD_DMAEND-]{+PL330_CMD_DMAEND+} 0x00 #define [-CMD_DMAFLUSHP-]{+PL330_CMD_DMAFLUSHP+} 0x35 #define [-CMD_DMAGO-]{+PL330_CMD_DMAGO+} 0xa0 #define [-CMD_DMALD-]{+PL330_CMD_DMALD+} 0x04 #define [-CMD_DMALDP-]{+PL330_CMD_DMALDP+} 0x25 #define [-CMD_DMALP-]{+PL330_CMD_DMALP+} 0x20 #define [-CMD_DMALPEND-]{+PL330_CMD_DMALPEND+} 0x28 #define [-CMD_DMAKILL-]{+PL330_CMD_DMAKILL+} 0x01 #define [-CMD_DMAMOV-]{+PL330_CMD_DMAMOV+} 0xbc #define [-CMD_DMANOP-]{+PL330_CMD_DMANOP+} 0x18 #define [-CMD_DMARMB-]{+PL330_CMD_DMARMB+} 0x12 #define [-CMD_DMASEV-]{+PL330_CMD_DMASEV+} 0x34 #define [-CMD_DMAST-]{+PL330_CMD_DMAST+} 0x08 #define [-CMD_DMASTP-]{+PL330_CMD_DMASTP+} 0x29 #define [-CMD_DMASTZ-]{+PL330_CMD_DMASTZ+} 0x0c #define [-CMD_DMAWFE-]{+PL330_CMD_DMAWFE+} 0x36 #define [-CMD_DMAWFP-]{+PL330_CMD_DMAWFP+} 0x30 #define [-CMD_DMAWMB-]{+PL330_CMD_DMAWMB+} 0x13 #define [-SZ_DMAADDH-]{+PL330_SZ_DMAADDH+} 3 #define [-SZ_DMAEND-]{+PL330_SZ_DMAEND+} 1 #define [-SZ_DMAFLUSHP-]{+PL330_SZ_DMAFLUSHP+} 2 #define [-SZ_DMALD-]{+PL330_SZ_DMALD+} 1 #define [-SZ_DMALDP-]{+PL330_SZ_DMALDP+} 2 #define [-SZ_DMALP-]{+PL330_SZ_DMALP+} 2 #define [-SZ_DMALPEND-]{+PL330_SZ_DMALPEND+} 2 #define [-SZ_DMAKILL-]{+PL330_SZ_DMAKILL+} 1 #define [-SZ_DMAMOV-]{+PL330_SZ_DMAMOV+} 6 #define [-SZ_DMANOP-]{+PL330_SZ_DMANOP+} 1 #define [-SZ_DMARMB-]{+PL330_SZ_DMARMB+} 1 #define [-SZ_DMASEV-]{+PL330_SZ_DMASEV+} 2 #define [-SZ_DMAST-]{+PL330_SZ_DMAST+} 1 #define [-SZ_DMASTP-]{+PL330_SZ_DMASTP+} 2 #define [-SZ_DMASTZ-]{+PL330_SZ_DMASTZ+} 1 #define [-SZ_DMAWFE-]{+PL330_SZ_DMAWFE+} 2 #define [-SZ_DMAWFP-]{+PL330_SZ_DMAWFP+} 2 #define [-SZ_DMAWMB-]{+PL330_SZ_DMAWMB+} 1 #define [-SZ_DMAGO-]{+PL330_SZ_DMAGO+} 6 #define BRST_LEN(ccr) ((((ccr) >> [-CC_SRCBRSTLEN_SHFT)-]{+PL330_CC_SRCBRSTLEN_SHFT)+} & 0xf) + 1) #define BRST_SIZE(ccr) (1 << (((ccr) >> [-CC_SRCBRSTSIZE_SHFT)-]{+PL330_CC_SRCBRSTSIZE_SHFT)+} & 0x7)) #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) @@ -265,7 +265,7 @@ enum pl330_reqtype { #define MCODE_BUFF_PER_REQ 256 /* If the _pl330_req is available to the client */ #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == [-CMD_DMAEND)-]{+PL330_CMD_DMAEND)+} /* Use this _only_ to wait on transient states */ #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); @@ -658,43 +658,43 @@ static inline u32 get_id(struct pl330_info *pi, u32 off) static inline u32 get_revision(u32 periph_id) { return (periph_id >> [-PERIPH_REV_SHIFT)-]{+PL330_PERIPH_REV_SHIFT)+} & [-PERIPH_REV_MASK;-]{+PL330_PERIPH_REV_MASK;+} } static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], enum pl330_dst da, u16 val) { if (dry_run) return [-SZ_DMAADDH;-]{+PL330_SZ_DMAADDH;+} buf[0] = [-CMD_DMAADDH;-]{+PL330_CMD_DMAADDH;+} buf[0] |= (da << 1); *((u16 *)&buf[1]) = val; [-PL330_DBGCMD_DUMP(SZ_DMAADDH,-]{+PL330_DBGCMD_DUMP(PL330_SZ_DMAADDH,+} "\tDMAADDH %s %u\n", da == 1 ? "DA" : "SA", val); return [-SZ_DMAADDH;-]{+PL330_SZ_DMAADDH;+} } static inline u32 _emit_END(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMAEND;-]{+PL330_SZ_DMAEND;+} buf[0] = [-CMD_DMAEND;-]{+PL330_CMD_DMAEND;+} [-PL330_DBGCMD_DUMP(SZ_DMAEND,-]{+PL330_DBGCMD_DUMP(PL330_SZ_DMAEND,+} "\tDMAEND\n"); return [-SZ_DMAEND;-]{+PL330_SZ_DMAEND;+} } static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) { if (dry_run) return [-SZ_DMAFLUSHP;-]{+PL330_SZ_DMAFLUSHP;+} buf[0] = [-CMD_DMAFLUSHP;-]{+PL330_CMD_DMAFLUSHP;+} peri &= 0x1f; peri <<= 3; @@ -702,15 +702,15 @@ static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); return [-SZ_DMAFLUSHP;-]{+PL330_SZ_DMAFLUSHP;+} } static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) return [-SZ_DMALD;-]{+PL330_SZ_DMALD;+} buf[0] = [-CMD_DMALD;-]{+PL330_CMD_DMALD;+} if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); @@ -720,16 +720,16 @@ static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); return [-SZ_DMALD;-]{+PL330_SZ_DMALD;+} } static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) return [-SZ_DMALDP;-]{+PL330_SZ_DMALDP;+} buf[0] = [-CMD_DMALDP;-]{+PL330_CMD_DMALDP;+} if (cond == BURST) buf[0] |= (1 << 1); @@ -741,16 +741,16 @@ static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); return [-SZ_DMALDP;-]{+PL330_SZ_DMALDP;+} } static inline u32 _emit_LP(unsigned dry_run, u8 buf[], unsigned loop, u8 cnt) { if (dry_run) return [-SZ_DMALP;-]{+PL330_SZ_DMALP;+} buf[0] = [-CMD_DMALP;-]{+PL330_CMD_DMALP;+} if (loop) buf[0] |= (1 << 1); @@ -760,7 +760,7 @@ static inline u32 _emit_LP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); return [-SZ_DMALP;-]{+PL330_SZ_DMALP;+} } struct _arg_LPEND { @@ -779,9 +779,9 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], u8 bjump = arg->bjump; if (dry_run) return [-SZ_DMALPEND;-]{+PL330_SZ_DMALPEND;+} buf[0] = [-CMD_DMALPEND;-]{+PL330_CMD_DMALPEND;+} if (loop) buf[0] |= (1 << 2); @@ -802,65 +802,65 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], loop ? '1' : '0', bjump); return [-SZ_DMALPEND;-]{+PL330_SZ_DMALPEND;+} } static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMAKILL;-]{+PL330_SZ_DMAKILL;+} buf[0] = [-CMD_DMAKILL;-]{+PL330_CMD_DMAKILL;+} return [-SZ_DMAKILL;-]{+PL330_SZ_DMAKILL;+} } static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], enum dmamov_dst dst, u32 val) { if (dry_run) return [-SZ_DMAMOV;-]{+PL330_SZ_DMAMOV;+} buf[0] = [-CMD_DMAMOV;-]{+PL330_CMD_DMAMOV;+} buf[1] = dst; *((u32 *)&buf[2]) = val; PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); return [-SZ_DMAMOV;-]{+PL330_SZ_DMAMOV;+} } static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMANOP;-]{+PL330_SZ_DMANOP;+} buf[0] = [-CMD_DMANOP;-]{+PL330_CMD_DMANOP;+} PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); return [-SZ_DMANOP;-]{+PL330_SZ_DMANOP;+} } static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMARMB;-]{+PL330_SZ_DMARMB;+} buf[0] = [-CMD_DMARMB;-]{+PL330_CMD_DMARMB;+} PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); return [-SZ_DMARMB;-]{+PL330_SZ_DMARMB;+} } static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) { if (dry_run) return [-SZ_DMASEV;-]{+PL330_SZ_DMASEV;+} buf[0] = [-CMD_DMASEV;-]{+PL330_CMD_DMASEV;+} ev &= 0x1f; ev <<= 3; @@ -868,15 +868,15 @@ static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); return [-SZ_DMASEV;-]{+PL330_SZ_DMASEV;+} } static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) return [-SZ_DMAST;-]{+PL330_SZ_DMAST;+} buf[0] = [-CMD_DMAST;-]{+PL330_CMD_DMAST;+} if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); @@ -886,16 +886,16 @@ static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); return [-SZ_DMAST;-]{+PL330_SZ_DMAST;+} } static inline u32 _emit_STP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) return [-SZ_DMASTP;-]{+PL330_SZ_DMASTP;+} buf[0] = [-CMD_DMASTP;-]{+PL330_CMD_DMASTP;+} if (cond == BURST) buf[0] |= (1 << 1); @@ -907,28 +907,28 @@ static inline u32 _emit_STP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); return [-SZ_DMASTP;-]{+PL330_SZ_DMASTP;+} } static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMASTZ;-]{+PL330_SZ_DMASTZ;+} buf[0] = [-CMD_DMASTZ;-]{+PL330_CMD_DMASTZ;+} PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); return [-SZ_DMASTZ;-]{+PL330_SZ_DMASTZ;+} } static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, unsigned invalidate) { if (dry_run) return [-SZ_DMAWFE;-]{+PL330_SZ_DMAWFE;+} buf[0] = [-CMD_DMAWFE;-]{+PL330_CMD_DMAWFE;+} ev &= 0x1f; ev <<= 3; @@ -940,16 +940,16 @@ static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", ev >> 3, invalidate ? ", I" : ""); return [-SZ_DMAWFE;-]{+PL330_SZ_DMAWFE;+} } static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) return [-SZ_DMAWFP;-]{+PL330_SZ_DMAWFP;+} buf[0] = [-CMD_DMAWFP;-]{+PL330_CMD_DMAWFP;+} if (cond == SINGLE) buf[0] |= (0 << 1) | (0 << 0); @@ -965,19 +965,19 @@ static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); return [-SZ_DMAWFP;-]{+PL330_SZ_DMAWFP;+} } static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMAWMB;-]{+PL330_SZ_DMAWMB;+} buf[0] = [-CMD_DMAWMB;-]{+PL330_CMD_DMAWMB;+} PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); return [-SZ_DMAWMB;-]{+PL330_SZ_DMAWMB;+} } struct _arg_GO { @@ -994,16 +994,16 @@ static inline u32 _emit_GO(unsigned dry_run, u8 buf[], unsigned ns = arg->ns; if (dry_run) return [-SZ_DMAGO;-]{+PL330_SZ_DMAGO;+} buf[0] = [-CMD_DMAGO;-]{+PL330_CMD_DMAGO;+} buf[0] |= (ns << 1); buf[1] = chan & 0x7; *((u32 *)&buf[2]) = addr; return [-SZ_DMAGO;-]{+PL330_SZ_DMAGO;+} } #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) @@ -1016,7 +1016,7 @@ static bool _until_dmac_idle(struct pl330_thread *thrd) do { /* Until Manager is Idle */ if (!(readl(regs + [-DBGSTATUS)-]{+PL330_DBGSTATUS)+} & [-DBG_BUSY))-]{+PL330_DBG_BUSY))+} break; cpu_relax(); @@ -1039,10 +1039,10 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, val |= (1 << 0); val |= (thrd->id << 8); /* Channel Number */ } writel(val, regs + [-DBGINST0);-]{+PL330_DBGINST0);+} val = *((u32 *)&insn[2]); writel(val, regs + [-DBGINST1);-]{+PL330_DBGINST1);+} /* If timed out due to halted state-machine */ if (_until_dmac_idle(thrd)) { @@ -1051,7 +1051,7 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, } /* Get going */ writel(0, regs + [-DBGCMD);-]{+PL330_DBGCMD);+} } /* @@ -1078,47 +1078,47 @@ static inline u32 _state(struct pl330_thread *thrd) if (is_manager(thrd)) val = readl(regs + DS) & 0xf; else val = readl(regs + [-CS(thrd->id))-]{+PL330_CS(thrd->id))+} & 0xf; switch (val) { case [-DS_ST_STOP:-]{+PL330_DS_ST_STOP:+} return PL330_STATE_STOPPED; case [-DS_ST_EXEC:-]{+PL330_DS_ST_EXEC:+} return PL330_STATE_EXECUTING; case [-DS_ST_CMISS:-]{+PL330_DS_ST_CMISS:+} return PL330_STATE_CACHEMISS; case [-DS_ST_UPDTPC:-]{+PL330_DS_ST_UPDTPC:+} return PL330_STATE_UPDTPC; case [-DS_ST_WFE:-]{+PL330_DS_ST_WFE:+} return PL330_STATE_WFE; case [-DS_ST_FAULT:-]{+PL330_DS_ST_FAULT:+} return PL330_STATE_FAULTING; case [-DS_ST_ATBRR:-]{+PL330_DS_ST_ATBRR:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_ATBARRIER; case [-DS_ST_QBUSY:-]{+PL330_DS_ST_QBUSY:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_QUEUEBUSY; case [-DS_ST_WFP:-]{+PL330_DS_ST_WFP:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_WFP; case [-DS_ST_KILL:-]{+PL330_DS_ST_KILL:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_KILLING; case [-DS_ST_CMPLT:-]{+PL330_DS_ST_CMPLT:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_COMPLETING; case [-DS_ST_FLTCMP:-]{+PL330_DS_ST_FLTCMP:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else @@ -1145,7 +1145,8 @@ static void _stop(struct pl330_thread *thrd) _emit_KILL(0, insn); /* Stop generating interrupts for SEV */ writel(readl(regs + [-INTEN)-]{+PL330_INTEN)+} & ~(1 << thrd->ev), regs + [-INTEN);-]{+PL330_INTEN);+} _execute_DBGINSN(thrd, insn, is_manager(thrd)); } @@ -1184,7 +1185,7 @@ static bool _trigger(struct pl330_thread *thrd) if (r->cfg) ns = r->cfg->nonsecure ? 1 : 0; else if (readl(regs + [-CS(thrd->id))-]{+PL330_CS(thrd->id))+} & [-CS_CNS)-]{+PL330_CS_CNS)+} ns = 1; else ns = 0; @@ -1200,7 +1201,7 @@ static bool _trigger(struct pl330_thread *thrd) _emit_GO(0, insn, &go); /* Set to generate interrupts for SEV */ writel(readl(regs + [-INTEN)-]{+PL330_INTEN)+} | (1 << thrd->ev), regs + [-INTEN);-]{+PL330_INTEN);+} /* Only manager can execute GO */ _execute_DBGINSN(thrd, insn, true); @@ -1250,7 +1251,7 @@ static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], struct pl330_config *pcfg = pxs->r->cfg->pcfg; /* check lock-up free version */ if (get_revision(pcfg->periph_id) >= [-PERIPH_REV_R1P0)-]{+PL330_PERIPH_REV_R1P0)+} { while (cyc--) { off += _emit_LD(dry_run, &buf[off], ALWAYS); off += _emit_ST(dry_run, &buf[off], ALWAYS); @@ -1475,29 +1476,29 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) u32 ccr = 0; if (rqc->src_inc) ccr |= [-CC_SRCINC;-]{+PL330_CC_SRCINC;+} if (rqc->dst_inc) ccr |= [-CC_DSTINC;-]{+PL330_CC_DSTINC;+} /* We set same protection levels for Src and DST for now */ if (rqc->privileged) ccr |= [-CC_SRCPRI-]{+PL330_CC_SRCPRI+} | [-CC_DSTPRI;-]{+PL330_CC_DSTPRI;+} if (rqc->nonsecure) ccr |= [-CC_SRCNS-]{+PL330_CC_SRCNS+} | [-CC_DSTNS;-]{+PL330_CC_DSTNS;+} if (rqc->insnaccess) ccr |= [-CC_SRCIA-]{+PL330_CC_SRCIA+} | [-CC_DSTIA;-]{+PL330_CC_DSTIA;+} ccr |= (((rqc->brst_len - 1) & 0xf) << [-CC_SRCBRSTLEN_SHFT);-]{+PL330_CC_SRCBRSTLEN_SHFT);+} ccr |= (((rqc->brst_len - 1) & 0xf) << [-CC_DSTBRSTLEN_SHFT);-]{+PL330_CC_DSTBRSTLEN_SHFT);+} ccr |= (rqc->brst_size << [-CC_SRCBRSTSIZE_SHFT);-]{+PL330_CC_SRCBRSTSIZE_SHFT);+} ccr |= (rqc->brst_size << [-CC_DSTBRSTSIZE_SHFT);-]{+PL330_CC_DSTBRSTSIZE_SHFT);+} ccr |= (rqc->scctl << [-CC_SRCCCTRL_SHFT);-]{+PL330_CC_SRCCCTRL_SHFT);+} ccr |= (rqc->dcctl << [-CC_DSTCCTRL_SHFT);-]{+PL330_CC_DSTCCTRL_SHFT);+} ccr |= (rqc->swap << [-CC_SWAP_SHFT);-]{+PL330_CC_SWAP_SHFT);+} return ccr; } @@ -1507,8 +1508,8 @@ static inline bool _is_valid(u32 ccr) enum pl330_dstcachectrl dcctl; enum pl330_srccachectrl scctl; dcctl = (ccr >> [-CC_DSTCCTRL_SHFT)-]{+PL330_CC_DSTCCTRL_SHFT)+} & [-CC_DRCCCTRL_MASK;-]{+PL330_CC_DRCCCTRL_MASK;+} scctl = (ccr >> [-CC_SRCCCTRL_SHFT)-]{+PL330_CC_SRCCCTRL_SHFT)+} & [-CC_SRCCCTRL_MASK;-]{+PL330_CC_SRCCCTRL_MASK;+} if (dcctl == DINVALID1 || dcctl == DINVALID2 || scctl == SINVALID1 || scctl == SINVALID2) @@ -1575,7 +1576,7 @@ static int pl330_submit_req(void *ch_id, struct pl330_req *r) ccr = _prepare_ccr(r->cfg); } else { ccr = readl(regs + [-CC(thrd->id));-]{+PL330_CC(thrd->id));+} } /* If this req doesn't have valid xfer settings */ @@ -1652,7 +1653,7 @@ static void pl330_dotask(unsigned long data) _stop(thrd); if (readl(regs + [-FSC)-]{+PL330_FSC)+} & (1 << thrd->id)) err = PL330_ERR_FAIL; else err = PL330_ERR_ABORT; @@ -1697,13 +1698,13 @@ static int pl330_update(const struct pl330_info *pi) spin_lock_irqsave(&pl330->lock, flags); val = readl(regs + [-FSM)-]{+PL330_FSM)+} & 0x1; if (val) pl330->dmac_tbd.reset_mngr = true; else pl330->dmac_tbd.reset_mngr = false; val = readl(regs + [-FSC)-]{+PL330_FSC)+} & ((1 << pi->pcfg.num_chan) - 1); pl330->dmac_tbd.reset_chan |= val; if (val) { int i = 0; @@ -1711,8 +1712,8 @@ static int pl330_update(const struct pl330_info *pi) if (val & (1 << i)) { dev_info(pi->dev, "Reset Channel-%d\t CS-%x FTC-%x\n", i, readl(regs + [-CS(i)),-]{+PL330_CS(i)),+} readl(regs + [-FTC(i)));-]{+PL330_FTC(i)));+} _stop(&pl330->channels[i]); } i++; @@ -1732,12 +1733,12 @@ static int pl330_update(const struct pl330_info *pi) for (ev = 0; ev < pi->pcfg.num_events; ev++) { if (val & (1 << ev)) { /* Event occurred */ struct pl330_thread *thrd; u32 inten = readl(regs + [-INTEN);-]{+PL330_INTEN);+} int active; /* Clear the event */ if (inten & (1 << ev)) writel(1 << ev, regs + [-INTCLR);-]{+PL330_INTCLR);+} ret = 1; @@ -1944,44 +1945,45 @@ static void read_dmac_config(struct pl330_info *pi) void __iomem *regs = pi->base; u32 val; val = readl(regs + [-CRD)-]{+PL330_CRD)+} >> [-CRD_DATA_WIDTH_SHIFT;-]{+PL330_CRD_DATA_WIDTH_SHIFT;+} val &= [-CRD_DATA_WIDTH_MASK;-]{+PL330_CRD_DATA_WIDTH_MASK;+} pi->pcfg.data_bus_width = 8 * (1 << val); val = readl(regs + [-CRD)-]{+PL330_CRD)+} >> [-CRD_DATA_BUFF_SHIFT;-]{+PL330_CRD_DATA_BUFF_SHIFT;+} val &= [-CRD_DATA_BUFF_MASK;-]{+PL330_CRD_DATA_BUFF_MASK;+} pi->pcfg.data_buf_dep = val + 1; val = readl(regs + [-CR0)-]{+PL330_CR0)+} >> [-CR0_NUM_CHANS_SHIFT;-]{+PL330_CR0_NUM_CHANS_SHIFT;+} val &= [-CR0_NUM_CHANS_MASK;-]{+PL330_CR0_NUM_CHANS_MASK;+} val += 1; pi->pcfg.num_chan = val; val = readl(regs + [-CR0);-]{+PL330_CR0);+} if (val & [-CR0_PERIPH_REQ_SET)-]{+PL330_CR0_PERIPH_REQ_SET)+} { val = (val >> [-CR0_NUM_PERIPH_SHIFT)-]{+PL330_CR0_NUM_PERIPH_SHIFT)+} & [-CR0_NUM_PERIPH_MASK;-]{+PL330_CR0_NUM_PERIPH_MASK;+} val += 1; pi->pcfg.num_peri = val; pi->pcfg.peri_ns = readl(regs + [-CR4);-]{+PL330_CR4);+} } else { pi->pcfg.num_peri = 0; } val = readl(regs + [-CR0);-]{+PL330_CR0);+} if (val & [-CR0_BOOT_MAN_NS)-]{+PL330_CR0_BOOT_MAN_NS)+} pi->pcfg.mode |= DMAC_MODE_NS; else pi->pcfg.mode &= ~DMAC_MODE_NS; val = readl(regs + [-CR0)-]{+PL330_CR0)+} >> [-CR0_NUM_EVENTS_SHIFT;-]{+PL330_CR0_NUM_EVENTS_SHIFT;+} val &= [-CR0_NUM_EVENTS_MASK;-]{+PL330_CR0_NUM_EVENTS_MASK;+} val += 1; pi->pcfg.num_events = val; pi->pcfg.irq_ns = readl(regs + [-CR3);-]{+PL330_CR3);+} pi->pcfg.periph_id = get_id(pi, [-PERIPH_ID);-]{+PL330_PERIPH_ID);+} pi->pcfg.pcell_id = get_id(pi, [-PCELL_ID);-]{+PL330_PCELL_ID);+} } static inline void _reset_thread(struct pl330_thread *thrd) @@ -2091,10 +2093,11 @@ static int pl330_add(struct pl330_info *pi) regs = pi->base; /* Check if we can handle this DMAC */ if ((get_id(pi, [-PERIPH_ID)-]{+PL330_PERIPH_ID)+} & 0xfffff) != [-PERIPH_ID_VAL-]{+PL330_PERIPH_ID_VAL+} || get_id(pi, [-PCELL_ID)-]{+PL330_PCELL_ID)+} != [-PCELL_ID_VAL)-]{+PL330_PCELL_ID_VAL)+} { dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n", get_id(pi, [-PERIPH_ID),-]{+PL330_PERIPH_ID),+} get_id(pi, [-PCELL_ID));-]{+PL330_PCELL_ID));+} return -EINVAL; } -- 1.7.10.4 ============================================================================ Please let me know if I can do something more to help you reviewing this. Thanks and regards Davide ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 1/8] DMA: PL330: use prefix in reg names to build under x86 2012-11-23 17:23 ` Davide Ciminaghi @ 2012-11-23 17:28 ` Viresh Kumar 2012-11-24 0:53 ` [PATCH 1/8 v3] " Davide Ciminaghi 0 siblings, 1 reply; 34+ messages in thread From: Viresh Kumar @ 2012-11-23 17:28 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On 23 November 2012 22:53, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > I tried that, but the resulting patch does not apply: It will not. Git doesn't support it. > $ git checkout -b pl330_test next-20121115 > Switched to a new branch 'pl330_test' > > $ git format-patch --word-diff 5f1e3c5~..5f1e3c5 I never asked you to do this. I asked you to use git diff command, just to verify what you have done is right or not? You can't send output of that as a patch :) And maybe post that as an part of non-commit log, so that others can quickly review it. But because your patch is too big, it will make it a huge patch. It was just an trick i was sharing with everybody else. > Did I do anything wrong (sorry, I'm not a git guru at all) ? Neither am i :) -- viresh ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 1/8 v3] DMA: PL330: use prefix in reg names to build under x86 2012-11-23 17:28 ` Viresh Kumar @ 2012-11-24 0:53 ` Davide Ciminaghi 2012-11-24 5:14 ` Jassi Brar 2012-11-24 7:03 ` Alessandro Rubini 0 siblings, 2 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-24 0:53 UTC (permalink / raw) To: viresh.linux Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> This driver would not compile if ARM_AMBA is selected under x86, because "CS" and "DS" are already defined there. But AMBA is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. The patch just adds the "PL330_" prefix to all register and bit fields, so it can be built by randomconfig after ARM_AMBA appears within x86. No other technical changes have been performed. The patch was build-tested only. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- The patch is very big, but what it actually does is just renaming the pl330 registers. As requested by Viresh Kumar, what follows is the output of git diff --word-diff b9740f9~..b9740f9 This format should allow better readability for reviewing. Note that 'index' and '@@' strings at the beginning of lines have been escaped by adding a leading '#' to avoid errors while actually applying the patch. The changelog has also been slightly adjusted with respect to 1/8 v2, so I'm resending as v3. diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c #index 665668b..6de6de3 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c #@@ -69,129 +69,129 @@ enum pl330_reqtype { }; /* Register and Bit field Definitions */ #define [-DS-]{+PL330_DS+} 0x0 #define [-DS_ST_STOP-]{+PL330_DS_ST_STOP+} 0x0 #define [-DS_ST_EXEC-]{+PL330_DS_ST_EXEC+} 0x1 #define [-DS_ST_CMISS-]{+PL330_DS_ST_CMISS+} 0x2 #define [-DS_ST_UPDTPC-]{+PL330_DS_ST_UPDTPC+} 0x3 #define [-DS_ST_WFE-]{+PL330_DS_ST_WFE+} 0x4 #define [-DS_ST_ATBRR-]{+PL330_DS_ST_ATBRR+} 0x5 #define [-DS_ST_QBUSY-]{+PL330_DS_ST_QBUSY+} 0x6 #define [-DS_ST_WFP-]{+PL330_DS_ST_WFP+} 0x7 #define [-DS_ST_KILL-]{+PL330_DS_ST_KILL+} 0x8 #define [-DS_ST_CMPLT-]{+PL330_DS_ST_CMPLT+} 0x9 #define [-DS_ST_FLTCMP-]{+PL330_DS_ST_FLTCMP+} 0xe #define [-DS_ST_FAULT-]{+PL330_DS_ST_FAULT+} 0xf #define [-DPC-]{+PL330_DPC+} 0x4 #define [-INTEN-]{+PL330_INTEN+} 0x20 #define [-ES-]{+PL330_ES+} 0x24 #define [-INTSTATUS-]{+PL330_INTSTATUS+} 0x28 #define [-INTCLR-]{+PL330_INTCLR+} 0x2c #define [-FSM-]{+PL330_FSM+} 0x30 #define [-FSC-]{+PL330_FSC+} 0x34 #define [-FTM-]{+PL330_FTM+} 0x38 #define _FTC 0x40 #define [-FTC(n)-]{+PL330_FTC(n)+} (_FTC + (n)*0x4) #define _CS 0x100 #define [-CS(n)-]{+PL330_CS(n)+} (_CS + (n)*0x8) #define [-CS_CNS-]{+PL330_CS_CNS+} (1 << 21) #define _CPC 0x104 #define [-CPC(n)-]{+PL330_CPC(n)+} (_CPC + (n)*0x8) #define _SA 0x400 #define [-SA(n)-]{+PL330_SA(n)+} (_SA + (n)*0x20) #define _DA 0x404 #define [-DA(n)-]{+PL330_DA(n)+} (_DA + (n)*0x20) #define _CC 0x408 #define [-CC(n)-]{+PL330_CC(n)+} (_CC + (n)*0x20) #define [-CC_SRCINC-]{+PL330_CC_SRCINC+} (1 << 0) #define [-CC_DSTINC-]{+PL330_CC_DSTINC+} (1 << 14) #define [-CC_SRCPRI-]{+PL330_CC_SRCPRI+} (1 << 8) #define [-CC_DSTPRI-]{+PL330_CC_DSTPRI+} (1 << 22) #define [-CC_SRCNS-]{+PL330_CC_SRCNS+} (1 << 9) #define [-CC_DSTNS-]{+PL330_CC_DSTNS+} (1 << 23) #define [-CC_SRCIA-]{+PL330_CC_SRCIA+} (1 << 10) #define [-CC_DSTIA-]{+PL330_CC_DSTIA+} (1 << 24) #define [-CC_SRCBRSTLEN_SHFT-]{+PL330_CC_SRCBRSTLEN_SHFT+} 4 #define [-CC_DSTBRSTLEN_SHFT-]{+PL330_CC_DSTBRSTLEN_SHFT+} 18 #define [-CC_SRCBRSTSIZE_SHFT-]{+PL330_CC_SRCBRSTSIZE_SHFT+} 1 #define [-CC_DSTBRSTSIZE_SHFT-]{+PL330_CC_DSTBRSTSIZE_SHFT+} 15 #define [-CC_SRCCCTRL_SHFT-]{+PL330_CC_SRCCCTRL_SHFT+} 11 #define [-CC_SRCCCTRL_MASK-]{+PL330_CC_SRCCCTRL_MASK+} 0x7 #define [-CC_DSTCCTRL_SHFT-]{+PL330_CC_DSTCCTRL_SHFT+} 25 #define [-CC_DRCCCTRL_MASK-]{+PL330_CC_DRCCCTRL_MASK+} 0x7 #define [-CC_SWAP_SHFT-]{+PL330_CC_SWAP_SHFT+} 28 #define _LC0 0x40c #define [-LC0(n)-]{+PL330_LC0(n)+} (_LC0 + (n)*0x20) #define _LC1 0x410 #define [-LC1(n)-]{+PL330_LC1(n)+} (_LC1 + (n)*0x20) #define [-DBGSTATUS-]{+PL330_DBGSTATUS+} 0xd00 #define [-DBG_BUSY-]{+PL330_DBG_BUSY+} (1 << 0) #define [-DBGCMD-]{+PL330_DBGCMD+} 0xd04 #define [-DBGINST0-]{+PL330_DBGINST0+} 0xd08 #define [-DBGINST1-]{+PL330_DBGINST1+} 0xd0c #define [-CR0-]{+PL330_CR0+} 0xe00 #define [-CR1-]{+PL330_CR1+} 0xe04 #define [-CR2-]{+PL330_CR2+} 0xe08 #define [-CR3-]{+PL330_CR3+} 0xe0c #define [-CR4-]{+PL330_CR4+} 0xe10 #define [-CRD-]{+PL330_CRD+} 0xe14 #define [-PERIPH_ID-]{+PL330_PERIPH_ID+} 0xfe0 #define [-PERIPH_REV_SHIFT-]{+PL330_PERIPH_REV_SHIFT+} 20 #define [-PERIPH_REV_MASK-]{+PL330_PERIPH_REV_MASK+} 0xf #define [-PERIPH_REV_R0P0-]{+PL330_PERIPH_REV_R0P0+} 0 #define [-PERIPH_REV_R1P0-]{+PL330_PERIPH_REV_R1P0+} 1 #define [-PERIPH_REV_R1P1-]{+PL330_PERIPH_REV_R1P1+} 2 #define [-PCELL_ID-]{+PL330_PCELL_ID+} 0xff0 #define [-CR0_PERIPH_REQ_SET-]{+PL330_CR0_PERIPH_REQ_SET+} (1 << 0) #define [-CR0_BOOT_EN_SET-]{+PL330_CR0_BOOT_EN_SET+} (1 << 1) #define [-CR0_BOOT_MAN_NS-]{+PL330_CR0_BOOT_MAN_NS+} (1 << 2) #define [-CR0_NUM_CHANS_SHIFT-]{+PL330_CR0_NUM_CHANS_SHIFT+} 4 #define [-CR0_NUM_CHANS_MASK-]{+PL330_CR0_NUM_CHANS_MASK+} 0x7 #define [-CR0_NUM_PERIPH_SHIFT-]{+PL330_CR0_NUM_PERIPH_SHIFT+} 12 #define [-CR0_NUM_PERIPH_MASK-]{+PL330_CR0_NUM_PERIPH_MASK+} 0x1f #define [-CR0_NUM_EVENTS_SHIFT-]{+PL330_CR0_NUM_EVENTS_SHIFT+} 17 #define [-CR0_NUM_EVENTS_MASK-]{+PL330_CR0_NUM_EVENTS_MASK+} 0x1f #define [-CR1_ICACHE_LEN_SHIFT-]{+PL330_CR1_ICACHE_LEN_SHIFT+} 0 #define [-CR1_ICACHE_LEN_MASK-]{+PL330_CR1_ICACHE_LEN_MASK+} 0x7 #define [-CR1_NUM_ICACHELINES_SHIFT-]{+PL330_CR1_NUM_ICACHELINES_SHIFT+} 4 #define [-CR1_NUM_ICACHELINES_MASK-]{+PL330_CR1_NUM_ICACHELINES_MASK+} 0xf #define [-CRD_DATA_WIDTH_SHIFT-]{+PL330_CRD_DATA_WIDTH_SHIFT+} 0 #define [-CRD_DATA_WIDTH_MASK-]{+PL330_CRD_DATA_WIDTH_MASK+} 0x7 #define [-CRD_WR_CAP_SHIFT-]{+PL330_CRD_WR_CAP_SHIFT+} 4 #define [-CRD_WR_CAP_MASK-]{+PL330_CRD_WR_CAP_MASK+} 0x7 #define [-CRD_WR_Q_DEP_SHIFT-]{+PL330_CRD_WR_Q_DEP_SHIFT+} 8 #define [-CRD_WR_Q_DEP_MASK-]{+PL330_CRD_WR_Q_DEP_MASK+} 0xf #define [-CRD_RD_CAP_SHIFT-]{+PL330_CRD_RD_CAP_SHIFT+} 12 #define [-CRD_RD_CAP_MASK-]{+PL330_CRD_RD_CAP_MASK+} 0x7 #define [-CRD_RD_Q_DEP_SHIFT-]{+PL330_CRD_RD_Q_DEP_SHIFT+} 16 #define [-CRD_RD_Q_DEP_MASK-]{+PL330_CRD_RD_Q_DEP_MASK+} 0xf #define [-CRD_DATA_BUFF_SHIFT-]{+PL330_CRD_DATA_BUFF_SHIFT+} 20 #define [-CRD_DATA_BUFF_MASK-]{+PL330_CRD_DATA_BUFF_MASK+} 0x3ff #define [-PART-]{+PL330_PART+} 0x330 #define [-DESIGNER-]{+PL330_DESIGNER+} 0x41 #define [-REVISION-]{+PL330_REVISION+} 0x0 #define [-INTEG_CFG-]{+PL330_INTEG_CFG+} 0x0 #define [-PERIPH_ID_VAL ((PART-]{+PL330_PERIPH_ID_VAL ((PL330_PART+} << 0) | [-(DESIGNER-]{+(PL330_DESIGNER+} << 12)) #define [-PCELL_ID_VAL-]{+PL330_PCELL_ID_VAL+} 0xb105f00d #define PL330_STATE_STOPPED (1 << 0) #define PL330_STATE_EXECUTING (1 << 1) #@@ -210,48 +210,48 @@ enum pl330_reqtype { #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | PL330_STATE_WFE | PL330_STATE_FAULTING) #define [-CMD_DMAADDH-]{+PL330_CMD_DMAADDH+} 0x54 #define [-CMD_DMAEND-]{+PL330_CMD_DMAEND+} 0x00 #define [-CMD_DMAFLUSHP-]{+PL330_CMD_DMAFLUSHP+} 0x35 #define [-CMD_DMAGO-]{+PL330_CMD_DMAGO+} 0xa0 #define [-CMD_DMALD-]{+PL330_CMD_DMALD+} 0x04 #define [-CMD_DMALDP-]{+PL330_CMD_DMALDP+} 0x25 #define [-CMD_DMALP-]{+PL330_CMD_DMALP+} 0x20 #define [-CMD_DMALPEND-]{+PL330_CMD_DMALPEND+} 0x28 #define [-CMD_DMAKILL-]{+PL330_CMD_DMAKILL+} 0x01 #define [-CMD_DMAMOV-]{+PL330_CMD_DMAMOV+} 0xbc #define [-CMD_DMANOP-]{+PL330_CMD_DMANOP+} 0x18 #define [-CMD_DMARMB-]{+PL330_CMD_DMARMB+} 0x12 #define [-CMD_DMASEV-]{+PL330_CMD_DMASEV+} 0x34 #define [-CMD_DMAST-]{+PL330_CMD_DMAST+} 0x08 #define [-CMD_DMASTP-]{+PL330_CMD_DMASTP+} 0x29 #define [-CMD_DMASTZ-]{+PL330_CMD_DMASTZ+} 0x0c #define [-CMD_DMAWFE-]{+PL330_CMD_DMAWFE+} 0x36 #define [-CMD_DMAWFP-]{+PL330_CMD_DMAWFP+} 0x30 #define [-CMD_DMAWMB-]{+PL330_CMD_DMAWMB+} 0x13 #define [-SZ_DMAADDH-]{+PL330_SZ_DMAADDH+} 3 #define [-SZ_DMAEND-]{+PL330_SZ_DMAEND+} 1 #define [-SZ_DMAFLUSHP-]{+PL330_SZ_DMAFLUSHP+} 2 #define [-SZ_DMALD-]{+PL330_SZ_DMALD+} 1 #define [-SZ_DMALDP-]{+PL330_SZ_DMALDP+} 2 #define [-SZ_DMALP-]{+PL330_SZ_DMALP+} 2 #define [-SZ_DMALPEND-]{+PL330_SZ_DMALPEND+} 2 #define [-SZ_DMAKILL-]{+PL330_SZ_DMAKILL+} 1 #define [-SZ_DMAMOV-]{+PL330_SZ_DMAMOV+} 6 #define [-SZ_DMANOP-]{+PL330_SZ_DMANOP+} 1 #define [-SZ_DMARMB-]{+PL330_SZ_DMARMB+} 1 #define [-SZ_DMASEV-]{+PL330_SZ_DMASEV+} 2 #define [-SZ_DMAST-]{+PL330_SZ_DMAST+} 1 #define [-SZ_DMASTP-]{+PL330_SZ_DMASTP+} 2 #define [-SZ_DMASTZ-]{+PL330_SZ_DMASTZ+} 1 #define [-SZ_DMAWFE-]{+PL330_SZ_DMAWFE+} 2 #define [-SZ_DMAWFP-]{+PL330_SZ_DMAWFP+} 2 #define [-SZ_DMAWMB-]{+PL330_SZ_DMAWMB+} 1 #define [-SZ_DMAGO-]{+PL330_SZ_DMAGO+} 6 #define BRST_LEN(ccr) ((((ccr) >> [-CC_SRCBRSTLEN_SHFT)-]{+PL330_CC_SRCBRSTLEN_SHFT)+} & 0xf) + 1) #define BRST_SIZE(ccr) (1 << (((ccr) >> [-CC_SRCBRSTSIZE_SHFT)-]{+PL330_CC_SRCBRSTSIZE_SHFT)+} & 0x7)) #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) #@@ -265,7 +265,7 @@ enum pl330_reqtype { #define MCODE_BUFF_PER_REQ 256 /* If the _pl330_req is available to the client */ #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == [-CMD_DMAEND)-]{+PL330_CMD_DMAEND)+} /* Use this _only_ to wait on transient states */ #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); #@@ -658,43 +658,43 @@ static inline u32 get_id(struct pl330_info *pi, u32 off) static inline u32 get_revision(u32 periph_id) { return (periph_id >> [-PERIPH_REV_SHIFT)-]{+PL330_PERIPH_REV_SHIFT)+} & [-PERIPH_REV_MASK;-]{+PL330_PERIPH_REV_MASK;+} } static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], enum pl330_dst da, u16 val) { if (dry_run) return [-SZ_DMAADDH;-]{+PL330_SZ_DMAADDH;+} buf[0] = [-CMD_DMAADDH;-]{+PL330_CMD_DMAADDH;+} buf[0] |= (da << 1); *((u16 *)&buf[1]) = val; [-PL330_DBGCMD_DUMP(SZ_DMAADDH,-]{+PL330_DBGCMD_DUMP(PL330_SZ_DMAADDH,+} "\tDMAADDH %s %u\n", da == 1 ? "DA" : "SA", val); return [-SZ_DMAADDH;-]{+PL330_SZ_DMAADDH;+} } static inline u32 _emit_END(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMAEND;-]{+PL330_SZ_DMAEND;+} buf[0] = [-CMD_DMAEND;-]{+PL330_CMD_DMAEND;+} [-PL330_DBGCMD_DUMP(SZ_DMAEND,-]{+PL330_DBGCMD_DUMP(PL330_SZ_DMAEND,+} "\tDMAEND\n"); return [-SZ_DMAEND;-]{+PL330_SZ_DMAEND;+} } static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) { if (dry_run) return [-SZ_DMAFLUSHP;-]{+PL330_SZ_DMAFLUSHP;+} buf[0] = [-CMD_DMAFLUSHP;-]{+PL330_CMD_DMAFLUSHP;+} peri &= 0x1f; peri <<= 3; #@@ -702,15 +702,15 @@ static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); return [-SZ_DMAFLUSHP;-]{+PL330_SZ_DMAFLUSHP;+} } static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) return [-SZ_DMALD;-]{+PL330_SZ_DMALD;+} buf[0] = [-CMD_DMALD;-]{+PL330_CMD_DMALD;+} if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); #@@ -720,16 +720,16 @@ static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); return [-SZ_DMALD;-]{+PL330_SZ_DMALD;+} } static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) return [-SZ_DMALDP;-]{+PL330_SZ_DMALDP;+} buf[0] = [-CMD_DMALDP;-]{+PL330_CMD_DMALDP;+} if (cond == BURST) buf[0] |= (1 << 1); #@@ -741,16 +741,16 @@ static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); return [-SZ_DMALDP;-]{+PL330_SZ_DMALDP;+} } static inline u32 _emit_LP(unsigned dry_run, u8 buf[], unsigned loop, u8 cnt) { if (dry_run) return [-SZ_DMALP;-]{+PL330_SZ_DMALP;+} buf[0] = [-CMD_DMALP;-]{+PL330_CMD_DMALP;+} if (loop) buf[0] |= (1 << 1); #@@ -760,7 +760,7 @@ static inline u32 _emit_LP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); return [-SZ_DMALP;-]{+PL330_SZ_DMALP;+} } struct _arg_LPEND { #@@ -779,9 +779,9 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], u8 bjump = arg->bjump; if (dry_run) return [-SZ_DMALPEND;-]{+PL330_SZ_DMALPEND;+} buf[0] = [-CMD_DMALPEND;-]{+PL330_CMD_DMALPEND;+} if (loop) buf[0] |= (1 << 2); #@@ -802,65 +802,65 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], loop ? '1' : '0', bjump); return [-SZ_DMALPEND;-]{+PL330_SZ_DMALPEND;+} } static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMAKILL;-]{+PL330_SZ_DMAKILL;+} buf[0] = [-CMD_DMAKILL;-]{+PL330_CMD_DMAKILL;+} return [-SZ_DMAKILL;-]{+PL330_SZ_DMAKILL;+} } static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], enum dmamov_dst dst, u32 val) { if (dry_run) return [-SZ_DMAMOV;-]{+PL330_SZ_DMAMOV;+} buf[0] = [-CMD_DMAMOV;-]{+PL330_CMD_DMAMOV;+} buf[1] = dst; *((u32 *)&buf[2]) = val; PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); return [-SZ_DMAMOV;-]{+PL330_SZ_DMAMOV;+} } static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMANOP;-]{+PL330_SZ_DMANOP;+} buf[0] = [-CMD_DMANOP;-]{+PL330_CMD_DMANOP;+} PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); return [-SZ_DMANOP;-]{+PL330_SZ_DMANOP;+} } static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMARMB;-]{+PL330_SZ_DMARMB;+} buf[0] = [-CMD_DMARMB;-]{+PL330_CMD_DMARMB;+} PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); return [-SZ_DMARMB;-]{+PL330_SZ_DMARMB;+} } static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) { if (dry_run) return [-SZ_DMASEV;-]{+PL330_SZ_DMASEV;+} buf[0] = [-CMD_DMASEV;-]{+PL330_CMD_DMASEV;+} ev &= 0x1f; ev <<= 3; #@@ -868,15 +868,15 @@ static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); return [-SZ_DMASEV;-]{+PL330_SZ_DMASEV;+} } static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) return [-SZ_DMAST;-]{+PL330_SZ_DMAST;+} buf[0] = [-CMD_DMAST;-]{+PL330_CMD_DMAST;+} if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); #@@ -886,16 +886,16 @@ static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); return [-SZ_DMAST;-]{+PL330_SZ_DMAST;+} } static inline u32 _emit_STP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) return [-SZ_DMASTP;-]{+PL330_SZ_DMASTP;+} buf[0] = [-CMD_DMASTP;-]{+PL330_CMD_DMASTP;+} if (cond == BURST) buf[0] |= (1 << 1); #@@ -907,28 +907,28 @@ static inline u32 _emit_STP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); return [-SZ_DMASTP;-]{+PL330_SZ_DMASTP;+} } static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMASTZ;-]{+PL330_SZ_DMASTZ;+} buf[0] = [-CMD_DMASTZ;-]{+PL330_CMD_DMASTZ;+} PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); return [-SZ_DMASTZ;-]{+PL330_SZ_DMASTZ;+} } static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, unsigned invalidate) { if (dry_run) return [-SZ_DMAWFE;-]{+PL330_SZ_DMAWFE;+} buf[0] = [-CMD_DMAWFE;-]{+PL330_CMD_DMAWFE;+} ev &= 0x1f; ev <<= 3; #@@ -940,16 +940,16 @@ static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", ev >> 3, invalidate ? ", I" : ""); return [-SZ_DMAWFE;-]{+PL330_SZ_DMAWFE;+} } static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) return [-SZ_DMAWFP;-]{+PL330_SZ_DMAWFP;+} buf[0] = [-CMD_DMAWFP;-]{+PL330_CMD_DMAWFP;+} if (cond == SINGLE) buf[0] |= (0 << 1) | (0 << 0); #@@ -965,19 +965,19 @@ static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); return [-SZ_DMAWFP;-]{+PL330_SZ_DMAWFP;+} } static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) { if (dry_run) return [-SZ_DMAWMB;-]{+PL330_SZ_DMAWMB;+} buf[0] = [-CMD_DMAWMB;-]{+PL330_CMD_DMAWMB;+} PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); return [-SZ_DMAWMB;-]{+PL330_SZ_DMAWMB;+} } struct _arg_GO { #@@ -994,16 +994,16 @@ static inline u32 _emit_GO(unsigned dry_run, u8 buf[], unsigned ns = arg->ns; if (dry_run) return [-SZ_DMAGO;-]{+PL330_SZ_DMAGO;+} buf[0] = [-CMD_DMAGO;-]{+PL330_CMD_DMAGO;+} buf[0] |= (ns << 1); buf[1] = chan & 0x7; *((u32 *)&buf[2]) = addr; return [-SZ_DMAGO;-]{+PL330_SZ_DMAGO;+} } #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) #@@ -1016,7 +1016,7 @@ static bool _until_dmac_idle(struct pl330_thread *thrd) do { /* Until Manager is Idle */ if (!(readl(regs + [-DBGSTATUS)-]{+PL330_DBGSTATUS)+} & [-DBG_BUSY))-]{+PL330_DBG_BUSY))+} break; cpu_relax(); #@@ -1039,10 +1039,10 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, val |= (1 << 0); val |= (thrd->id << 8); /* Channel Number */ } writel(val, regs + [-DBGINST0);-]{+PL330_DBGINST0);+} val = *((u32 *)&insn[2]); writel(val, regs + [-DBGINST1);-]{+PL330_DBGINST1);+} /* If timed out due to halted state-machine */ if (_until_dmac_idle(thrd)) { #@@ -1051,7 +1051,7 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, } /* Get going */ writel(0, regs + [-DBGCMD);-]{+PL330_DBGCMD);+} } /* #@@ -1078,47 +1078,47 @@ static inline u32 _state(struct pl330_thread *thrd) if (is_manager(thrd)) val = readl(regs + DS) & 0xf; else val = readl(regs + [-CS(thrd->id))-]{+PL330_CS(thrd->id))+} & 0xf; switch (val) { case [-DS_ST_STOP:-]{+PL330_DS_ST_STOP:+} return PL330_STATE_STOPPED; case [-DS_ST_EXEC:-]{+PL330_DS_ST_EXEC:+} return PL330_STATE_EXECUTING; case [-DS_ST_CMISS:-]{+PL330_DS_ST_CMISS:+} return PL330_STATE_CACHEMISS; case [-DS_ST_UPDTPC:-]{+PL330_DS_ST_UPDTPC:+} return PL330_STATE_UPDTPC; case [-DS_ST_WFE:-]{+PL330_DS_ST_WFE:+} return PL330_STATE_WFE; case [-DS_ST_FAULT:-]{+PL330_DS_ST_FAULT:+} return PL330_STATE_FAULTING; case [-DS_ST_ATBRR:-]{+PL330_DS_ST_ATBRR:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_ATBARRIER; case [-DS_ST_QBUSY:-]{+PL330_DS_ST_QBUSY:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_QUEUEBUSY; case [-DS_ST_WFP:-]{+PL330_DS_ST_WFP:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_WFP; case [-DS_ST_KILL:-]{+PL330_DS_ST_KILL:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_KILLING; case [-DS_ST_CMPLT:-]{+PL330_DS_ST_CMPLT:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_COMPLETING; case [-DS_ST_FLTCMP:-]{+PL330_DS_ST_FLTCMP:+} if (is_manager(thrd)) return PL330_STATE_INVALID; else #@@ -1145,7 +1145,8 @@ static void _stop(struct pl330_thread *thrd) _emit_KILL(0, insn); /* Stop generating interrupts for SEV */ writel(readl(regs + [-INTEN)-]{+PL330_INTEN)+} & ~(1 << thrd->ev), regs + [-INTEN);-]{+PL330_INTEN);+} _execute_DBGINSN(thrd, insn, is_manager(thrd)); } #@@ -1184,7 +1185,7 @@ static bool _trigger(struct pl330_thread *thrd) if (r->cfg) ns = r->cfg->nonsecure ? 1 : 0; else if (readl(regs + [-CS(thrd->id))-]{+PL330_CS(thrd->id))+} & [-CS_CNS)-]{+PL330_CS_CNS)+} ns = 1; else ns = 0; #@@ -1200,7 +1201,7 @@ static bool _trigger(struct pl330_thread *thrd) _emit_GO(0, insn, &go); /* Set to generate interrupts for SEV */ writel(readl(regs + [-INTEN)-]{+PL330_INTEN)+} | (1 << thrd->ev), regs + [-INTEN);-]{+PL330_INTEN);+} /* Only manager can execute GO */ _execute_DBGINSN(thrd, insn, true); #@@ -1250,7 +1251,7 @@ static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], struct pl330_config *pcfg = pxs->r->cfg->pcfg; /* check lock-up free version */ if (get_revision(pcfg->periph_id) >= [-PERIPH_REV_R1P0)-]{+PL330_PERIPH_REV_R1P0)+} { while (cyc--) { off += _emit_LD(dry_run, &buf[off], ALWAYS); off += _emit_ST(dry_run, &buf[off], ALWAYS); #@@ -1475,29 +1476,29 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) u32 ccr = 0; if (rqc->src_inc) ccr |= [-CC_SRCINC;-]{+PL330_CC_SRCINC;+} if (rqc->dst_inc) ccr |= [-CC_DSTINC;-]{+PL330_CC_DSTINC;+} /* We set same protection levels for Src and DST for now */ if (rqc->privileged) ccr |= [-CC_SRCPRI-]{+PL330_CC_SRCPRI+} | [-CC_DSTPRI;-]{+PL330_CC_DSTPRI;+} if (rqc->nonsecure) ccr |= [-CC_SRCNS-]{+PL330_CC_SRCNS+} | [-CC_DSTNS;-]{+PL330_CC_DSTNS;+} if (rqc->insnaccess) ccr |= [-CC_SRCIA-]{+PL330_CC_SRCIA+} | [-CC_DSTIA;-]{+PL330_CC_DSTIA;+} ccr |= (((rqc->brst_len - 1) & 0xf) << [-CC_SRCBRSTLEN_SHFT);-]{+PL330_CC_SRCBRSTLEN_SHFT);+} ccr |= (((rqc->brst_len - 1) & 0xf) << [-CC_DSTBRSTLEN_SHFT);-]{+PL330_CC_DSTBRSTLEN_SHFT);+} ccr |= (rqc->brst_size << [-CC_SRCBRSTSIZE_SHFT);-]{+PL330_CC_SRCBRSTSIZE_SHFT);+} ccr |= (rqc->brst_size << [-CC_DSTBRSTSIZE_SHFT);-]{+PL330_CC_DSTBRSTSIZE_SHFT);+} ccr |= (rqc->scctl << [-CC_SRCCCTRL_SHFT);-]{+PL330_CC_SRCCCTRL_SHFT);+} ccr |= (rqc->dcctl << [-CC_DSTCCTRL_SHFT);-]{+PL330_CC_DSTCCTRL_SHFT);+} ccr |= (rqc->swap << [-CC_SWAP_SHFT);-]{+PL330_CC_SWAP_SHFT);+} return ccr; } #@@ -1507,8 +1508,8 @@ static inline bool _is_valid(u32 ccr) enum pl330_dstcachectrl dcctl; enum pl330_srccachectrl scctl; dcctl = (ccr >> [-CC_DSTCCTRL_SHFT)-]{+PL330_CC_DSTCCTRL_SHFT)+} & [-CC_DRCCCTRL_MASK;-]{+PL330_CC_DRCCCTRL_MASK;+} scctl = (ccr >> [-CC_SRCCCTRL_SHFT)-]{+PL330_CC_SRCCCTRL_SHFT)+} & [-CC_SRCCCTRL_MASK;-]{+PL330_CC_SRCCCTRL_MASK;+} if (dcctl == DINVALID1 || dcctl == DINVALID2 || scctl == SINVALID1 || scctl == SINVALID2) #@@ -1575,7 +1576,7 @@ static int pl330_submit_req(void *ch_id, struct pl330_req *r) ccr = _prepare_ccr(r->cfg); } else { ccr = readl(regs + [-CC(thrd->id));-]{+PL330_CC(thrd->id));+} } /* If this req doesn't have valid xfer settings */ #@@ -1652,7 +1653,7 @@ static void pl330_dotask(unsigned long data) _stop(thrd); if (readl(regs + [-FSC)-]{+PL330_FSC)+} & (1 << thrd->id)) err = PL330_ERR_FAIL; else err = PL330_ERR_ABORT; #@@ -1697,13 +1698,13 @@ static int pl330_update(const struct pl330_info *pi) spin_lock_irqsave(&pl330->lock, flags); val = readl(regs + [-FSM)-]{+PL330_FSM)+} & 0x1; if (val) pl330->dmac_tbd.reset_mngr = true; else pl330->dmac_tbd.reset_mngr = false; val = readl(regs + [-FSC)-]{+PL330_FSC)+} & ((1 << pi->pcfg.num_chan) - 1); pl330->dmac_tbd.reset_chan |= val; if (val) { int i = 0; #@@ -1711,8 +1712,8 @@ static int pl330_update(const struct pl330_info *pi) if (val & (1 << i)) { dev_info(pi->dev, "Reset Channel-%d\t CS-%x FTC-%x\n", i, readl(regs + [-CS(i)),-]{+PL330_CS(i)),+} readl(regs + [-FTC(i)));-]{+PL330_FTC(i)));+} _stop(&pl330->channels[i]); } i++; #@@ -1732,12 +1733,12 @@ static int pl330_update(const struct pl330_info *pi) for (ev = 0; ev < pi->pcfg.num_events; ev++) { if (val & (1 << ev)) { /* Event occurred */ struct pl330_thread *thrd; u32 inten = readl(regs + [-INTEN);-]{+PL330_INTEN);+} int active; /* Clear the event */ if (inten & (1 << ev)) writel(1 << ev, regs + [-INTCLR);-]{+PL330_INTCLR);+} ret = 1; #@@ -1944,44 +1945,45 @@ static void read_dmac_config(struct pl330_info *pi) void __iomem *regs = pi->base; u32 val; val = readl(regs + [-CRD)-]{+PL330_CRD)+} >> [-CRD_DATA_WIDTH_SHIFT;-]{+PL330_CRD_DATA_WIDTH_SHIFT;+} val &= [-CRD_DATA_WIDTH_MASK;-]{+PL330_CRD_DATA_WIDTH_MASK;+} pi->pcfg.data_bus_width = 8 * (1 << val); val = readl(regs + [-CRD)-]{+PL330_CRD)+} >> [-CRD_DATA_BUFF_SHIFT;-]{+PL330_CRD_DATA_BUFF_SHIFT;+} val &= [-CRD_DATA_BUFF_MASK;-]{+PL330_CRD_DATA_BUFF_MASK;+} pi->pcfg.data_buf_dep = val + 1; val = readl(regs + [-CR0)-]{+PL330_CR0)+} >> [-CR0_NUM_CHANS_SHIFT;-]{+PL330_CR0_NUM_CHANS_SHIFT;+} val &= [-CR0_NUM_CHANS_MASK;-]{+PL330_CR0_NUM_CHANS_MASK;+} val += 1; pi->pcfg.num_chan = val; val = readl(regs + [-CR0);-]{+PL330_CR0);+} if (val & [-CR0_PERIPH_REQ_SET)-]{+PL330_CR0_PERIPH_REQ_SET)+} { val = (val >> [-CR0_NUM_PERIPH_SHIFT)-]{+PL330_CR0_NUM_PERIPH_SHIFT)+} & [-CR0_NUM_PERIPH_MASK;-]{+PL330_CR0_NUM_PERIPH_MASK;+} val += 1; pi->pcfg.num_peri = val; pi->pcfg.peri_ns = readl(regs + [-CR4);-]{+PL330_CR4);+} } else { pi->pcfg.num_peri = 0; } val = readl(regs + [-CR0);-]{+PL330_CR0);+} if (val & [-CR0_BOOT_MAN_NS)-]{+PL330_CR0_BOOT_MAN_NS)+} pi->pcfg.mode |= DMAC_MODE_NS; else pi->pcfg.mode &= ~DMAC_MODE_NS; val = readl(regs + [-CR0)-]{+PL330_CR0)+} >> [-CR0_NUM_EVENTS_SHIFT;-]{+PL330_CR0_NUM_EVENTS_SHIFT;+} val &= [-CR0_NUM_EVENTS_MASK;-]{+PL330_CR0_NUM_EVENTS_MASK;+} val += 1; pi->pcfg.num_events = val; pi->pcfg.irq_ns = readl(regs + [-CR3);-]{+PL330_CR3);+} pi->pcfg.periph_id = get_id(pi, [-PERIPH_ID);-]{+PL330_PERIPH_ID);+} pi->pcfg.pcell_id = get_id(pi, [-PCELL_ID);-]{+PL330_PCELL_ID);+} } static inline void _reset_thread(struct pl330_thread *thrd) #@@ -2091,10 +2093,11 @@ static int pl330_add(struct pl330_info *pi) regs = pi->base; /* Check if we can handle this DMAC */ if ((get_id(pi, [-PERIPH_ID)-]{+PL330_PERIPH_ID)+} & 0xfffff) != [-PERIPH_ID_VAL-]{+PL330_PERIPH_ID_VAL+} || get_id(pi, [-PCELL_ID)-]{+PL330_PCELL_ID)+} != [-PCELL_ID_VAL)-]{+PL330_PCELL_ID_VAL)+} { dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n", get_id(pi, [-PERIPH_ID),-]{+PL330_PERIPH_ID),+} get_id(pi, [-PCELL_ID));-]{+PL330_PCELL_ID));+} return -EINVAL; } And here's the actual patch, finally: drivers/dma/pl330.c | 581 ++++++++++++++++++++++++++------------------------- 1 file changed, 292 insertions(+), 289 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 665668b..6de6de3 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -69,129 +69,129 @@ enum pl330_reqtype { }; /* Register and Bit field Definitions */ -#define DS 0x0 -#define DS_ST_STOP 0x0 -#define DS_ST_EXEC 0x1 -#define DS_ST_CMISS 0x2 -#define DS_ST_UPDTPC 0x3 -#define DS_ST_WFE 0x4 -#define DS_ST_ATBRR 0x5 -#define DS_ST_QBUSY 0x6 -#define DS_ST_WFP 0x7 -#define DS_ST_KILL 0x8 -#define DS_ST_CMPLT 0x9 -#define DS_ST_FLTCMP 0xe -#define DS_ST_FAULT 0xf - -#define DPC 0x4 -#define INTEN 0x20 -#define ES 0x24 -#define INTSTATUS 0x28 -#define INTCLR 0x2c -#define FSM 0x30 -#define FSC 0x34 -#define FTM 0x38 - -#define _FTC 0x40 -#define FTC(n) (_FTC + (n)*0x4) - -#define _CS 0x100 -#define CS(n) (_CS + (n)*0x8) -#define CS_CNS (1 << 21) - -#define _CPC 0x104 -#define CPC(n) (_CPC + (n)*0x8) - -#define _SA 0x400 -#define SA(n) (_SA + (n)*0x20) - -#define _DA 0x404 -#define DA(n) (_DA + (n)*0x20) - -#define _CC 0x408 -#define CC(n) (_CC + (n)*0x20) - -#define CC_SRCINC (1 << 0) -#define CC_DSTINC (1 << 14) -#define CC_SRCPRI (1 << 8) -#define CC_DSTPRI (1 << 22) -#define CC_SRCNS (1 << 9) -#define CC_DSTNS (1 << 23) -#define CC_SRCIA (1 << 10) -#define CC_DSTIA (1 << 24) -#define CC_SRCBRSTLEN_SHFT 4 -#define CC_DSTBRSTLEN_SHFT 18 -#define CC_SRCBRSTSIZE_SHFT 1 -#define CC_DSTBRSTSIZE_SHFT 15 -#define CC_SRCCCTRL_SHFT 11 -#define CC_SRCCCTRL_MASK 0x7 -#define CC_DSTCCTRL_SHFT 25 -#define CC_DRCCCTRL_MASK 0x7 -#define CC_SWAP_SHFT 28 - -#define _LC0 0x40c -#define LC0(n) (_LC0 + (n)*0x20) - -#define _LC1 0x410 -#define LC1(n) (_LC1 + (n)*0x20) - -#define DBGSTATUS 0xd00 -#define DBG_BUSY (1 << 0) - -#define DBGCMD 0xd04 -#define DBGINST0 0xd08 -#define DBGINST1 0xd0c - -#define CR0 0xe00 -#define CR1 0xe04 -#define CR2 0xe08 -#define CR3 0xe0c -#define CR4 0xe10 -#define CRD 0xe14 - -#define PERIPH_ID 0xfe0 -#define PERIPH_REV_SHIFT 20 -#define PERIPH_REV_MASK 0xf -#define PERIPH_REV_R0P0 0 -#define PERIPH_REV_R1P0 1 -#define PERIPH_REV_R1P1 2 -#define PCELL_ID 0xff0 - -#define CR0_PERIPH_REQ_SET (1 << 0) -#define CR0_BOOT_EN_SET (1 << 1) -#define CR0_BOOT_MAN_NS (1 << 2) -#define CR0_NUM_CHANS_SHIFT 4 -#define CR0_NUM_CHANS_MASK 0x7 -#define CR0_NUM_PERIPH_SHIFT 12 -#define CR0_NUM_PERIPH_MASK 0x1f -#define CR0_NUM_EVENTS_SHIFT 17 -#define CR0_NUM_EVENTS_MASK 0x1f - -#define CR1_ICACHE_LEN_SHIFT 0 -#define CR1_ICACHE_LEN_MASK 0x7 -#define CR1_NUM_ICACHELINES_SHIFT 4 -#define CR1_NUM_ICACHELINES_MASK 0xf - -#define CRD_DATA_WIDTH_SHIFT 0 -#define CRD_DATA_WIDTH_MASK 0x7 -#define CRD_WR_CAP_SHIFT 4 -#define CRD_WR_CAP_MASK 0x7 -#define CRD_WR_Q_DEP_SHIFT 8 -#define CRD_WR_Q_DEP_MASK 0xf -#define CRD_RD_CAP_SHIFT 12 -#define CRD_RD_CAP_MASK 0x7 -#define CRD_RD_Q_DEP_SHIFT 16 -#define CRD_RD_Q_DEP_MASK 0xf -#define CRD_DATA_BUFF_SHIFT 20 -#define CRD_DATA_BUFF_MASK 0x3ff - -#define PART 0x330 -#define DESIGNER 0x41 -#define REVISION 0x0 -#define INTEG_CFG 0x0 -#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) - -#define PCELL_ID_VAL 0xb105f00d +#define PL330_DS 0x0 +#define PL330_DS_ST_STOP 0x0 +#define PL330_DS_ST_EXEC 0x1 +#define PL330_DS_ST_CMISS 0x2 +#define PL330_DS_ST_UPDTPC 0x3 +#define PL330_DS_ST_WFE 0x4 +#define PL330_DS_ST_ATBRR 0x5 +#define PL330_DS_ST_QBUSY 0x6 +#define PL330_DS_ST_WFP 0x7 +#define PL330_DS_ST_KILL 0x8 +#define PL330_DS_ST_CMPLT 0x9 +#define PL330_DS_ST_FLTCMP 0xe +#define PL330_DS_ST_FAULT 0xf + +#define PL330_DPC 0x4 +#define PL330_INTEN 0x20 +#define PL330_ES 0x24 +#define PL330_INTSTATUS 0x28 +#define PL330_INTCLR 0x2c +#define PL330_FSM 0x30 +#define PL330_FSC 0x34 +#define PL330_FTM 0x38 + +#define _FTC 0x40 +#define PL330_FTC(n) (_FTC + (n)*0x4) + +#define _CS 0x100 +#define PL330_CS(n) (_CS + (n)*0x8) +#define PL330_CS_CNS (1 << 21) + +#define _CPC 0x104 +#define PL330_CPC(n) (_CPC + (n)*0x8) + +#define _SA 0x400 +#define PL330_SA(n) (_SA + (n)*0x20) + +#define _DA 0x404 +#define PL330_DA(n) (_DA + (n)*0x20) + +#define _CC 0x408 +#define PL330_CC(n) (_CC + (n)*0x20) + +#define PL330_CC_SRCINC (1 << 0) +#define PL330_CC_DSTINC (1 << 14) +#define PL330_CC_SRCPRI (1 << 8) +#define PL330_CC_DSTPRI (1 << 22) +#define PL330_CC_SRCNS (1 << 9) +#define PL330_CC_DSTNS (1 << 23) +#define PL330_CC_SRCIA (1 << 10) +#define PL330_CC_DSTIA (1 << 24) +#define PL330_CC_SRCBRSTLEN_SHFT 4 +#define PL330_CC_DSTBRSTLEN_SHFT 18 +#define PL330_CC_SRCBRSTSIZE_SHFT 1 +#define PL330_CC_DSTBRSTSIZE_SHFT 15 +#define PL330_CC_SRCCCTRL_SHFT 11 +#define PL330_CC_SRCCCTRL_MASK 0x7 +#define PL330_CC_DSTCCTRL_SHFT 25 +#define PL330_CC_DRCCCTRL_MASK 0x7 +#define PL330_CC_SWAP_SHFT 28 + +#define _LC0 0x40c +#define PL330_LC0(n) (_LC0 + (n)*0x20) + +#define _LC1 0x410 +#define PL330_LC1(n) (_LC1 + (n)*0x20) + +#define PL330_DBGSTATUS 0xd00 +#define PL330_DBG_BUSY (1 << 0) + +#define PL330_DBGCMD 0xd04 +#define PL330_DBGINST0 0xd08 +#define PL330_DBGINST1 0xd0c + +#define PL330_CR0 0xe00 +#define PL330_CR1 0xe04 +#define PL330_CR2 0xe08 +#define PL330_CR3 0xe0c +#define PL330_CR4 0xe10 +#define PL330_CRD 0xe14 + +#define PL330_PERIPH_ID 0xfe0 +#define PL330_PERIPH_REV_SHIFT 20 +#define PL330_PERIPH_REV_MASK 0xf +#define PL330_PERIPH_REV_R0P0 0 +#define PL330_PERIPH_REV_R1P0 1 +#define PL330_PERIPH_REV_R1P1 2 +#define PL330_PCELL_ID 0xff0 + +#define PL330_CR0_PERIPH_REQ_SET (1 << 0) +#define PL330_CR0_BOOT_EN_SET (1 << 1) +#define PL330_CR0_BOOT_MAN_NS (1 << 2) +#define PL330_CR0_NUM_CHANS_SHIFT 4 +#define PL330_CR0_NUM_CHANS_MASK 0x7 +#define PL330_CR0_NUM_PERIPH_SHIFT 12 +#define PL330_CR0_NUM_PERIPH_MASK 0x1f +#define PL330_CR0_NUM_EVENTS_SHIFT 17 +#define PL330_CR0_NUM_EVENTS_MASK 0x1f + +#define PL330_CR1_ICACHE_LEN_SHIFT 0 +#define PL330_CR1_ICACHE_LEN_MASK 0x7 +#define PL330_CR1_NUM_ICACHELINES_SHIFT 4 +#define PL330_CR1_NUM_ICACHELINES_MASK 0xf + +#define PL330_CRD_DATA_WIDTH_SHIFT 0 +#define PL330_CRD_DATA_WIDTH_MASK 0x7 +#define PL330_CRD_WR_CAP_SHIFT 4 +#define PL330_CRD_WR_CAP_MASK 0x7 +#define PL330_CRD_WR_Q_DEP_SHIFT 8 +#define PL330_CRD_WR_Q_DEP_MASK 0xf +#define PL330_CRD_RD_CAP_SHIFT 12 +#define PL330_CRD_RD_CAP_MASK 0x7 +#define PL330_CRD_RD_Q_DEP_SHIFT 16 +#define PL330_CRD_RD_Q_DEP_MASK 0xf +#define PL330_CRD_DATA_BUFF_SHIFT 20 +#define PL330_CRD_DATA_BUFF_MASK 0x3ff + +#define PL330_PART 0x330 +#define PL330_DESIGNER 0x41 +#define PL330_REVISION 0x0 +#define PL330_INTEG_CFG 0x0 +#define PL330_PERIPH_ID_VAL ((PL330_PART << 0) | (PL330_DESIGNER << 12)) + +#define PL330_PCELL_ID_VAL 0xb105f00d #define PL330_STATE_STOPPED (1 << 0) #define PL330_STATE_EXECUTING (1 << 1) @@ -210,48 +210,48 @@ enum pl330_reqtype { #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | PL330_STATE_WFE | PL330_STATE_FAULTING) -#define CMD_DMAADDH 0x54 -#define CMD_DMAEND 0x00 -#define CMD_DMAFLUSHP 0x35 -#define CMD_DMAGO 0xa0 -#define CMD_DMALD 0x04 -#define CMD_DMALDP 0x25 -#define CMD_DMALP 0x20 -#define CMD_DMALPEND 0x28 -#define CMD_DMAKILL 0x01 -#define CMD_DMAMOV 0xbc -#define CMD_DMANOP 0x18 -#define CMD_DMARMB 0x12 -#define CMD_DMASEV 0x34 -#define CMD_DMAST 0x08 -#define CMD_DMASTP 0x29 -#define CMD_DMASTZ 0x0c -#define CMD_DMAWFE 0x36 -#define CMD_DMAWFP 0x30 -#define CMD_DMAWMB 0x13 - -#define SZ_DMAADDH 3 -#define SZ_DMAEND 1 -#define SZ_DMAFLUSHP 2 -#define SZ_DMALD 1 -#define SZ_DMALDP 2 -#define SZ_DMALP 2 -#define SZ_DMALPEND 2 -#define SZ_DMAKILL 1 -#define SZ_DMAMOV 6 -#define SZ_DMANOP 1 -#define SZ_DMARMB 1 -#define SZ_DMASEV 2 -#define SZ_DMAST 1 -#define SZ_DMASTP 2 -#define SZ_DMASTZ 1 -#define SZ_DMAWFE 2 -#define SZ_DMAWFP 2 -#define SZ_DMAWMB 1 -#define SZ_DMAGO 6 - -#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) -#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) +#define PL330_CMD_DMAADDH 0x54 +#define PL330_CMD_DMAEND 0x00 +#define PL330_CMD_DMAFLUSHP 0x35 +#define PL330_CMD_DMAGO 0xa0 +#define PL330_CMD_DMALD 0x04 +#define PL330_CMD_DMALDP 0x25 +#define PL330_CMD_DMALP 0x20 +#define PL330_CMD_DMALPEND 0x28 +#define PL330_CMD_DMAKILL 0x01 +#define PL330_CMD_DMAMOV 0xbc +#define PL330_CMD_DMANOP 0x18 +#define PL330_CMD_DMARMB 0x12 +#define PL330_CMD_DMASEV 0x34 +#define PL330_CMD_DMAST 0x08 +#define PL330_CMD_DMASTP 0x29 +#define PL330_CMD_DMASTZ 0x0c +#define PL330_CMD_DMAWFE 0x36 +#define PL330_CMD_DMAWFP 0x30 +#define PL330_CMD_DMAWMB 0x13 + +#define PL330_SZ_DMAADDH 3 +#define PL330_SZ_DMAEND 1 +#define PL330_SZ_DMAFLUSHP 2 +#define PL330_SZ_DMALD 1 +#define PL330_SZ_DMALDP 2 +#define PL330_SZ_DMALP 2 +#define PL330_SZ_DMALPEND 2 +#define PL330_SZ_DMAKILL 1 +#define PL330_SZ_DMAMOV 6 +#define PL330_SZ_DMANOP 1 +#define PL330_SZ_DMARMB 1 +#define PL330_SZ_DMASEV 2 +#define PL330_SZ_DMAST 1 +#define PL330_SZ_DMASTP 2 +#define PL330_SZ_DMASTZ 1 +#define PL330_SZ_DMAWFE 2 +#define PL330_SZ_DMAWFP 2 +#define PL330_SZ_DMAWMB 1 +#define PL330_SZ_DMAGO 6 + +#define BRST_LEN(ccr) ((((ccr) >> PL330_CC_SRCBRSTLEN_SHFT) & 0xf) + 1) +#define BRST_SIZE(ccr) (1 << (((ccr) >> PL330_CC_SRCBRSTSIZE_SHFT) & 0x7)) #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) @@ -265,7 +265,7 @@ enum pl330_reqtype { #define MCODE_BUFF_PER_REQ 256 /* If the _pl330_req is available to the client */ -#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) +#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == PL330_CMD_DMAEND) /* Use this _only_ to wait on transient states */ #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); @@ -658,43 +658,43 @@ static inline u32 get_id(struct pl330_info *pi, u32 off) static inline u32 get_revision(u32 periph_id) { - return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; + return (periph_id >> PL330_PERIPH_REV_SHIFT) & PL330_PERIPH_REV_MASK; } static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], enum pl330_dst da, u16 val) { if (dry_run) - return SZ_DMAADDH; + return PL330_SZ_DMAADDH; - buf[0] = CMD_DMAADDH; + buf[0] = PL330_CMD_DMAADDH; buf[0] |= (da << 1); *((u16 *)&buf[1]) = val; - PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", + PL330_DBGCMD_DUMP(PL330_SZ_DMAADDH, "\tDMAADDH %s %u\n", da == 1 ? "DA" : "SA", val); - return SZ_DMAADDH; + return PL330_SZ_DMAADDH; } static inline u32 _emit_END(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMAEND; + return PL330_SZ_DMAEND; - buf[0] = CMD_DMAEND; + buf[0] = PL330_CMD_DMAEND; - PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); + PL330_DBGCMD_DUMP(PL330_SZ_DMAEND, "\tDMAEND\n"); - return SZ_DMAEND; + return PL330_SZ_DMAEND; } static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) { if (dry_run) - return SZ_DMAFLUSHP; + return PL330_SZ_DMAFLUSHP; - buf[0] = CMD_DMAFLUSHP; + buf[0] = PL330_CMD_DMAFLUSHP; peri &= 0x1f; peri <<= 3; @@ -702,15 +702,15 @@ static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); - return SZ_DMAFLUSHP; + return PL330_SZ_DMAFLUSHP; } static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) - return SZ_DMALD; + return PL330_SZ_DMALD; - buf[0] = CMD_DMALD; + buf[0] = PL330_CMD_DMALD; if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); @@ -720,16 +720,16 @@ static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); - return SZ_DMALD; + return PL330_SZ_DMALD; } static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) - return SZ_DMALDP; + return PL330_SZ_DMALDP; - buf[0] = CMD_DMALDP; + buf[0] = PL330_CMD_DMALDP; if (cond == BURST) buf[0] |= (1 << 1); @@ -741,16 +741,16 @@ static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); - return SZ_DMALDP; + return PL330_SZ_DMALDP; } static inline u32 _emit_LP(unsigned dry_run, u8 buf[], unsigned loop, u8 cnt) { if (dry_run) - return SZ_DMALP; + return PL330_SZ_DMALP; - buf[0] = CMD_DMALP; + buf[0] = PL330_CMD_DMALP; if (loop) buf[0] |= (1 << 1); @@ -760,7 +760,7 @@ static inline u32 _emit_LP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); - return SZ_DMALP; + return PL330_SZ_DMALP; } struct _arg_LPEND { @@ -779,9 +779,9 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], u8 bjump = arg->bjump; if (dry_run) - return SZ_DMALPEND; + return PL330_SZ_DMALPEND; - buf[0] = CMD_DMALPEND; + buf[0] = PL330_CMD_DMALPEND; if (loop) buf[0] |= (1 << 2); @@ -802,65 +802,65 @@ static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], loop ? '1' : '0', bjump); - return SZ_DMALPEND; + return PL330_SZ_DMALPEND; } static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMAKILL; + return PL330_SZ_DMAKILL; - buf[0] = CMD_DMAKILL; + buf[0] = PL330_CMD_DMAKILL; - return SZ_DMAKILL; + return PL330_SZ_DMAKILL; } static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], enum dmamov_dst dst, u32 val) { if (dry_run) - return SZ_DMAMOV; + return PL330_SZ_DMAMOV; - buf[0] = CMD_DMAMOV; + buf[0] = PL330_CMD_DMAMOV; buf[1] = dst; *((u32 *)&buf[2]) = val; PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); - return SZ_DMAMOV; + return PL330_SZ_DMAMOV; } static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMANOP; + return PL330_SZ_DMANOP; - buf[0] = CMD_DMANOP; + buf[0] = PL330_CMD_DMANOP; PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); - return SZ_DMANOP; + return PL330_SZ_DMANOP; } static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMARMB; + return PL330_SZ_DMARMB; - buf[0] = CMD_DMARMB; + buf[0] = PL330_CMD_DMARMB; PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); - return SZ_DMARMB; + return PL330_SZ_DMARMB; } static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) { if (dry_run) - return SZ_DMASEV; + return PL330_SZ_DMASEV; - buf[0] = CMD_DMASEV; + buf[0] = PL330_CMD_DMASEV; ev &= 0x1f; ev <<= 3; @@ -868,15 +868,15 @@ static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); - return SZ_DMASEV; + return PL330_SZ_DMASEV; } static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) { if (dry_run) - return SZ_DMAST; + return PL330_SZ_DMAST; - buf[0] = CMD_DMAST; + buf[0] = PL330_CMD_DMAST; if (cond == SINGLE) buf[0] |= (0 << 1) | (1 << 0); @@ -886,16 +886,16 @@ static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); - return SZ_DMAST; + return PL330_SZ_DMAST; } static inline u32 _emit_STP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) - return SZ_DMASTP; + return PL330_SZ_DMASTP; - buf[0] = CMD_DMASTP; + buf[0] = PL330_CMD_DMASTP; if (cond == BURST) buf[0] |= (1 << 1); @@ -907,28 +907,28 @@ static inline u32 _emit_STP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", cond == SINGLE ? 'S' : 'B', peri >> 3); - return SZ_DMASTP; + return PL330_SZ_DMASTP; } static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMASTZ; + return PL330_SZ_DMASTZ; - buf[0] = CMD_DMASTZ; + buf[0] = PL330_CMD_DMASTZ; PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); - return SZ_DMASTZ; + return PL330_SZ_DMASTZ; } static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, unsigned invalidate) { if (dry_run) - return SZ_DMAWFE; + return PL330_SZ_DMAWFE; - buf[0] = CMD_DMAWFE; + buf[0] = PL330_CMD_DMAWFE; ev &= 0x1f; ev <<= 3; @@ -940,16 +940,16 @@ static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", ev >> 3, invalidate ? ", I" : ""); - return SZ_DMAWFE; + return PL330_SZ_DMAWFE; } static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], enum pl330_cond cond, u8 peri) { if (dry_run) - return SZ_DMAWFP; + return PL330_SZ_DMAWFP; - buf[0] = CMD_DMAWFP; + buf[0] = PL330_CMD_DMAWFP; if (cond == SINGLE) buf[0] |= (0 << 1) | (0 << 0); @@ -965,19 +965,19 @@ static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); - return SZ_DMAWFP; + return PL330_SZ_DMAWFP; } static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) { if (dry_run) - return SZ_DMAWMB; + return PL330_SZ_DMAWMB; - buf[0] = CMD_DMAWMB; + buf[0] = PL330_CMD_DMAWMB; PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); - return SZ_DMAWMB; + return PL330_SZ_DMAWMB; } struct _arg_GO { @@ -994,16 +994,16 @@ static inline u32 _emit_GO(unsigned dry_run, u8 buf[], unsigned ns = arg->ns; if (dry_run) - return SZ_DMAGO; + return PL330_SZ_DMAGO; - buf[0] = CMD_DMAGO; + buf[0] = PL330_CMD_DMAGO; buf[0] |= (ns << 1); buf[1] = chan & 0x7; *((u32 *)&buf[2]) = addr; - return SZ_DMAGO; + return PL330_SZ_DMAGO; } #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) @@ -1016,7 +1016,7 @@ static bool _until_dmac_idle(struct pl330_thread *thrd) do { /* Until Manager is Idle */ - if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) + if (!(readl(regs + PL330_DBGSTATUS) & PL330_DBG_BUSY)) break; cpu_relax(); @@ -1039,10 +1039,10 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, val |= (1 << 0); val |= (thrd->id << 8); /* Channel Number */ } - writel(val, regs + DBGINST0); + writel(val, regs + PL330_DBGINST0); val = *((u32 *)&insn[2]); - writel(val, regs + DBGINST1); + writel(val, regs + PL330_DBGINST1); /* If timed out due to halted state-machine */ if (_until_dmac_idle(thrd)) { @@ -1051,7 +1051,7 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd, } /* Get going */ - writel(0, regs + DBGCMD); + writel(0, regs + PL330_DBGCMD); } /* @@ -1078,47 +1078,47 @@ static inline u32 _state(struct pl330_thread *thrd) if (is_manager(thrd)) val = readl(regs + DS) & 0xf; else - val = readl(regs + CS(thrd->id)) & 0xf; + val = readl(regs + PL330_CS(thrd->id)) & 0xf; switch (val) { - case DS_ST_STOP: + case PL330_DS_ST_STOP: return PL330_STATE_STOPPED; - case DS_ST_EXEC: + case PL330_DS_ST_EXEC: return PL330_STATE_EXECUTING; - case DS_ST_CMISS: + case PL330_DS_ST_CMISS: return PL330_STATE_CACHEMISS; - case DS_ST_UPDTPC: + case PL330_DS_ST_UPDTPC: return PL330_STATE_UPDTPC; - case DS_ST_WFE: + case PL330_DS_ST_WFE: return PL330_STATE_WFE; - case DS_ST_FAULT: + case PL330_DS_ST_FAULT: return PL330_STATE_FAULTING; - case DS_ST_ATBRR: + case PL330_DS_ST_ATBRR: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_ATBARRIER; - case DS_ST_QBUSY: + case PL330_DS_ST_QBUSY: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_QUEUEBUSY; - case DS_ST_WFP: + case PL330_DS_ST_WFP: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_WFP; - case DS_ST_KILL: + case PL330_DS_ST_KILL: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_KILLING; - case DS_ST_CMPLT: + case PL330_DS_ST_CMPLT: if (is_manager(thrd)) return PL330_STATE_INVALID; else return PL330_STATE_COMPLETING; - case DS_ST_FLTCMP: + case PL330_DS_ST_FLTCMP: if (is_manager(thrd)) return PL330_STATE_INVALID; else @@ -1145,7 +1145,8 @@ static void _stop(struct pl330_thread *thrd) _emit_KILL(0, insn); /* Stop generating interrupts for SEV */ - writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); + writel(readl(regs + PL330_INTEN) & ~(1 << thrd->ev), + regs + PL330_INTEN); _execute_DBGINSN(thrd, insn, is_manager(thrd)); } @@ -1184,7 +1185,7 @@ static bool _trigger(struct pl330_thread *thrd) if (r->cfg) ns = r->cfg->nonsecure ? 1 : 0; - else if (readl(regs + CS(thrd->id)) & CS_CNS) + else if (readl(regs + PL330_CS(thrd->id)) & PL330_CS_CNS) ns = 1; else ns = 0; @@ -1200,7 +1201,7 @@ static bool _trigger(struct pl330_thread *thrd) _emit_GO(0, insn, &go); /* Set to generate interrupts for SEV */ - writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); + writel(readl(regs + PL330_INTEN) | (1 << thrd->ev), regs + PL330_INTEN); /* Only manager can execute GO */ _execute_DBGINSN(thrd, insn, true); @@ -1250,7 +1251,7 @@ static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], struct pl330_config *pcfg = pxs->r->cfg->pcfg; /* check lock-up free version */ - if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { + if (get_revision(pcfg->periph_id) >= PL330_PERIPH_REV_R1P0) { while (cyc--) { off += _emit_LD(dry_run, &buf[off], ALWAYS); off += _emit_ST(dry_run, &buf[off], ALWAYS); @@ -1475,29 +1476,29 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) u32 ccr = 0; if (rqc->src_inc) - ccr |= CC_SRCINC; + ccr |= PL330_CC_SRCINC; if (rqc->dst_inc) - ccr |= CC_DSTINC; + ccr |= PL330_CC_DSTINC; /* We set same protection levels for Src and DST for now */ if (rqc->privileged) - ccr |= CC_SRCPRI | CC_DSTPRI; + ccr |= PL330_CC_SRCPRI | PL330_CC_DSTPRI; if (rqc->nonsecure) - ccr |= CC_SRCNS | CC_DSTNS; + ccr |= PL330_CC_SRCNS | PL330_CC_DSTNS; if (rqc->insnaccess) - ccr |= CC_SRCIA | CC_DSTIA; + ccr |= PL330_CC_SRCIA | PL330_CC_DSTIA; - ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); - ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); + ccr |= (((rqc->brst_len - 1) & 0xf) << PL330_CC_SRCBRSTLEN_SHFT); + ccr |= (((rqc->brst_len - 1) & 0xf) << PL330_CC_DSTBRSTLEN_SHFT); - ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); - ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); + ccr |= (rqc->brst_size << PL330_CC_SRCBRSTSIZE_SHFT); + ccr |= (rqc->brst_size << PL330_CC_DSTBRSTSIZE_SHFT); - ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); - ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); + ccr |= (rqc->scctl << PL330_CC_SRCCCTRL_SHFT); + ccr |= (rqc->dcctl << PL330_CC_DSTCCTRL_SHFT); - ccr |= (rqc->swap << CC_SWAP_SHFT); + ccr |= (rqc->swap << PL330_CC_SWAP_SHFT); return ccr; } @@ -1507,8 +1508,8 @@ static inline bool _is_valid(u32 ccr) enum pl330_dstcachectrl dcctl; enum pl330_srccachectrl scctl; - dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK; - scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK; + dcctl = (ccr >> PL330_CC_DSTCCTRL_SHFT) & PL330_CC_DRCCCTRL_MASK; + scctl = (ccr >> PL330_CC_SRCCCTRL_SHFT) & PL330_CC_SRCCCTRL_MASK; if (dcctl == DINVALID1 || dcctl == DINVALID2 || scctl == SINVALID1 || scctl == SINVALID2) @@ -1575,7 +1576,7 @@ static int pl330_submit_req(void *ch_id, struct pl330_req *r) ccr = _prepare_ccr(r->cfg); } else { - ccr = readl(regs + CC(thrd->id)); + ccr = readl(regs + PL330_CC(thrd->id)); } /* If this req doesn't have valid xfer settings */ @@ -1652,7 +1653,7 @@ static void pl330_dotask(unsigned long data) _stop(thrd); - if (readl(regs + FSC) & (1 << thrd->id)) + if (readl(regs + PL330_FSC) & (1 << thrd->id)) err = PL330_ERR_FAIL; else err = PL330_ERR_ABORT; @@ -1697,13 +1698,13 @@ static int pl330_update(const struct pl330_info *pi) spin_lock_irqsave(&pl330->lock, flags); - val = readl(regs + FSM) & 0x1; + val = readl(regs + PL330_FSM) & 0x1; if (val) pl330->dmac_tbd.reset_mngr = true; else pl330->dmac_tbd.reset_mngr = false; - val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1); + val = readl(regs + PL330_FSC) & ((1 << pi->pcfg.num_chan) - 1); pl330->dmac_tbd.reset_chan |= val; if (val) { int i = 0; @@ -1711,8 +1712,8 @@ static int pl330_update(const struct pl330_info *pi) if (val & (1 << i)) { dev_info(pi->dev, "Reset Channel-%d\t CS-%x FTC-%x\n", - i, readl(regs + CS(i)), - readl(regs + FTC(i))); + i, readl(regs + PL330_CS(i)), + readl(regs + PL330_FTC(i))); _stop(&pl330->channels[i]); } i++; @@ -1732,12 +1733,12 @@ static int pl330_update(const struct pl330_info *pi) for (ev = 0; ev < pi->pcfg.num_events; ev++) { if (val & (1 << ev)) { /* Event occurred */ struct pl330_thread *thrd; - u32 inten = readl(regs + INTEN); + u32 inten = readl(regs + PL330_INTEN); int active; /* Clear the event */ if (inten & (1 << ev)) - writel(1 << ev, regs + INTCLR); + writel(1 << ev, regs + PL330_INTCLR); ret = 1; @@ -1944,44 +1945,45 @@ static void read_dmac_config(struct pl330_info *pi) void __iomem *regs = pi->base; u32 val; - val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; - val &= CRD_DATA_WIDTH_MASK; + val = readl(regs + PL330_CRD) >> PL330_CRD_DATA_WIDTH_SHIFT; + val &= PL330_CRD_DATA_WIDTH_MASK; pi->pcfg.data_bus_width = 8 * (1 << val); - val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; - val &= CRD_DATA_BUFF_MASK; + val = readl(regs + PL330_CRD) >> PL330_CRD_DATA_BUFF_SHIFT; + val &= PL330_CRD_DATA_BUFF_MASK; pi->pcfg.data_buf_dep = val + 1; - val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; - val &= CR0_NUM_CHANS_MASK; + val = readl(regs + PL330_CR0) >> PL330_CR0_NUM_CHANS_SHIFT; + val &= PL330_CR0_NUM_CHANS_MASK; val += 1; pi->pcfg.num_chan = val; - val = readl(regs + CR0); - if (val & CR0_PERIPH_REQ_SET) { - val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; + val = readl(regs + PL330_CR0); + if (val & PL330_CR0_PERIPH_REQ_SET) { + val = (val >> PL330_CR0_NUM_PERIPH_SHIFT) + & PL330_CR0_NUM_PERIPH_MASK; val += 1; pi->pcfg.num_peri = val; - pi->pcfg.peri_ns = readl(regs + CR4); + pi->pcfg.peri_ns = readl(regs + PL330_CR4); } else { pi->pcfg.num_peri = 0; } - val = readl(regs + CR0); - if (val & CR0_BOOT_MAN_NS) + val = readl(regs + PL330_CR0); + if (val & PL330_CR0_BOOT_MAN_NS) pi->pcfg.mode |= DMAC_MODE_NS; else pi->pcfg.mode &= ~DMAC_MODE_NS; - val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; - val &= CR0_NUM_EVENTS_MASK; + val = readl(regs + PL330_CR0) >> PL330_CR0_NUM_EVENTS_SHIFT; + val &= PL330_CR0_NUM_EVENTS_MASK; val += 1; pi->pcfg.num_events = val; - pi->pcfg.irq_ns = readl(regs + CR3); + pi->pcfg.irq_ns = readl(regs + PL330_CR3); - pi->pcfg.periph_id = get_id(pi, PERIPH_ID); - pi->pcfg.pcell_id = get_id(pi, PCELL_ID); + pi->pcfg.periph_id = get_id(pi, PL330_PERIPH_ID); + pi->pcfg.pcell_id = get_id(pi, PL330_PCELL_ID); } static inline void _reset_thread(struct pl330_thread *thrd) @@ -2091,10 +2093,11 @@ static int pl330_add(struct pl330_info *pi) regs = pi->base; /* Check if we can handle this DMAC */ - if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL - || get_id(pi, PCELL_ID) != PCELL_ID_VAL) { + if ((get_id(pi, PL330_PERIPH_ID) & 0xfffff) != PL330_PERIPH_ID_VAL + || get_id(pi, PL330_PCELL_ID) != PL330_PCELL_ID_VAL) { dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n", - get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID)); + get_id(pi, PL330_PERIPH_ID), + get_id(pi, PL330_PCELL_ID)); return -EINVAL; } -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 1/8 v3] DMA: PL330: use prefix in reg names to build under x86 2012-11-24 0:53 ` [PATCH 1/8 v3] " Davide Ciminaghi @ 2012-11-24 5:14 ` Jassi Brar 2012-11-24 7:03 ` Alessandro Rubini 1 sibling, 0 replies; 34+ messages in thread From: Jassi Brar @ 2012-11-24 5:14 UTC (permalink / raw) To: Davide Ciminaghi Cc: viresh.linux, giancarlo.asnaghi, rajeev-dlh.kumar, linux, nico, vinod.koul, linus.walleij, hpa, linux-kernel, grant.likely, wim, mingo, ben-linux, djbw, tglx, cjb, rubini, linux-arm-kernel, davidb On 24 November 2012 06:23, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > This driver would not compile if ARM_AMBA is selected under x86, > because "CS" and "DS" are already defined there. But AMBA > is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. > > The patch just adds the "PL330_" prefix to all register and bit fields, > so it can be built by randomconfig after ARM_AMBA appears within x86. Prefixing only CS and DS should be do the job. Why do we have to make every symbol noisy with PL330_ ? ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/8 v3] DMA: PL330: use prefix in reg names to build under x86 2012-11-24 0:53 ` [PATCH 1/8 v3] " Davide Ciminaghi 2012-11-24 5:14 ` Jassi Brar @ 2012-11-24 7:03 ` Alessandro Rubini 2012-11-24 11:05 ` Jassi Brar 1 sibling, 1 reply; 34+ messages in thread From: Alessandro Rubini @ 2012-11-24 7:03 UTC (permalink / raw) To: jaswinder.singh Cc: ciminaghi, viresh.linux, giancarlo.asnaghi, rajeev-dlh.kumar, linux, nico, vinod.koul, linus.walleij, hpa, linux-kernel, grant.likely, wim, mingo, ben-linux, djbw, tglx, cjb, linux-arm-kernel, davidb My patch: >> This driver would not compile if ARM_AMBA is selected under x86, >> because "CS" and "DS" are already defined there. But AMBA >> is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. >> >> The patch just adds the "PL330_" prefix to all register and bit fields, >> so it can be built by randomconfig after ARM_AMBA appears within x86. Jassy Brar: > Prefixing only CS and DS should be do the job. > Why do we have to make every symbol noisy with PL330_ ? For internal consistency. I attacked this problem in July. This is what you wrote: I fully agree with your point and IIRC I always add some prefix to definitions in header files. Private defines in a .c file, without redundant prefixes, sounded like safe to me at the time, but perhaps I was wrong. (references: http://lkml.org/lkml/2012/7/1/56) So I made the changes overall. I dislike needless long patches, but picking symbols to work around the conflict of the day while introducing inconsistent naming doesn't look good to me. The other option is making the driver depend on CONFIG_ARM, like other patches in the series. That would be a smaller patch: we have a dozen AMBA peripherals under X86, and the PL330 was not thre. But I got the impression that we don't want to single-out every driver that doesn't compile: an overall more portable system is better. I'm fine either way, but your "perhaps I was wrong" above made me choose the overall-prefixing approach. Thank you all for your patience in this (especially Davide for the upstreaming effort) /alessandro ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/8 v3] DMA: PL330: use prefix in reg names to build under x86 2012-11-24 7:03 ` Alessandro Rubini @ 2012-11-24 11:05 ` Jassi Brar 2012-11-28 16:15 ` Davide Ciminaghi 0 siblings, 1 reply; 34+ messages in thread From: Jassi Brar @ 2012-11-24 11:05 UTC (permalink / raw) To: Alessandro Rubini Cc: ciminaghi, viresh.linux, giancarlo.asnaghi, rajeev-dlh.kumar, linux, nico, vinod.koul, linus.walleij, hpa, linux-kernel, grant.likely, wim, mingo, ben-linux, djbw, tglx, cjb, linux-arm-kernel, davidb On 24 November 2012 12:33, Alessandro Rubini <rubini@gnudd.com> wrote: > My patch: >>> This driver would not compile if ARM_AMBA is selected under x86, >>> because "CS" and "DS" are already defined there. But AMBA >>> is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. >>> >>> The patch just adds the "PL330_" prefix to all register and bit fields, >>> so it can be built by randomconfig after ARM_AMBA appears within x86. > > Jassy Brar: >> Prefixing only CS and DS should be do the job. >> Why do we have to make every symbol noisy with PL330_ ? > > For internal consistency. I attacked this problem in July. This is > what you wrote: > > I fully agree with your point and IIRC I always add some prefix to > definitions in header files. > Private defines in a .c file, without redundant prefixes, sounded like > safe to me at the time, but perhaps I was wrong. > > (references: http://lkml.org/lkml/2012/7/1/56) > > So I made the changes overall. I dislike needless long patches, but > picking symbols to work around the conflict of the day while > introducing inconsistent naming doesn't look good to me. > Sorry if I gave the wrong impression. I didn't agree (and IIRC nobody suggested) we prefix _every_ symbol in the driver now. Just CS, DS, ES and maybe SA, DA, CC too for some consistency. IOW, only regs, not bit-fields. regards. ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/8 v3] DMA: PL330: use prefix in reg names to build under x86 2012-11-24 11:05 ` Jassi Brar @ 2012-11-28 16:15 ` Davide Ciminaghi 0 siblings, 0 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-28 16:15 UTC (permalink / raw) To: Jassi Brar Cc: Alessandro Rubini, viresh.linux, giancarlo.asnaghi, rajeev-dlh.kumar, linux, nico, vinod.koul, linus.walleij, hpa, linux-kernel, grant.likely, wim, mingo, ben-linux, djbw, tglx, cjb, linux-arm-kernel, davidb On Sat, Nov 24, 2012 at 04:35:37PM +0530, Jassi Brar wrote: > On 24 November 2012 12:33, Alessandro Rubini <rubini@gnudd.com> wrote: > > My patch: > >>> This driver would not compile if ARM_AMBA is selected under x86, > >>> because "CS" and "DS" are already defined there. But AMBA > >>> is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. > >>> > >>> The patch just adds the "PL330_" prefix to all register and bit fields, > >>> so it can be built by randomconfig after ARM_AMBA appears within x86. > > > > Jassy Brar: > >> Prefixing only CS and DS should be do the job. > >> Why do we have to make every symbol noisy with PL330_ ? > > > > For internal consistency. I attacked this problem in July. This is > > what you wrote: > > > > I fully agree with your point and IIRC I always add some prefix to > > definitions in header files. > > Private defines in a .c file, without redundant prefixes, sounded like > > safe to me at the time, but perhaps I was wrong. > > > > (references: http://lkml.org/lkml/2012/7/1/56) > > > > So I made the changes overall. I dislike needless long patches, but > > picking symbols to work around the conflict of the day while > > introducing inconsistent naming doesn't look good to me. > > > Sorry if I gave the wrong impression. I didn't agree (and IIRC nobody > suggested) we prefix _every_ symbol in the driver now. Just CS, DS, ES > and maybe SA, DA, CC too for some consistency. IOW, only regs, not > bit-fields. > Hi Jassi, I've changed the patch to have registers only prefixed with PL300_ (no prefix for bitfields). Will send the new version in a few days (I'm still waiting for comments on the other patches of the set). Thanks and regards Davide ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 2/8] gpio: pl061 depends on ARM 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 1/8] DMA: PL330: use prefix in reg names to build " Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 2012-11-23 15:57 ` viresh kumar 2012-12-01 15:11 ` Linus Walleij 2012-11-23 15:08 ` [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ Davide Ciminaghi ` (5 subsequent siblings) 7 siblings, 2 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> Commit dece904d (gpio: pl061: use chained_irq_* functions in irq handler) introduced chained_irq_enter/exit, which is only available for arch/arm and the driver won't compile elsewhere. The dependency is thus made explicit, because AMBA is used in the x86 world by a PCI-to-AMBA bridge, to be submitted. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 536bc23..fb238d3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -185,7 +185,7 @@ config GPIO_MXS config GPIO_PL061 bool "PrimeCell PL061 GPIO support" - depends on ARM_AMBA + depends on ARM && ARM_AMBA select GENERIC_IRQ_CHIP help Say yes here to support the PrimeCell PL061 GPIO device -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 2/8] gpio: pl061 depends on ARM 2012-11-23 15:08 ` [PATCH 2/8] gpio: pl061 depends on ARM Davide Ciminaghi @ 2012-11-23 15:57 ` viresh kumar 2012-12-01 15:11 ` Linus Walleij 1 sibling, 0 replies; 34+ messages in thread From: viresh kumar @ 2012-11-23 15:57 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 8:38 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > Commit dece904d (gpio: pl061: use chained_irq_* functions in irq > handler) introduced chained_irq_enter/exit, which is only > available for arch/arm and the driver won't compile elsewhere. > > The dependency is thus made explicit, because AMBA is used in the x86 > world by a PCI-to-AMBA bridge, to be submitted. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 2/8] gpio: pl061 depends on ARM 2012-11-23 15:08 ` [PATCH 2/8] gpio: pl061 depends on ARM Davide Ciminaghi 2012-11-23 15:57 ` viresh kumar @ 2012-12-01 15:11 ` Linus Walleij 2012-12-03 13:31 ` Davide Ciminaghi 1 sibling, 1 reply; 34+ messages in thread From: Linus Walleij @ 2012-12-01 15:11 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 4:08 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > Commit dece904d (gpio: pl061: use chained_irq_* functions in irq > handler) introduced chained_irq_enter/exit, which is only > available for arch/arm and the driver won't compile elsewhere. > > The dependency is thus made explicit, because AMBA is used in the x86 > world by a PCI-to-AMBA bridge, to be submitted. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Patch applied with Viresh's ACK. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 2/8] gpio: pl061 depends on ARM 2012-12-01 15:11 ` Linus Walleij @ 2012-12-03 13:31 ` Davide Ciminaghi 0 siblings, 0 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-12-03 13:31 UTC (permalink / raw) To: Linus Walleij Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Sat, Dec 01, 2012 at 04:11:08PM +0100, Linus Walleij wrote: > On Fri, Nov 23, 2012 at 4:08 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > > > From: Alessandro Rubini <rubini@gnudd.com> > > > > Commit dece904d (gpio: pl061: use chained_irq_* functions in irq > > handler) introduced chained_irq_enter/exit, which is only > > available for arch/arm and the driver won't compile elsewhere. > > > > The dependency is thus made explicit, because AMBA is used in the x86 > > world by a PCI-to-AMBA bridge, to be submitted. > > > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> > > Patch applied with Viresh's ACK. > ok thanks a lot and regards Davide ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 1/8] DMA: PL330: use prefix in reg names to build " Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 2/8] gpio: pl061 depends on ARM Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 2012-11-23 15:53 ` viresh kumar 2012-11-23 15:08 ` [PATCH 4/8] watchdog: sp805_wdt depends on ARM Davide Ciminaghi ` (4 subsequent siblings) 7 siblings, 1 reply; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> The header is used by drivers/dma/amba-pl08x.c, which can be compiled under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche moves it where it can be accessed by other architectures, and fixes all users. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- arch/arm/include/asm/hardware/pl080.h | 146 --------------------------------- arch/arm/mach-s3c64xx/dma.c | 2 +- arch/arm/mach-spear3xx/spear3xx.c | 2 +- arch/arm/mach-spear6xx/spear6xx.c | 2 +- drivers/dma/amba-pl08x.c | 2 +- include/linux/amba/pl080.h | 146 +++++++++++++++++++++++++++++++++ 6 files changed, 150 insertions(+), 150 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/pl080.h create mode 100644 include/linux/amba/pl080.h diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h deleted file mode 100644 index 4eea210..0000000 --- a/arch/arm/include/asm/hardware/pl080.h +++ /dev/null @@ -1,146 +0,0 @@ -/* arch/arm/include/asm/hardware/pl080.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * ARM PrimeCell PL080 DMA controller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* Note, there are some Samsung updates to this controller block which - * make it not entierly compatible with the PL080 specification from - * ARM. When in doubt, check the Samsung documentation first. - * - * The Samsung defines are PL080S, and add an extra control register, - * the ability to move more than 2^11 counts of data and some extra - * OneNAND features. -*/ - -#ifndef ASM_PL080_H -#define ASM_PL080_H - -#define PL080_INT_STATUS (0x00) -#define PL080_TC_STATUS (0x04) -#define PL080_TC_CLEAR (0x08) -#define PL080_ERR_STATUS (0x0C) -#define PL080_ERR_CLEAR (0x10) -#define PL080_RAW_TC_STATUS (0x14) -#define PL080_RAW_ERR_STATUS (0x18) -#define PL080_EN_CHAN (0x1c) -#define PL080_SOFT_BREQ (0x20) -#define PL080_SOFT_SREQ (0x24) -#define PL080_SOFT_LBREQ (0x28) -#define PL080_SOFT_LSREQ (0x2C) - -#define PL080_CONFIG (0x30) -#define PL080_CONFIG_M2_BE (1 << 2) -#define PL080_CONFIG_M1_BE (1 << 1) -#define PL080_CONFIG_ENABLE (1 << 0) - -#define PL080_SYNC (0x34) - -/* Per channel configuration registers */ - -#define PL080_Cx_STRIDE (0x20) -#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) -#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20))) -#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20))) -#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20))) -#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20))) -#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20))) -#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20))) -#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20))) - -#define PL080_CH_SRC_ADDR (0x00) -#define PL080_CH_DST_ADDR (0x04) -#define PL080_CH_LLI (0x08) -#define PL080_CH_CONTROL (0x0C) -#define PL080_CH_CONFIG (0x10) -#define PL080S_CH_CONTROL2 (0x10) -#define PL080S_CH_CONFIG (0x14) - -#define PL080_LLI_ADDR_MASK (0x3fffffff << 2) -#define PL080_LLI_ADDR_SHIFT (2) -#define PL080_LLI_LM_AHB2 (1 << 0) - -#define PL080_CONTROL_TC_IRQ_EN (1 << 31) -#define PL080_CONTROL_PROT_MASK (0x7 << 28) -#define PL080_CONTROL_PROT_SHIFT (28) -#define PL080_CONTROL_PROT_CACHE (1 << 30) -#define PL080_CONTROL_PROT_BUFF (1 << 29) -#define PL080_CONTROL_PROT_SYS (1 << 28) -#define PL080_CONTROL_DST_INCR (1 << 27) -#define PL080_CONTROL_SRC_INCR (1 << 26) -#define PL080_CONTROL_DST_AHB2 (1 << 25) -#define PL080_CONTROL_SRC_AHB2 (1 << 24) -#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) -#define PL080_CONTROL_DWIDTH_SHIFT (21) -#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) -#define PL080_CONTROL_SWIDTH_SHIFT (18) -#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) -#define PL080_CONTROL_DB_SIZE_SHIFT (15) -#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) -#define PL080_CONTROL_SB_SIZE_SHIFT (12) -#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) -#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) - -#define PL080_BSIZE_1 (0x0) -#define PL080_BSIZE_4 (0x1) -#define PL080_BSIZE_8 (0x2) -#define PL080_BSIZE_16 (0x3) -#define PL080_BSIZE_32 (0x4) -#define PL080_BSIZE_64 (0x5) -#define PL080_BSIZE_128 (0x6) -#define PL080_BSIZE_256 (0x7) - -#define PL080_WIDTH_8BIT (0x0) -#define PL080_WIDTH_16BIT (0x1) -#define PL080_WIDTH_32BIT (0x2) - -#define PL080N_CONFIG_ITPROT (1 << 20) -#define PL080N_CONFIG_SECPROT (1 << 19) -#define PL080_CONFIG_HALT (1 << 18) -#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */ -#define PL080_CONFIG_LOCK (1 << 16) -#define PL080_CONFIG_TC_IRQ_MASK (1 << 15) -#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14) -#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) -#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) -#define PL080_CONFIG_DST_SEL_MASK (0xf << 6) -#define PL080_CONFIG_DST_SEL_SHIFT (6) -#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) -#define PL080_CONFIG_SRC_SEL_SHIFT (1) -#define PL080_CONFIG_ENABLE (1 << 0) - -#define PL080_FLOW_MEM2MEM (0x0) -#define PL080_FLOW_MEM2PER (0x1) -#define PL080_FLOW_PER2MEM (0x2) -#define PL080_FLOW_SRC2DST (0x3) -#define PL080_FLOW_SRC2DST_DST (0x4) -#define PL080_FLOW_MEM2PER_PER (0x5) -#define PL080_FLOW_PER2MEM_PER (0x6) -#define PL080_FLOW_SRC2DST_SRC (0x7) - -/* DMA linked list chain structure */ - -struct pl080_lli { - u32 src_addr; - u32 dst_addr; - u32 next_lli; - u32 control0; -}; - -struct pl080s_lli { - u32 src_addr; - u32 dst_addr; - u32 next_lli; - u32 control0; - u32 control1; -}; - -#endif /* ASM_PL080_H */ diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index f2a7a17..a77f521 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -23,6 +23,7 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/amba/pl080.h> #include <mach/dma.h> #include <mach/map.h> @@ -30,7 +31,6 @@ #include <mach/regs-sys.h> -#include <asm/hardware/pl080.h> /* dma channel state information */ diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 98144ba..ba61129 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -15,9 +15,9 @@ #include <linux/amba/pl022.h> #include <linux/amba/pl08x.h> +#include <linux/amba/pl080.h> #include <linux/of_irq.h> #include <linux/io.h> -#include <asm/hardware/pl080.h> #include <asm/hardware/vic.h> #include <plat/pl080.h> #include <mach/generic.h> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 5a5a52d..8ce65a2 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -20,7 +20,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <asm/hardware/pl080.h> +#include <linux/amba/pl080.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index 6eb6a5c..8bad254 100644 --- a/drivers/dma/amba-pl08x.c +++ b/drivers/dma/amba-pl08x.c @@ -83,7 +83,7 @@ #include <linux/pm_runtime.h> #include <linux/seq_file.h> #include <linux/slab.h> -#include <asm/hardware/pl080.h> +#include <linux/amba/pl080.h> #include "dmaengine.h" #include "virt-dma.h" diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h new file mode 100644 index 0000000..3e7b62f --- /dev/null +++ b/include/linux/amba/pl080.h @@ -0,0 +1,146 @@ +/* include/linux/amba/pl080.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * ARM PrimeCell PL080 DMA controller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Note, there are some Samsung updates to this controller block which + * make it not entierly compatible with the PL080 specification from + * ARM. When in doubt, check the Samsung documentation first. + * + * The Samsung defines are PL080S, and add an extra control register, + * the ability to move more than 2^11 counts of data and some extra + * OneNAND features. +*/ + +#ifndef ASM_PL080_H +#define ASM_PL080_H + +#define PL080_INT_STATUS (0x00) +#define PL080_TC_STATUS (0x04) +#define PL080_TC_CLEAR (0x08) +#define PL080_ERR_STATUS (0x0C) +#define PL080_ERR_CLEAR (0x10) +#define PL080_RAW_TC_STATUS (0x14) +#define PL080_RAW_ERR_STATUS (0x18) +#define PL080_EN_CHAN (0x1c) +#define PL080_SOFT_BREQ (0x20) +#define PL080_SOFT_SREQ (0x24) +#define PL080_SOFT_LBREQ (0x28) +#define PL080_SOFT_LSREQ (0x2C) + +#define PL080_CONFIG (0x30) +#define PL080_CONFIG_M2_BE (1 << 2) +#define PL080_CONFIG_M1_BE (1 << 1) +#define PL080_CONFIG_ENABLE (1 << 0) + +#define PL080_SYNC (0x34) + +/* Per channel configuration registers */ + +#define PL080_Cx_STRIDE (0x20) +#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) +#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20))) +#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20))) +#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20))) +#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20))) +#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20))) +#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20))) +#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20))) + +#define PL080_CH_SRC_ADDR (0x00) +#define PL080_CH_DST_ADDR (0x04) +#define PL080_CH_LLI (0x08) +#define PL080_CH_CONTROL (0x0C) +#define PL080_CH_CONFIG (0x10) +#define PL080S_CH_CONTROL2 (0x10) +#define PL080S_CH_CONFIG (0x14) + +#define PL080_LLI_ADDR_MASK (0x3fffffff << 2) +#define PL080_LLI_ADDR_SHIFT (2) +#define PL080_LLI_LM_AHB2 (1 << 0) + +#define PL080_CONTROL_TC_IRQ_EN (1 << 31) +#define PL080_CONTROL_PROT_MASK (0x7 << 28) +#define PL080_CONTROL_PROT_SHIFT (28) +#define PL080_CONTROL_PROT_CACHE (1 << 30) +#define PL080_CONTROL_PROT_BUFF (1 << 29) +#define PL080_CONTROL_PROT_SYS (1 << 28) +#define PL080_CONTROL_DST_INCR (1 << 27) +#define PL080_CONTROL_SRC_INCR (1 << 26) +#define PL080_CONTROL_DST_AHB2 (1 << 25) +#define PL080_CONTROL_SRC_AHB2 (1 << 24) +#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) +#define PL080_CONTROL_DWIDTH_SHIFT (21) +#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) +#define PL080_CONTROL_SWIDTH_SHIFT (18) +#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) +#define PL080_CONTROL_DB_SIZE_SHIFT (15) +#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) +#define PL080_CONTROL_SB_SIZE_SHIFT (12) +#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) +#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) + +#define PL080_BSIZE_1 (0x0) +#define PL080_BSIZE_4 (0x1) +#define PL080_BSIZE_8 (0x2) +#define PL080_BSIZE_16 (0x3) +#define PL080_BSIZE_32 (0x4) +#define PL080_BSIZE_64 (0x5) +#define PL080_BSIZE_128 (0x6) +#define PL080_BSIZE_256 (0x7) + +#define PL080_WIDTH_8BIT (0x0) +#define PL080_WIDTH_16BIT (0x1) +#define PL080_WIDTH_32BIT (0x2) + +#define PL080N_CONFIG_ITPROT (1 << 20) +#define PL080N_CONFIG_SECPROT (1 << 19) +#define PL080_CONFIG_HALT (1 << 18) +#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */ +#define PL080_CONFIG_LOCK (1 << 16) +#define PL080_CONFIG_TC_IRQ_MASK (1 << 15) +#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14) +#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) +#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) +#define PL080_CONFIG_DST_SEL_MASK (0xf << 6) +#define PL080_CONFIG_DST_SEL_SHIFT (6) +#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) +#define PL080_CONFIG_SRC_SEL_SHIFT (1) +#define PL080_CONFIG_ENABLE (1 << 0) + +#define PL080_FLOW_MEM2MEM (0x0) +#define PL080_FLOW_MEM2PER (0x1) +#define PL080_FLOW_PER2MEM (0x2) +#define PL080_FLOW_SRC2DST (0x3) +#define PL080_FLOW_SRC2DST_DST (0x4) +#define PL080_FLOW_MEM2PER_PER (0x5) +#define PL080_FLOW_PER2MEM_PER (0x6) +#define PL080_FLOW_SRC2DST_SRC (0x7) + +/* DMA linked list chain structure */ + +struct pl080_lli { + u32 src_addr; + u32 dst_addr; + u32 next_lli; + u32 control0; +}; + +struct pl080s_lli { + u32 src_addr; + u32 dst_addr; + u32 next_lli; + u32 control0; + u32 control1; +}; + +#endif /* ASM_PL080_H */ -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ 2012-11-23 15:08 ` [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ Davide Ciminaghi @ 2012-11-23 15:53 ` viresh kumar 2012-11-24 0:22 ` [PATCH 3/8 v3] " Davide Ciminaghi 0 siblings, 1 reply; 34+ messages in thread From: viresh kumar @ 2012-11-23 15:53 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 8:38 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > The header is used by drivers/dma/amba-pl08x.c, which can be compiled > under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche > moves it where it can be accessed by other architectures, and fixes > all users. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> > --- > arch/arm/include/asm/hardware/pl080.h | 146 --------------------------------- > arch/arm/mach-s3c64xx/dma.c | 2 +- > arch/arm/mach-spear3xx/spear3xx.c | 2 +- > arch/arm/mach-spear6xx/spear6xx.c | 2 +- > drivers/dma/amba-pl08x.c | 2 +- > include/linux/amba/pl080.h | 146 +++++++++++++++++++++++++++++++++ > 6 files changed, 150 insertions(+), 150 deletions(-) > delete mode 100644 arch/arm/include/asm/hardware/pl080.h > create mode 100644 include/linux/amba/pl080.h Again, generating this patch with git format-patch -C -M would have given us an easier patch to review. -- viresh ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 3/8 v3] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ 2012-11-23 15:53 ` viresh kumar @ 2012-11-24 0:22 ` Davide Ciminaghi 2012-11-28 16:04 ` Linus Walleij 0 siblings, 1 reply; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-24 0:22 UTC (permalink / raw) To: viresh.linux Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> The header is used by drivers/dma/amba-pl08x.c, which can be compiled under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche moves it where it can be accessed by other architectures, and fixes all users. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- As requested by Viresh Kumar, this is 3/8 again, generated with git format-patch -C -M Since the patch is not identical to the previous 3/8, I added "v3" to the subject. arch/arm/mach-s3c64xx/dma.c | 2 +- arch/arm/mach-spear3xx/spear3xx.c | 2 +- arch/arm/mach-spear6xx/spear6xx.c | 2 +- drivers/dma/amba-pl08x.c | 2 +- {arch/arm/include/asm/hardware => include/linux/amba}/pl080.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) rename {arch/arm/include/asm/hardware => include/linux/amba}/pl080.h (99%) diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index f2a7a17..a77f521 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -23,6 +23,7 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/amba/pl080.h> #include <mach/dma.h> #include <mach/map.h> @@ -30,7 +31,6 @@ #include <mach/regs-sys.h> -#include <asm/hardware/pl080.h> /* dma channel state information */ diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 98144ba..ba61129 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -15,9 +15,9 @@ #include <linux/amba/pl022.h> #include <linux/amba/pl08x.h> +#include <linux/amba/pl080.h> #include <linux/of_irq.h> #include <linux/io.h> -#include <asm/hardware/pl080.h> #include <asm/hardware/vic.h> #include <plat/pl080.h> #include <mach/generic.h> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 5a5a52d..8ce65a2 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -20,7 +20,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <asm/hardware/pl080.h> +#include <linux/amba/pl080.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index 6eb6a5c..8bad254 100644 --- a/drivers/dma/amba-pl08x.c +++ b/drivers/dma/amba-pl08x.c @@ -83,7 +83,7 @@ #include <linux/pm_runtime.h> #include <linux/seq_file.h> #include <linux/slab.h> -#include <asm/hardware/pl080.h> +#include <linux/amba/pl080.h> #include "dmaengine.h" #include "virt-dma.h" diff --git a/arch/arm/include/asm/hardware/pl080.h b/include/linux/amba/pl080.h similarity index 99% rename from arch/arm/include/asm/hardware/pl080.h rename to include/linux/amba/pl080.h index 4eea210..3e7b62f 100644 --- a/arch/arm/include/asm/hardware/pl080.h +++ b/include/linux/amba/pl080.h @@ -1,4 +1,4 @@ -/* arch/arm/include/asm/hardware/pl080.h +/* include/linux/amba/pl080.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 3/8 v3] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ 2012-11-24 0:22 ` [PATCH 3/8 v3] " Davide Ciminaghi @ 2012-11-28 16:04 ` Linus Walleij 0 siblings, 0 replies; 34+ messages in thread From: Linus Walleij @ 2012-11-28 16:04 UTC (permalink / raw) To: Davide Ciminaghi Cc: viresh.linux, linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Sat, Nov 24, 2012 at 1:22 AM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > The header is used by drivers/dma/amba-pl08x.c, which can be compiled > under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche > moves it where it can be accessed by other architectures, and fixes > all users. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> OK! Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 4/8] watchdog: sp805_wdt depends on ARM 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi ` (2 preceding siblings ...) 2012-11-23 15:08 ` [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 2012-11-23 15:56 ` viresh kumar 2012-11-28 16:00 ` Linus Walleij 2012-11-23 15:08 ` [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep Davide Ciminaghi ` (3 subsequent siblings) 7 siblings, 2 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> The SP805 driver is only used by the Spear machines, and uses writel_relaxed, which is not available on all architectures. The dependency from CONFIG_ARM avoids compilation problems under randomconfig when CONFIG_ARM_AMBA is enabled for x86 builds. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com> --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index ad1bb93..c76fc07 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -98,7 +98,7 @@ config WM8350_WATCHDOG config ARM_SP805_WATCHDOG tristate "ARM SP805 Watchdog" - depends on ARM_AMBA + depends on ARM && ARM_AMBA select WATCHDOG_CORE help ARM Primecell SP805 Watchdog timer. This will reboot your system when -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 4/8] watchdog: sp805_wdt depends on ARM 2012-11-23 15:08 ` [PATCH 4/8] watchdog: sp805_wdt depends on ARM Davide Ciminaghi @ 2012-11-23 15:56 ` viresh kumar 2012-11-28 16:00 ` Linus Walleij 1 sibling, 0 replies; 34+ messages in thread From: viresh kumar @ 2012-11-23 15:56 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 8:38 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > The SP805 driver is only used by the Spear machines, and uses > writel_relaxed, which is not available on all architectures. > > The dependency from CONFIG_ARM avoids compilation problems under > randomconfig when CONFIG_ARM_AMBA is enabled for x86 builds. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> > Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 4/8] watchdog: sp805_wdt depends on ARM 2012-11-23 15:08 ` [PATCH 4/8] watchdog: sp805_wdt depends on ARM Davide Ciminaghi 2012-11-23 15:56 ` viresh kumar @ 2012-11-28 16:00 ` Linus Walleij 1 sibling, 0 replies; 34+ messages in thread From: Linus Walleij @ 2012-11-28 16:00 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 4:08 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > The SP805 driver is only used by the Spear machines, and uses > writel_relaxed, which is not available on all architectures. > > The dependency from CONFIG_ARM avoids compilation problems under > randomconfig when CONFIG_ARM_AMBA is enabled for x86 builds. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> > Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi ` (3 preceding siblings ...) 2012-11-23 15:08 ` [PATCH 4/8] watchdog: sp805_wdt depends on ARM Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 2012-11-28 16:08 ` Linus Walleij 2012-12-03 14:47 ` Will Deacon 2012-11-23 15:08 ` [PATCH 6/8] mmc: use the new <linux/sizes.h> Davide Ciminaghi ` (2 subsequent siblings) 7 siblings, 2 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi Not all the architectures have readsl/writesl, use the more portable ioread32_rep/iowrite32_rep functions instead. Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com> --- drivers/mmc/host/mmci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 9446c17..5e39b31 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -863,14 +863,14 @@ static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int rema if (unlikely(count & 0x3)) { if (count < 4) { unsigned char buf[4]; - readsl(base + MMCIFIFO, buf, 1); + ioread32_rep(base + MMCIFIFO, buf, 1); memcpy(ptr, buf, count); } else { - readsl(base + MMCIFIFO, ptr, count >> 2); + ioread32_rep(base + MMCIFIFO, ptr, count >> 2); count &= ~0x3; } } else { - readsl(base + MMCIFIFO, ptr, count >> 2); + ioread32_rep(base + MMCIFIFO, ptr, count >> 2); } ptr += count; @@ -907,7 +907,7 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem * byte become a 32bit write, 7 bytes will be two * 32bit writes etc. */ - writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); + iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); ptr += count; remain -= count; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep 2012-11-23 15:08 ` [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep Davide Ciminaghi @ 2012-11-28 16:08 ` Linus Walleij 2012-11-28 16:33 ` Davide Ciminaghi 2012-12-03 14:47 ` Will Deacon 1 sibling, 1 reply; 34+ messages in thread From: Linus Walleij @ 2012-11-28 16:08 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 4:08 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > Not all the architectures have readsl/writesl, > use the more portable ioread32_rep/iowrite32_rep functions instead. > > Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com> Can't think of anything better, put it in Russell's patch tracker when you think you're finished with it. Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep 2012-11-28 16:08 ` Linus Walleij @ 2012-11-28 16:33 ` Davide Ciminaghi 0 siblings, 0 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-28 16:33 UTC (permalink / raw) To: Linus Walleij Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Wed, Nov 28, 2012 at 05:08:27PM +0100, Linus Walleij wrote: > On Fri, Nov 23, 2012 at 4:08 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > > > Not all the architectures have readsl/writesl, > > use the more portable ioread32_rep/iowrite32_rep functions instead. > > > > Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com> > > Can't think of anything better, put it in Russell's patch tracker when > you think you're finished with it. ok, will do that. Thanks and regards Davide ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep 2012-11-23 15:08 ` [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep Davide Ciminaghi 2012-11-28 16:08 ` Linus Walleij @ 2012-12-03 14:47 ` Will Deacon 2012-12-03 16:55 ` Davide Ciminaghi 1 sibling, 1 reply; 34+ messages in thread From: Will Deacon @ 2012-12-03 14:47 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, giancarlo.asnaghi, linux-kernel, linux-arm-kernel Hi Davide, On Fri, Nov 23, 2012 at 03:08:27PM +0000, Davide Ciminaghi wrote: > Not all the architectures have readsl/writesl, > use the more portable ioread32_rep/iowrite32_rep functions instead. I've already got a patch for this in my io branch: https://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=shortlog;h=refs/heads/io but since I've been dragging my feet on that series, you can also have my ack: Acked-by: Will Deacon <will.deacon@arm.com> I should get round to sending another version of that lot soon. Will ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep 2012-12-03 14:47 ` Will Deacon @ 2012-12-03 16:55 ` Davide Ciminaghi 0 siblings, 0 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-12-03 16:55 UTC (permalink / raw) To: Will Deacon Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, giancarlo.asnaghi, linux-kernel, linux-arm-kernel On Mon, Dec 03, 2012 at 02:47:54PM +0000, Will Deacon wrote: > Hi Davide, > > On Fri, Nov 23, 2012 at 03:08:27PM +0000, Davide Ciminaghi wrote: > > Not all the architectures have readsl/writesl, > > use the more portable ioread32_rep/iowrite32_rep functions instead. > > I've already got a patch for this in my io branch: > > https://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=shortlog;h=refs/heads/io > oh sorry, didn't know that. > but since I've been dragging my feet on that series, you can also have my > ack: > > Acked-by: Will Deacon <will.deacon@arm.com> > ok thanks and regards Davide ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 6/8] mmc: use the new <linux/sizes.h> 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi ` (4 preceding siblings ...) 2012-11-23 15:08 ` [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 2012-11-23 15:59 ` viresh kumar ` (2 more replies) 2012-11-23 15:08 ` [PATCH 7/8] drivers/amba: add support for a PCI bridge Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 8/8] x86: add CONFIG_ARM_AMBA, selected by STA2X11 Davide Ciminaghi 7 siblings, 3 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- drivers/mmc/host/mmci.c | 2 +- drivers/mmc/host/msm_sdcc.c | 2 +- drivers/mmc/host/mvsdio.c | 2 +- drivers/mmc/host/mxcmmc.c | 2 +- drivers/mmc/host/pxamci.c | 3 +-- 5 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 5e39b31..731d98e 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -34,10 +34,10 @@ #include <linux/pm_runtime.h> #include <linux/types.h> #include <linux/pinctrl/consumer.h> +#include <linux/sizes.h> #include <asm/div64.h> #include <asm/io.h> -#include <asm/sizes.h> #include "mmci.h" diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 7c0af0e..aa61b79 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -37,10 +37,10 @@ #include <linux/memory.h> #include <linux/gfp.h> #include <linux/gpio.h> +#include <linux/sizes.h> #include <asm/cacheflush.h> #include <asm/div64.h> -#include <asm/sizes.h> #include <linux/platform_data/mmc-msm_sdcc.h> #include <mach/msm_iomap.h> diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c index de4c20b..e313cd9 100644 --- a/drivers/mmc/host/mvsdio.c +++ b/drivers/mmc/host/mvsdio.c @@ -22,8 +22,8 @@ #include <linux/clk.h> #include <linux/gpio.h> #include <linux/mmc/host.h> +#include <linux/sizes.h> -#include <asm/sizes.h> #include <asm/unaligned.h> #include <linux/platform_data/mmc-mvsdio.h> diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index a72936e..8ce7e73 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c @@ -34,10 +34,10 @@ #include <linux/regulator/consumer.h> #include <linux/dmaengine.h> #include <linux/types.h> +#include <linux/sizes.h> #include <asm/dma.h> #include <asm/irq.h> -#include <asm/sizes.h> #include <linux/platform_data/mmc-mxcmmc.h> #include <linux/platform_data/dma-imx.h> diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index 3f9d6d5..af3604a 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c @@ -33,8 +33,7 @@ #include <linux/of.h> #include <linux/of_gpio.h> #include <linux/of_device.h> - -#include <asm/sizes.h> +#include <linux/sizes.h> #include <mach/hardware.h> #include <mach/dma.h> -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 6/8] mmc: use the new <linux/sizes.h> 2012-11-23 15:08 ` [PATCH 6/8] mmc: use the new <linux/sizes.h> Davide Ciminaghi @ 2012-11-23 15:59 ` viresh kumar 2012-11-26 19:08 ` David Brown 2012-12-01 17:05 ` Linus Walleij 2 siblings, 0 replies; 34+ messages in thread From: viresh kumar @ 2012-11-23 15:59 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 8:38 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 6/8] mmc: use the new <linux/sizes.h> 2012-11-23 15:08 ` [PATCH 6/8] mmc: use the new <linux/sizes.h> Davide Ciminaghi 2012-11-23 15:59 ` viresh kumar @ 2012-11-26 19:08 ` David Brown 2012-12-01 17:05 ` Linus Walleij 2 siblings, 0 replies; 34+ messages in thread From: David Brown @ 2012-11-26 19:08 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 04:08:28PM +0100, Davide Ciminaghi wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> > --- > drivers/mmc/host/msm_sdcc.c | 2 +- Acked-by: David Brown <davidb@codeaurora.org> -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 6/8] mmc: use the new <linux/sizes.h> 2012-11-23 15:08 ` [PATCH 6/8] mmc: use the new <linux/sizes.h> Davide Ciminaghi 2012-11-23 15:59 ` viresh kumar 2012-11-26 19:08 ` David Brown @ 2012-12-01 17:05 ` Linus Walleij 2 siblings, 0 replies; 34+ messages in thread From: Linus Walleij @ 2012-12-01 17:05 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Nov 23, 2012 at 4:08 PM, Davide Ciminaghi <ciminaghi@gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 7/8] drivers/amba: add support for a PCI bridge 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi ` (5 preceding siblings ...) 2012-11-23 15:08 ` [PATCH 6/8] mmc: use the new <linux/sizes.h> Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 8/8] x86: add CONFIG_ARM_AMBA, selected by STA2X11 Davide Ciminaghi 7 siblings, 0 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> This is a PCI driver that registers AMBA devices for the range of supported devices. It is currently used by STA2X11, which exports AMBA peripherals under PCIe. The original AMBA drivers work with no changes or minimal ones. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Alan Cox <alan@linux.intel.com> --- drivers/Kconfig | 2 + drivers/amba/Kconfig | 10 +++++ drivers/amba/Makefile | 1 + drivers/amba/pci-amba.c | 93 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 106 insertions(+) create mode 100644 drivers/amba/Kconfig create mode 100644 drivers/amba/pci-amba.c diff --git a/drivers/Kconfig b/drivers/Kconfig index dbdefa3..6d98cb9 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -156,4 +156,6 @@ source "drivers/pwm/Kconfig" source "drivers/irqchip/Kconfig" +source "drivers/amba/Kconfig" + endmenu diff --git a/drivers/amba/Kconfig b/drivers/amba/Kconfig new file mode 100644 index 0000000..b5b5aca --- /dev/null +++ b/drivers/amba/Kconfig @@ -0,0 +1,10 @@ + +config PCI_AMBA + tristate "PCI-to-AMBA bridge" + depends on ARM_AMBA && PCI + ---help--- + This compiles a PCI driver that registers AMBA devices, so + the respective AMBA driver can be used unchanged if you have + a PCI to amba bridge. This is required for STA2X11 support. + + If uncertain, choose N. diff --git a/drivers/amba/Makefile b/drivers/amba/Makefile index 66e81c2..d30e947 100644 --- a/drivers/amba/Makefile +++ b/drivers/amba/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_ARM_AMBA) += bus.o +obj-$(CONFIG_PCI_AMBA) += pci-amba.o obj-$(CONFIG_TEGRA_AHB) += tegra-ahb.o diff --git a/drivers/amba/pci-amba.c b/drivers/amba/pci-amba.c new file mode 100644 index 0000000..0b0a240 --- /dev/null +++ b/drivers/amba/pci-amba.c @@ -0,0 +1,93 @@ +/* + * Support for AMBA devices (both APB and AHB) behind a PCI bridge + * Copyright 2012 ST Microelectronics (Alessandro Rubini) + * GNU GPL version 2. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/amba/bus.h> +#include <linux/pci.h> +#include <linux/pci_ids.h> +#include <linux/slab.h> +#include <linux/irq.h> +#include <linux/sizes.h> + +static int __devinit pci_amba_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct amba_device *adev; + char *name; + int ret; + + pci_enable_msi(pdev); + ret = pci_enable_device(pdev); + if (ret) + return ret; + + /* Create a name: each of them must be different */ + name = devm_kzalloc(&pdev->dev, strlen(dev_name(&pdev->dev)) + 6, + GFP_KERNEL); + sprintf(name, "amba-%s", dev_name(&pdev->dev)); + + /* Simply build an amba device and register it */ + adev = amba_device_alloc(name, pdev->resource[0].start, SZ_4K); + if (!adev) + return -ENOMEM; + adev->irq[0] = pdev->irq; + + /* This bridge can host both APB and AHB devices, so set master */ + pci_set_master(pdev); + if (pdev->vendor == PCI_VENDOR_ID_STMICRO) { + /* Under sta2x11, DMA is there but limited to 512M */ + adev->dma_mask = SZ_512M - 1; + adev->dev.coherent_dma_mask = SZ_512M - 1; + } + + adev->dev.platform_data = pdev->dev.platform_data; + pci_set_drvdata(pdev, adev); + + return amba_device_add(adev, &pdev->resource[0]); +}; + +static void __devexit pci_amba_remove(struct pci_dev *pdev) +{ + struct amba_device *adev = pci_get_drvdata(pdev); + amba_device_unregister(adev); + pci_disable_msi(pdev); +} + +static DEFINE_PCI_DEVICE_TABLE(pci_amba_table) = { + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_UART_HWFC)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_UART_NO_HWFC)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SOC_DMA)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_I2C)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SPI_HS)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SDIO_EMMC)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SDIO)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA)}, + {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS)}, + {0,} +}; + +static struct pci_driver pci_amba_driver = { + .name = "pci-amba", + .id_table = pci_amba_table, + .probe = pci_amba_probe, + .remove = __devexit_p(pci_amba_remove), +}; + +static int __init pci_amba_init(void) +{ + return pci_register_driver(&pci_amba_driver); +} + +static void __exit pci_amba_exit(void) +{ + pci_unregister_driver(&pci_amba_driver); +} + +module_init(pci_amba_init); +module_exit(pci_amba_exit); + +MODULE_LICENSE("GPL"); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 8/8] x86: add CONFIG_ARM_AMBA, selected by STA2X11 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi ` (6 preceding siblings ...) 2012-11-23 15:08 ` [PATCH 7/8] drivers/amba: add support for a PCI bridge Davide Ciminaghi @ 2012-11-23 15:08 ` Davide Ciminaghi 7 siblings, 0 replies; 34+ messages in thread From: Davide Ciminaghi @ 2012-11-23 15:08 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> The sta2x11 I/O Hub is a bridge from PCIe to AMBA. It reuses a number of amba drivers and needs to activate core bus support. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- arch/x86/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3e6a59f..79304a0 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -525,6 +525,7 @@ config STA2X11 select SWIOTLB select MFD_STA2X11 select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA default n ---help--- This adds support for boards based on the STA2X11 IO-Hub, @@ -2179,6 +2180,9 @@ config GEOS endif # X86_32 +config ARM_AMBA + bool + config AMD_NB def_bool y depends on CPU_SUP_AMD && PCI -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 0/8] enable support for AMBA drivers under x86 @ 2012-09-14 16:23 Davide Ciminaghi 2012-09-14 16:23 ` [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ Davide Ciminaghi 0 siblings, 1 reply; 34+ messages in thread From: Davide Ciminaghi @ 2012-09-14 16:23 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, gregkh, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi, Davide Ciminaghi From: Davide Ciminaghi <ciminaghi@gnudd.com> Following Alessandro's report on build errors for amba drivers under x86 (see [1]), here's a patchset fixing the errors and adding a pci-amba bridge driver. Some notes: * 1/8 (DMA: PL330 ...) is quite fat. Should this be a problem, we could simply disable the PL330 driver under non ARM systems (we actually don't need the PL330 driver for our x86 platform). * All the mmc drivers have been fixed to use the new linux/sizes.h header. * As far as the mmci driver is concerned, readsl/writesl have been replaced by ioread32_rep/iowrite32_rep as suggested by Arnd Bergmann (see [2]). * asm/amba/pl080.h is needed by arch/arm/mach-s3c64xx/dma.c (registers definitions, struct pl080s_lli), so we need most of it to be globally visible. As a consequence Arnd's suggestion (see [2]) about splitting the file into two parts was not followed for now. Davide Notes: [1] https://lkml.org/lkml/2012/7/3/227 [2] https://lkml.org/lkml/2012/7/3/236 Alessandro Rubini (7): DMA: PL330: use prefix in reg names to build under x86 gpio: pl061 depends on ARM pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ watchdog: sp805_wdt depends on ARM mmc: use the new <linux/sizes.h> drivers/amba: add support for a PCI bridge x86: add CONFIG_ARM_AMBA, selected by STA2X11 Davide Ciminaghi (1): mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep arch/arm/include/asm/hardware/pl080.h | 146 --------- arch/arm/mach-s3c64xx/dma.c | 2 +- arch/arm/mach-spear3xx/spear3xx.c | 2 +- arch/arm/mach-spear6xx/spear6xx.c | 2 +- arch/x86/Kconfig | 4 + drivers/Kconfig | 2 + drivers/amba/Kconfig | 10 + drivers/amba/Makefile | 1 + drivers/amba/pci-amba.c | 96 ++++++ drivers/dma/amba-pl08x.c | 2 +- drivers/dma/pl330.c | 581 +++++++++++++++++---------------- drivers/gpio/Kconfig | 2 +- drivers/mmc/host/mmci.c | 10 +- drivers/mmc/host/msm_sdcc.c | 2 +- drivers/mmc/host/mvsdio.c | 2 +- drivers/mmc/host/mxcmmc.c | 2 +- drivers/mmc/host/pxamci.c | 3 +- drivers/watchdog/Kconfig | 2 +- include/linux/amba/pl080.h | 146 +++++++++ 19 files changed, 566 insertions(+), 451 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/pl080.h create mode 100644 drivers/amba/Kconfig create mode 100644 drivers/amba/pci-amba.c create mode 100644 include/linux/amba/pl080.h -- 1.7.9.1 ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ 2012-09-14 16:23 [PATCH 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi @ 2012-09-14 16:23 ` Davide Ciminaghi 2012-09-16 22:11 ` Linus Walleij 0 siblings, 1 reply; 34+ messages in thread From: Davide Ciminaghi @ 2012-09-14 16:23 UTC (permalink / raw) To: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, linus.walleij, rubini, wim, cjb, davidb, nico, gregkh, ben-linux, viresh.linux, rajeev-dlh.kumar Cc: linux-kernel, linux-arm-kernel, giancarlo.asnaghi From: Alessandro Rubini <rubini@gnudd.com> The header is used by drivers/dma/amba-pl08x.c, which can be compiled under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche moves it where it can be accessed by other architectures, and fixes all users. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> --- arch/arm/include/asm/hardware/pl080.h | 146 --------------------------------- arch/arm/mach-s3c64xx/dma.c | 2 +- arch/arm/mach-spear3xx/spear3xx.c | 2 +- arch/arm/mach-spear6xx/spear6xx.c | 2 +- drivers/dma/amba-pl08x.c | 2 +- include/linux/amba/pl080.h | 146 +++++++++++++++++++++++++++++++++ 6 files changed, 150 insertions(+), 150 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/pl080.h create mode 100644 include/linux/amba/pl080.h diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h deleted file mode 100644 index 4eea210..0000000 --- a/arch/arm/include/asm/hardware/pl080.h +++ /dev/null @@ -1,146 +0,0 @@ -/* arch/arm/include/asm/hardware/pl080.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * ARM PrimeCell PL080 DMA controller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* Note, there are some Samsung updates to this controller block which - * make it not entierly compatible with the PL080 specification from - * ARM. When in doubt, check the Samsung documentation first. - * - * The Samsung defines are PL080S, and add an extra control register, - * the ability to move more than 2^11 counts of data and some extra - * OneNAND features. -*/ - -#ifndef ASM_PL080_H -#define ASM_PL080_H - -#define PL080_INT_STATUS (0x00) -#define PL080_TC_STATUS (0x04) -#define PL080_TC_CLEAR (0x08) -#define PL080_ERR_STATUS (0x0C) -#define PL080_ERR_CLEAR (0x10) -#define PL080_RAW_TC_STATUS (0x14) -#define PL080_RAW_ERR_STATUS (0x18) -#define PL080_EN_CHAN (0x1c) -#define PL080_SOFT_BREQ (0x20) -#define PL080_SOFT_SREQ (0x24) -#define PL080_SOFT_LBREQ (0x28) -#define PL080_SOFT_LSREQ (0x2C) - -#define PL080_CONFIG (0x30) -#define PL080_CONFIG_M2_BE (1 << 2) -#define PL080_CONFIG_M1_BE (1 << 1) -#define PL080_CONFIG_ENABLE (1 << 0) - -#define PL080_SYNC (0x34) - -/* Per channel configuration registers */ - -#define PL080_Cx_STRIDE (0x20) -#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) -#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20))) -#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20))) -#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20))) -#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20))) -#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20))) -#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20))) -#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20))) - -#define PL080_CH_SRC_ADDR (0x00) -#define PL080_CH_DST_ADDR (0x04) -#define PL080_CH_LLI (0x08) -#define PL080_CH_CONTROL (0x0C) -#define PL080_CH_CONFIG (0x10) -#define PL080S_CH_CONTROL2 (0x10) -#define PL080S_CH_CONFIG (0x14) - -#define PL080_LLI_ADDR_MASK (0x3fffffff << 2) -#define PL080_LLI_ADDR_SHIFT (2) -#define PL080_LLI_LM_AHB2 (1 << 0) - -#define PL080_CONTROL_TC_IRQ_EN (1 << 31) -#define PL080_CONTROL_PROT_MASK (0x7 << 28) -#define PL080_CONTROL_PROT_SHIFT (28) -#define PL080_CONTROL_PROT_CACHE (1 << 30) -#define PL080_CONTROL_PROT_BUFF (1 << 29) -#define PL080_CONTROL_PROT_SYS (1 << 28) -#define PL080_CONTROL_DST_INCR (1 << 27) -#define PL080_CONTROL_SRC_INCR (1 << 26) -#define PL080_CONTROL_DST_AHB2 (1 << 25) -#define PL080_CONTROL_SRC_AHB2 (1 << 24) -#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) -#define PL080_CONTROL_DWIDTH_SHIFT (21) -#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) -#define PL080_CONTROL_SWIDTH_SHIFT (18) -#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) -#define PL080_CONTROL_DB_SIZE_SHIFT (15) -#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) -#define PL080_CONTROL_SB_SIZE_SHIFT (12) -#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) -#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) - -#define PL080_BSIZE_1 (0x0) -#define PL080_BSIZE_4 (0x1) -#define PL080_BSIZE_8 (0x2) -#define PL080_BSIZE_16 (0x3) -#define PL080_BSIZE_32 (0x4) -#define PL080_BSIZE_64 (0x5) -#define PL080_BSIZE_128 (0x6) -#define PL080_BSIZE_256 (0x7) - -#define PL080_WIDTH_8BIT (0x0) -#define PL080_WIDTH_16BIT (0x1) -#define PL080_WIDTH_32BIT (0x2) - -#define PL080N_CONFIG_ITPROT (1 << 20) -#define PL080N_CONFIG_SECPROT (1 << 19) -#define PL080_CONFIG_HALT (1 << 18) -#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */ -#define PL080_CONFIG_LOCK (1 << 16) -#define PL080_CONFIG_TC_IRQ_MASK (1 << 15) -#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14) -#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) -#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) -#define PL080_CONFIG_DST_SEL_MASK (0xf << 6) -#define PL080_CONFIG_DST_SEL_SHIFT (6) -#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) -#define PL080_CONFIG_SRC_SEL_SHIFT (1) -#define PL080_CONFIG_ENABLE (1 << 0) - -#define PL080_FLOW_MEM2MEM (0x0) -#define PL080_FLOW_MEM2PER (0x1) -#define PL080_FLOW_PER2MEM (0x2) -#define PL080_FLOW_SRC2DST (0x3) -#define PL080_FLOW_SRC2DST_DST (0x4) -#define PL080_FLOW_MEM2PER_PER (0x5) -#define PL080_FLOW_PER2MEM_PER (0x6) -#define PL080_FLOW_SRC2DST_SRC (0x7) - -/* DMA linked list chain structure */ - -struct pl080_lli { - u32 src_addr; - u32 dst_addr; - u32 next_lli; - u32 control0; -}; - -struct pl080s_lli { - u32 src_addr; - u32 dst_addr; - u32 next_lli; - u32 control0; - u32 control1; -}; - -#endif /* ASM_PL080_H */ diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index f2a7a17..a77f521 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -23,6 +23,7 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/amba/pl080.h> #include <mach/dma.h> #include <mach/map.h> @@ -30,7 +31,6 @@ #include <mach/regs-sys.h> -#include <asm/hardware/pl080.h> /* dma channel state information */ diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 98144ba..ba61129 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -15,9 +15,9 @@ #include <linux/amba/pl022.h> #include <linux/amba/pl08x.h> +#include <linux/amba/pl080.h> #include <linux/of_irq.h> #include <linux/io.h> -#include <asm/hardware/pl080.h> #include <asm/hardware/vic.h> #include <plat/pl080.h> #include <mach/generic.h> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 5a5a52d..8ce65a2 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -20,7 +20,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <asm/hardware/pl080.h> +#include <linux/amba/pl080.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index d1cc579..b453c2f 100644 --- a/drivers/dma/amba-pl08x.c +++ b/drivers/dma/amba-pl08x.c @@ -83,7 +83,7 @@ #include <linux/pm_runtime.h> #include <linux/seq_file.h> #include <linux/slab.h> -#include <asm/hardware/pl080.h> +#include <linux/amba/pl080.h> #include "dmaengine.h" #include "virt-dma.h" diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h new file mode 100644 index 0000000..3e7b62f --- /dev/null +++ b/include/linux/amba/pl080.h @@ -0,0 +1,146 @@ +/* include/linux/amba/pl080.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * ARM PrimeCell PL080 DMA controller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Note, there are some Samsung updates to this controller block which + * make it not entierly compatible with the PL080 specification from + * ARM. When in doubt, check the Samsung documentation first. + * + * The Samsung defines are PL080S, and add an extra control register, + * the ability to move more than 2^11 counts of data and some extra + * OneNAND features. +*/ + +#ifndef ASM_PL080_H +#define ASM_PL080_H + +#define PL080_INT_STATUS (0x00) +#define PL080_TC_STATUS (0x04) +#define PL080_TC_CLEAR (0x08) +#define PL080_ERR_STATUS (0x0C) +#define PL080_ERR_CLEAR (0x10) +#define PL080_RAW_TC_STATUS (0x14) +#define PL080_RAW_ERR_STATUS (0x18) +#define PL080_EN_CHAN (0x1c) +#define PL080_SOFT_BREQ (0x20) +#define PL080_SOFT_SREQ (0x24) +#define PL080_SOFT_LBREQ (0x28) +#define PL080_SOFT_LSREQ (0x2C) + +#define PL080_CONFIG (0x30) +#define PL080_CONFIG_M2_BE (1 << 2) +#define PL080_CONFIG_M1_BE (1 << 1) +#define PL080_CONFIG_ENABLE (1 << 0) + +#define PL080_SYNC (0x34) + +/* Per channel configuration registers */ + +#define PL080_Cx_STRIDE (0x20) +#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) +#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20))) +#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20))) +#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20))) +#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20))) +#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20))) +#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20))) +#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20))) + +#define PL080_CH_SRC_ADDR (0x00) +#define PL080_CH_DST_ADDR (0x04) +#define PL080_CH_LLI (0x08) +#define PL080_CH_CONTROL (0x0C) +#define PL080_CH_CONFIG (0x10) +#define PL080S_CH_CONTROL2 (0x10) +#define PL080S_CH_CONFIG (0x14) + +#define PL080_LLI_ADDR_MASK (0x3fffffff << 2) +#define PL080_LLI_ADDR_SHIFT (2) +#define PL080_LLI_LM_AHB2 (1 << 0) + +#define PL080_CONTROL_TC_IRQ_EN (1 << 31) +#define PL080_CONTROL_PROT_MASK (0x7 << 28) +#define PL080_CONTROL_PROT_SHIFT (28) +#define PL080_CONTROL_PROT_CACHE (1 << 30) +#define PL080_CONTROL_PROT_BUFF (1 << 29) +#define PL080_CONTROL_PROT_SYS (1 << 28) +#define PL080_CONTROL_DST_INCR (1 << 27) +#define PL080_CONTROL_SRC_INCR (1 << 26) +#define PL080_CONTROL_DST_AHB2 (1 << 25) +#define PL080_CONTROL_SRC_AHB2 (1 << 24) +#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) +#define PL080_CONTROL_DWIDTH_SHIFT (21) +#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) +#define PL080_CONTROL_SWIDTH_SHIFT (18) +#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) +#define PL080_CONTROL_DB_SIZE_SHIFT (15) +#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) +#define PL080_CONTROL_SB_SIZE_SHIFT (12) +#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) +#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) + +#define PL080_BSIZE_1 (0x0) +#define PL080_BSIZE_4 (0x1) +#define PL080_BSIZE_8 (0x2) +#define PL080_BSIZE_16 (0x3) +#define PL080_BSIZE_32 (0x4) +#define PL080_BSIZE_64 (0x5) +#define PL080_BSIZE_128 (0x6) +#define PL080_BSIZE_256 (0x7) + +#define PL080_WIDTH_8BIT (0x0) +#define PL080_WIDTH_16BIT (0x1) +#define PL080_WIDTH_32BIT (0x2) + +#define PL080N_CONFIG_ITPROT (1 << 20) +#define PL080N_CONFIG_SECPROT (1 << 19) +#define PL080_CONFIG_HALT (1 << 18) +#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */ +#define PL080_CONFIG_LOCK (1 << 16) +#define PL080_CONFIG_TC_IRQ_MASK (1 << 15) +#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14) +#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) +#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) +#define PL080_CONFIG_DST_SEL_MASK (0xf << 6) +#define PL080_CONFIG_DST_SEL_SHIFT (6) +#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) +#define PL080_CONFIG_SRC_SEL_SHIFT (1) +#define PL080_CONFIG_ENABLE (1 << 0) + +#define PL080_FLOW_MEM2MEM (0x0) +#define PL080_FLOW_MEM2PER (0x1) +#define PL080_FLOW_PER2MEM (0x2) +#define PL080_FLOW_SRC2DST (0x3) +#define PL080_FLOW_SRC2DST_DST (0x4) +#define PL080_FLOW_MEM2PER_PER (0x5) +#define PL080_FLOW_PER2MEM_PER (0x6) +#define PL080_FLOW_SRC2DST_SRC (0x7) + +/* DMA linked list chain structure */ + +struct pl080_lli { + u32 src_addr; + u32 dst_addr; + u32 next_lli; + u32 control0; +}; + +struct pl080s_lli { + u32 src_addr; + u32 dst_addr; + u32 next_lli; + u32 control0; + u32 control1; +}; + +#endif /* ASM_PL080_H */ -- 1.7.9.1 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ 2012-09-14 16:23 ` [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ Davide Ciminaghi @ 2012-09-16 22:11 ` Linus Walleij 0 siblings, 0 replies; 34+ messages in thread From: Linus Walleij @ 2012-09-16 22:11 UTC (permalink / raw) To: Davide Ciminaghi Cc: linux, tglx, mingo, hpa, djbw, vinod.koul, grant.likely, rubini, wim, cjb, davidb, nico, gregkh, ben-linux, viresh.linux, rajeev-dlh.kumar, linux-kernel, linux-arm-kernel, giancarlo.asnaghi On Fri, Sep 14, 2012 at 6:23 PM, Davide Ciminaghi <dciminaghi@mail.gnudd.com> wrote: > From: Alessandro Rubini <rubini@gnudd.com> > > The header is used by drivers/dma/amba-pl08x.c, which can be compiled > under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche > moves it where it can be accessed by other architectures, and fixes > all users. > > Signed-off-by: Alessandro Rubini <rubini@gnudd.com> > Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> It's not really platform data or anything, but as long as the old Samsung drivers are using it we cannot cut it from the global scope, and I cannot think of anything better to do so: Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij ^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2012-12-03 16:57 UTC | newest] Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-11-23 15:08 [PATCH v2 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 1/8] DMA: PL330: use prefix in reg names to build " Davide Ciminaghi 2012-11-23 15:51 ` viresh kumar 2012-11-23 17:23 ` Davide Ciminaghi 2012-11-23 17:28 ` Viresh Kumar 2012-11-24 0:53 ` [PATCH 1/8 v3] " Davide Ciminaghi 2012-11-24 5:14 ` Jassi Brar 2012-11-24 7:03 ` Alessandro Rubini 2012-11-24 11:05 ` Jassi Brar 2012-11-28 16:15 ` Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 2/8] gpio: pl061 depends on ARM Davide Ciminaghi 2012-11-23 15:57 ` viresh kumar 2012-12-01 15:11 ` Linus Walleij 2012-12-03 13:31 ` Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ Davide Ciminaghi 2012-11-23 15:53 ` viresh kumar 2012-11-24 0:22 ` [PATCH 3/8 v3] " Davide Ciminaghi 2012-11-28 16:04 ` Linus Walleij 2012-11-23 15:08 ` [PATCH 4/8] watchdog: sp805_wdt depends on ARM Davide Ciminaghi 2012-11-23 15:56 ` viresh kumar 2012-11-28 16:00 ` Linus Walleij 2012-11-23 15:08 ` [PATCH 5/8] mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep Davide Ciminaghi 2012-11-28 16:08 ` Linus Walleij 2012-11-28 16:33 ` Davide Ciminaghi 2012-12-03 14:47 ` Will Deacon 2012-12-03 16:55 ` Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 6/8] mmc: use the new <linux/sizes.h> Davide Ciminaghi 2012-11-23 15:59 ` viresh kumar 2012-11-26 19:08 ` David Brown 2012-12-01 17:05 ` Linus Walleij 2012-11-23 15:08 ` [PATCH 7/8] drivers/amba: add support for a PCI bridge Davide Ciminaghi 2012-11-23 15:08 ` [PATCH 8/8] x86: add CONFIG_ARM_AMBA, selected by STA2X11 Davide Ciminaghi -- strict thread matches above, loose matches on Subject: below -- 2012-09-14 16:23 [PATCH 0/8] enable support for AMBA drivers under x86 Davide Ciminaghi 2012-09-14 16:23 ` [PATCH 3/8] pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ Davide Ciminaghi 2012-09-16 22:11 ` Linus Walleij
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