[PATCH 0/6] metag: misc & priv patches

[PATCH 0/6] metag: misc & priv patches

[James Hogan]

Here are some additional metag patches I intend to add on top of the
existing v4 arch/metag patchset.

James Hogan (6):
  metag: add __init to metag_cache_probe()
  metag: add boot time LNKGET/LNKSET check
  perf: Enable building perf tools for Meta
  metag: kernel/setup.c: sort includes
  metag: make TXPRIVEXT bits explicit
  metag: protect more non-MMU memory regions

 arch/metag/include/asm/metag_regs.h |    4 +
 arch/metag/include/asm/processor.h  |    2 +-
 arch/metag/kernel/setup.c           |  125 +++++++++++++++++++++++++----------
 arch/metag/kernel/smp.c             |    2 +-
 arch/metag/mm/cache.c               |   81 ++++++++++++++++++++++-
 tools/perf/perf.h                   |    6 ++
 6 files changed, 182 insertions(+), 38 deletions(-)

-- 
1.7.7.6

[PATCH 1/6] metag: add __init to metag_cache_probe()

[James Hogan]

metag_cache_probe() is only called from setup_arch(), so add the __init
attribute to it.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
---
 arch/metag/mm/cache.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/metag/mm/cache.c b/arch/metag/mm/cache.c
index b713ec0..89da74a 100644
--- a/arch/metag/mm/cache.c
+++ b/arch/metag/mm/cache.c
@@ -42,7 +42,7 @@ static unsigned char icache_sets_log2 = DEFAULT_CACHE_WAYS_LOG2;
  * Probe the L1 cache configuration to aid the L1 physical cache flushing
  * functions.
  */
-void metag_cache_probe(void)
+void __init metag_cache_probe(void)
 {
 #ifndef CONFIG_METAG_META12
 	int coreid = metag_in32(METAC_CORE_ID);
-- 
1.7.7.6

[PATCH 2/6] metag: add boot time LNKGET/LNKSET check

[James Hogan]

Add boot time check for whether LNKGET/LNKSET go through or around the
cache. Depending on the configuration an info message (no harm), warning
(technically wrong but no harm), or big WARN (expect failure in either
kernel or userland) may be emitted if the behaviour is not as expected:

Configuration                                Hardware   Response
------------------------------------------   --------   --------
AROUND_CACHE                                 through    pr_info
!AROUND_CACHE && ATOMICITY_LNKGET            around     WARN (kernel)
     "        && !ATOMICITY_LNKGET && SMP    around     WARN (user)
     "                   "         && !SMP   around     pr_warn

Signed-off-by: James Hogan <james.hogan@imgtec.com>
---
 arch/metag/mm/cache.c |   79 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 79 insertions(+), 0 deletions(-)

diff --git a/arch/metag/mm/cache.c b/arch/metag/mm/cache.c
index 89da74a..4dd96e4 100644
--- a/arch/metag/mm/cache.c
+++ b/arch/metag/mm/cache.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <asm/cacheflush.h>
 #include <asm/core_reg.h>
+#include <asm/global_lock.h>
 #include <asm/metag_isa.h>
 #include <asm/metag_mem.h>
 #include <asm/metag_regs.h>
@@ -36,6 +37,82 @@ static int icache_set_shift = METAG_TBI_CACHE_SIZE_BASE_LOG2
 static unsigned char dcache_sets_log2 = DEFAULT_CACHE_WAYS_LOG2;
 static unsigned char icache_sets_log2 = DEFAULT_CACHE_WAYS_LOG2;
 
+#ifndef CONFIG_METAG_META12
+/**
+ * metag_lnkget_probe() - Probe whether lnkget/lnkset go around the cache
+ */
+static volatile u32 lnkget_testdata[16] __initdata __aligned(64);
+
+#define LNKGET_CONSTANT 0xdeadbeef
+
+void __init metag_lnkget_probe(void)
+{
+	int temp;
+	long flags;
+
+	/*
+	 * It's conceivable the user has configured a globally coherent cache
+	 * shared with non-Linux hardware threads, so use LOCK2 to prevent them
+	 * from executing and causing cache eviction during the test.
+	 */
+	__global_lock2(flags);
+
+	/* read a value to bring it into the cache */
+	(void)lnkget_testdata[0];
+	lnkget_testdata[0] = 0;
+
+	/* lnkget/lnkset it to modify it */
+	asm volatile(
+		"1:	LNKGETD %0, [%1]\n"
+		"	LNKSETD [%1], %2\n"
+		"	DEFR	%0, TXSTAT\n"
+		"	ANDT	%0, %0, #HI(0x3f000000)\n"
+		"	CMPT	%0, #HI(0x02000000)\n"
+		"	BNZ	1b\n"
+		: "=&d" (temp)
+		: "da" (&lnkget_testdata[0]), "bd" (LNKGET_CONSTANT)
+		: "cc");
+
+	/* re-read it to see if the cached value changed */
+	temp = lnkget_testdata[0];
+
+	__global_unlock2(flags);
+
+	/* flush the cache line to fix any incoherency */
+	__builtin_dcache_flush((void *)&lnkget_testdata[0]);
+
+#if defined(CONFIG_METAG_LNKGET_AROUND_CACHE)
+	/* if the cache is right, LNKGET_AROUND_CACHE is unnecessary */
+	if (temp == LNKGET_CONSTANT)
+		pr_info("LNKGET/SET go through cache but CONFIG_METAG_LNKGET_AROUND_CACHE=y\n");
+#elif defined(CONFIG_METAG_ATOMICITY_LNKGET)
+	/*
+	 * if the cache is wrong, LNKGET_AROUND_CACHE is really necessary
+	 * because the kernel is configured to use LNKGET/SET for atomicity
+	 */
+	WARN(temp != LNKGET_CONSTANT,
+	     "LNKGET/SET go around cache but CONFIG_METAG_LNKGET_AROUND_CACHE=n\n"
+	     "Expect kernel failure as it's used for atomicity primitives\n");
+#elif defined(CONFIG_SMP)
+	/*
+	 * if the cache is wrong, LNKGET_AROUND_CACHE should be used or the
+	 * gateway page won't flush and userland could break.
+	 */
+	WARN(temp != LNKGET_CONSTANT,
+	     "LNKGET/SET go around cache but CONFIG_METAG_LNKGET_AROUND_CACHE=n\n"
+	     "Expect userland failure as it's used for user gateway page\n");
+#else
+	/*
+	 * if the cache is wrong, LNKGET_AROUND_CACHE is set wrong, but it
+	 * doesn't actually matter as it doesn't have any effect on !SMP &&
+	 * !ATOMICITY_LNKGET.
+	 */
+	if (temp != LNKGET_CONSTANT)
+		pr_warn("LNKGET/SET go around cache but CONFIG_METAG_LNKGET_AROUND_CACHE=n\n");
+#endif
+}
+#endif /* !CONFIG_METAG_META12 */
+
 /**
  * metag_cache_probe() - Probe L1 cache configuration.
  *
@@ -68,6 +145,8 @@ void __init metag_cache_probe(void)
 	dcache_set_shift += (config & METAC_CORECFG2_DCSZ_BITS)
 				>> METAC_CORECFG2_DCSZ_S;
 	dcache_set_shift -= dcache_sets_log2;
+
+	metag_lnkget_probe();
 #else
 	/* Extract cache sizes from global heap segment */
 	unsigned long val, u;
-- 
1.7.7.6

[PATCH 3/6] perf: Enable building perf tools for Meta

[James Hogan]

Define rmb(), cpu_relax(), and CPUINFO_PROC for Meta so that the perf
tools can be built for Meta.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
---
 tools/perf/perf.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/tools/perf/perf.h b/tools/perf/perf.h
index 2c340e7..768507e 100644
--- a/tools/perf/perf.h
+++ b/tools/perf/perf.h
@@ -98,6 +98,12 @@ void get_term_dimensions(struct winsize *ws);
 #define CPUINFO_PROC	"cpu model"
 #endif
 
+#ifdef __metag__
+#define rmb()		asm volatile("" ::: "memory")
+#define cpu_relax()	asm volatile("" ::: "memory")
+#define CPUINFO_PROC	"CPU"
+#endif
+
 #include <time.h>
 #include <unistd.h>
 #include <sys/types.h>
-- 
1.7.7.6

[PATCH 4/6] metag: kernel/setup.c: sort includes

[James Hogan]

Sort includes in kernel/setup.c.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
---
 arch/metag/kernel/setup.c |   46 ++++++++++++++++++++++----------------------
 1 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/arch/metag/kernel/setup.c b/arch/metag/kernel/setup.c
index 89f9cdc..aaebc56 100644
--- a/arch/metag/kernel/setup.c
+++ b/arch/metag/kernel/setup.c
@@ -5,43 +5,43 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
+#include <linux/bootmem.h>
+#include <linux/console.h>
+#include <linux/cpu.h>
 #include <linux/delay.h>
-#include <linux/interrupt.h>
+#include <linux/errno.h>
 #include <linux/fs.h>
-#include <linux/console.h>
 #include <linux/genhd.h>
-#include <linux/errno.h>
-#include <linux/string.h>
 #include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/root_dev.h>
 #include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/pfn.h>
-#include <linux/start_kernel.h>
-#include <linux/cpu.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
 #include <linux/memblock.h>
+#include <linux/mm.h>
 #include <linux/of_fdt.h>
+#include <linux/pfn.h>
+#include <linux/root_dev.h>
+#include <linux/sched.h>
+#include <linux/seq_file.h>
+#include <linux/start_kernel.h>
+#include <linux/string.h>
 
 #include <asm/cachepart.h>
 #include <asm/clock.h>
-#include <asm/sections.h>
-#include <asm/setup.h>
-#include <asm/processor.h>
-#include <asm/traps.h>
-#include <asm/mmu.h>
+#include <asm/core_reg.h>
 #include <asm/cpu.h>
+#include <asm/da.h>
+#include <asm/highmem.h>
 #include <asm/hwthread.h>
-#include <asm/mmzone.h>
 #include <asm/l2cache.h>
-#include <asm/da.h>
-#include <asm/prom.h>
 #include <asm/mach/arch.h>
-#include <asm/core_reg.h>
-#include <asm/highmem.h>
+#include <asm/mmu.h>
+#include <asm/mmzone.h>
+#include <asm/processor.h>
+#include <asm/prom.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+#include <asm/traps.h>
 
 /* PRIV protect as many registers as possible. */
 #define DEFAULT_PRIV	0xff0f7f00
-- 
1.7.7.6

[PATCH 5/6] metag: make TXPRIVEXT bits explicit

[James Hogan]

Define PRIV_BITS using explicit constants from <asm/metag_regs.h> rather
than with a hard coded value. This also adds a couple of missing
definitions for the TXPRIVEXT priv bits for protecting writes to TXTIMER
and the trace registers.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
---
 arch/metag/include/asm/metag_regs.h |    4 ++++
 arch/metag/kernel/setup.c           |   34 +++++++++++++++++++++++++++-------
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/arch/metag/include/asm/metag_regs.h b/arch/metag/include/asm/metag_regs.h
index 022fcad..acf4b8e 100644
--- a/arch/metag/include/asm/metag_regs.h
+++ b/arch/metag/include/asm/metag_regs.h
@@ -414,6 +414,10 @@
 #define TXPRIVEXT_REGNUM 29
 #define     TXPRIVEXT_COPRO_BITS    0xFF000000 /* Co-processor 0-7 */
 #define     TXPRIVEXT_COPRO_S       24
+#ifndef METAC_1_2
+#define     TXPRIVEXT_TXTIMER_BIT   0x00080000 /* TXTIMER   priv */
+#define     TXPRIVEXT_TRACE_BIT     0x00040000 /* TTEXEC|TTCTRL|GTEXEC */
+#endif
 #define     TXPRIVEXT_TXTRIGGER_BIT 0x00020000 /* TXSTAT|TXMASK|TXPOLL */
 #define     TXPRIVEXT_TXGBLCREG_BIT 0x00010000 /* Global common regs */
 #define     TXPRIVEXT_CBPRIV_BIT    0x00008000 /* Mem i/f dump priv */
diff --git a/arch/metag/kernel/setup.c b/arch/metag/kernel/setup.c
index aaebc56..dcb1d6d 100644
--- a/arch/metag/kernel/setup.c
+++ b/arch/metag/kernel/setup.c
@@ -35,6 +35,7 @@
 #include <asm/hwthread.h>
 #include <asm/l2cache.h>
 #include <asm/mach/arch.h>
+#include <asm/metag_regs.h>
 #include <asm/mmu.h>
 #include <asm/mmzone.h>
 #include <asm/processor.h>
@@ -43,18 +44,37 @@
 #include <asm/setup.h>
 #include <asm/traps.h>
 
-/* PRIV protect as many registers as possible. */
-#define DEFAULT_PRIV	0xff0f7f00
-
-/* Enable unaligned access checking. */
-#define UNALIGNED_PRIV	0x00000010
+/* Priv protect as many registers as possible. */
+#define DEFAULT_PRIV	(TXPRIVEXT_COPRO_BITS		| \
+			 TXPRIVEXT_TXTRIGGER_BIT	| \
+			 TXPRIVEXT_TXGBLCREG_BIT	| \
+			 TXPRIVEXT_ILOCK_BIT		| \
+			 TXPRIVEXT_TXITACCYC_BIT	| \
+			 TXPRIVEXT_TXDIVTIME_BIT	| \
+			 TXPRIVEXT_TXAMAREGX_BIT	| \
+			 TXPRIVEXT_TXTIMERI_BIT		| \
+			 TXPRIVEXT_TXSTATUS_BIT		| \
+			 TXPRIVEXT_TXDISABLE_BIT)
+
+/* Meta2 specific bits. */
+#ifdef CONFIG_METAG_META12
+#define META2_PRIV	0
+#else
+#define META2_PRIV	(TXPRIVEXT_TXTIMER_BIT		| \
+			 TXPRIVEXT_TRACE_BIT)
+#endif
 
+/* Unaligned access checking bits. */
 #ifdef CONFIG_METAG_UNALIGNED
-#define PRIV_BITS (DEFAULT_PRIV | UNALIGNED_PRIV)
+#define UNALIGNED_PRIV	TXPRIVEXT_ALIGNREW_BIT
 #else
-#define PRIV_BITS DEFAULT_PRIV
+#define UNALIGNED_PRIV	0
 #endif
 
+#define PRIV_BITS 	(DEFAULT_PRIV			| \
+			 META2_PRIV			| \
+			 UNALIGNED_PRIV)
+
 extern char _heap_start[];
 
 #ifdef CONFIG_METAG_BUILTIN_DTB
-- 
1.7.7.6

[PATCH 6/6] metag: protect more non-MMU memory regions

[James Hogan]

Rename setup_txprivext() to setup_priv() and add initialisation of some
more per-thread privilege protection registers:

 - TxPRIVSYSR: 0x04400000-0x047fffff
               0x05000000-0x07ffffff
               0x84000000-0x87ffffff
 - TxPIOREG:   0x02000000-0x02ffffff
               0x04800000-0x048fffff
 - TxSYREG:    0x04000000-0x04000fff (except write fetch system event)

Signed-off-by: James Hogan <james.hogan@imgtec.com>
---
 arch/metag/include/asm/processor.h |    2 +-
 arch/metag/kernel/setup.c          |   45 ++++++++++++++++++++++++++++++++----
 arch/metag/kernel/smp.c            |    2 +-
 3 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/arch/metag/include/asm/processor.h b/arch/metag/include/asm/processor.h
index b7e2528..9b029a7 100644
--- a/arch/metag/include/asm/processor.h
+++ b/arch/metag/include/asm/processor.h
@@ -154,7 +154,7 @@ unsigned long get_wchan(struct task_struct *p);
 
 #define cpu_relax()     barrier()
 
-extern void setup_txprivext(void);
+extern void setup_priv(void);
 
 static inline unsigned int hard_processor_id(void)
 {
diff --git a/arch/metag/kernel/setup.c b/arch/metag/kernel/setup.c
index dcb1d6d..9803ca4 100644
--- a/arch/metag/kernel/setup.c
+++ b/arch/metag/kernel/setup.c
@@ -35,6 +35,7 @@
 #include <asm/hwthread.h>
 #include <asm/l2cache.h>
 #include <asm/mach/arch.h>
+#include <asm/metag_mem.h>
 #include <asm/metag_regs.h>
 #include <asm/mmu.h>
 #include <asm/mmzone.h>
@@ -75,6 +76,32 @@
 			 META2_PRIV			| \
 			 UNALIGNED_PRIV)
 
+/*
+ * Protect access to:
+ * 0x06000000-0x07ffffff Direct mapped region
+ * 0x05000000-0x05ffffff MMU table region (Meta1)
+ * 0x04400000-0x047fffff Cache flush region
+ * 0x84000000-0x87ffffff Core cache memory region (Meta2)
+ *
+ * Allow access to:
+ * 0x80000000-0x81ffffff Core code memory region (Meta2)
+ */
+#ifdef CONFIG_METAG_META12
+#define PRIVSYSR_BITS	TXPRIVSYSR_ALL_BITS
+#else
+#define PRIVSYSR_BITS	(TXPRIVSYSR_ALL_BITS & ~TXPRIVSYSR_CORECODE_BIT)
+#endif
+
+/* Protect all 0x02xxxxxx and 0x048xxxxx. */
+#define PIOREG_BITS	0xffffffff
+
+/*
+ * Protect all 0x04000xx0 (system events)
+ * except write combiner flush and write fence (system events 4 and 5).
+ */
+#define PSYREG_BITS	0xfffffffb
+
+
 extern char _heap_start[];
 
 #ifdef CONFIG_METAG_BUILTIN_DTB
@@ -371,7 +398,7 @@ void __init setup_arch(char **cmdline_p)
 
 	paging_init(heap_end);
 
-	setup_txprivext();
+	setup_priv();
 
 	/* Setup the boot cpu's mapping. The rest will be setup below. */
 	cpu_2_hwthread_id[smp_processor_id()] = hard_processor_id();
@@ -531,13 +558,21 @@ void __init metag_start_kernel(char *args)
 	start_kernel();
 }
 
-/*
- * Setup TXPRIVEXT register to be prevent userland from touching our
- * precious registers.
+/**
+ * setup_priv() - Set up privilege protection registers.
+ *
+ * Set up privilege protection registers such as TXPRIVEXT to prevent userland
+ * from touching our precious registers and sensitive memory areas.
  */
-void setup_txprivext(void)
+void setup_priv(void)
 {
+	unsigned int offset = hard_processor_id() << TXPRIVREG_STRIDE_S;
+
 	__core_reg_set(TXPRIVEXT, PRIV_BITS);
+
+	metag_out32(PRIVSYSR_BITS, T0PRIVSYSR + offset);
+	metag_out32(PIOREG_BITS,   T0PIOREG   + offset);
+	metag_out32(PSYREG_BITS,   T0PSYREG   + offset);
 }
 
 PTBI pTBI_get(unsigned int cpu)
diff --git a/arch/metag/kernel/smp.c b/arch/metag/kernel/smp.c
index d116312..4b6d1f14 100644
--- a/arch/metag/kernel/smp.c
+++ b/arch/metag/kernel/smp.c
@@ -268,7 +268,7 @@ asmlinkage void secondary_start_kernel(void)
 
 	preempt_disable();
 
-	setup_txprivext();
+	setup_priv();
 
 	/*
 	 * Enable local interrupts.
-- 
1.7.7.6