[PATCH v3 0/4] Exynos 5410 Dual cluster support

[PATCH v3 0/4] Exynos 5410 Dual cluster support

[Vyacheslav Tyrtov]

The series of patches represent support of Exynos 5410 SoC

The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time

Patches add new platform description, support of clock controller,
dual cluster support and device tree for Exynos 5410

Has been build on v3.12.
Has been tested on Exynos 5410 reference board (exynos_defconfig).

Thanks,
        Vyacheslav.


Changelog:

v3:
	In drivers/clk/samsung/clk-exynos5410.c
1. Fixed rate clock "samsung,clock-oscclk" removed.
	In arch/arm/boot/dts/exynos5410.dtsi
1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk.
	In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. Fixed rate oscclk clock added.
	In arch/arm/mach-exynos/edcs.c
1. Added write memory barrier in exynos_core_power_control function.
2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed.
3. #define added for some magic constants.
4. Disabled the GIC CPU interface in exynos_power_down function.

v2:
	In drivers/clk/samsung/clk-exynos5410.c
1. Clock driver converted to use preprocessor macros instead of enums.
   Clock IDs now defined in include/dt-bindings/clock/exynos5410.h.
2. Unused spinlock removed.
3. Function exynos5410_clk_init defined as static.
   Struct exynos5410_fixed_rate_ext_clks defined as static.
   Struct exynos5410_mux_clks defined as static.
   Struct exynos5410_div_clks defined as static.
   Struct exynos5410_gate_clks defined as static.
4. Removed aliases.
5. Pll's magic register offsets defined as preprocessor macros.
6. Redundant check of device_node pointer removed.
	
	In arch/arm/boot/dts/exynos5410.dtsi
1. dwmmcX nodes renamed to mmc.
   dwmmc_X renamed to mmc_X.
   dwmmc status="disabled" field added.
   fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts
2. Blank lines added where necessary.
3. cpu@ suffixes corrected.
4. edcs node removed.
5. Hexadecimal characters case corrected.
6. Clock IDs replaced with preprocessor macros.
	
	In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. status = "okay" field added to mmc nodes.
	
	In arch/arm/mach-exynos/edcs.c
1. "kfs_" prefix replaced with "edcs_"
2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values.
3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c
4. mcpm_sync_init() call added.
5. power management functions reworked.
	
	Other
1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected.
2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and
   ARM_CCI in arch/arm/mach-exynos/Kconfig.
3. edcs_status driver removed.


Tarek Dakhran (4):
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  clk: exynos5410: register clocks using common clock framework
  ARM: EXYNOS: add Exynos Dual Cluster Support
  ARM: dts: Add initial device tree support for EXYNOS5410

 .../devicetree/bindings/clock/exynos5410-clock.txt |  37 +++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts          |  65 +++++
 arch/arm/boot/dts/exynos5410.dtsi                  | 209 ++++++++++++++++
 arch/arm/mach-exynos/Kconfig                       |  12 +
 arch/arm/mach-exynos/Makefile                      |   2 +
 arch/arm/mach-exynos/common.c                      |  18 ++
 arch/arm/mach-exynos/edcs.c                        | 278 +++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |   1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |   1 +
 arch/arm/plat-samsung/include/plat/cpu.h           |   8 +
 drivers/clk/samsung/Makefile                       |   1 +
 drivers/clk/samsung/clk-exynos5410.c               | 239 ++++++++++++++++++
 include/dt-bindings/clock/exynos5410.h             | 175 +++++++++++++
 14 files changed, 1047 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
 create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
 create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
 create mode 100644 arch/arm/mach-exynos/edcs.c
 create mode 100644 drivers/clk/samsung/clk-exynos5410.c
 create mode 100644 include/dt-bindings/clock/exynos5410.h

-- 
1.8.1.5

[PATCH v3 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Vyacheslav Tyrtov]

From: Tarek Dakhran <t.dakhran@samsung.com>

EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.

Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
 arch/arm/mach-exynos/Kconfig             | 12 ++++++++++++
 arch/arm/mach-exynos/common.c            | 18 ++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h  |  1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c   |  1 +
 arch/arm/plat-samsung/include/plat/cpu.h |  8 ++++++++
 5 files changed, 40 insertions(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..9ea1799 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,18 @@ config SOC_EXYNOS5250
 	help
 	  Enable EXYNOS5250 SoC support
 
+config SOC_EXYNOS5410
+	bool "SAMSUNG EXYNOS5410"
+	default y
+	depends on ARCH_EXYNOS5
+	select MCPM
+	select ARM_CCI
+	select PM_GENERIC_DOMAINS if PM
+	select S5P_PM if PM
+	select S5P_SLEEP if PM
+	help
+	  Enable EXYNOS5410 SoC support
+
 config SOC_EXYNOS5420
 	bool "SAMSUNG EXYNOS5420"
 	default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
 static const char name_exynos5420[] = "EXYNOS5420";
 static const char name_exynos5440[] = "EXYNOS5440";
 
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init		= exynos_init,
 		.name		= name_exynos5250,
 	}, {
+		.idcode		= EXYNOS5410_SOC_ID,
+		.idmask		= EXYNOS5_SOC_MASK,
+		.map_io		= exynos5_map_io,
+		.init		= exynos_init,
+		.name		= name_exynos5410,
+	}, {
 		.idcode		= EXYNOS5420_SOC_ID,
 		.idmask		= EXYNOS5_SOC_MASK,
 		.map_io		= exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
 	},
 };
 
+static struct map_desc exynos5410_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
+		.pfn		= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
 static struct map_desc exynos5250_iodesc[] __initdata = {
 	{
 		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
 
 	if (soc_is_exynos5250())
 		iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+	if (soc_is_exynos5410())
+		iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
 }
 
 void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
 #define EXYNOS4210_PA_SYSRAM_NS		0x0203F000
 #define EXYNOS4x12_PA_SYSRAM_NS		0x0204F000
 #define EXYNOS5250_PA_SYSRAM_NS		0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS		0x02073000
 
 #define EXYNOS_PA_CHIPID		0x10000000
 
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
 
 static char const *exynos5_dt_compat[] __initdata = {
 	"samsung,exynos5250",
+	"samsung,exynos5410",
 	"samsung,exynos5420",
 	"samsung,exynos5440",
 	NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4_CPU_MASK	0xFFFE0000
 
 #define EXYNOS5250_SOC_ID	0x43520000
+#define EXYNOS5410_SOC_ID	0xE5410023
 #define EXYNOS5420_SOC_ID	0xE5420000
 #define EXYNOS5440_SOC_ID	0xE5440000
 #define EXYNOS5_SOC_MASK	0xFFFFF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 
@@ -144,6 +146,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5250()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410()	is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410()	0
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5420)
 # define soc_is_exynos5420()	is_samsung_exynos5420()
 #else
-- 
1.8.1.5

[PATCH v3 2/4] clk: exynos5410: register clocks using common clock framework

[Vyacheslav Tyrtov]

From: Tarek Dakhran <t.dakhran@samsung.com>

The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.

Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
 .../devicetree/bindings/clock/exynos5410-clock.txt |  37 ++++
 drivers/clk/samsung/Makefile                       |   1 +
 drivers/clk/samsung/clk-exynos5410.c               | 239 +++++++++++++++++++++
 include/dt-bindings/clock/exynos5410.h             | 175 +++++++++++++++
 4 files changed, 452 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
 create mode 100644 drivers/clk/samsung/clk-exynos5410.c
 create mode 100644 include/dt-bindings/clock/exynos5410.h

diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 0000000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+	clock: clock-controller@0x10010000 {
+		compatible = "samsung,exynos5410-clock";
+		reg = <0x10010000 0x30000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the clock
+	   controller. Refer to the standard clock bindings for information
+	   about 'clocks' and 'clock-names' property.
+
+	serial@12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410)	+= clk-exynos5410.o
 obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 0000000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5410.h>
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+#define APLL_LOCK               0x0
+#define APLL_CON0               0x100
+#define CPLL_LOCK               0x10020
+#define CPLL_CON0               0x10120
+#define MPLL_LOCK               0x4000
+#define MPLL_CON0               0x4100
+#define BPLL_LOCK               0x20010
+#define BPLL_CON0               0x20110
+#define KPLL_LOCK               0x28000
+#define KPLL_CON0               0x28100
+
+#define SRC_CPU			0x200
+#define DIV_CPU0		0x500
+#define SRC_CPERI1		0x4204
+#define DIV_TOP0		0x10510
+#define DIV_TOP1		0x10514
+#define DIV_FSYS1		0x1054c
+#define DIV_FSYS2		0x10550
+#define DIV_PERIC0		0x10558
+#define SRC_TOP0		0x10210
+#define SRC_TOP1		0x10214
+#define SRC_TOP2		0x10218
+#define SRC_FSYS		0x10244
+#define SRC_PERIC0		0x10250
+#define SRC_MASK_FSYS		0x10340
+#define SRC_MASK_PERIC0		0x10350
+#define GATE_BUS_FSYS0		0x10740
+#define GATE_IP_FSYS		0x10944
+#define GATE_IP_PERIC		0x10950
+#define GATE_IP_PERIS		0x10960
+#define SRC_CDREX		0x20200
+#define SRC_KFC			0x28200
+#define DIV_KFC0		0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+	apll, cpll, mpll,
+	bpll, kpll,
+	nr_plls                 /* number of PLLs */
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long exynos5410_clk_regs[] __initdata = {
+	SRC_CPU,
+	DIV_CPU0,
+	SRC_CPERI1,
+	DIV_TOP0,
+	DIV_TOP1,
+	DIV_FSYS1,
+	DIV_FSYS2,
+	DIV_PERIC0,
+	SRC_TOP0,
+	SRC_TOP1,
+	SRC_TOP2,
+	SRC_FSYS,
+	SRC_PERIC0,
+	SRC_MASK_FSYS,
+	SRC_MASK_PERIC0,
+	GATE_BUS_FSYS0,
+	GATE_IP_FSYS,
+	GATE_IP_PERIC,
+	GATE_IP_PERIS,
+	SRC_CDREX,
+	SRC_KFC,
+	DIV_KFC0,
+};
+
+/* list of all parent clocks */
+PNAME(apll_p)		= { "fin_pll", "fout_apll", };
+PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
+PNAME(cpll_p)		= { "fin_pll", "fout_cpll" };
+PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
+PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
+
+PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };
+PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
+
+PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
+PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
+PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+
+PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
+			"none", "none", "sclk_mpll_bpll",
+			 "none", "none", "sclk_cpll" };
+
+static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
+	MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
+	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+
+	MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
+	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+
+	MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
+	MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
+
+	MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+	MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
+
+	MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
+
+	MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
+
+	MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
+	MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
+	MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+
+	MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
+	MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
+	MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+
+	MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
+	MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
+};
+
+static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
+	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+	DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
+
+	DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
+	DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
+	DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
+	DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
+
+	DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
+	DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
+	DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
+
+	DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
+	DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+
+	DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+	DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+	DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
+	DIV_F(0, "div_mmc_pre0", "div_mmc0",
+			DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+	DIV_F(0, "div_mmc_pre1", "div_mmc1",
+			DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+	DIV_F(0, "div_mmc_pre2", "div_mmc2",
+			DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+
+	DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+	DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+	DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+	DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+
+	DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+	DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
+};
+
+static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
+	GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+
+	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
+			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
+			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
+			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
+	GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
+	GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
+
+	GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+	GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+	GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+
+	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+		APLL_CON0, NULL),
+	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+		CPLL_CON0, NULL),
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+		MPLL_CON0, NULL),
+	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+		BPLL_CON0, NULL),
+	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+		KPLL_CON0, NULL),
+};
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+	void __iomem *reg_base;
+
+	reg_base = of_iomap(np, 0);
+	if (!reg_base)
+		panic("%s: failed to map registers\n", __func__);
+
+	samsung_clk_init(np, reg_base, CLK_NR_CLKS,
+			exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
+			NULL, 0);
+
+	samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
+					reg_base);
+
+	samsung_clk_register_mux(exynos5410_mux_clks,
+			ARRAY_SIZE(exynos5410_mux_clks));
+	samsung_clk_register_div(exynos5410_div_clks,
+			ARRAY_SIZE(exynos5410_div_clks));
+	samsung_clk_register_gate(exynos5410_gate_clks,
+			ARRAY_SIZE(exynos5410_gate_clks));
+
+	pr_debug("Exynos5410: clock setup completed.\n");
+}
+CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 0000000..9b4a58b
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,175 @@
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL 1
+#define CLK_FOUT_APLL 2
+#define CLK_FOUT_CPLL 3
+#define CLK_FOUT_DPLL 4
+#define CLK_FOUT_EPLL 5
+#define CLK_FOUT_RPLL 6
+#define CLK_FOUT_IPLL 7
+#define CLK_FOUT_SPLL 8
+#define CLK_FOUT_VPLL 9
+#define CLK_FOUT_MPLL 10
+#define CLK_FOUT_BPLL 11
+#define CLK_FOUT_KPLL 12
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+#define CLK_SCLK_SPI0 135
+#define CLK_SCLK_SPI1 136
+#define CLK_SCLK_SPI2 137
+#define CLK_SCLK_I2S1 138
+#define CLK_SCLK_I2S2 139
+#define CLK_SCLK_PCM1 140
+#define CLK_SCLK_PCM2 141
+#define CLK_SCLK_SPDIF 142
+#define CLK_SCLK_HDMI 143
+#define CLK_SCLK_PIXEL 144
+#define CLK_SCLK_DP1 145
+#define CLK_SCLK_MIPI1 146
+#define CLK_SCLK_FIMD1 147
+#define CLK_SCLK_MAUDIO0 148
+#define CLK_SCLK_MAUPCM0 149
+#define CLK_SCLK_USBD300 150
+#define CLK_SCLK_USBD301 151
+#define CLK_SCLK_USBPHY300 152
+#define CLK_SCLK_USBPHY301 153
+#define CLK_SCLK_UNIPRO 154
+#define CLK_SCLK_PWM 155
+#define CLK_SCLK_GSCL_WA 156
+#define CLK_SCLK_GSCL_WB 157
+#define CLK_SCLK_HDMIPHY 158
+
+/* gate clocks */
+#define CLK_ACLK66_PERIC 256
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_I2C0 261
+#define CLK_I2C1 262
+#define CLK_I2C2 263
+#define CLK_I2C3 264
+#define CLK_I2C4 265
+#define CLK_I2C5 266
+#define CLK_I2C6 267
+#define CLK_I2C7 268
+#define CLK_I2C_HDMI 269
+#define CLK_TSADC 270
+#define CLK_SPI0 271
+#define CLK_SPI1 272
+#define CLK_SPI2 273
+#define CLK_KEYIF 274
+#define CLK_I2S1 275
+#define CLK_I2S2 276
+#define CLK_PCM1 277
+#define CLK_PCM2 278
+#define CLK_PWM 279
+#define CLK_SPDIF 280
+#define CLK_I2C8 281
+#define CLK_I2C9 282
+#define CLK_I2C10 283
+#define CLK_ACLK66_PSGEN 300
+#define CLK_CHIPID 301
+#define CLK_SYSREG 302
+#define CLK_TZPC0 303
+#define CLK_TZPC1 304
+#define CLK_TZPC2 305
+#define CLK_TZPC3 306
+#define CLK_TZPC4 307
+#define CLK_TZPC5 308
+#define CLK_TZPC6 309
+#define CLK_TZPC7 310
+#define CLK_TZPC8 311
+#define CLK_TZPC9 312
+#define CLK_HDMI_CEC 313
+#define CLK_SECKEY 314
+#define CLK_MCT 315
+#define CLK_WDT 316
+#define CLK_RTC 317
+#define CLK_TMU 318
+#define CLK_TMU_GPU 319
+#define CLK_PCLK66_GPIO 330
+#define CLK_ACLK200_FSYS2 350
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+#define CLK_SROMC 354
+#define CLK_UFS 355
+#define CLK_ACLK200_FSYS 360
+#define CLK_TSI 361
+#define CLK_PDMA0 362
+#define CLK_PDMA1 363
+#define CLK_RTIC 364
+#define CLK_USBH20 365
+#define CLK_USBD300 366
+#define CLK_USBD301 367
+#define CLK_ACLK400_MSCL 380
+#define CLK_MSCL0 381
+#define CLK_MSCL1 382
+#define CLK_MSCL2 383
+#define CLK_SMMU_MSCL0 384
+#define CLK_SMMU_MSCL1 385
+#define CLK_SMMU_MSCL2 386
+#define CLK_ACLK333 400
+#define CLK_MFC 401
+#define CLK_SMMU_MFCL 402
+#define CLK_SMMU_MFCR 403
+#define CLK_ACLK200_DISP1 410
+#define CLK_DSIM1 411
+#define CLK_DP1 412
+#define CLK_HDMI 413
+#define CLK_ACLK300_DISP1 420
+#define CLK_FIMD1 421
+#define CLK_SMMU_FIMD1 422
+#define CLK_ACLK166 430
+#define CLK_MIXER 431
+#define CLK_ACLK266 440
+#define CLK_ROTATOR 441
+#define CLK_MDMA1 442
+#define CLK_SMMU_ROTATOR 443
+#define CLK_SMMU_MDMA1 444
+#define CLK_ACLK300_JPEG 450
+#define CLK_JPEG 451
+#define CLK_JPEG2 452
+#define CLK_SMMU_JPEG 453
+#define CLK_ACLK300_GSCL 460
+#define CLK_SMMU_GSCL0 461
+#define CLK_SMMU_GSCL1 462
+#define CLK_GSCL_WA 463
+#define CLK_GSCL_WB 464
+#define CLK_GSCL0 465
+#define CLK_GSCL1 466
+#define CLK_CLK_3AA 467
+#define CLK_ACLK266_G2D 470
+#define CLK_SSS 471
+#define CLK_SLIM_SSS 472
+#define CLK_MDMA0 473
+#define CLK_ACLK333_G2D 480
+#define CLK_G2D 481
+#define CLK_ACLK333_432_GSCL 490
+#define CLK_SMMU_3AA 491
+#define CLK_SMMU_FIMCL0 492
+#define CLK_SMMU_FIMCL1 493
+#define CLK_SMMU_FIMCL3 494
+#define CLK_FIMC_LITE3 495
+#define CLK_ACLK_G3D 500
+#define CLK_G3D 501
+#define CLK_SMMU_MIXER 502
+
+/* mux clocks */
+#define CLK_MOUT_HDMI 640
+
+/* divider clocks */
+#define CLK_DOUT_PIXEL 768
+#define CLK_NR_CLKS 769
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
-- 
1.8.1.5

[PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support

[Vyacheslav Tyrtov]

From: Tarek Dakhran <t.dakhran@samsung.com>

Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.

Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
 arch/arm/mach-exynos/Makefile |   2 +
 arch/arm/mach-exynos/edcs.c   | 278 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 280 insertions(+)
 create mode 100644 arch/arm/mach-exynos/edcs.c

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
 obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410)		+= edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 0000000..980bfdd
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,278 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/irqchip/arm-gic.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+#include <linux/arm-cci.h>
+#include <mach/regs-pmu.h>
+
+#define EDCS_CPUS_PER_CLUSTER	4
+#define EDCS_CLUSTERS		2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr)	(S5P_ARM_CORE0_CONFIGURATION	\
+						+ ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr)		(EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr)		(EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0		(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)		(REG_CPU_STATE_ADDR0 +	\
+						 (_nr) * EDCS_CPUS_PER_CLUSTER)
+
+#define SECONDARY_RESET		(1 << 1)
+#define REG_ENTRY_ADDR		(S5P_VA_SYSRAM_NS + 0x1c)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+				bool enable)
+{
+	unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
+	int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+	if ((readl_relaxed(EDCS_CORE_STATUS(offset)) & 0x3) != value) {
+		wmb();
+		writel_relaxed(value, EDCS_CORE_CONFIGURATION(offset));
+	}
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+	exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+	exynos_core_power_control(cpu, cluster, false);
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+	writel_relaxed(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+	local_irq_disable();
+	arch_spin_lock(&edcs_lock);
+
+	edcs_use_count[cpu][cluster]++;
+	if (edcs_use_count[cpu][cluster] == 1) {
+		++core_count[cluster];
+		set_boot_flag(cpu, SECONDARY_RESET);
+		exynos_core_power_up(cpu, cluster);
+	} else if (edcs_use_count[cpu][cluster] != 2) {
+		/*
+		 * The only possible values are:
+		 * 0 = CPU down
+		 * 1 = CPU (still) up
+		 * 2 = CPU requested to be up before it had a chance
+		 *     to actually make itself down.
+		 * Any other value is a bug.
+		 */
+		BUG();
+	}
+
+	arch_spin_unlock(&edcs_lock);
+	local_irq_enable();
+
+	return 0;
+}
+static void exynos_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool last_man = false, skip_wfi = false;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	pr_debug("%s: CORE%d on CLUSTER %d\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER  || cluster >= EDCS_CLUSTERS);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	arch_spin_lock(&edcs_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	edcs_use_count[cpu][cluster]--;
+	if (edcs_use_count[cpu][cluster] == 0) {
+		--core_count[cluster];
+		if (core_count[cluster] == 0)
+			last_man = true;
+	} else if (edcs_use_count[cpu][cluster] == 1) {
+		/*
+		 * A power_up request went ahead of us.
+		 * Even if we do not want to shut this CPU down,
+		 * the caller expects a certain state as if the WFI
+		 * was aborted.  So let's continue with cache cleaning.
+		 */
+		skip_wfi = true;
+	} else
+		BUG();
+
+	if (!skip_wfi)
+		gic_cpu_if_down();
+
+	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+		arch_spin_unlock(&edcs_lock);
+
+		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+			/*
+			 * On the Cortex-A15 we need to disable
+			 * L2 prefetching before flushing the cache.
+			 */
+			asm volatile(
+			"mcr	p15, 1, %0, c15, c0, 3\n\t"
+			"isb\n\t"
+			"dsb"
+			: : "r" (0x400));
+		}
+
+		/*
+		 * We need to disable and flush the whole (L1 and L2) cache.
+		 * Let's do it in the safest possible way i.e. with
+		 * no memory access within the following sequence
+		 * including the stack.
+		 *
+		 * Note: fp is preserved to the stack explicitly prior doing
+		 * this since adding it to the clobber list is incompatible
+		 * with having CONFIG_FRAME_POINTER=y.
+		 */
+		asm volatile(
+		"str	fp, [sp, #-4]!\n\t"
+		"mrc	p15, 0, r0, c1, c0, 0	@ get CR\n\t"
+		"bic	r0, r0, #"__stringify(CR_C)"\n\t"
+		"mcr	p15, 0, r0, c1, c0, 0	@ set CR\n\t"
+		"isb\n\t"
+		"bl	v7_flush_dcache_all\n\t"
+		"clrex\n\t"
+		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR\n\t"
+		"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t"
+		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR\n\t"
+		"isb\n\t"
+		"dsb\n\t"
+		"ldr	fp, [sp], #4"
+		: : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+			"r9", "r10", "lr", "memory");
+
+		cci_disable_port_by_cpu(mpidr);
+
+		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+
+	} else {
+		arch_spin_unlock(&edcs_lock);
+		/*
+			* We need to disable and flush only the L1 cache.
+			* Let's do it in the safest possible way as above.
+		*/
+		asm volatile(
+		"str	fp, [sp, #-4]!\n\t"
+		"mrc	p15, 0, r0, c1, c0, 0	@ get CR\n\t"
+		"bic	r0, r0, #"__stringify(CR_C)"\n\t"
+		"mcr	p15, 0, r0, c1, c0, 0	@ set CR\n\t"
+		"isb\n\t"
+		"bl	v7_flush_dcache_louis\n\t"
+		"clrex\n\t"
+		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR\n\t"
+		"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t"
+		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR\n\t"
+		"isb\n\t"
+		"dsb\n\t"
+		"ldr	fp, [sp], #4"
+		: : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+		      "r9", "r10", "lr", "memory");
+
+	}
+	__mcpm_cpu_down(cpu, cluster);
+
+	if (!skip_wfi) {
+		exynos_core_power_down(cpu, cluster);
+		wfi();
+	}
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+	.power_up	= exynos_power_up,
+	.power_down	= exynos_power_down,
+};
+
+static void __init edcs_data_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER  || cluster >= EDCS_CLUSTERS);
+	edcs_use_count[cpu][cluster] = 1;
+	++core_count[cluster];
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked edcs_power_up_setup(unsigned int affinity_level)
+{
+	asm volatile ("\n"
+	"b	cci_enable_port_for_self");
+}
+
+static int __init edcs_init(void)
+{
+	int ret;
+	struct device_node *node;
+
+	node = of_find_compatible_node(NULL, NULL, "samsung,exynos5410");
+	if (!node)
+		return -ENODEV;
+
+	if (!cci_probed())
+		return -ENODEV;
+
+	/*
+	 * Future entries into the kernel can now go
+	 * through the cluster entry vectors.
+	 */
+	writel_relaxed(virt_to_phys(mcpm_entry_point), REG_ENTRY_ADDR);
+
+	edcs_data_init();
+	mcpm_smp_set_ops();
+
+	ret = mcpm_platform_register(&exynos_power_ops);
+	if (!ret) {
+		mcpm_sync_init(edcs_power_up_setup);
+		pr_info("EDCS power management initialized\n");
+	}
+	return ret;
+}
+
+early_initcall(edcs_init);
-- 
1.8.1.5

[PATCH v3 4/4] ARM: dts: Add initial device tree support for EXYNOS5410

[Vyacheslav Tyrtov]

From: Tarek Dakhran <t.dakhran@samsung.com>

Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.

Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
 arch/arm/boot/dts/Makefile                |   1 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts |  65 ++++++++++
 arch/arm/boot/dts/exynos5410.dtsi         | 209 ++++++++++++++++++++++++++++++
 3 files changed, 275 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
 create mode 100644 arch/arm/boot/dts/exynos5410.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e991739 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos5250-arndale.dtb \
 	exynos5250-smdk5250.dtb \
 	exynos5250-snow.dtb \
+	exynos5410-smdk5410.dtb \
 	exynos5420-smdk5420.dtb \
 	exynos5440-sd5v1.dtb \
 	exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 0000000..06ae479
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+	model = "Samsung SMDK5410 board based on EXYNOS5410";
+	compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttySAC2,115200";
+	};
+
+	oscclk: oscclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "fin_pll";
+	};
+
+	mmc@12200000 {
+		status = "okay";
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-ciu-div = <3>;
+		samsung,dw-mshc-sdr-timing = <2 3>;
+		samsung,dw-mshc-ddr-timing = <1 2>;
+
+		slot@0 {
+			reg = <0>;
+			bus-width = <8>;
+		};
+	};
+
+	mmc@12220000 {
+		status = "okay";
+		num-slots = <1>;
+		supports-highspeed;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-ciu-div = <3>;
+		samsung,dw-mshc-sdr-timing = <2 3>;
+		samsung,dw-mshc-ddr-timing = <1 2>;
+
+		slot@0 {
+			reg = <0>;
+			bus-width = <4>;
+			disable-wp;
+		};
+	};
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 0000000..9921b66
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/exynos5410.h>
+#include "exynos5.dtsi"
+/ {
+	compatible = "samsung,exynos5410";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+			cci-control-port = <&cci_control2>;
+			clock-frequency = <1600000000>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+			cci-control-port = <&cci_control2>;
+			clock-frequency = <1600000000>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+			cci-control-port = <&cci_control2>;
+			clock-frequency = <1600000000>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+			cci-control-port = <&cci_control2>;
+			clock-frequency = <1600000000>;
+		};
+
+		CPU4: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+			cci-control-port = <&cci_control1>;
+			clock-frequency = <1200000000>;
+		};
+
+		CPU5: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+			cci-control-port = <&cci_control1>;
+			clock-frequency = <1200000000>;
+		};
+
+		CPU6: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+			cci-control-port = <&cci_control1>;
+			clock-frequency = <1200000000>;
+		};
+
+		CPU7: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x103>;
+			cci-control-port = <&cci_control1>;
+			clock-frequency = <1200000000>;
+		};
+	};
+
+	cci@10D20000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x10D20000 0x1000>;
+		ranges = <0 0x10D20000 0x6000>;
+
+		cci_control0: slave-if@1000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace-lite";
+			reg = <0x1000 0x1000>;
+		};
+
+		cci_control1: slave-if@4000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x4000 0x1000>;
+		};
+
+		cci_control2: slave-if@5000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x5000 0x1000>;
+		};
+	};
+
+	clock: clock-controller@10010000 {
+		compatible = "samsung,exynos5410-clock";
+		reg = <0x10010000 0x30000>;
+		#clock-cells = <1>;
+	};
+
+	mct@101C0000 {
+		compatible = "samsung,exynos4210-mct";
+		reg = <0x101C0000 0xB00>;
+		interrupt-controller;
+		#interrups-cells = <1>;
+		interrupt-parent = <&mct_map>;
+		interrupts = <0>, <1>, <2>, <3>,
+			<4>, <5>, <6>, <7>,
+			<8>, <9>, <10>, <11>;
+		clocks = <&oscclk>, <&clock CLK_MCT>;
+		clock-names = "fin_pll", "mct";
+
+		mct_map: mct-map {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-map = <0 &combiner 23 3>,
+					<1 &combiner 23 4>,
+					<2 &combiner 25 2>,
+					<3 &combiner 25 3>,
+					<4 &gic 0 120 0>,
+					<5 &gic 0 121 0>,
+					<6 &gic 0 122 0>,
+					<7 &gic 0 123 0>,
+					<8 &gic 0 128 0>,
+					<9 &gic 0 129 0>,
+					<10 &gic 0 130 0>,
+					<11 &gic 0 131 0>;
+		};
+	};
+
+	mmc_0: mmc@12200000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		interrupts = <0 75 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x12200000 0x1000>;
+		clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		status = "disabled";
+	};
+
+	mmc_1: mmc@12210000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		interrupts = <0 76 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x12210000 0x1000>;
+		clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		status = "disabled";
+	};
+
+	mmc_2: mmc@12220000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		interrupts = <0 77 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x12220000 0x1000>;
+		clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		status = "disabled";
+	};
+
+	serial@12C00000 {
+		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
+
+	serial@12C10000 {
+		clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
+
+	serial@12C20000 {
+		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
+
+	serial@12C30000 {
+		clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
+
+};
-- 
1.8.1.5

Re: [PATCH v3 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tomasz Figa]

Hi,

On Thursday 07 of November 2013 12:12:46 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
> 
> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> Add initial support for this SoC.

In general the patch looks pretty good, however there are several things
that I overlooked when reviewing previous revision. I have pointed them
inline.

> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig             | 12 ++++++++++++
>  arch/arm/mach-exynos/common.c            | 18 ++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/map.h  |  1 +
>  arch/arm/mach-exynos/mach-exynos5-dt.c   |  1 +
>  arch/arm/plat-samsung/include/plat/cpu.h |  8 ++++++++
>  5 files changed, 40 insertions(+)
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 56fe819..9ea1799 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -84,6 +84,18 @@ config SOC_EXYNOS5250
>  	help
>  	  Enable EXYNOS5250 SoC support
>  
> +config SOC_EXYNOS5410
> +	bool "SAMSUNG EXYNOS5410"
> +	default y
> +	depends on ARCH_EXYNOS5
> +	select MCPM

Please keep the selects sorted alphabetically.

> +	select ARM_CCI
> +	select PM_GENERIC_DOMAINS if PM

Should be if PM_RUNTIME.

> +	select S5P_PM if PM
> +	select S5P_SLEEP if PM

Both should be if PM_SLEEP.

> +	help
> +	  Enable EXYNOS5410 SoC support
> +
>  config SOC_EXYNOS5420
>  	bool "SAMSUNG EXYNOS5420"
>  	default y
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index ba95e5d..187c0a4 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
>  static const char name_exynos4212[] = "EXYNOS4212";
>  static const char name_exynos4412[] = "EXYNOS4412";
>  static const char name_exynos5250[] = "EXYNOS5250";
> +static const char name_exynos5410[] = "EXYNOS5410";
>  static const char name_exynos5420[] = "EXYNOS5420";
>  static const char name_exynos5440[] = "EXYNOS5440";
>  
> @@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
>  		.init		= exynos_init,
>  		.name		= name_exynos5250,
>  	}, {
> +		.idcode		= EXYNOS5410_SOC_ID,
> +		.idmask		= EXYNOS5_SOC_MASK,
> +		.map_io		= exynos5_map_io,
> +		.init		= exynos_init,
> +		.name		= name_exynos5410,
> +	}, {
>  		.idcode		= EXYNOS5420_SOC_ID,
>  		.idmask		= EXYNOS5_SOC_MASK,
>  		.map_io		= exynos5_map_io,
> @@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
>  	},
>  };
>  
> +static struct map_desc exynos5410_iodesc[] __initdata = {
> +	{
> +		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
> +		.pfn		= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	},
> +};
> +
>  static struct map_desc exynos5250_iodesc[] __initdata = {
>  	{
>  		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
> @@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
>  
>  	if (soc_is_exynos5250())
>  		iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
> +	if (soc_is_exynos5410())
> +		iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
>  }
>  
>  void __init exynos_init_time(void)
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 7b046b5..894f431 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -29,6 +29,7 @@
>  #define EXYNOS4210_PA_SYSRAM_NS		0x0203F000
>  #define EXYNOS4x12_PA_SYSRAM_NS		0x0204F000
>  #define EXYNOS5250_PA_SYSRAM_NS		0x0204F000
> +#define EXYNOS5410_PA_SYSRAM_NS		0x02073000
>  
>  #define EXYNOS_PA_CHIPID		0x10000000
>  
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index f874b77..9515186 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
>  
>  static char const *exynos5_dt_compat[] __initdata = {
>  	"samsung,exynos5250",
> +	"samsung,exynos5410",
>  	"samsung,exynos5420",
>  	"samsung,exynos5440",
>  	NULL
> diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
> index 4fb1f03..aad7c40 100644
> --- a/arch/arm/plat-samsung/include/plat/cpu.h
> +++ b/arch/arm/plat-samsung/include/plat/cpu.h
> @@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
>  #define EXYNOS4_CPU_MASK	0xFFFE0000
>  
>  #define EXYNOS5250_SOC_ID	0x43520000
> +#define EXYNOS5410_SOC_ID	0xE5410023

Please mask out the revision bits, so they don't confuse potential readers
of this code.

Best regards,
Tomasz

Re: [PATCH v3 2/4] clk: exynos5410: register clocks using common clock framework

[Tomasz Figa]

Hi,

On Thursday 07 of November 2013 12:12:47 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
> 
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.

Thanks for keeping up with addressing the comments. However there are
still few things that need to be corrected. Please see my comments inline.

> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  .../devicetree/bindings/clock/exynos5410-clock.txt |  37 ++++
>  drivers/clk/samsung/Makefile                       |   1 +
>  drivers/clk/samsung/clk-exynos5410.c               | 239 +++++++++++++++++++++
>  include/dt-bindings/clock/exynos5410.h             | 175 +++++++++++++++
>  4 files changed, 452 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>  create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>  create mode 100644 include/dt-bindings/clock/exynos5410.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> new file mode 100644
> index 0000000..a462da231
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> @@ -0,0 +1,37 @@
> +* Samsung Exynos5410 Clock Controller
> +
> +The Exynos5410 clock controller generates and supplies clock to various
> +controllers within the Exynos5410 SoC.
> +
> +Required Properties:
> +
> +- compatible: should be "samsung,exynos5410-clock"
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #clock-cells: should be 1.

If there are any external clocks that need to be provided (and I believe
there are), you should mention them in the documentation.

Also, to make this more future-proof, I would add clock-names and clocks
properties to the binding, listing all those external clocks. It's just
about the binding definition - you don't have to implement this in the
driver yet, as we don't have the framework to handle this at early system
initialization. However, when we finally implement this in the Common
Clock Framework, we will not have to change existing DT bindings.

> +
> +All available clocks are defined as preprocessor macros in
> +dt-bindings/clock/exynos5410.h header and can be used in device
> +tree sources.
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> +	clock: clock-controller@0x10010000 {
> +		compatible = "samsung,exynos5410-clock";
> +		reg = <0x10010000 0x30000>;
> +		#clock-cells = <1>;
> +	};
> +
> +Example 2: UART controller node that consumes the clock generated by the clock
> +	   controller. Refer to the standard clock bindings for information
> +	   about 'clocks' and 'clock-names' property.
> +
> +	serial@12C20000 {
> +		compatible = "samsung,exynos4210-uart";
> +		reg = <0x12C00000 0x100>;
> +		interrupts = <0 51 0>;
> +		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
> +		clock-names = "uart", "clk_uart_baud0";
> +	};
[snip]
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
> new file mode 100644
> index 0000000..9b4a58b
> --- /dev/null
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -0,0 +1,175 @@
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
> +#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
> +
> +/* core clocks */
> +#define CLK_FIN_PLL 1

This is external clock, not provided by this clock controller, isn't it?

> +#define CLK_FOUT_APLL 2
> +#define CLK_FOUT_CPLL 3
> +#define CLK_FOUT_DPLL 4
> +#define CLK_FOUT_EPLL 5
[snip]
> +#define CLK_ACLK_G3D 500
> +#define CLK_G3D 501
> +#define CLK_SMMU_MIXER 502
> +
> +/* mux clocks */
> +#define CLK_MOUT_HDMI 640

This definition does not seem to be used anywhere in the driver itself.

> +
> +/* divider clocks */
> +#define CLK_DOUT_PIXEL 768

Ditto.

Please don't define IDs for clocks that are not yet provided by the
driver.

Best regards,
Tomasz

Re: [PATCH v3 4/4] ARM: dts: Add initial device tree support for EXYNOS5410

[Tomasz Figa]

Hi,

Please see my comments inline.

On Thursday 07 of November 2013 12:12:49 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
> 
> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
> 
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  arch/arm/boot/dts/Makefile                |   1 +
>  arch/arm/boot/dts/exynos5410-smdk5410.dts |  65 ++++++++++
>  arch/arm/boot/dts/exynos5410.dtsi         | 209 ++++++++++++++++++++++++++++++
>  3 files changed, 275 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
>  create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
[snip]
> diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
> new file mode 100644
> index 0000000..06ae479
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
> @@ -0,0 +1,65 @@
> +/*
> + * SAMSUNG SMDK5410 board device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +#include "exynos5410.dtsi"
> +/ {
> +	model = "Samsung SMDK5410 board based on EXYNOS5410";
> +	compatible = "samsung,smdk5410", "samsung,exynos5410";
> +
> +	memory {
> +		reg = <0x40000000 0x80000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttySAC2,115200";
> +	};
> +
> +	oscclk: oscclk {

coding style: According to ePAPR recommendation, node name should
represent hardware type, not particular instance of hardware.

So instead, the preferred way would be to specify the clock using
following layout:

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		oscclk: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "fin_pll";
		};
	};

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <24000000>;
> +		clock-output-names = "fin_pll";
> +	};
[snip]
> +
> +};
> diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
> new file mode 100644
> index 0000000..9921b66
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5410.dtsi
> @@ -0,0 +1,209 @@
> +/*
> + * SAMSUNG EXYNOS5410 SoC device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
> + * EXYNOS5410 based board files can include this file and provide
> + * values for board specfic bindings.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/clock/exynos5410.h>
> +#include "exynos5.dtsi"
> +/ {
[snip]
> +	clock: clock-controller@10010000 {
> +		compatible = "samsung,exynos5410-clock";
> +		reg = <0x10010000 0x30000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	mct@101C0000 {

A generic name would be: timer@101C0000

> +		compatible = "samsung,exynos4210-mct";
> +		reg = <0x101C0000 0xB00>;
> +		interrupt-controller;
> +		#interrups-cells = <1>;

MCT is not an interrupt controller, so both interrupt-controller and
#interrupt-cells properties are incorrect. I guess that's due to the
broken example in the documentation, that I already posted patches to fix.

> +		interrupt-parent = <&mct_map>;
> +		interrupts = <0>, <1>, <2>, <3>,
> +			<4>, <5>, <6>, <7>,
> +			<8>, <9>, <10>, <11>;
> +		clocks = <&oscclk>, <&clock CLK_MCT>;
> +		clock-names = "fin_pll", "mct";
> +
> +		mct_map: mct-map {

Again, interrupt-map would be a better name for this node.

> +			#interrupt-cells = <1>;
> +			#address-cells = <0>;
> +			#size-cells = <0>;
> +			interrupt-map = <0 &combiner 23 3>,
> +					<1 &combiner 23 4>,
> +					<2 &combiner 25 2>,
> +					<3 &combiner 25 3>,
> +					<4 &gic 0 120 0>,
> +					<5 &gic 0 121 0>,
> +					<6 &gic 0 122 0>,
> +					<7 &gic 0 123 0>,
> +					<8 &gic 0 128 0>,
> +					<9 &gic 0 129 0>,
> +					<10 &gic 0 130 0>,
> +					<11 &gic 0 131 0>;
> +		};
> +	};

Otherwise, the patch looks good.

Best regards,
Tomasz

Re: [PATCH v3 4/4] ARM: dts: Add initial device tree support for EXYNOS5410

[Tarek Dakhran]

Hi,

On 10.11.2013 22:02, Tomasz Figa wrote:
> Hi,
>
> Please see my comments inline.
>
> On Thursday 07 of November 2013 12:12:49 Vyacheslav Tyrtov wrote:
>> From: Tarek Dakhran <t.dakhran@samsung.com>
>>
>> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
>>
>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>> ---
>>   arch/arm/boot/dts/Makefile                |   1 +
>>   arch/arm/boot/dts/exynos5410-smdk5410.dts |  65 ++++++++++
>>   arch/arm/boot/dts/exynos5410.dtsi         | 209 ++++++++++++++++++++++++++++++
>>   3 files changed, 275 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
>>   create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
> [snip]
>> diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
>> new file mode 100644
>> index 0000000..06ae479
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
>> @@ -0,0 +1,65 @@
>> +/*
>> + * SAMSUNG SMDK5410 board device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + *		http://www.samsung.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/dts-v1/;
>> +#include "exynos5410.dtsi"
>> +/ {
>> +	model = "Samsung SMDK5410 board based on EXYNOS5410";
>> +	compatible = "samsung,smdk5410", "samsung,exynos5410";
>> +
>> +	memory {
>> +		reg = <0x40000000 0x80000000>;
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "console=ttySAC2,115200";
>> +	};
>> +
>> +	oscclk: oscclk {
> coding style: According to ePAPR recommendation, node name should
> represent hardware type, not particular instance of hardware.
>
> So instead, the preferred way would be to specify the clock using
> following layout:
>
> 	clocks {
> 		compatible = "simple-bus";
> 		#address-cells = <1>;
> 		#size-cells = <0>;
>
> 		oscclk: clock@0 {
> 			compatible = "fixed-clock";
> 			reg = <0>;
> 			#clock-cells = <0>;
> 			clock-frequency = <24000000>;
> 			clock-output-names = "fin_pll";
> 		};
> 	};
>
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <24000000>;
>> +		clock-output-names = "fin_pll";
>> +	};
> [snip]
>> +
>> +};
>> diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
>> new file mode 100644
>> index 0000000..9921b66
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos5410.dtsi
>> @@ -0,0 +1,209 @@
>> +/*
>> + * SAMSUNG EXYNOS5410 SoC device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + *		http://www.samsung.com
>> + *
>> + * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
>> + * EXYNOS5410 based board files can include this file and provide
>> + * values for board specfic bindings.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <dt-bindings/clock/exynos5410.h>
>> +#include "exynos5.dtsi"
>> +/ {
> [snip]
>> +	clock: clock-controller@10010000 {
>> +		compatible = "samsung,exynos5410-clock";
>> +		reg = <0x10010000 0x30000>;
>> +		#clock-cells = <1>;
>> +	};
>> +
>> +	mct@101C0000 {
> A generic name would be: timer@101C0000
>
>> +		compatible = "samsung,exynos4210-mct";
>> +		reg = <0x101C0000 0xB00>;
>> +		interrupt-controller;
>> +		#interrups-cells = <1>;
> MCT is not an interrupt controller, so both interrupt-controller and
> #interrupt-cells properties are incorrect. I guess that's due to the
> broken example in the documentation, that I already posted patches to fix.
>
>> +		interrupt-parent = <&mct_map>;
>> +		interrupts = <0>, <1>, <2>, <3>,
>> +			<4>, <5>, <6>, <7>,
>> +			<8>, <9>, <10>, <11>;
>> +		clocks = <&oscclk>, <&clock CLK_MCT>;
>> +		clock-names = "fin_pll", "mct";
>> +
>> +		mct_map: mct-map {
> Again, interrupt-map would be a better name for this node.
>
>> +			#interrupt-cells = <1>;
>> +			#address-cells = <0>;
>> +			#size-cells = <0>;
>> +			interrupt-map = <0 &combiner 23 3>,
>> +					<1 &combiner 23 4>,
>> +					<2 &combiner 25 2>,
>> +					<3 &combiner 25 3>,
>> +					<4 &gic 0 120 0>,
>> +					<5 &gic 0 121 0>,
>> +					<6 &gic 0 122 0>,
>> +					<7 &gic 0 123 0>,
>> +					<8 &gic 0 128 0>,
>> +					<9 &gic 0 129 0>,
>> +					<10 &gic 0 130 0>,
>> +					<11 &gic 0 131 0>;
>> +		};
>> +	};
> Otherwise, the patch looks good.
>
> Best regards,
> Tomasz
>
>
Thanks a lot, Tomasz.
All will be corrected in v4.

Best regards,
     Tarek Dakhran

Re: [PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support

[Tarek Dakhran]

On 07.11.2013 17:01, Dave Martin wrote:
> On Thu, Nov 07, 2013 at 08:12:48AM +0000, Vyacheslav Tyrtov wrote:
>> From: Tarek Dakhran <t.dakhran@samsung.com>
>>
>> Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
>> This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
>>
>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>> ---
>>   arch/arm/mach-exynos/Makefile |   2 +
>>   arch/arm/mach-exynos/edcs.c   | 278 ++++++++++++++++++++++++++++++++++++++++++
>>   2 files changed, 280 insertions(+)
>>   create mode 100644 arch/arm/mach-exynos/edcs.c
>>
>> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
>> index 5369615..ba6efdb 100644
>> --- a/arch/arm/mach-exynos/Makefile
>> +++ b/arch/arm/mach-exynos/Makefile
>> @@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
>>   
>>   obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
>>   obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
>> +
>> +obj-$(CONFIG_SOC_EXYNOS5410)		+= edcs.o
>> diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
>> new file mode 100644
>> index 0000000..980bfdd
>> --- /dev/null
>> +++ b/arch/arm/mach-exynos/edcs.c
>> @@ -0,0 +1,278 @@
>> +/*
>> + * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * EDCS(exynos dual cluster support) for Exynos5410 SoC.
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/of_address.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/errno.h>
>> +#include <linux/irqchip/arm-gic.h>
>> +
>> +#include <asm/mcpm.h>
>> +#include <asm/proc-fns.h>
>> +#include <asm/cacheflush.h>
>> +#include <asm/cputype.h>
>> +#include <asm/cp15.h>
>> +
>> +#include <linux/arm-cci.h>
>> +#include <mach/regs-pmu.h>
>> +
>> +#define EDCS_CPUS_PER_CLUSTER	4
>> +#define EDCS_CLUSTERS		2
>> +
>> +/* Exynos5410 power management registers */
>> +#define EDCS_CORE_CONFIGURATION(_nr)	(S5P_ARM_CORE0_CONFIGURATION	\
>> +						+ ((_nr) * 0x80))
>> +#define EDCS_CORE_STATUS(_nr)		(EDCS_CORE_CONFIGURATION(_nr) + 0x4)
>> +#define EDCS_CORE_OPTION(_nr)		(EDCS_CORE_CONFIGURATION(_nr) + 0x8)
>> +
>> +#define REG_CPU_STATE_ADDR0		(S5P_VA_SYSRAM_NS + 0x28)
>> +#define REG_CPU_STATE_ADDR(_nr)		(REG_CPU_STATE_ADDR0 +	\
>> +						 (_nr) * EDCS_CPUS_PER_CLUSTER)
>> +
>> +#define SECONDARY_RESET		(1 << 1)
>> +#define REG_ENTRY_ADDR		(S5P_VA_SYSRAM_NS + 0x1c)
>> +
>> +static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
>> +
>> +static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
>> +static int core_count[EDCS_CLUSTERS];
>> +
>> +static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
>> +				bool enable)
>> +{
>> +	unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
>> +	int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
>> +
>> +	if ((readl_relaxed(EDCS_CORE_STATUS(offset)) & 0x3) != value) {
> I wonder if there is a race here.
>
> If there is a pending powerdown which has reached the __mcpm_cpu_down()
> stage, then the kernel has no way to know what is still pending.  This
> means that when calling exynos_power_up(cpu, cluster) after a successful
> call to exynos_power_down(same cpu, cluster), there is a chance that
> the CPU still gets powered down, because of the pending
> exynos_core_power_control() on the outbound side.
>
> This isn't an issue for TC2, because TC2's power controller queues
> requests and services them in order, so a new powerup request cannot
> race with a powerdown request in that way.
>
> For exynos5410, it looks like the kernel needs to do that sequencing,
> based on my guess about what the EDCS_CORE_STATUS() bits tell us.
>
>
> I think that for correct behaviour we would need to wait for the race to
> be resolved here, but only if a powerdown might be pending.
>
> This implies that something like a call to the power_down_finish()
> method (which you would need to write -- see my comments below) is
> needed in exynos_core_power_up().
>
>
> It might make sense to have a per-cpu flag that tracks whether a
> powerdown is pending.  The flag could be set after
> __mcpm_cpu_going_down() is called, and cleared in the powered_up()
> method (which you would need to add).
>
>
> Maybe we should always just poll and wait, though.  exynos_power_up()
> should never be called for a CPU that the kernel thinks is already up,
> so it should either be down already (in which case we will poll the
> status once and then continue), or a power down is pending (in which
> case we must wait, but we know the wait will terminate).  This would
> be simpler than tracking a "power down pending" flag for each CPU.
>
>> +		wmb();
>> +		writel_relaxed(value, EDCS_CORE_CONFIGURATION(offset));
>> +	}
>> +}
>> +
>> +static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
>> +{
>> +	exynos_core_power_control(cpu, cluster, true);
>> +}
>> +
>> +static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
>> +{
>> +	exynos_core_power_control(cpu, cluster, false);
>> +}
>> +
>> +void set_boot_flag(unsigned int cpu, unsigned int mode)
>> +{
>> +	writel_relaxed(mode, REG_CPU_STATE_ADDR(cpu));
>> +}
>> +
>> +static int exynos_power_up(unsigned int cpu, unsigned int cluster)
>> +{
>> +	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
>> +	BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
>> +
>> +	local_irq_disable();
>> +	arch_spin_lock(&edcs_lock);
>> +
>> +	edcs_use_count[cpu][cluster]++;
>> +	if (edcs_use_count[cpu][cluster] == 1) {
>> +		++core_count[cluster];
>> +		set_boot_flag(cpu, SECONDARY_RESET);
>> +		exynos_core_power_up(cpu, cluster);
>> +	} else if (edcs_use_count[cpu][cluster] != 2) {
>> +		/*
>> +		 * The only possible values are:
>> +		 * 0 = CPU down
>> +		 * 1 = CPU (still) up
>> +		 * 2 = CPU requested to be up before it had a chance
>> +		 *     to actually make itself down.
>> +		 * Any other value is a bug.
>> +		 */
>> +		BUG();
>> +	}
>> +
>> +	arch_spin_unlock(&edcs_lock);
>> +	local_irq_enable();
>> +
>> +	return 0;
>> +}
>> +static void exynos_power_down(void)
>> +{
>> +	unsigned int mpidr, cpu, cluster;
>> +	bool last_man = false, skip_wfi = false;
>> +
>> +	mpidr = read_cpuid_mpidr();
>> +	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
>> +	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
>> +
>> +	pr_debug("%s: CORE%d on CLUSTER %d\n", __func__, cpu, cluster);
>> +	BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER  || cluster >= EDCS_CLUSTERS);
>> +
>> +	__mcpm_cpu_going_down(cpu, cluster);
>> +
>> +	arch_spin_lock(&edcs_lock);
>> +	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
>> +	edcs_use_count[cpu][cluster]--;
>> +	if (edcs_use_count[cpu][cluster] == 0) {
>> +		--core_count[cluster];
>> +		if (core_count[cluster] == 0)
>> +			last_man = true;
>> +	} else if (edcs_use_count[cpu][cluster] == 1) {
>> +		/*
>> +		 * A power_up request went ahead of us.
>> +		 * Even if we do not want to shut this CPU down,
>> +		 * the caller expects a certain state as if the WFI
>> +		 * was aborted.  So let's continue with cache cleaning.
>> +		 */
>> +		skip_wfi = true;
>> +	} else
>> +		BUG();
>> +
>> +	if (!skip_wfi)
>> +		gic_cpu_if_down();
>> +
>> +	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
>> +		arch_spin_unlock(&edcs_lock);
>> +
>> +		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
>> +			/*
>> +			 * On the Cortex-A15 we need to disable
>> +			 * L2 prefetching before flushing the cache.
>> +			 */
>> +			asm volatile(
>> +			"mcr	p15, 1, %0, c15, c0, 3\n\t"
>> +			"isb\n\t"
>> +			"dsb"
>> +			: : "r" (0x400));
>> +		}
>> +
>> +		/*
>> +		 * We need to disable and flush the whole (L1 and L2) cache.
>> +		 * Let's do it in the safest possible way i.e. with
>> +		 * no memory access within the following sequence
>> +		 * including the stack.
>> +		 *
>> +		 * Note: fp is preserved to the stack explicitly prior doing
>> +		 * this since adding it to the clobber list is incompatible
>> +		 * with having CONFIG_FRAME_POINTER=y.
>> +		 */
>> +		asm volatile(
>> +		"str	fp, [sp, #-4]!\n\t"
>> +		"mrc	p15, 0, r0, c1, c0, 0	@ get CR\n\t"
>> +		"bic	r0, r0, #"__stringify(CR_C)"\n\t"
>> +		"mcr	p15, 0, r0, c1, c0, 0	@ set CR\n\t"
>> +		"isb\n\t"
>> +		"bl	v7_flush_dcache_all\n\t"
>> +		"clrex\n\t"
>> +		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR\n\t"
>> +		"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t"
>> +		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR\n\t"
>> +		"isb\n\t"
>> +		"dsb\n\t"
>> +		"ldr	fp, [sp], #4"
> The v7_exit_coherency_flush() macro is now in linux-next, so
> you can now use it to replace these sequences.
>
> This can be replaced by v7_exit_coherency_flush(all).
>
>> +		: : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
>> +			"r9", "r10", "lr", "memory");
>> +
>> +		cci_disable_port_by_cpu(mpidr);
>> +
>> +		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
>> +
>> +	} else {
>> +		arch_spin_unlock(&edcs_lock);
>> +		/*
>> +			* We need to disable and flush only the L1 cache.
>> +			* Let's do it in the safest possible way as above.
>> +		*/
>> +		asm volatile(
>> +		"str	fp, [sp, #-4]!\n\t"
>> +		"mrc	p15, 0, r0, c1, c0, 0	@ get CR\n\t"
>> +		"bic	r0, r0, #"__stringify(CR_C)"\n\t"
>> +		"mcr	p15, 0, r0, c1, c0, 0	@ set CR\n\t"
>> +		"isb\n\t"
>> +		"bl	v7_flush_dcache_louis\n\t"
>> +		"clrex\n\t"
>> +		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR\n\t"
>> +		"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t"
>> +		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR\n\t"
>> +		"isb\n\t"
>> +		"dsb\n\t"
>> +		"ldr	fp, [sp], #4"
> v7_exit_coherency_flush(louis) should work here.
>
> arch/arm/mach-vexpress/tc2_pm.c (in linux-next) shows how to use it.
>
>> +		: : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
>> +		      "r9", "r10", "lr", "memory");
>> +
>> +	}
>> +	__mcpm_cpu_down(cpu, cluster);
>> +
>> +	if (!skip_wfi) {
>> +		exynos_core_power_down(cpu, cluster);
>> +		wfi();
>> +	}
>> +}
>> +
>> +static const struct mcpm_platform_ops exynos_power_ops = {
>> +	.power_up	= exynos_power_up,
>> +	.power_down	= exynos_power_down,
>> +};
> The new mcpm_power_down_finish() call is also present in linux-next now,
> so it should get merged into v3.13.
>
> One effect of this is that you should provide a power_down_finish()
> method in your mcpm_platform_ops, to provide the kernel with a way to
> check that a CPU has finished powering down.  This would usually involve
> checking some status bits in the power controller.  See the comments for
> mcpm_power_down_finish() in arch/arm/include/asm/mcpm.h for details.
>
> No platform backend for power_down_finish() is merged yet.  The most
> recent patch for TC2 was posted here -- I need to follow up on it.
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-October/201619.html
> [PATCH v3 3/3] ARM: vexpress/TC2: Implement MCPM power_down_finish()
>
> This may look quite different for exynos5410.
>
> Cheers
> ---Dave
>
Thanks Dave.
I'm working on this problem.

Best regards,
     Tarek Dakhran.

Re: [PATCH v3 0/4] Exynos 5410 Dual cluster support

[Tomasz Figa]

Hi,

On Thursday 07 of November 2013 12:12:45 Vyacheslav Tyrtov wrote:
> The series of patches represent support of Exynos 5410 SoC
> 
> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
> Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
> 
> Patches add new platform description, support of clock controller,
> dual cluster support and device tree for Exynos 5410
> 
> Has been build on v3.12.
> Has been tested on Exynos 5410 reference board (exynos_defconfig).

I've applied the patches on top of today's linux-next and tried to boot
my ODROID-XU using exynos5410-smdk5410.dts and exynos_defconfig, but all
I can get is an imprecise external abort, when the kernel tries to jump
to init. Full boot log below. Any ideas?

Best regards,
Tomasz

8><------------

U-Boot 2012.07-g2bcb371 (Nov 19 2013 - 20:17:37) for Exynos5410

CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15]
APLL = 900MHz, KPLL = 600MHz
MPLL = 532MHz, BPLL = 800MHz
DRAM:  2 GiB
WARNING: Caches not enabled

TrustZone Enabled BSP
BL1 version: 
PMIC VER : 0, CHIP REV : 6
VDD MIF : 1.00000V
VDD ARM : 1.00000V
VDD INT : 1.00000V
VDD G3D : 1.00000V
VDD KFC : 1.00000V

Checking Boot Mode ... SDMMC
MMC:   S5P_MSHC2: 0, S5P_MSHC0: 1
MMC Device 0: 14.8 GiB
MMC Device 1: [ERROR] response error : 00000006 cmd 8
[ERROR] response error : 00000006 cmd 55
[ERROR] response error : 00000006 cmd 2
In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Press 'Enter' or 'Space' to stop autoboot:  0 
ODROID-XU # 
ODROID-XU # 
ODROID-XU # pri        
baudrate=115200
bootargs=console=ttySAC2,115200n8 earlyprintk ignore_loglevel mem=1G root=/dev/mmcblk0p1 rootwait
bootcmd=run netboot
bootdelay=1
bootfile=uImage.xu
bootscript=source 40008000
copy_uboot_emmc2sd=emmc open 0;movi r z f 0 40000000;emmc close 0;movi w f 1 40000000;emmc open 0;movi r z b 0 40000000;emmc close 0;movi w b 1 40000000;emmc open 0;movi r z u 0 40000000;emmc close 0;movi w u 1 40000000;emmc open 0;movi r z t 0 40000000;emmc close 0;movi w t 1 40000000;mmc write 1 0x40008000 0x4CF 0x20;
copy_uboot_sd2emmc=movi r f 0 40000000;emmc open 1;movi w z f 1 40000000;emmc close 1;movi r b 0 40000000;emmc open 1;movi w z b 1 40000000;emmc close 1;movi r u 0 40000000;emmc open 1;movi w z u 1 40000000;emmc close 1;movi r t 0 40000000;emmc open 1;movi w z t 1 40000000;emmc close 1;mmc write 1 0x40008000 0x4CF 0x20;
default_bootcmd=echo >>> Run Default Bootcmd <<<;movi read kernel 0 40008000;bootz 40008000
ethact=sms0
ipaddr=192.168.1.20
loadbootscript_1=echo >>> Load Boot Script from mmc 0:1 <<<;fatload mmc 0:1 40008000 boot.scr
loadbootscript_2=echo >>> Load Boot Script from mmc 0:2 <<<;fatload mmc 0:2 40008000 boot.scr
loadbootscript_3=echo >>> Load Boot Script from mmc 1:1 <<<;fatload mmc 1:1 40008000 boot.scr
loadbootscript_4=echo >>> Load Boot Script from mmc 1:2 <<<;fatload mmc 1:2 40008000 boot.scr
netboot=usb start && tftpboot 40008000 && bootm 40008000
rootfslen=100000
serverip=192.168.1.2
stderr=serial
stdin=serial
stdout=serial
usbethaddr=00:11:22:33:44:55

Environment size: 1546/16380 bytes
ODROID-XU # run netboot
(Re)start USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 3 USB Device(s) found
       scanning bus for storage devices... 0 Storage Device(s) found
       scanning usb for ethernet devices... 1 Ethernet Device(s) found
Waiting for Ethernet connection... done.
Using sms0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.20
Filename 'uImage.xu'.
Load address: 0x40008000
Loading: #################################################################
         #################################################################
         #################################################################
         #########
done
Bytes transferred = 2980232 (2d7988 hex)
## Booting kernel from Legacy Image at 40008000 ...
   Image Name:   Linux-exynos5410-odroidxu
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2980168 Bytes = 2.8 MiB
   Load Address: 50008000
   Entry Point:  50008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK
  
Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 3.12.0-next-20131119-00004-g27f3f5f-dirty (tom3q@flatron) (gcc version 4.7.2 (Gentoo 4.7.2-r1 p1.6, pie-0.5.5) ) #11 SMP PREEMPT Wed Nov 20 00:08:02 CET 2013
[    0.000000] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine model: Hardkernel ODROID-XU board based on EXYNOS5410
[    0.000000] bootconsole [earlycon0] enabled
[    0.000000] debug: ignoring loglevel setting.
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] CPU EXYNOS5410 (id 0xe5410023)
[    0.000000] On node 0 totalpages: 262144
[    0.000000]   Normal zone: 1520 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 194560 pages, LIFO batch:31
[    0.000000]   HighMem zone: 528 pages used for memmap
[    0.000000]   HighMem zone: 67584 pages, LIFO batch:15
[    0.000000] PERCPU: Embedded 7 pages/cpu @c07e4000 s7552 r8192 d12928 u32768
[    0.000000] pcpu-alloc: s7552 r8192 d12928 u32768 alloc=8*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260624
[    0.000000] Kernel command line: console=ttySAC2,115200n8 earlyprintk ignore_loglevel mem=1G root=/dev/mmcblk0p1 rootwait
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1033268K/1048576K available (3860K kernel code, 254K rwdata, 1300K rodata, 231K init, 288K bss, 15308K reserved, 270336K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0512398   (5161 kB)
[    0.000000]       .init : 0xc0513000 - 0xc054cd80   ( 232 kB)
[    0.000000]       .data : 0xc054e000 - 0xc058d9e0   ( 255 kB)
[    0.000000]        .bss : 0xc058d9ec - 0xc05d5aa8   ( 289 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] sched_clock: 32 bits at 200 Hz, resolution 5000000ns, wraps every 10737418240000000ns
[    0.000000] Console: colour dummy device 80x30
[    0.000000] allocated 2097152 bytes of page_cgroup
[    0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
[    0.020000] Calibrating delay loop... 1785.85 BogoMIPS (lpj=4464640)
[    0.045000] pid_max: default: 32768 minimum: 301
[    0.050000] Mount-cache hash table entries: 512
[    0.055000] Initializing cgroup subsys memory
[    0.060000] Initializing cgroup subsys devices
[    0.065000] Initializing cgroup subsys freezer
[    0.070000] Initializing cgroup subsys blkio
[    0.075000] CPU: Testing write buffer coherency: ok
[    0.080000] CPU0: update cpu_power 1468
[    0.085000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.090000] Setting up static identity map for 0x503a9c48 - 0x503a9ca0
[    0.095000] ARM CCI driver probed
[    0.100000] EDCS power management initialized
[    0.135000] CPU1: Booted secondary processor
[    0.175000] CPU1: update cpu_power 1468
[    0.175000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.185000] CPU2: Booted secondary processor
[    0.225000] CPU2: update cpu_power 1468
[    0.225000] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[    0.235000] CPU3: Booted secondary processor
[    0.275000] CPU3: update cpu_power 1468
[    0.275000] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[    1.285000] CPU4: failed to come online
[    2.300000] CPU5: failed to come online
[    3.310000] CPU6: failed to come online
[    4.320000] CPU7: failed to come online
[    4.320000] Brought up 4 CPUs
[    4.325000] SMP: Total of 4 processors activated.
[    4.330000] CPU: All CPU(s) started in SVC mode.
[    4.335000] devtmpfs: initialized
[    4.345000] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    4.350000] pinctrl core: initialized pinctrl subsystem
[    4.355000] regulator-dummy: no parameters
[    4.355000] NET: Registered protocol family 16
[    4.360000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    4.370000] S3C Power Management, Copyright 2004 Simtec Electronics
[    4.375000] EXYNOS: PMU not supported
[    4.380000] EXYNOS: Initializing architecture
[    4.395000] bio: create slab <bio-0> at 0
[    4.405000] SCSI subsystem initialized
[    4.405000] usbcore: registered new interface driver usbfs
[    4.410000] usbcore: registered new interface driver hub
[    4.420000] usbcore: registered new device driver usb
[    4.425000] Switched to clocksource mct-frc
[    4.440000] NET: Registered protocol family 2
[    4.445000] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    4.455000] TCP bind hash table entries: 8192 (order: 5, 163840 bytes)
[    4.460000] TCP: Hash tables configured (established 8192 bind 8192)
[    4.465000] TCP: reno registered
[    4.470000] UDP hash table entries: 512 (order: 2, 24576 bytes)
[    4.475000] UDP-Lite hash table entries: 512 (order: 2, 24576 bytes)
[    4.485000] NET: Registered protocol family 1
[    4.490000] audit: initializing netlink socket (disabled)
[    4.495000] type=2000 audit(4.495:1): initialized
[    4.500000] bounce pool size: 64 pages
[    4.520000] ROMFS MTD (C) 2007 Red Hat, Inc.
[    4.525000] msgmni has been set to 1490
[    4.530000] io scheduler noop registered
[    4.530000] io scheduler deadline registered (default)
[    4.535000] io scheduler cfq registered
[    4.655000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    4.665000] 12c00000.serial: ttySAC0 at MMIO 0x12c00000 (irq = 83, base_baud = 0) is a S3C6400/10
[    4.675000] 12c10000.serial: ttySAC1 at MMIO 0x12c10000 (irq = 84, base_baud = 0) is a S3C6400/10
[    4.680000] console [tt[SAC2] enabled
    4.680000] console [ttySAC2] enabled
[    4.690000] bootconsole [early[on0] disabled
    4.690000] bootconsole [earlycon0] disabled
[    4.700000] 12c30000.serial: ttySAC3 at MMIO 0x12c30000 (irq = 86, base_baud = 0) is a S3C6400/10
[    4.715000] brd: module loaded
[    4.720000] loop: module loaded
[    4.725000] usbcore: registered new interface driver asix
[    4.730000] usbcore: registered new interface driver ax88179_178a
[    4.735000] usbcore: registered new interface driver cdc_ether
[    4.740000] usbcore: registered new interface driver r815x
[    4.745000] usbcore: registered new interface driver smsc75xx
[    4.755000] usbcore: registered new interface driver smsc95xx
[    4.760000] usbcore: registered new interface driver net1080
[    4.765000] usbcore: registered new interface driver cdc_subset
[    4.770000] usbcore: registered new interface driver zaurus
[    4.775000] usbcore: registered new interface driver cdc_ncm
[    4.780000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    4.790000] usbcore: registered new interface driver usb-storage
[    4.795000] mousedev: PS/2 mouse device common for all mice
[    4.800000] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com
[    4.810000] sdhci: Secure Digital Host Controller Interface driver
[    4.815000] sdhci: Copyright(c) Pierre Ossman
[    4.820000] Synopsys Designware Multimedia Card Interface Driver
[    4.825000] dwmmc_exynos 12200000.mmc: dummy supplies not allowed
[    4.830000] dwmmc_exynos 12200000.mmc: no vmmc regulator found: -19
[    4.835000] dwmmc_exynos 12200000.mmc: Using internal DMA controller.
[    4.845000] dwmmc_exynos 12200000.mmc: Version ID is 241a
[    4.850000] dwmmc_exynos 12200000.mmc: DW MMC controller at irq 107, 64 bit host data width, 128 deep fifo
[    4.860000] of_get_named_gpiod_flags: can't parse gpios property of node '/mmc@12200000/slot@0[0]'
[    4.895000] dwmmc_exynos 12200000.mmc: 1 slots initialized
[    4.895000] dwmmc_exynos 12220000.mmc: dummy supplies not allowed
[    4.905000] dwmmc_exynos 12220000.mmc: no vmmc regulator found: -19
[    4.910000] dwmmc_exynos 12220000.mmc: Using internal DMA controller.
[    4.915000] dwmmc_exynos 12220000.mmc: Version ID is 241a
[    4.920000] dwmmc_exynos 12220000.mmc: DW MMC controller at irq 109, 64 bit host data width, 128 deep fifo
[    4.930000] of_get_named_gpiod_flags: can't parse gpios property of node '/mmc@12220000/slot@0[0]'
[    4.970000] dwmmc_exynos 12220000.mmc: 1 slots initialized
[    4.975000] usbcore: registered new interface driver usbhid
[    4.980000] usbhid: USB HID core driver
[    4.980000] TCP: cubic registered
[    4.985000] NET: Registered protocol family 17
[    4.990000] NET: Registered protocol family 15
[    4.995000] Registering SWP/SWPB emulation handler
[    5.000000] registered taskstats version 1
[    5.005000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[    5.010000] Waiting for root device /dev/mmcblk0p1...
[    5.025000] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 25000000Hz, actual 25000000HZ div = 1)
[    5.035000] mmc1: new SDHC card at address e624
[    5.040000] isa bounce pool size: 16 pages
[    5.045000] mmcblk0: mmc1:e624 SU16G 14.8 GiB 
[    5.050000]  mmcblk0: p1
[    5.120000] EXT3-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240)
[    5.125000] EXT2-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240)
[    5.145000] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null)
[    5.150000] VFS: Mounted root (ext4 filesystem) readonly on device 179:1.
[    5.165000] devtmpfs: mounted
[    5.170000] Freeing unused kernel memory: 228K (c0513000 - c054c000)
[    5.195000] Unhandled fault: imprecise external abort (0x1406) at 0x00000000
[    5.210000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
[    5.210000] 
[    5.210000] CPU: 2 PID: 1 Comm: init Not tainted 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
[    5.210000] [<c0014068>] (unwind_backtrace+0x0/0xf8) from [<c0011438>] (show_stack+0x10/0x14)
[    5.210000] [<c0011438>] (show_stack+0x10/0x14) from [<c03a486c>] (dump_stack+0x7c/0xbc)
[    5.210000] [<c03a486c>] (dump_stack+0x7c/0xbc) from [<c03a1e78>] (panic+0x8c/0x1e4)
[    5.210000] [<c03a1e78>] (panic+0x8c/0x1e4) from [<c001f504>] (do_exit+0x850/0x920)
[    5.210000] [<c001f504>] (do_exit+0x850/0x920) from [<c001f63c>] (do_group_exit+0x3c/0xb0)
[    5.210000] [<c001f63c>] (do_group_exit+0x3c/0xb0) from [<c0029e1c>] (get_signal_to_deliver+0x1d4/0x538)
[    5.210000] [<c0029e1c>] (get_signal_to_deliver+0x1d4/0x538) from [<c0010974>] (do_signal+0x100/0x40c)
[    5.210000] [<c0010974>] (do_signal+0x100/0x40c) from [<c0010fb4>] (do_work_pending+0x68/0xa8)
[    5.210000] [<c0010fb4>] (do_work_pending+0x68/0xa8) from [<c000e620>] (work_pending+0xc/0x20)
[    5.300000] CPU3: stopping
[    5.300000] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
[    5.300000] [<c0014068>] (unwind_backtrace+0x0/0xf8) from [<c0011438>] (show_stack+0x10/0x14)
[    5.300000] [<c0011438>] (show_stack+0x10/0x14) from [<c03a486c>] (dump_stack+0x7c/0xbc)
[    5.300000] [<c03a486c>] (dump_stack+0x7c/0xbc) from [<c00132e0>] (handle_IPI+0x130/0x15c)
[    5.300000] [<c00132e0>] (handle_IPI+0x130/0x15c) from [<c000859c>] (gic_handle_irq+0x60/0x68)
[    5.300000] [<c000859c>] (gic_handle_irq+0x60/0x68) from [<c0011f00>] (__irq_svc+0x40/0x70)
[    5.300000] Exception stack(0xef29ff80 to 0xef29ffc8)
[    5.300000] ff80: c07fc558 00000000 0093a607 00000000 00000000 00000000 c054b558 002b1000
[    5.300000] ffa0: 60000113 00000001 c07fc558 ef29e000 c0556438 ef29ffc8 c0064254 c0064258
[    5.300000] ffc0: 60000113 ffffffff
[    5.300000] [<c0011f00>] (__irq_svc+0x40/0x70) from [<c0064258>] (rcu_idle_exit+0x5c/0xb0)
[    5.300000] [<c0064258>] (rcu_idle_exit+0x5c/0xb0) from [<c005b4a4>] (cpu_startup_entry+0x68/0x148)
[    5.300000] [<c005b4a4>] (cpu_startup_entry+0x68/0x148) from [<50008644>] (0x50008644)
[    5.300000] CPU1: stopping
[    5.300000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
[    5.300000] [<c0014068>] (unwind_backtrace+0x0/0xf8) from [<c0011438>] (show_stack+0x10/0x14)
[    5.300000] [<c0011438>] (show_stack+0x10/0x14) from [<c03a486c>] (dump_stack+0x7c/0xbc)
[    5.300000] [<c03a486c>] (dump_stack+0x7c/0xbc) from [<c00132e0>] (handle_IPI+0x130/0x15c)
[    5.300000] [<c00132e0>] (handle_IPI+0x130/0x15c) from [<c000859c>] (gic_handle_irq+0x60/0x68)
[    5.300000] [<c000859c>] (gic_handle_irq+0x60/0x68) from [<c0011f00>] (__irq_svc+0x40/0x70)
[    5.300000] Exception stack(0xef29bf80 to 0xef29bfc8)
[    5.300000] SMP: failed to stop secondary CPUs
[    5.465000] bf80: c07ec558 00000000 00938a81 00000000 00000000 00000000 c054b558 002a1000
[    5.475000] bfa0: 60000113 00000001 c07ec558 ef29a000 5572448d ef29bfc8 c0064254 c0064258
[    5.480000] bfc0: 60000113 ffffffff
[    5.485000] [<c0011f00>] (__irq_svc+0x40/0x70) from [<c0064258>] (rcu_idle_exit+0x5c/0xb0)
[    5.495000] [<c0064258>] (rcu_idle_exit+0x5c/0xb0) from [<c005b4a4>] (cpu_startup_entry+0x68/0x148)
[    5.505000] [<c005b4a4>] (cpu_startup_entry+0x68/0x148) from [<50008644>] (0x50008644)
[    5.510000] CPU0: stopping
[    5.515000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
[    5.525000] [<c0014068>] (unwind_backtrace+0x0/0xf8) from [<c0011438>] (show_stack+0x10/0x14)
[    5.530000] [<c0011438>] (show_stack+0x10/0x14) from [<c03a486c>] (dump_stack+0x7c/0xbc)
[    5.540000] [<c03a486c>] (dump_stack+0x7c/0xbc) from [<c00132e0>] (handle_IPI+0x130/0x15c)
[    5.550000] [<c00132e0>] (handle_IPI+0x130/0x15c) from [<c000859c>] (gic_handle_irq+0x60/0x68)
[    5.555000] [<c000859c>] (gic_handle_irq+0x60/0x68) from [<c0011f00>] (__irq_svc+0x40/0x70)
[    5.565000] Exception stack(0xc054ff60 to 0xc054ffa8)
[    5.570000] ff60: c07e4558 00000000 00001796 00000000 c054e000 c05564b8 c03ab8d4 c054e000
[    5.580000] ff80: c058d3d5 00000001 c058d3d5 c054e000 55529a03 c054ffa8 c000f18c c000f190
[    5.585000] ffa0: 60000113 ffffffff
[    5.590000] [<c0011f00>] (__irq_svc+0x40/0x70) from [<c000f190>] (arch_cpu_idle+0x28/0x30)
[    5.600000] [<c000f190>] (arch_cpu_idle+0x28/0x30) from [<c005b494>] (cpu_startup_entry+0x58/0x148)
[    5.605000] [<c005b494>] (cpu_startup_entry+0x58/0x148) from [<c0513b28>] (start_kernel+0x384/0x3e4)

Re: [PATCH v3 0/4] Exynos 5410 Dual cluster support

[Tarek Dakhran]

Hi,

On 20.11.2013 03:23, Tomasz Figa wrote:
> Hi,
>
> On Thursday 07 of November 2013 12:12:45 Vyacheslav Tyrtov wrote:
>> The series of patches represent support of Exynos 5410 SoC
>>
>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>> Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
>>
>> Patches add new platform description, support of clock controller,
>> dual cluster support and device tree for Exynos 5410
>>
>> Has been build on v3.12.
>> Has been tested on Exynos 5410 reference board (exynos_defconfig).
> I've applied the patches on top of today's linux-next and tried to boot
> my ODROID-XU using exynos5410-smdk5410.dts and exynos_defconfig, but all
> I can get is an imprecise external abort, when the kernel tries to jump
> to init. Full boot log below. Any ideas?
>
> Best regards,
> Tomasz
>
> 8><------------
>
> U-Boot 2012.07-g2bcb371 (Nov 19 2013 - 20:17:37) for Exynos5410
>
> CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15]
> APLL = 900MHz, KPLL = 600MHz
[snip]
>    
> Starting kernel ...
>
> Uncompressing Linux... done, booting the kernel.
> [    0.000000] Booting Linux on physical CPU 0x0
> [    0.000000] Initializing cgroup subsys cpuset
> [    0.000000] Initializing cgroup subsys cpu
> [    0.000000] Initializing cgroup subsys cpuacct
> [    0.000000] Linux version 3.12.0-next-20131119-00004-g27f3f5f-dirty (tom3q@flatron) (gcc version 4.7.2 (Gentoo 4.7.2-r1 p1.6, pie-0.5.5) ) #11 SMP PREEMPT Wed Nov 20 00:08:02 CET 2013
> [    0.000000] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d
> [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> [    0.000000] Machine model: Hardkernel ODROID-XU board based on EXYNOS5410
> [    0.000000] bootconsole [earlycon0] enabled
> [    0.000000] debug: ignoring loglevel setting.
> [    0.000000] Memory policy: Data cache writealloc
> [    0.000000] CPU EXYNOS5410 (id 0xe5410023)
> [    0.000000] On node 0 totalpages: 262144
[snip]
> [    5.040000] isa bounce pool size: 16 pages
> [    5.045000] mmcblk0: mmc1:e624 SU16G 14.8 GiB
> [    5.050000]  mmcblk0: p1
> [    5.120000] EXT3-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240)
> [    5.125000] EXT2-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240)
> [    5.145000] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null)
> [    5.150000] VFS: Mounted root (ext4 filesystem) readonly on device 179:1.
> [    5.165000] devtmpfs: mounted
> [    5.170000] Freeing unused kernel memory: 228K (c0513000 - c054c000)
> [    5.195000] Unhandled fault: imprecise external abort (0x1406) at 0x00000000
> [    5.210000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
> [    5.210000]
> [    5.210000] CPU: 2 PID: 1 Comm: init Not tainted 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
> [    5.210000] [<c0014068>] (unwind_backtrace+0x0/0xf8) from [<c0011438>] (show_stack+0x10/0x14)
> [    5.210000] [<c0011438>] (show_stack+0x10/0x14) from [<c03a486c>] (dump_stack+0x7c/0xbc)
> [    5.210000] [<c03a486c>] (dump_stack+0x7c/0xbc) from [<c03a1e78>] (panic+0x8c/0x1e4)
> [    5.210000] [<c03a1e78>] (panic+0x8c/0x1e4) from [<c001f504>] (do_exit+0x850/0x920)
> [    5.210000] [<c001f504>] (do_exit+0x850/0x920) from [<c001f63c>] (do_group_exit+0x3c/0xb0)
> [    5.210000] [<c001f63c>] (do_group_exit+0x3c/0xb0) from [<c0029e1c>] (get_signal_to_deliver+0x1d4/0x538)
> [    5.210000] [<c0029e1c>] (get_signal_to_deliver+0x1d4/0x538) from [<c0010974>] (do_signal+0x100/0x40c)
> [    5.210000] [<c0010974>] (do_signal+0x100/0x40c) from [<c0010fb4>] (do_work_pending+0x68/0xa8)
> [    5.210000] [<c0010fb4>] (do_work_pending+0x68/0xa8) from [<c000e620>] (work_pending+0xc/0x20)
> [    5.300000] CPU3: stopping
> [    5.300000] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
>
Tomasz, there is CCI on/off switcher on smdk5410 board, also there is 
XOMCCI pin on SoC.
Looks like switcher on board controls the XOMCCI SoC pin.

When I turn switcher OFF, I getting the same problem you got.
Please, check the cci state on Odroid-XU Board, maybe it is turned off.

Best regards,
     Tarek Dakhran

Re: [PATCH v3 0/4] Exynos 5410 Dual cluster support

[Mauro Ribeiro]

Hello,

On ODROID-XU XOMCCI is connected to VDD.

Best Regards,
Mauro

On Wed, Nov 20, 2013 at 10:54 PM, Tarek Dakhran <t.dakhran@samsung.com> wrote:
> Hi,
>
>
> On 20.11.2013 03:23, Tomasz Figa wrote:
>>
>> Hi,
>>
>> On Thursday 07 of November 2013 12:12:45 Vyacheslav Tyrtov wrote:
>>>
>>> The series of patches represent support of Exynos 5410 SoC
>>>
>>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>>> Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same
>>> time
>>>
>>> Patches add new platform description, support of clock controller,
>>> dual cluster support and device tree for Exynos 5410
>>>
>>> Has been build on v3.12.
>>> Has been tested on Exynos 5410 reference board (exynos_defconfig).
>>
>> I've applied the patches on top of today's linux-next and tried to boot
>> my ODROID-XU using exynos5410-smdk5410.dts and exynos_defconfig, but all
>> I can get is an imprecise external abort, when the kernel tries to jump
>> to init. Full boot log below. Any ideas?
>>
>> Best regards,
>> Tomasz
>>
>> 8><------------
>>
>> U-Boot 2012.07-g2bcb371 (Nov 19 2013 - 20:17:37) for Exynos5410
>>
>> CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15]
>> APLL = 900MHz, KPLL = 600MHz
>
> [snip]
>
>>    Starting kernel ...
>>
>> Uncompressing Linux... done, booting the kernel.
>> [    0.000000] Booting Linux on physical CPU 0x0
>> [    0.000000] Initializing cgroup subsys cpuset
>> [    0.000000] Initializing cgroup subsys cpu
>> [    0.000000] Initializing cgroup subsys cpuacct
>> [    0.000000] Linux version 3.12.0-next-20131119-00004-g27f3f5f-dirty
>> (tom3q@flatron) (gcc version 4.7.2 (Gentoo 4.7.2-r1 p1.6, pie-0.5.5) ) #11
>> SMP PREEMPT Wed Nov 20 00:08:02 CET 2013
>> [    0.000000] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7),
>> cr=10c5387d
>> [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction
>> cache
>> [    0.000000] Machine model: Hardkernel ODROID-XU board based on
>> EXYNOS5410
>> [    0.000000] bootconsole [earlycon0] enabled
>> [    0.000000] debug: ignoring loglevel setting.
>> [    0.000000] Memory policy: Data cache writealloc
>> [    0.000000] CPU EXYNOS5410 (id 0xe5410023)
>> [    0.000000] On node 0 totalpages: 262144
>
> [snip]
>
>> [    5.040000] isa bounce pool size: 16 pages
>> [    5.045000] mmcblk0: mmc1:e624 SU16G 14.8 GiB
>> [    5.050000]  mmcblk0: p1
>> [    5.120000] EXT3-fs (mmcblk0p1): error: couldn't mount because of
>> unsupported optional features (240)
>> [    5.125000] EXT2-fs (mmcblk0p1): error: couldn't mount because of
>> unsupported optional features (240)
>> [    5.145000] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data
>> mode. Opts: (null)
>> [    5.150000] VFS: Mounted root (ext4 filesystem) readonly on device
>> 179:1.
>> [    5.165000] devtmpfs: mounted
>> [    5.170000] Freeing unused kernel memory: 228K (c0513000 - c054c000)
>> [    5.195000] Unhandled fault: imprecise external abort (0x1406) at
>> 0x00000000
>> [    5.210000] Kernel panic - not syncing: Attempted to kill init!
>> exitcode=0x00000007
>> [    5.210000]
>> [    5.210000] CPU: 2 PID: 1 Comm: init Not tainted
>> 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
>> [    5.210000] [<c0014068>] (unwind_backtrace+0x0/0xf8) from [<c0011438>]
>> (show_stack+0x10/0x14)
>> [    5.210000] [<c0011438>] (show_stack+0x10/0x14) from [<c03a486c>]
>> (dump_stack+0x7c/0xbc)
>> [    5.210000] [<c03a486c>] (dump_stack+0x7c/0xbc) from [<c03a1e78>]
>> (panic+0x8c/0x1e4)
>> [    5.210000] [<c03a1e78>] (panic+0x8c/0x1e4) from [<c001f504>]
>> (do_exit+0x850/0x920)
>> [    5.210000] [<c001f504>] (do_exit+0x850/0x920) from [<c001f63c>]
>> (do_group_exit+0x3c/0xb0)
>> [    5.210000] [<c001f63c>] (do_group_exit+0x3c/0xb0) from [<c0029e1c>]
>> (get_signal_to_deliver+0x1d4/0x538)
>> [    5.210000] [<c0029e1c>] (get_signal_to_deliver+0x1d4/0x538) from
>> [<c0010974>] (do_signal+0x100/0x40c)
>> [    5.210000] [<c0010974>] (do_signal+0x100/0x40c) from [<c0010fb4>]
>> (do_work_pending+0x68/0xa8)
>> [    5.210000] [<c0010fb4>] (do_work_pending+0x68/0xa8) from [<c000e620>]
>> (work_pending+0xc/0x20)
>> [    5.300000] CPU3: stopping
>> [    5.300000] CPU: 3 PID: 0 Comm: swapper/3 Not tainted
>> 3.12.0-next-20131119-00004-g27f3f5f-dirty #11
>>
> Tomasz, there is CCI on/off switcher on smdk5410 board, also there is XOMCCI
> pin on SoC.
> Looks like switcher on board controls the XOMCCI SoC pin.
>
> When I turn switcher OFF, I getting the same problem you got.
> Please, check the cci state on Odroid-XU Board, maybe it is turned off.
>
> Best regards,
>     Tarek Dakhran
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 0/4] Exynos 5410 Dual cluster support

[Alexei Colin]

On 11/20/2013 08:54 AM, Tarek Dakhran wrote:
> On 20.11.2013 03:23, Tomasz Figa wrote:
>> I've applied the patches on top of today's linux-next and tried to boot
>> my ODROID-XU using exynos5410-smdk5410.dts and exynos_defconfig, but all
>> I can get is an imprecise external abort, when the kernel tries to jump
>> to init. Full boot log below. Any ideas?

>> [    5.195000] Unhandled fault: imprecise external abort (0x1406) at 0x00000000
>> [    5.210000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
>>
> Tomasz, there is CCI on/off switcher on smdk5410 board, also there is 
> XOMCCI pin on SoC.
> Looks like switcher on board controls the XOMCCI SoC pin.
> 
> When I turn switcher OFF, I getting the same problem you got.
> Please, check the cci state on Odroid-XU Board, maybe it is turned off.

I've soldered a wire to the XOMCCI pin on Odroid-XU+E. When pulled to
Vdd via 100k (original configuration), the fault is "imprecise external
abort (0x1406)" (as above). When pulled to ground, the fault is
"imprecise external abort (0x406)". This is consistently reproducible.

AFAICT, from ARM reference [1]: the 5 status bits in both cases are
"Asynchronous external abort." and the difference is bit 12 "external
abort type:" when pulled to Vdd, caused by "AXI Slave error," when
pulled to ground, caused by "AXI Decode error".

Any pointers on further differences between SMDK5410 and ODROID-XU that
are preventing the patch from booting? Thanks in advance.

[1]
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Bgbiaghh.html