[PATCH V4 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[PATCH V4 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the interrupt
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt controllers are preceded by an
IRQ CROSSBAR that provides flexibility in muxing the device interrupt
requests to the controller inputs.

This series models the peripheral interrupts that can be routed through
the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
in a separate linear domain inside the GIC. The registered routable domain's
callback are invoked as a part of the GIC's callback, which in turn should
allocate a free irq line and configure the IP accordingly. So every peripheral
in the dts files mentions the fixed crossbar number as its interrupt. A free
gic line for that gets allocated and configured when the peripheral interrupts
are mapped.

The minimal crossbar driver to track and allocate free GIC lines and configure the
crossbar is added here, along with the DT bindings.

V4:
   Addressed a couple of comments and split the DTS file updates in to
   a separate series.

V3:
   Addressed few more comments from Thomas Gleixner <tglx@linutronix.de>

   Rebased patches 3,4,5,7 which updates the DTS file on top of below branch
	   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
	   for_3.13/dts

   Rebased patches 1,2,6 on top of 3.12 mainline
   Updated Commit tags

V2:
   Addressed Thomas Gleixner <tglx@linutronix.de> comments and
   Kumar Gala <galak@codeaurora.org>

   Split updating the DRA7.dtsi file for adding the routable-irqs

Previous discussions that led to this is at
	https://lkml.org/lkml/2013/9/18/540

The V1,V2,V3 post of these patches is at
      [V1]  https://lkml.org/lkml/2013/9/30/283
      [V2]  http://www.spinics.net/lists/linux-omap/msg99540.html
      [V3]  http://www.kernelhub.org/?msg=356470&p=2

Sricharan R (4):
  DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
  DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
  ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
  ARM: DRA: Enable Crossbar IP support for DRA7XX

 Documentation/devicetree/bindings/arm/gic.txt      |    6 +
 .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
 arch/arm/mach-omap2/Kconfig                        |    1 +
 arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
 arch/arm/mach-omap2/omap4-common.c                 |    3 +
 drivers/irqchip/Kconfig                            |    8 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-crossbar.c                     |  206 ++++++++++++++++++++
 drivers/irqchip/irq-gic.c                          |   81 +++++++-
 include/linux/irqchip/arm-gic.h                    |    7 +-
 include/linux/irqchip/irq-crossbar.h               |   11 ++
 11 files changed, 342 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
 create mode 100644 drivers/irqchip/irq-crossbar.c
 create mode 100644 include/linux/irqchip/irq-crossbar.h

-- 
1.7.9.5

[PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Sricharan R]

In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.

The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 [V2] Added default routable-irqs functions to avoid
      unnecessary if checks as per Thomas Gleixner comments
      and renamed routable-irq binding as per
      Kumar Gala <galak@codeaurora.org> comments.

 [V3] Addressed unnecessary warn-on and updated default
      xlate function as per Thomas Gleixner comments

 Documentation/devicetree/bindings/arm/gic.txt |    6 ++
 drivers/irqchip/irq-gic.c                     |   81 ++++++++++++++++++++++---
 include/linux/irqchip/arm-gic.h               |    7 ++-
 3 files changed, 83 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..5357745 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+		  connected from the peripherals, but are routed dynamically
+		  by a crossbar/multiplexer preceding the GIC. The GIC irq
+		  input line is assigned dynamically when the corresponding
+		  peripheral's crossbar line is mapped.
 Example:
 
 	intc: interrupt-controller@fff11000 {
@@ -56,6 +61,7 @@ Example:
 		#interrupt-cells = <3>;
 		#address-cells = <1>;
 		interrupt-controller;
+		arm,routable-irqs = <160>;
 		reg = <0xfff11000 0x1000>,
 		      <0xfff10100 0x100>;
 	};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9031171..b7b39a7 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -824,16 +824,25 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 		irq_set_chip_and_handler(irq, &gic_chip,
 					 handle_fasteoi_irq);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+		gic_routable_irq_domain_ops->map(d, irq, hw);
 	}
 	irq_set_chip_data(irq, d->host_data);
 	return 0;
 }
 
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+	gic_routable_irq_domain_ops->unmap(d, irq);
+}
+
 static int gic_irq_domain_xlate(struct irq_domain *d,
 				struct device_node *controller,
 				const u32 *intspec, unsigned int intsize,
 				unsigned long *out_hwirq, unsigned int *out_type)
 {
+	unsigned long ret = 0;
+
 	if (d->of_node != controller)
 		return -EINVAL;
 	if (intsize < 3)
@@ -843,11 +852,20 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
 	*out_hwirq = intspec[1] + 16;
 
 	/* For SPIs, we need to add 16 more to get the GIC irq ID number */
-	if (!intspec[0])
-		*out_hwirq += 16;
+	if (!intspec[0]) {
+		ret = gic_routable_irq_domain_ops->xlate(d, controller,
+							 intspec,
+							 intsize,
+							 out_hwirq,
+							 out_type);
+
+		if (IS_ERR_VALUE(ret))
+			return ret;
+	}
 
 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
-	return 0;
+
+	return ret;
 }
 
 #ifdef CONFIG_SMP
@@ -871,9 +889,41 @@ static struct notifier_block gic_cpu_notifier = {
 
 const struct irq_domain_ops gic_irq_domain_ops = {
 	.map = gic_irq_domain_map,
+	.unmap = gic_irq_domain_unmap,
 	.xlate = gic_irq_domain_xlate,
 };
 
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
+			      irq_hw_number_t hw)
+{
+	return 0;
+}
+
+static void gic_routable_irq_domain_unmap(struct irq_domain *d,
+					  unsigned int irq)
+{
+}
+
+static int gic_routable_irq_domain_xlate(struct irq_domain *d,
+				struct device_node *controller,
+				const u32 *intspec, unsigned int intsize,
+				unsigned long *out_hwirq,
+				unsigned int *out_type)
+{
+	*out_hwirq += 16;
+	return 0;
+}
+
+const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
+	.map = gic_routable_irq_domain_map,
+	.unmap = gic_routable_irq_domain_unmap,
+	.xlate = gic_routable_irq_domain_xlate,
+};
+
+const struct irq_domain_ops *gic_routable_irq_domain_ops =
+					&gic_default_routable_irq_domain_ops;
+
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 			   void __iomem *dist_base, void __iomem *cpu_base,
 			   u32 percpu_offset, struct device_node *node)
@@ -881,6 +931,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 	irq_hw_number_t hwirq_base;
 	struct gic_chip_data *gic;
 	int gic_irqs, irq_base, i;
+	int nr_routable_irqs;
 
 	BUG_ON(gic_nr >= MAX_GIC_NR);
 
@@ -946,14 +997,24 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 	gic->gic_irqs = gic_irqs;
 
 	gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
-	irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
-	if (IS_ERR_VALUE(irq_base)) {
-		WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-		     irq_start);
-		irq_base = irq_start;
+
+	if (of_property_read_u32(node, "arm,routable-irqs", &nr_routable_irqs)) {
+		irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
+					   numa_node_id());
+		if (IS_ERR_VALUE(irq_base)) {
+			WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+			     irq_start);
+			irq_base = irq_start;
+		}
+
+		gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
+					hwirq_base, &gic_irq_domain_ops, gic);
+	} else {
+		gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
+						    &gic_irq_domain_ops,
+						    gic);
 	}
-	gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
-				    hwirq_base, &gic_irq_domain_ops, gic);
+
 	if (WARN_ON(!gic->domain))
 		return;
 
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index cac496b..fcb02d7 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -81,6 +81,11 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
+extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
+static inline void __init register_routable_domain_ops
+					(const struct irq_domain_ops *ops)
+{
+	gic_routable_irq_domain_ops = ops;
+}
 #endif /* __ASSEMBLY */
-
 #endif
-- 
1.7.9.5

[PATCH V4 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.

This driver takes care a allocating a free irq and then configuring the
crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
be called right before the irqchip_init, so that it is setup to handle the
irqchip callbacks.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 [V2] Addressed Thomas Gleixner <tglx@linutronix.de> comments
      and renamed the bindings as per Kumar Gala <galak@codeaurora.org>
      comments.
 [V3] Changed static inline const to static inline int and removed
      unnecessary variable initialization as per
      Thomas Gleixner <tglx@linutronix.de>. Updated commit tags
 [V4] Renamed crossbar_init as irqcrossbar_init as per
      Rajendra Nayak <rnayak@ti.com> suggestion.

 .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
 drivers/irqchip/Kconfig                            |    8 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-crossbar.c                     |  206 ++++++++++++++++++++
 include/linux/irqchip/irq-crossbar.h               |   11 ++
 5 files changed, 253 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
 create mode 100644 drivers/irqchip/irq-crossbar.c
 create mode 100644 include/linux/irqchip/irq-crossbar.h

diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
new file mode 100644
index 0000000..fb88585
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -0,0 +1,27 @@
+Some socs have a large number of interrupts requests to service
+the needs of its many peripherals and subsystems. All of the
+interrupt lines from the subsystems are not needed at the same
+time, so they have to be muxed to the irq-controller appropriately.
+In such places a interrupt controllers are preceded by an CROSSBAR
+that provides flexibility in muxing the device requests to the controller
+inputs.
+
+Required properties:
+- compatible : Should be "ti,irq-crossbar"
+- reg: Base address and the size of the crossbar registers.
+- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- ti,reg-size: Size of a individual register in bytes. Every individual
+	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
+- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
+		 crossbar. These interrupt lines are reserved in the soc,
+		 so crossbar bar driver should not consider them as free
+		 lines.
+
+Examples:
+		crossbar_mpu: @4a020000 {
+			compatible = "ti,irq-crossbar";
+			reg = <0x4a002a48 0x130>;
+			ti,max-irqs = <160>;
+			ti,reg-size = <2>;
+			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+		};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..2efcde6 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -61,3 +61,11 @@ config VERSATILE_FPGA_IRQ_NR
        int
        default 4
        depends on VERSATILE_FPGA_IRQ
+
+config IRQ_CROSSBAR
+	bool
+	help
+	  Support for a CROSSBAR ip that preceeds the main interrupt controller.
+	  The primary irqchip invokes the crossbar's callback which inturn allocates
+	  a free irq and configures the IP. Thus the peripheral interrupts are
+	  routed to one of the free irqchip interrupt lines.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c60b901..2edead9 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
 obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
 obj-$(CONFIG_TB10X_IRQC)		+= irq-tb10x.o
+obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
new file mode 100644
index 0000000..2b9c5f3
--- /dev/null
+++ b/drivers/irqchip/irq-crossbar.c
@@ -0,0 +1,206 @@
+/*
+ *  drivers/irqchip/irq-crossbar.c
+ *
+ *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *  Author: Sricharan R <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/irqchip/arm-gic.h>
+
+#define IRQ_FREE	-1
+#define GIC_IRQ_START	32
+
+/*
+ * @int_max: maximum number of supported interrupts
+ * @irq_map: array of interrupts to crossbar number mapping
+ * @crossbar_base: crossbar base address
+ * @register_offsets: offsets for each irq number
+ */
+struct crossbar_device {
+	uint int_max;
+	uint *irq_map;
+	void __iomem *crossbar_base;
+	int *register_offsets;
+	void (*write) (int, int);
+};
+
+static struct crossbar_device *cb;
+
+static inline void crossbar_writel(int irq_no, int cb_no)
+{
+	writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
+}
+
+static inline void crossbar_writew(int irq_no, int cb_no)
+{
+	writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
+}
+
+static inline void crossbar_writeb(int irq_no, int cb_no)
+{
+	writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
+}
+
+static inline int allocate_free_irq(int cb_no)
+{
+	int i;
+
+	for (i = 0; i < cb->int_max; i++) {
+		if (cb->irq_map[i] == IRQ_FREE) {
+			cb->irq_map[i] = cb_no;
+			return i;
+		}
+	}
+
+	return -ENODEV;
+}
+
+static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
+			       irq_hw_number_t hw)
+{
+	cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
+	return 0;
+}
+
+static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+	irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
+
+	if (hw > GIC_IRQ_START)
+		cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
+}
+
+static int crossbar_domain_xlate(struct irq_domain *d,
+				 struct device_node *controller,
+				 const u32 *intspec, unsigned int intsize,
+				 unsigned long *out_hwirq,
+				 unsigned int *out_type)
+{
+	unsigned long ret;
+
+	ret = allocate_free_irq(intspec[1]);
+
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	*out_hwirq = ret + GIC_IRQ_START;
+	return 0;
+}
+
+const struct irq_domain_ops routable_irq_domain_ops = {
+	.map = crossbar_domain_map,
+	.unmap = crossbar_domain_unmap,
+	.xlate = crossbar_domain_xlate
+};
+
+static int __init crossbar_of_init(struct device_node *node)
+{
+	int i, size, max, reserved = 0, entry;
+	const __be32 *irqsr;
+
+	cb = kzalloc(sizeof(struct cb_device *), GFP_KERNEL);
+
+	if (!cb)
+		return -ENOMEM;
+
+	cb->crossbar_base = of_iomap(node, 0);
+	if (!cb->crossbar_base)
+		goto err1;
+
+	of_property_read_u32(node, "ti,max-irqs", &max);
+	cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
+	if (!cb->irq_map)
+		goto err2;
+
+	cb->int_max = max;
+
+	for (i = 0; i < max; i++)
+		cb->irq_map[i] = IRQ_FREE;
+
+	/* Get and mark reserved irqs */
+	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
+	if (irqsr) {
+		size /= sizeof(__be32);
+
+		for (i = 0; i < size; i++) {
+			entry = be32_to_cpup(irqsr + i);
+			if (entry > max) {
+				pr_err("Invalid reserved entry\n");
+				goto err3;
+			}
+			cb->irq_map[entry] = 0;
+		}
+	}
+
+	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
+	if (!cb->register_offsets)
+		goto err3;
+
+	of_property_read_u32(node, "ti,reg-size", &size);
+
+	switch (size) {
+	case 1:
+		cb->write = crossbar_writeb;
+		break;
+	case 2:
+		cb->write = crossbar_writew;
+		break;
+	case 4:
+		cb->write = crossbar_writel;
+		break;
+	default:
+		pr_err("Invalid reg-size property\n");
+		goto err4;
+		break;
+	}
+
+	/*
+	 * Register offsets are not linear because of the
+	 * reserved irqs. so find and store the offsets once.
+	 */
+	for (i = 0; i < max; i++) {
+		if (!cb->irq_map[i])
+			continue;
+
+		cb->register_offsets[i] = reserved;
+		reserved += size;
+	}
+
+	register_routable_domain_ops(&routable_irq_domain_ops);
+	return 0;
+
+err4:
+	kfree(cb->register_offsets);
+err3:
+	kfree(cb->irq_map);
+err2:
+	iounmap(cb->crossbar_base);
+err1:
+	kfree(cb);
+	return -ENOMEM;
+}
+
+static const struct of_device_id crossbar_match[] __initconst = {
+	{ .compatible = "ti,irq-crossbar" },
+	{}
+};
+
+int irqcrossbar_init(void)
+{
+	struct device_node *np;
+	np = of_find_matching_node(NULL, crossbar_match);
+	if (!np)
+		return -ENODEV;
+
+	crossbar_of_init(np);
+	return 0;
+}
diff --git a/include/linux/irqchip/irq-crossbar.h b/include/linux/irqchip/irq-crossbar.h
new file mode 100644
index 0000000..e5537b8
--- /dev/null
+++ b/include/linux/irqchip/irq-crossbar.h
@@ -0,0 +1,11 @@
+/*
+ *  drivers/irqchip/irq-crossbar.h
+ *
+ *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+int irqcrossbar_init(void);
-- 
1.7.9.5

[PATCH V4 3/4] ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number

[Sricharan R]

The wakeup gen mask/unmask callback uses the irq element of the
irq_data to setup. The irq is the linux virtual irq number and
is same as the hardware irq number only when the parent irqchip
is setup as a legacy domain. When it is used as a linear domain,
the virtual irqs are allocated dynamically and wakeup gen code
cannot rely on these numbers to access the irq registers. Instead
use the hwirq element of the irq_data which represent the physical
irq number.

Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/omap-wakeupgen.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 3664562..693fe48 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -138,7 +138,7 @@ static void wakeupgen_mask(struct irq_data *d)
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
-	_wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
+	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
 	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 
@@ -150,7 +150,7 @@ static void wakeupgen_unmask(struct irq_data *d)
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
-	_wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
+	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
 	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 
-- 
1.7.9.5

[PATCH V4 4/4] ARM: DRA: Enable Crossbar IP support for DRA7XX

[Sricharan R]

Enable the crossbar IP support for DRA7xx soc.

Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
[V4] Removed the unnecessary soc check as per
     Nishanth Menon <nm@ti.com> comments

 arch/arm/mach-omap2/Kconfig        |    1 +
 arch/arm/mach-omap2/omap4-common.c |    2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dc21df1..d538df6 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -135,6 +135,7 @@ config SOC_DRA7XX
 	select ARM_GIC
 	select HAVE_SMP
 	select COMMON_CLK
+	select IRQ_CROSSBAR
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 5791143..5430c31 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/irq-crossbar.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
 
@@ -282,6 +283,7 @@ void __init omap_gic_of_init(void)
 
 skip_errata_init:
 	omap_wakeupgen_init();
+	irqcrossbar_init();
 	irqchip_init();
 }
 
-- 
1.7.9.5

Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Thomas Gleixner]

On Thu, 14 Nov 2013, Sricharan R wrote:
>  [V3] Addressed unnecessary warn-on and updated default
>       xlate function as per Thomas Gleixner comments

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>

Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Sricharan R]

On Thursday 14 November 2013 06:03 PM, Thomas Gleixner wrote:
> On Thu, 14 Nov 2013, Sricharan R wrote:
>>  [V3] Addressed unnecessary warn-on and updated default
>>       xlate function as per Thomas Gleixner comments
> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
 Thanks Thomas..

Regards,
 Sricharan

Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Mark Rutland]

On Thu, Nov 14, 2013 at 12:18:47PM +0000, Sricharan R wrote:
> In some socs the gic can be preceded by a crossbar IP which
> routes the peripheral interrupts to the gic inputs. The peripheral
> interrupts are associated with a fixed crossbar input line and the
> crossbar routes that to one of the free gic input line.
> 
> The DT entries for peripherals provides the fixed crossbar input line
> as its interrupt number and the mapping code should associate this with
> a free gic input line. This patch adds the support inside the gic irqchip
> to handle such routable irqs. The routable irqs are registered in a linear
> domain. The registered routable domain's callback should be implemented
> to get a free irq and to configure the IP to route it.
> 
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  [V2] Added default routable-irqs functions to avoid
>       unnecessary if checks as per Thomas Gleixner comments
>       and renamed routable-irq binding as per
>       Kumar Gala <galak@codeaurora.org> comments.
> 
>  [V3] Addressed unnecessary warn-on and updated default
>       xlate function as per Thomas Gleixner comments
> 
>  Documentation/devicetree/bindings/arm/gic.txt |    6 ++
>  drivers/irqchip/irq-gic.c                     |   81 ++++++++++++++++++++++---
>  include/linux/irqchip/arm-gic.h               |    7 ++-
>  3 files changed, 83 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
> index 3dfb0c0..5357745 100644
> --- a/Documentation/devicetree/bindings/arm/gic.txt
> +++ b/Documentation/devicetree/bindings/arm/gic.txt
> @@ -49,6 +49,11 @@ Optional
>    regions, used when the GIC doesn't have banked registers. The offset is
>    cpu-offset * cpu-nr.
>  
> +- arm,routable-irqs : Total number of gic irq inputs which are not directly
> +		  connected from the peripherals, but are routed dynamically
> +		  by a crossbar/multiplexer preceding the GIC. The GIC irq
> +		  input line is assigned dynamically when the corresponding
> +		  peripheral's crossbar line is mapped.

I'm not keen on the design of the arm,routable-irqs property. The set of
IRQs which the crossbar IP can use is a property of which IRQ lines it
has routed to the GIC. I don't see why that should be considered a
property of the GIC; it's a property of the crossbar IP's attachment to
the GIC.

Given we already have a mechanism for describing the attachment (i.e.
the interrupts property) where the property appears on the node for the
device generating/propagating the interrupt, I don't see why we should
do differently here.

Listing 160 interrupts in the crossbar node is clearly something we
don't want to have to do.  If we had a property that we could use to
define a range (or multiple ranges) of interrupts, then the crossbar
driver could go and request those ranges from its interrupt-parent (the
GIC) and the GIC driver could reserve/allocate the irqdomain at that
time.

This feels like a point-hack, counter in style to the vast majority of
provider/consumer bindings. It only allows for one multiplexer before
the GIC. What if we had multiple multiplexers feeding into the GIC?
Describing the attachment on the multiplexer allows that to be handled,
describing that on the GIC does not.

Describing the attachement on the multiplexer would also prevent the
duplication of information (i.e. the max-irqs property in the crossbar
binding).

Thanks,
Mark.

Re: [PATCH V4 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Mark Rutland]

On Thu, Nov 14, 2013 at 12:18:48PM +0000, Sricharan R wrote:
> Some socs have a large number of interrupts requests to service
> the needs of its many peripherals and subsystems. All of the
> interrupt lines from the subsystems are not needed at the same
> time, so they have to be muxed to the irq-controller appropriately.
> In such places a interrupt controllers are preceded by an CROSSBAR
> that provides flexibility in muxing the device requests to the controller
> inputs.
> 
> This driver takes care a allocating a free irq and then configuring the
> crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
> be called right before the irqchip_init, so that it is setup to handle the
> irqchip callbacks.
> 
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  [V2] Addressed Thomas Gleixner <tglx@linutronix.de> comments
>       and renamed the bindings as per Kumar Gala <galak@codeaurora.org>
>       comments.
>  [V3] Changed static inline const to static inline int and removed
>       unnecessary variable initialization as per
>       Thomas Gleixner <tglx@linutronix.de>. Updated commit tags
>  [V4] Renamed crossbar_init as irqcrossbar_init as per
>       Rajendra Nayak <rnayak@ti.com> suggestion.
> 
>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>  drivers/irqchip/Kconfig                            |    8 +
>  drivers/irqchip/Makefile                           |    1 +
>  drivers/irqchip/irq-crossbar.c                     |  206 ++++++++++++++++++++
>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>  5 files changed, 253 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>  create mode 100644 drivers/irqchip/irq-crossbar.c
>  create mode 100644 include/linux/irqchip/irq-crossbar.h
> 
> diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> new file mode 100644
> index 0000000..fb88585
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> @@ -0,0 +1,27 @@
> +Some socs have a large number of interrupts requests to service
> +the needs of its many peripherals and subsystems. All of the
> +interrupt lines from the subsystems are not needed at the same
> +time, so they have to be muxed to the irq-controller appropriately.
> +In such places a interrupt controllers are preceded by an CROSSBAR
> +that provides flexibility in muxing the device requests to the controller
> +inputs.
> +
> +Required properties:
> +- compatible : Should be "ti,irq-crossbar"
> +- reg: Base address and the size of the crossbar registers.
> +- ti,max-irqs: Total number of irqs available at the interrupt controller.
> +- ti,reg-size: Size of a individual register in bytes. Every individual
> +	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
> +- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
> +		 crossbar. These interrupt lines are reserved in the soc,
> +		 so crossbar bar driver should not consider them as free
> +		 lines.

The combination of the ti,max-irqs and ti,irqs-reserved properties seems
backwards to me. Why can we not describe the set of IRQs that _can_ be
used?

> +
> +Examples:
> +		crossbar_mpu: @4a020000 {
> +			compatible = "ti,irq-crossbar";
> +			reg = <0x4a002a48 0x130>;
> +			ti,max-irqs = <160>;
> +			ti,reg-size = <2>;
> +			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
> +		};

[...]

> +	/* Get and mark reserved irqs */
> +	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
> +	if (irqsr) {
> +		size /= sizeof(__be32);
> +
> +		for (i = 0; i < size; i++) {
> +			entry = be32_to_cpup(irqsr + i);
> +			if (entry > max) {
> +				pr_err("Invalid reserved entry\n");
> +				goto err3;
> +			}
> +			cb->irq_map[entry] = 0;
> +		}
> +	}

Don't deal with the raw DTB. Use of_property_read_u32_index.

> +
> +	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
> +	if (!cb->register_offsets)
> +		goto err3;
> +
> +	of_property_read_u32(node, "ti,reg-size", &size);

If "ti,reg-size" isn't present, size is uninitialized. Please check the
return value of of_property_read_u32.

Thanks,
Mark.

Re: [PATCH V4 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Santosh Shilimkar]

On Thursday 14 November 2013 07:18 AM, Sricharan R wrote:
> Some socs have a large number of interrupts requests to service
> the needs of its many peripherals and subsystems. All of the interrupt
> requests lines from the subsystems are not needed at the same
> time, so they have to be muxed to the controllers appropriately.
> In such places a interrupt controllers are preceded by an
> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
> requests to the controller inputs.
> 
> This series models the peripheral interrupts that can be routed through
> the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
> in a separate linear domain inside the GIC. The registered routable domain's
> callback are invoked as a part of the GIC's callback, which in turn should
> allocate a free irq line and configure the IP accordingly. So every peripheral
> in the dts files mentions the fixed crossbar number as its interrupt. A free
> gic line for that gets allocated and configured when the peripheral interrupts
> are mapped.
> 
> The minimal crossbar driver to track and allocate free GIC lines and configure the
> crossbar is added here, along with the DT bindings.
> 
> V4:
>    Addressed a couple of comments and split the DTS file updates in to
>    a separate series.
> 
Thanks for the split.
For entire series,
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Re: [PATCH V4 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Hi Mark,

On Thursday 14 November 2013 07:42 PM, Mark Rutland wrote:
> On Thu, Nov 14, 2013 at 12:18:48PM +0000, Sricharan R wrote:
>> Some socs have a large number of interrupts requests to service
>> the needs of its many peripherals and subsystems. All of the
>> interrupt lines from the subsystems are not needed at the same
>> time, so they have to be muxed to the irq-controller appropriately.
>> In such places a interrupt controllers are preceded by an CROSSBAR
>> that provides flexibility in muxing the device requests to the controller
>> inputs.
>>
>> This driver takes care a allocating a free irq and then configuring the
>> crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
>> be called right before the irqchip_init, so that it is setup to handle the
>> irqchip callbacks.
>>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Rajendra Nayak <rnayak@ti.com>
>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>> Cc: Grant Likely <grant.likely@linaro.org>
>> Cc: Rob Herring <rob.herring@calxeda.com>
>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>> Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> ---
>>  [V2] Addressed Thomas Gleixner <tglx@linutronix.de> comments
>>       and renamed the bindings as per Kumar Gala <galak@codeaurora.org>
>>       comments.
>>  [V3] Changed static inline const to static inline int and removed
>>       unnecessary variable initialization as per
>>       Thomas Gleixner <tglx@linutronix.de>. Updated commit tags
>>  [V4] Renamed crossbar_init as irqcrossbar_init as per
>>       Rajendra Nayak <rnayak@ti.com> suggestion.
>>
>>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>>  drivers/irqchip/Kconfig                            |    8 +
>>  drivers/irqchip/Makefile                           |    1 +
>>  drivers/irqchip/irq-crossbar.c                     |  206 ++++++++++++++++++++
>>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>>  5 files changed, 253 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>>  create mode 100644 drivers/irqchip/irq-crossbar.c
>>  create mode 100644 include/linux/irqchip/irq-crossbar.h
>>
>> diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
>> new file mode 100644
>> index 0000000..fb88585
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
>> @@ -0,0 +1,27 @@
>> +Some socs have a large number of interrupts requests to service
>> +the needs of its many peripherals and subsystems. All of the
>> +interrupt lines from the subsystems are not needed at the same
>> +time, so they have to be muxed to the irq-controller appropriately.
>> +In such places a interrupt controllers are preceded by an CROSSBAR
>> +that provides flexibility in muxing the device requests to the controller
>> +inputs.
>> +
>> +Required properties:
>> +- compatible : Should be "ti,irq-crossbar"
>> +- reg: Base address and the size of the crossbar registers.
>> +- ti,max-irqs: Total number of irqs available at the interrupt controller.
>> +- ti,reg-size: Size of a individual register in bytes. Every individual
>> +	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
>> +- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
>> +		 crossbar. These interrupt lines are reserved in the soc,
>> +		 so crossbar bar driver should not consider them as free
>> +		 lines.
> The combination of the ti,max-irqs and ti,irqs-reserved properties seems
> backwards to me. Why can we not describe the set of IRQs that _can_ be
> used?
 Total set of irqs that are usable is max - reserved. Since reserved irqs
 are not continuous, we have to give the list. During the init we count
 the total number of reserved and get the usable one.
>> +
>> +Examples:
>> +		crossbar_mpu: @4a020000 {
>> +			compatible = "ti,irq-crossbar";
>> +			reg = <0x4a002a48 0x130>;
>> +			ti,max-irqs = <160>;
>> +			ti,reg-size = <2>;
>> +			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
>> +		};
> [...]
>
>> +	/* Get and mark reserved irqs */
>> +	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
>> +	if (irqsr) {
>> +		size /= sizeof(__be32);
>> +
>> +		for (i = 0; i < size; i++) {
>> +			entry = be32_to_cpup(irqsr + i);
>> +			if (entry > max) {
>> +				pr_err("Invalid reserved entry\n");
>> +				goto err3;
>> +			}
>> +			cb->irq_map[entry] = 0;
>> +		}
>> +	}
> Don't deal with the raw DTB. Use of_property_read_u32_index.
 Ok, i will correct this.
>> +
>> +	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
>> +	if (!cb->register_offsets)
>> +		goto err3;
>> +
>> +	of_property_read_u32(node, "ti,reg-size", &size);
> If "ti,reg-size" isn't present, size is uninitialized. Please check the
> return value of of_property_read_u32.
Ok, will correct this.

Regards,
 Sricharan

Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Sricharan R]

Hi Mark,

On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote:
> On Thu, Nov 14, 2013 at 12:18:47PM +0000, Sricharan R wrote:
>> In some socs the gic can be preceded by a crossbar IP which
>> routes the peripheral interrupts to the gic inputs. The peripheral
>> interrupts are associated with a fixed crossbar input line and the
>> crossbar routes that to one of the free gic input line.
>>
>> The DT entries for peripherals provides the fixed crossbar input line
>> as its interrupt number and the mapping code should associate this with
>> a free gic input line. This patch adds the support inside the gic irqchip
>> to handle such routable irqs. The routable irqs are registered in a linear
>> domain. The registered routable domain's callback should be implemented
>> to get a free irq and to configure the IP to route it.
>>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Rajendra Nayak <rnayak@ti.com>
>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>> Cc: Grant Likely <grant.likely@linaro.org>
>> Cc: Rob Herring <rob.herring@calxeda.com>
>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> ---
>>  [V2] Added default routable-irqs functions to avoid
>>       unnecessary if checks as per Thomas Gleixner comments
>>       and renamed routable-irq binding as per
>>       Kumar Gala <galak@codeaurora.org> comments.
>>
>>  [V3] Addressed unnecessary warn-on and updated default
>>       xlate function as per Thomas Gleixner comments
>>
>>  Documentation/devicetree/bindings/arm/gic.txt |    6 ++
>>  drivers/irqchip/irq-gic.c                     |   81 ++++++++++++++++++++++---
>>  include/linux/irqchip/arm-gic.h               |    7 ++-
>>  3 files changed, 83 insertions(+), 11 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
>> index 3dfb0c0..5357745 100644
>> --- a/Documentation/devicetree/bindings/arm/gic.txt
>> +++ b/Documentation/devicetree/bindings/arm/gic.txt
>> @@ -49,6 +49,11 @@ Optional
>>    regions, used when the GIC doesn't have banked registers. The offset is
>>    cpu-offset * cpu-nr.
>>  
>> +- arm,routable-irqs : Total number of gic irq inputs which are not directly
>> +		  connected from the peripherals, but are routed dynamically
>> +		  by a crossbar/multiplexer preceding the GIC. The GIC irq
>> +		  input line is assigned dynamically when the corresponding
>> +		  peripheral's crossbar line is mapped.
> I'm not keen on the design of the arm,routable-irqs property. The set of
> IRQs which the crossbar IP can use is a property of which IRQ lines it
> has routed to the GIC. I don't see why that should be considered a
> property of the GIC; it's a property of the crossbar IP's attachment to
> the GIC.
>
> Given we already have a mechanism for describing the attachment (i.e.
> the interrupts property) where the property appears on the node for the
> device generating/propagating the interrupt, I don't see why we should
> do differently here.
 We did try using interrupts=<> property for all peripherals and
 mapping them as crossbar's parent. But that approach of representing
 crossbar as a interrupt parent was not accepted, since the crossbar
 was just routing the interrupts from peripherals to GIC and nothing more.
 Also  mapping all the interrupts using interrupt-map like property by a fixed way
 in DTS itself was considered hacky
> Listing 160 interrupts in the crossbar node is clearly something we
> don't want to have to do.  If we had a property that we could use to
> define a range (or multiple ranges) of interrupts, then the crossbar
> driver could go and request those ranges from its interrupt-parent (the
> GIC) and the GIC driver could reserve/allocate the irqdomain at that
> time.
Again, this kind of approach of crossbar requesting irqs from GIC
was tried earlier and it did not go anywhere. Subsequently after lot of
discussions this design was considered the best one.

http://www.spinics.net/lists/linux-omap/msg97085.html
> This feels like a point-hack, counter in style to the vast majority of
> provider/consumer bindings. It only allows for one multiplexer before
> the GIC. What if we had multiple multiplexers feeding into the GIC?
> Describing the attachment on the multiplexer allows that to be handled,
> describing that on the GIC does not.
 This is case where the interrupts to GIC is not coming from full irqchip,
 but just a router and support added in the GIC helps to handle
 such cases. In the case of more than one multiplexer, the crossbar
 driver should really take care of handling the downward muxes and
 crossbar like driver can be expanded to handle if such a scenario happens.
> Describing the attachement on the multiplexer would also prevent the
> duplication of information (i.e. the max-irqs property in the crossbar
> binding).
>
> Thanks,
> Mark.
Here max-irqs is the total number of output lines of the crossbar itself and
its property.

Regards,
 Sricharan

Re: [PATCH V4 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Mark Rutland]

On Thu, Nov 14, 2013 at 04:41:41PM +0000, Sricharan R wrote:
> Hi Mark,
> 
> On Thursday 14 November 2013 07:42 PM, Mark Rutland wrote:
> > On Thu, Nov 14, 2013 at 12:18:48PM +0000, Sricharan R wrote:
> >> Some socs have a large number of interrupts requests to service
> >> the needs of its many peripherals and subsystems. All of the
> >> interrupt lines from the subsystems are not needed at the same
> >> time, so they have to be muxed to the irq-controller appropriately.
> >> In such places a interrupt controllers are preceded by an CROSSBAR
> >> that provides flexibility in muxing the device requests to the controller
> >> inputs.
> >>
> >> This driver takes care a allocating a free irq and then configuring the
> >> crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
> >> be called right before the irqchip_init, so that it is setup to handle the
> >> irqchip callbacks.
> >>
> >> Cc: Thomas Gleixner <tglx@linutronix.de>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >> Cc: Russell King <linux@arm.linux.org.uk>
> >> Cc: Tony Lindgren <tony@atomide.com>
> >> Cc: Rajendra Nayak <rnayak@ti.com>
> >> Cc: Marc Zyngier <marc.zyngier@arm.com>
> >> Cc: Grant Likely <grant.likely@linaro.org>
> >> Cc: Rob Herring <rob.herring@calxeda.com>
> >> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> >> Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
> >> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >> ---
> >>  [V2] Addressed Thomas Gleixner <tglx@linutronix.de> comments
> >>       and renamed the bindings as per Kumar Gala <galak@codeaurora.org>
> >>       comments.
> >>  [V3] Changed static inline const to static inline int and removed
> >>       unnecessary variable initialization as per
> >>       Thomas Gleixner <tglx@linutronix.de>. Updated commit tags
> >>  [V4] Renamed crossbar_init as irqcrossbar_init as per
> >>       Rajendra Nayak <rnayak@ti.com> suggestion.
> >>
> >>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
> >>  drivers/irqchip/Kconfig                            |    8 +
> >>  drivers/irqchip/Makefile                           |    1 +
> >>  drivers/irqchip/irq-crossbar.c                     |  206 ++++++++++++++++++++
> >>  include/linux/irqchip/irq-crossbar.h               |   11 ++
> >>  5 files changed, 253 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
> >>  create mode 100644 drivers/irqchip/irq-crossbar.c
> >>  create mode 100644 include/linux/irqchip/irq-crossbar.h
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> >> new file mode 100644
> >> index 0000000..fb88585
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> >> @@ -0,0 +1,27 @@
> >> +Some socs have a large number of interrupts requests to service
> >> +the needs of its many peripherals and subsystems. All of the
> >> +interrupt lines from the subsystems are not needed at the same
> >> +time, so they have to be muxed to the irq-controller appropriately.
> >> +In such places a interrupt controllers are preceded by an CROSSBAR
> >> +that provides flexibility in muxing the device requests to the controller
> >> +inputs.
> >> +
> >> +Required properties:
> >> +- compatible : Should be "ti,irq-crossbar"
> >> +- reg: Base address and the size of the crossbar registers.
> >> +- ti,max-irqs: Total number of irqs available at the interrupt controller.
> >> +- ti,reg-size: Size of a individual register in bytes. Every individual
> >> +	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
> >> +- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
> >> +		 crossbar. These interrupt lines are reserved in the soc,
> >> +		 so crossbar bar driver should not consider them as free
> >> +		 lines.
> > The combination of the ti,max-irqs and ti,irqs-reserved properties seems
> > backwards to me. Why can we not describe the set of IRQs that _can_ be
> > used?
>  Total set of irqs that are usable is max - reserved. Since reserved irqs
>  are not continuous, we have to give the list. During the init we count
>  the total number of reserved and get the usable one.

So why not describe the set of usable IRQs, rather than a set of IRQs
for which only some are usable then subtracting the set of unusable
IRQs?

It seems backwards to me to have a binding for a device describe
resources it doesn't have.

> >> +
> >> +Examples:
> >> +		crossbar_mpu: @4a020000 {
> >> +			compatible = "ti,irq-crossbar";
> >> +			reg = <0x4a002a48 0x130>;
> >> +			ti,max-irqs = <160>;
> >> +			ti,reg-size = <2>;
> >> +			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
> >> +		};
> > [...]
> >
> >> +	/* Get and mark reserved irqs */
> >> +	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
> >> +	if (irqsr) {
> >> +		size /= sizeof(__be32);
> >> +
> >> +		for (i = 0; i < size; i++) {
> >> +			entry = be32_to_cpup(irqsr + i);
> >> +			if (entry > max) {
> >> +				pr_err("Invalid reserved entry\n");
> >> +				goto err3;
> >> +			}
> >> +			cb->irq_map[entry] = 0;
> >> +		}
> >> +	}
> > Don't deal with the raw DTB. Use of_property_read_u32_index.
>  Ok, i will correct this.
> >> +
> >> +	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
> >> +	if (!cb->register_offsets)
> >> +		goto err3;
> >> +
> >> +	of_property_read_u32(node, "ti,reg-size", &size);
> > If "ti,reg-size" isn't present, size is uninitialized. Please check the
> > return value of of_property_read_u32.
> Ok, will correct this.

Cheers.

Mark.

Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Mark Rutland]

On Thu, Nov 14, 2013 at 04:46:36PM +0000, Sricharan R wrote:
> Hi Mark,
> 
> On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote:
> > On Thu, Nov 14, 2013 at 12:18:47PM +0000, Sricharan R wrote:
> >> In some socs the gic can be preceded by a crossbar IP which
> >> routes the peripheral interrupts to the gic inputs. The peripheral
> >> interrupts are associated with a fixed crossbar input line and the
> >> crossbar routes that to one of the free gic input line.
> >>
> >> The DT entries for peripherals provides the fixed crossbar input line
> >> as its interrupt number and the mapping code should associate this with
> >> a free gic input line. This patch adds the support inside the gic irqchip
> >> to handle such routable irqs. The routable irqs are registered in a linear
> >> domain. The registered routable domain's callback should be implemented
> >> to get a free irq and to configure the IP to route it.
> >>
> >> Cc: Thomas Gleixner <tglx@linutronix.de>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >> Cc: Russell King <linux@arm.linux.org.uk>
> >> Cc: Tony Lindgren <tony@atomide.com>
> >> Cc: Rajendra Nayak <rnayak@ti.com>
> >> Cc: Marc Zyngier <marc.zyngier@arm.com>
> >> Cc: Grant Likely <grant.likely@linaro.org>
> >> Cc: Rob Herring <rob.herring@calxeda.com>
> >> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> >> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >> ---
> >>  [V2] Added default routable-irqs functions to avoid
> >>       unnecessary if checks as per Thomas Gleixner comments
> >>       and renamed routable-irq binding as per
> >>       Kumar Gala <galak@codeaurora.org> comments.
> >>
> >>  [V3] Addressed unnecessary warn-on and updated default
> >>       xlate function as per Thomas Gleixner comments
> >>
> >>  Documentation/devicetree/bindings/arm/gic.txt |    6 ++
> >>  drivers/irqchip/irq-gic.c                     |   81 ++++++++++++++++++++++---
> >>  include/linux/irqchip/arm-gic.h               |    7 ++-
> >>  3 files changed, 83 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
> >> index 3dfb0c0..5357745 100644
> >> --- a/Documentation/devicetree/bindings/arm/gic.txt
> >> +++ b/Documentation/devicetree/bindings/arm/gic.txt
> >> @@ -49,6 +49,11 @@ Optional
> >>    regions, used when the GIC doesn't have banked registers. The offset is
> >>    cpu-offset * cpu-nr.
> >>  
> >> +- arm,routable-irqs : Total number of gic irq inputs which are not directly
> >> +		  connected from the peripherals, but are routed dynamically
> >> +		  by a crossbar/multiplexer preceding the GIC. The GIC irq
> >> +		  input line is assigned dynamically when the corresponding
> >> +		  peripheral's crossbar line is mapped.
> > I'm not keen on the design of the arm,routable-irqs property. The set of
> > IRQs which the crossbar IP can use is a property of which IRQ lines it
> > has routed to the GIC. I don't see why that should be considered a
> > property of the GIC; it's a property of the crossbar IP's attachment to
> > the GIC.
> >
> > Given we already have a mechanism for describing the attachment (i.e.
> > the interrupts property) where the property appears on the node for the
> > device generating/propagating the interrupt, I don't see why we should
> > do differently here.
>  We did try using interrupts=<> property for all peripherals and
>  mapping them as crossbar's parent. But that approach of representing
>  crossbar as a interrupt parent was not accepted, since the crossbar
>  was just routing the interrupts from peripherals to GIC and nothing more.
>  Also  mapping all the interrupts using interrupt-map like property by a fixed way
>  in DTS itself was considered hacky

I'm not suggesting you should interrupt-map. I agree that that
interrupt-map is not suitable for a dynamically configurable device like
the crossbar.

When you say that the crossbar is just routing the interrupts, at what
level is it doing so? Does it accept a logical interrupt and output
another logical interrupt, or does it just connect the two lines
electrically?

We don't necessarily have to use the interrupts property, but I still
think that the set of GIC input IRQ lines that the crossbar is wired to
should be described on the crossbar node.

> > Listing 160 interrupts in the crossbar node is clearly something we
> > don't want to have to do.  If we had a property that we could use to
> > define a range (or multiple ranges) of interrupts, then the crossbar
> > driver could go and request those ranges from its interrupt-parent (the
> > GIC) and the GIC driver could reserve/allocate the irqdomain at that
> > time.
> Again, this kind of approach of crossbar requesting irqs from GIC
> was tried earlier and it did not go anywhere. Subsequently after lot of
> discussions this design was considered the best one.
> 
> http://www.spinics.net/lists/linux-omap/msg97085.html

As far as I can see, the comment there was to use irqdomains, which I am
not arguing against. I am arguing that the linkage of the GIC and the
crossbar is being described the wrong way around. The GIC input lines
that the crossbar is wired to should be described on the crossbar node,
and the crossbar driver should request the appropriate domain from the
GIC.

> > This feels like a point-hack, counter in style to the vast majority of
> > provider/consumer bindings. It only allows for one multiplexer before
> > the GIC. What if we had multiple multiplexers feeding into the GIC?
> > Describing the attachment on the multiplexer allows that to be handled,
> > describing that on the GIC does not.
>  This is case where the interrupts to GIC is not coming from full irqchip,
>  but just a router and support added in the GIC helps to handle
>  such cases. In the case of more than one multiplexer, the crossbar
>  driver should really take care of handling the downward muxes and
>  crossbar like driver can be expanded to handle if such a scenario happens.

That still feels like a hack. If there are multiple instances, I see no
reason why they should have to know about each other. It's fundamentally
at odds to the generic composable model we have now.

> > Describing the attachement on the multiplexer would also prevent the
> > duplication of information (i.e. the max-irqs property in the crossbar
> > binding).
> >
> > Thanks,
> > Mark.
> Here max-irqs is the total number of output lines of the crossbar itself and
> its property.

This would be implicit if the set of IRQ inputs on the GIC that these
lines fed out to were described.

Thanks,
Mark.

Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Santosh Shilimkar]

On Friday 15 November 2013 06:23 AM, Mark Rutland wrote:
> On Thu, Nov 14, 2013 at 04:46:36PM +0000, Sricharan R wrote:
>> Hi Mark,
>>
>> On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote:
>>> On Thu, Nov 14, 2013 at 12:18:47PM +0000, Sricharan R wrote:
>>>> In some socs the gic can be preceded by a crossbar IP which
>>>> routes the peripheral interrupts to the gic inputs. The peripheral
>>>> interrupts are associated with a fixed crossbar input line and the
>>>> crossbar routes that to one of the free gic input line.
>>>>
>>>> The DT entries for peripherals provides the fixed crossbar input line
>>>> as its interrupt number and the mapping code should associate this with
>>>> a free gic input line. This patch adds the support inside the gic irqchip
>>>> to handle such routable irqs. The routable irqs are registered in a linear
>>>> domain. The registered routable domain's callback should be implemented
>>>> to get a free irq and to configure the IP to route it.
>>>>
>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>> Cc: Linus Walleij <linus.walleij@linaro.org>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Cc: Rajendra Nayak <rnayak@ti.com>
>>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>>>> Cc: Grant Likely <grant.likely@linaro.org>
>>>> Cc: Rob Herring <rob.herring@calxeda.com>
>>>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>>>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> ---
>>>>  [V2] Added default routable-irqs functions to avoid
>>>>       unnecessary if checks as per Thomas Gleixner comments
>>>>       and renamed routable-irq binding as per
>>>>       Kumar Gala <galak@codeaurora.org> comments.
>>>>
>>>>  [V3] Addressed unnecessary warn-on and updated default
>>>>       xlate function as per Thomas Gleixner comments
>>>>
>>>>  Documentation/devicetree/bindings/arm/gic.txt |    6 ++
>>>>  drivers/irqchip/irq-gic.c                     |   81 ++++++++++++++++++++++---
>>>>  include/linux/irqchip/arm-gic.h               |    7 ++-
>>>>  3 files changed, 83 insertions(+), 11 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
>>>> index 3dfb0c0..5357745 100644
>>>> --- a/Documentation/devicetree/bindings/arm/gic.txt
>>>> +++ b/Documentation/devicetree/bindings/arm/gic.txt
>>>> @@ -49,6 +49,11 @@ Optional
>>>>    regions, used when the GIC doesn't have banked registers. The offset is
>>>>    cpu-offset * cpu-nr.
>>>>  
>>>> +- arm,routable-irqs : Total number of gic irq inputs which are not directly
>>>> +		  connected from the peripherals, but are routed dynamically
>>>> +		  by a crossbar/multiplexer preceding the GIC. The GIC irq
>>>> +		  input line is assigned dynamically when the corresponding
>>>> +		  peripheral's crossbar line is mapped.
>>> I'm not keen on the design of the arm,routable-irqs property. The set of
>>> IRQs which the crossbar IP can use is a property of which IRQ lines it
>>> has routed to the GIC. I don't see why that should be considered a
>>> property of the GIC; it's a property of the crossbar IP's attachment to
>>> the GIC.
>>>
>>> Given we already have a mechanism for describing the attachment (i.e.
>>> the interrupts property) where the property appears on the node for the
>>> device generating/propagating the interrupt, I don't see why we should
>>> do differently here.
>>  We did try using interrupts=<> property for all peripherals and
>>  mapping them as crossbar's parent. But that approach of representing
>>  crossbar as a interrupt parent was not accepted, since the crossbar
>>  was just routing the interrupts from peripherals to GIC and nothing more.
>>  Also  mapping all the interrupts using interrupt-map like property by a fixed way
>>  in DTS itself was considered hacky
> 
> I'm not suggesting you should interrupt-map. I agree that that
> interrupt-map is not suitable for a dynamically configurable device like
> the crossbar.
> 
> When you say that the crossbar is just routing the interrupts, at what
> level is it doing so? Does it accept a logical interrupt and output
> another logical interrupt, or does it just connect the two lines
> electrically?
> 
Its just makes electrical connection between input and output line and
thats it.

Regards,
Santosh

Re: [PATCH V4 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Linus Walleij]

On Thu, Nov 14, 2013 at 1:18 PM, Sricharan R <r.sricharan@ti.com> wrote:

> The minimal crossbar driver to track and allocate free GIC lines and configure the
> crossbar is added here, along with the DT bindings.
>
> V4:
>    Addressed a couple of comments and split the DTS file updates in to
>    a separate series.

I'm pretty happy with the work and effort put into this now it's looking
real elegant.
FWIW: Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH V4 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

On Tuesday 19 November 2013 02:07 PM, Linus Walleij wrote:
> On Thu, Nov 14, 2013 at 1:18 PM, Sricharan R <r.sricharan@ti.com> wrote:
>
>> The minimal crossbar driver to track and allocate free GIC lines and configure the
>> crossbar is added here, along with the DT bindings.
>>
>> V4:
>>    Addressed a couple of comments and split the DTS file updates in to
>>    a separate series.
> I'm pretty happy with the work and effort put into this now it's looking
> real elegant.
> FWIW: Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
Thanks Linus.

Regards,
 Sricharan

Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Sricharan R]

Hi Mark,

Sorry for delayed response. I was away for some time.

On Friday 15 November 2013 04:53 PM, Mark Rutland wrote:
> On Thu, Nov 14, 2013 at 04:46:36PM +0000, Sricharan R wrote:
>> Hi Mark,
>>
>> On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote:
>>> On Thu, Nov 14, 2013 at 12:18:47PM +0000, Sricharan R wrote:
>>>> In some socs the gic can be preceded by a crossbar IP which
>>>> routes the peripheral interrupts to the gic inputs. The peripheral
>>>> interrupts are associated with a fixed crossbar input line and the
>>>> crossbar routes that to one of the free gic input line.
>>>>
>>>> The DT entries for peripherals provides the fixed crossbar input line
>>>> as its interrupt number and the mapping code should associate this with
>>>> a free gic input line. This patch adds the support inside the gic irqchip
>>>> to handle such routable irqs. The routable irqs are registered in a linear
>>>> domain. The registered routable domain's callback should be implemented
>>>> to get a free irq and to configure the IP to route it.
>>>>
>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>> Cc: Linus Walleij <linus.walleij@linaro.org>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Cc: Rajendra Nayak <rnayak@ti.com>
>>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>>>> Cc: Grant Likely <grant.likely@linaro.org>
>>>> Cc: Rob Herring <rob.herring@calxeda.com>
>>>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>>>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> ---
>>>>  [V2] Added default routable-irqs functions to avoid
>>>>       unnecessary if checks as per Thomas Gleixner comments
>>>>       and renamed routable-irq binding as per
>>>>       Kumar Gala <galak@codeaurora.org> comments.
>>>>
>>>>  [V3] Addressed unnecessary warn-on and updated default
>>>>       xlate function as per Thomas Gleixner comments
>>>>
>>>>  Documentation/devicetree/bindings/arm/gic.txt |    6 ++
>>>>  drivers/irqchip/irq-gic.c                     |   81 ++++++++++++++++++++++---
>>>>  include/linux/irqchip/arm-gic.h               |    7 ++-
>>>>  3 files changed, 83 insertions(+), 11 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
>>>> index 3dfb0c0..5357745 100644
>>>> --- a/Documentation/devicetree/bindings/arm/gic.txt
>>>> +++ b/Documentation/devicetree/bindings/arm/gic.txt
>>>> @@ -49,6 +49,11 @@ Optional
>>>>    regions, used when the GIC doesn't have banked registers. The offset is
>>>>    cpu-offset * cpu-nr.
>>>>  
>>>> +- arm,routable-irqs : Total number of gic irq inputs which are not directly
>>>> +		  connected from the peripherals, but are routed dynamically
>>>> +		  by a crossbar/multiplexer preceding the GIC. The GIC irq
>>>> +		  input line is assigned dynamically when the corresponding
>>>> +		  peripheral's crossbar line is mapped.
>>> I'm not keen on the design of the arm,routable-irqs property. The set of
>>> IRQs which the crossbar IP can use is a property of which IRQ lines it
>>> has routed to the GIC. I don't see why that should be considered a
>>> property of the GIC; it's a property of the crossbar IP's attachment to
>>> the GIC.
>>>
>>> Given we already have a mechanism for describing the attachment (i.e.
>>> the interrupts property) where the property appears on the node for the
>>> device generating/propagating the interrupt, I don't see why we should
>>> do differently here.
>>  We did try using interrupts=<> property for all peripherals and
>>  mapping them as crossbar's parent. But that approach of representing
>>  crossbar as a interrupt parent was not accepted, since the crossbar
>>  was just routing the interrupts from peripherals to GIC and nothing more.
>>  Also  mapping all the interrupts using interrupt-map like property by a fixed way
>>  in DTS itself was considered hacky
> I'm not suggesting you should interrupt-map. I agree that that
> interrupt-map is not suitable for a dynamically configurable device like
> the crossbar.
>
> When you say that the crossbar is just routing the interrupts, at what
> level is it doing so? Does it accept a logical interrupt and output
> another logical interrupt, or does it just connect the two lines
> electrically?
As Santosh, already mentioned this just makes a physical connection
 and thats it
>
> We don't necessarily have to use the interrupts property, but I still
> think that the set of GIC input IRQ lines that the crossbar is wired to
> should be described on the crossbar node.
>
>>> Listing 160 interrupts in the crossbar node is clearly something we
>>> don't want to have to do.  If we had a property that we could use to
>>> define a range (or multiple ranges) of interrupts, then the crossbar
>>> driver could go and request those ranges from its interrupt-parent (the
>>> GIC) and the GIC driver could reserve/allocate the irqdomain at that
>>> time.
>> Again, this kind of approach of crossbar requesting irqs from GIC
>> was tried earlier and it did not go anywhere. Subsequently after lot of
>> discussions this design was considered the best one.
>>
>> http://www.spinics.net/lists/linux-omap/msg97085.html
> As far as I can see, the comment there was to use irqdomains, which I am
> not arguing against. I am arguing that the linkage of the GIC and the
> crossbar is being described the wrong way around. The GIC input lines
> that the crossbar is wired to should be described on the crossbar node,
> and the crossbar driver should request the appropriate domain from the
> GIC.
  The comment was and there was also a code snippet suggested which
 was to use GIC's irq domain and to use GIC xlate, map, unmap functions.
 This patch simply does that.
>>> This feels like a point-hack, counter in style to the vast majority of
>>> provider/consumer bindings. It only allows for one multiplexer before
>>> the GIC. What if we had multiple multiplexers feeding into the GIC?
>>> Describing the attachment on the multiplexer allows that to be handled,
>>> describing that on the GIC does not.
>>  This is case where the interrupts to GIC is not coming from full irqchip,
>>  but just a router and support added in the GIC helps to handle
>>  such cases. In the case of more than one multiplexer, the crossbar
>>  driver should really take care of handling the downward muxes and
>>  crossbar like driver can be expanded to handle if such a scenario happens.
> That still feels like a hack. If there are multiple instances, I see no
> reason why they should have to know about each other. It's fundamentally
> at odds to the generic composable model we have now.
>
Infact it looks like this because crossbar is not full irqchip and the
whole aim here was to use the existing infrastructure best to support this.
After all discussions, this was considered the ideal way. Atleast now,
we do not have any Socs with multiple *routers* feeding in to each other.

Regards,
 Sricharan