[PATCH 0/7] AES/DES hwmod data and dmtimer fix

[PATCH 0/7] AES/DES hwmod data and dmtimer fix

[Joel Fernandes]

Here are patches adding hwmod for AES/DES crypto modules for OMAP4, DRA7 SoCs.

Also included is a fix that disables POSTED mode when dmtimer is requested.

Joel Fernandes (7):
  ARM: OMAP: hwmod: Add SYSC offsets for AES IP
  ARM: DRA7xx: hwmod: Add hwmod data for DES IP
  ARM: DRA7xx: hwmod: Add hwmod data for AES IP
  ARM: OMAP4: hwmod: Add hwmod data for AES IP
  ARM: OMAP4: hwmod: add hwmod data for DES IP
  ARM: OMAP: Disable POSTED mode for errata i103 and i767
  OMAP: AM33xx: hwmod: Correct AES module SYSC type

 arch/arm/mach-omap2/omap_hwmod.h                   |  11 +++
 .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c |   1 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         | 101 +++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c          |  78 ++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.c       |  10 ++
 arch/arm/plat-omap/include/plat/dmtimer.h          |   5 +-
 6 files changed, 205 insertions(+), 1 deletion(-)

-- 
1.8.1.2

[PATCH 1/7] ARM: OMAP: hwmod: Add SYSC offsets for AES IP

[Joel Fernandes]

The AES IP has the SIDLE offset by 2 and not 3, to allow SIDLE modes
to work for AES, we add a new SYSC type to hwmod.

Signed-off-by: Joel Fernandes <joelf@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.h             | 11 +++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.c | 10 ++++++++++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0f97d63..b2efcc8 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -41,6 +41,7 @@ struct omap_device;
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4;
 
 /*
  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
@@ -81,6 +82,16 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
 #define SYSC_TYPE3_MIDLEMODE_SHIFT	2
 #define SYSC_TYPE3_MIDLEMODE_MASK	(0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
 
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE4.
+ */
+#define SYSC_TYPE4_SIDLEMODE_SHIFT	2
+#define SYSC_TYPE4_SIDLEMODE_MASK	(0x3 << SYSC_TYPE4_SIDLEMODE_SHIFT)
+#define SYSC_TYPE4_SOFTRESET_SHIFT	1
+#define SYSC_TYPE4_SOFTRESET_MASK	(1 << SYSC_TYPE4_SOFTRESET_SHIFT)
+#define SYSC_TYPE4_AUTOIDLE_SHIFT	0
+#define SYSC_TYPE4_AUTOIDLE_MASK	(1 << SYSC_TYPE4_AUTOIDLE_SHIFT)
+
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT		0
 #define SYSS_RESETDONE_MASK		(1 << SYSS_RESETDONE_SHIFT)
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 79d623b..7443dc0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -59,6 +59,16 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
 	.sidle_shift	= SYSC_TYPE3_SIDLEMODE_SHIFT,
 };
 
+/**
+ * struct omap_hwmod_sysc_type4 - TYPE4 sysconfig scheme.
+ * Used by some IPs on AM33xx
+ */
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4 = {
+	.sidle_shift	= SYSC_TYPE4_SIDLEMODE_SHIFT,
+	.srst_shift	= SYSC_TYPE4_SOFTRESET_SHIFT,
+	.autoidle_shift	= SYSC_TYPE4_AUTOIDLE_SHIFT,
+};
+
 struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
 	.manager_count		= 2,
 	.has_framedonetv_irq	= 0
-- 
1.8.1.2

[PATCH 2/7] ARM: DRA7xx: hwmod: Add hwmod data for DES IP

[Joel Fernandes]

DRA7xx SoC has a DES module. Add hwmod data for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 39 +++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index db32d53..efae736 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -561,6 +561,23 @@ static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 	.rev	= 2,
 };
 
+static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
+	.rev_offs	= 0x0030,
+	.sysc_offs	= 0x0034,
+	.syss_offs	= 0x0038,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
+	.sysc_fields	= &omap_hwmod_sysc_type4,
+};
+
+static struct omap_hwmod_class dra7xx_des_hwmod_class = {
+	.name	= "des",
+	.sysc	= &dra7xx_des_sysc,
+	.rev	= 2,
+};
+
 /* gpio dev_attr */
 static struct omap_gpio_dev_attr gpio_dev_attr = {
 	.bank_width	= 32,
@@ -750,6 +767,19 @@ static struct omap_hwmod dra7xx_gpio8_hwmod = {
 	.dev_attr	= &gpio_dev_attr,
 };
 
+static struct omap_hwmod dra7xx_des_hwmod = {
+	.name		= "des",
+	.class		= &dra7xx_des_hwmod_class,
+	.clkdm_name	= "l4sec_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
 /*
  * 'gpmc' class
  *
@@ -2171,6 +2201,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per1 -> des */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
+	.master		= &dra7xx_l4_per1_hwmod,
+	.slave		= &dra7xx_des_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
 	{
 		.pa_start	= 0x50000000,
@@ -2705,6 +2743,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_per1__uart4,
 	&dra7xx_l4_per1__uart5,
 	&dra7xx_l4_per1__uart6,
+	&dra7xx_l4_per1__des,
 	&dra7xx_l4_per3__usb_otg_ss1,
 	&dra7xx_l4_per3__usb_otg_ss2,
 	&dra7xx_l4_per3__usb_otg_ss3,
-- 
1.8.1.2

[PATCH 3/7] ARM: DRA7xx: hwmod: Add hwmod data for AES IP

[Joel Fernandes]

DRA7xx SoC has an AES IP found also on OMAP4. Add hwmod data for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 39 +++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index efae736..5831ac6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -561,6 +561,17 @@ static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 	.rev	= 2,
 };
 
+static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
+	.rev_offs	= 0x0080,
+	.sysc_offs	= 0x0084,
+	.syss_offs	= 0x0088,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type4,
+};
+
 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
 	.rev_offs	= 0x0030,
 	.sysc_offs	= 0x0034,
@@ -572,6 +583,12 @@ static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
 	.sysc_fields	= &omap_hwmod_sysc_type4,
 };
 
+static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
+	.name	= "aes",
+	.sysc	= &dra7xx_aes_sysc,
+	.rev	= 2,
+};
+
 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
 	.name	= "des",
 	.sysc	= &dra7xx_des_sysc,
@@ -767,6 +784,19 @@ static struct omap_hwmod dra7xx_gpio8_hwmod = {
 	.dev_attr	= &gpio_dev_attr,
 };
 
+static struct omap_hwmod dra7xx_aes_hwmod = {
+	.name		= "aes",
+	.class		= &dra7xx_aes_hwmod_class,
+	.clkdm_name	= "l4sec_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
 static struct omap_hwmod dra7xx_des_hwmod = {
 	.name		= "des",
 	.class		= &dra7xx_des_hwmod_class,
@@ -2119,6 +2149,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main_1 -> aes */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_aes_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
 	{
 		.pa_start	= 0x48078000,
@@ -2695,6 +2733,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l3_main_1__dss,
 	&dra7xx_l3_main_1__dispc,
 	&dra7xx_l3_main_1__hdmi,
+	&dra7xx_l3_main_1__aes,
 	&dra7xx_l4_per1__elm,
 	&dra7xx_l4_wkup__gpio1,
 	&dra7xx_l4_per1__gpio2,
-- 
1.8.1.2

[PATCH 4/7] ARM: OMAP4: hwmod: Add hwmod data for AES IP

[Joel Fernandes]

Crypto modules AES0/1 belong to:
    PD_L4_PER power domain
    CD_L4_SEC clock domain
    On the L3, the AES modules are mapped to
    L3_CLK2: Peripherals and multimedia sub clock domain

We add hwmod data for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 54 ++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 1e5b12c..664b2c6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -4791,6 +4791,59 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/*
+    Crypto modules AES0/1 belong to:
+	PD_L4_PER power domain
+	CD_L4_SEC clock domain
+	On the L3, the AES modules are mapped to
+	L3_CLK2: Peripherals and multimedia sub clock domain
+*/
+
+static struct omap_hwmod_class_sysconfig omap4_aes1_sysc = {
+	.rev_offs	= 0x80,
+	.sysc_offs	= 0x84,
+	.syss_offs	= 0x88,
+	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+	.sysc_fields	= &omap_hwmod_sysc_type4,
+};
+
+static struct omap_hwmod_class omap4_aes1_hwmod_class = {
+	.name		= "aes1",
+	.sysc		= &omap4_aes1_sysc,
+};
+
+static struct omap_hwmod omap4_aes1_hwmod = {
+	.name		= "aes",
+	.class		= &omap4_aes1_hwmod_class,
+	.clkdm_name	= "l4_secure_clkdm",
+	.main_clk	= "aes1_fck",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* l3_main_2 -> aes1 */
+static struct omap_hwmod_addr_space omap4_aes1_addrs[] = {
+	{
+		.pa_start	= 0x4B500000,
+		.pa_end		= 0x4B500000 + SZ_1M - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if omap4_l3_main_2__aes1 = {
+	.master		= &omap44xx_l3_main_2_hwmod,
+	.slave		= &omap4_aes1_hwmod,
+	.clk		= "aes1_fck",
+	.addr		= omap4_aes1_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l3_main_1__dmm,
 	&omap44xx_mpu__dmm,
@@ -4945,6 +4998,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_abe__wd_timer3_dma,
 	&omap44xx_mpu__emif1,
 	&omap44xx_mpu__emif2,
+	&omap4_l3_main_2__aes1,
 	NULL,
 };
 
-- 
1.8.1.2

[PATCH 5/7] ARM: OMAP4: hwmod: add hwmod data for DES IP

[Joel Fernandes]

OMAP4 has a DES IP for DES and 3DES encryption, Add hwmod data for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 47 ++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 664b2c6..e0992d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -4844,6 +4844,52 @@ static struct omap_hwmod_ocp_if omap4_l3_main_2__aes1 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* DES3DES */
+static struct omap_hwmod_class_sysconfig omap4_des_sysc = {
+	.rev_offs	= 0x30,
+	.sysc_offs	= 0x34,
+	.syss_offs	= 0x38,
+	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+	.sysc_fields	= &omap_hwmod_sysc_type4,
+};
+
+static struct omap_hwmod_class omap4_des_hwmod_class = {
+	.name		= "des",
+	.sysc		= &omap4_des_sysc,
+};
+
+
+static struct omap_hwmod omap4_des_hwmod = {
+	.name		= "des",
+	.class		= &omap4_des_hwmod_class,
+	.clkdm_name	= "l4_secure_clkdm",
+	.main_clk	= "des_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+static struct omap_hwmod_addr_space omap4_des_addrs[] = {
+	{
+		.pa_start	= 0x480A4000,
+		.pa_end		= 0x481A4000,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if omap4_l4_per__des = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap4_des_hwmod,
+	.clk		= "des_fck",
+	.addr		= omap4_des_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l3_main_1__dmm,
 	&omap44xx_mpu__dmm,
@@ -4999,6 +5045,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mpu__emif1,
 	&omap44xx_mpu__emif2,
 	&omap4_l3_main_2__aes1,
+	&omap4_l4_per__des,
 	NULL,
 };
 
-- 
1.8.1.2

[PATCH 6/7] ARM: OMAP: Disable POSTED mode for errata i103 and i767

[Joel Fernandes]

Enabling of Posted mode is seen to cause problems on dmtimer modules on AM33xx
(much like other OMAPs).  Reference discussions on forums [1] [2]. Earlier
patch solving this on other OMAPs [3].

For OMAP SoCs with this errata, the fix has been to not enable Posted mode.
However, on some SoCs (atleast AM33xx) which carry this errata, Posted mode
is enabled on reset. So we not only need to ignore enabling of the POSTED bit
when the timer is requested, but also disable Posted mode if errata is present.

[1] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/285744.aspx
[2] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/270632.aspx
[3] http://www.spinics.net/lists/linux-omap/msg81770.html

Reported-by: Russ Dill <russ.dill@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Joel Fernandes <joelf@ti.com>
---
 arch/arm/plat-omap/include/plat/dmtimer.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index fb92abb..2861b15 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -336,8 +336,11 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
 	if (timer->posted)
 		return;
 
-	if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
+	if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
+		timer->posted = OMAP_TIMER_NONPOSTED;
+		__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
 		return;
+	}
 
 	__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
 			      OMAP_TIMER_CTRL_POSTED, 0);
-- 
1.8.1.2

[PATCH 7/7] OMAP: AM33xx: hwmod: Correct AES module SYSC type

[Joel Fernandes]

Use the newly added sysc type4 for AES module.

Signed-off-by: Joel Fernandes <joelf@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 0f17862..7f97863 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -209,6 +209,7 @@ static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 	.sysc_offs	= 0x84,
 	.syss_offs	= 0x88,
 	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+	.sysc_fields    = &omap_hwmod_sysc_type4,
 };
 
 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
-- 
1.8.1.2

Re: [PATCH 5/7] ARM: OMAP4: hwmod: add hwmod data for DES IP

[Tony Lindgren]

* Joel Fernandes <joelf@ti.com> [131125 13:45]:
> +
> +static struct omap_hwmod_addr_space omap4_des_addrs[] = {
> +	{
> +		.pa_start	= 0x480A4000,
> +		.pa_end		= 0x481A4000,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{ }
> +};

Let's not add new address space entries. The address
space should be already coming from device tree.

Regards,

Tony

Re: [PATCH 0/7] AES/DES hwmod data and dmtimer fix

[Tony Lindgren]

* Joel Fernandes <joelf@ti.com> [131125 13:46]:
> Here are patches adding hwmod for AES/DES crypto modules for OMAP4, DRA7 SoCs.
> 
> Also included is a fix that disables POSTED mode when dmtimer is requested.
> 
> Joel Fernandes (7):
>   ARM: OMAP: hwmod: Add SYSC offsets for AES IP
>   ARM: DRA7xx: hwmod: Add hwmod data for DES IP
>   ARM: DRA7xx: hwmod: Add hwmod data for AES IP
>   ARM: OMAP4: hwmod: Add hwmod data for AES IP
>   ARM: OMAP4: hwmod: add hwmod data for DES IP
>   ARM: OMAP: Disable POSTED mode for errata i103 and i767
>   OMAP: AM33xx: hwmod: Correct AES module SYSC type
> 
>  arch/arm/mach-omap2/omap_hwmod.h                   |  11 +++
>  .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c |   1 +
>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c         | 101 +++++++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c          |  78 ++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_common_data.c       |  10 ++
>  arch/arm/plat-omap/include/plat/dmtimer.h          |   5 +-
>  6 files changed, 205 insertions(+), 1 deletion(-)

To me it seems we should wait on these until we have the clocks
coming from device tree. That leaves out some parts of this
patchset.

Regards,

Tony

Re: [PATCH 6/7] ARM: OMAP: Disable POSTED mode for errata i103 and i767

[Tony Lindgren]

* Joel Fernandes <joelf@ti.com> [131125 13:46]:
> Enabling of Posted mode is seen to cause problems on dmtimer modules on AM33xx
> (much like other OMAPs).  Reference discussions on forums [1] [2]. Earlier
> patch solving this on other OMAPs [3].
> 
> For OMAP SoCs with this errata, the fix has been to not enable Posted mode.
> However, on some SoCs (atleast AM33xx) which carry this errata, Posted mode
> is enabled on reset. So we not only need to ignore enabling of the POSTED bit
> when the timer is requested, but also disable Posted mode if errata is present.

This could explain some occasional lost timers I saw a while back when
testing things.. We most likely should merge for the -rc series with cc stable.

Does this depend on the other patches in this series?

Regards,

Tony
 
> [1] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/285744.aspx
> [2] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/270632.aspx
> [3] http://www.spinics.net/lists/linux-omap/msg81770.html
> 
> Reported-by: Russ Dill <russ.dill@ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Joel Fernandes <joelf@ti.com>
> ---
>  arch/arm/plat-omap/include/plat/dmtimer.h | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
> index fb92abb..2861b15 100644
> --- a/arch/arm/plat-omap/include/plat/dmtimer.h
> +++ b/arch/arm/plat-omap/include/plat/dmtimer.h
> @@ -336,8 +336,11 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
>  	if (timer->posted)
>  		return;
>  
> -	if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
> +	if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
> +		timer->posted = OMAP_TIMER_NONPOSTED;
> +		__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
>  		return;
> +	}
>  
>  	__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
>  			      OMAP_TIMER_CTRL_POSTED, 0);
> -- 
> 1.8.1.2
> 

Re: [PATCH 6/7] ARM: OMAP: Disable POSTED mode for errata i103 and i767

[Joel Fernandes]

On 11/25/2013 04:14 PM, Tony Lindgren wrote:
> * Joel Fernandes <joelf@ti.com> [131125 13:46]:
>> Enabling of Posted mode is seen to cause problems on dmtimer modules on AM33xx
>> (much like other OMAPs).  Reference discussions on forums [1] [2]. Earlier
>> patch solving this on other OMAPs [3].
>>
>> For OMAP SoCs with this errata, the fix has been to not enable Posted mode.
>> However, on some SoCs (atleast AM33xx) which carry this errata, Posted mode
>> is enabled on reset. So we not only need to ignore enabling of the POSTED bit
>> when the timer is requested, but also disable Posted mode if errata is present.
> 
> This could explain some occasional lost timers I saw a while back when
> testing things.. We most likely should merge for the -rc series with cc stable.

Sure, I agree.

> 
> Does this depend on the other patches in this series?
> 

No it doesn't depend.


thanks,

-Joel

Re: [PATCH 0/7] AES/DES hwmod data and dmtimer fix

[Joel Fernandes]

On 11/25/2013 04:12 PM, Tony Lindgren wrote:
> * Joel Fernandes <joelf@ti.com> [131125 13:46]:
>> Here are patches adding hwmod for AES/DES crypto modules for OMAP4, DRA7 SoCs.
>>
>> Also included is a fix that disables POSTED mode when dmtimer is requested.
>>
>> Joel Fernandes (7):
>>   ARM: OMAP: hwmod: Add SYSC offsets for AES IP
>>   ARM: DRA7xx: hwmod: Add hwmod data for DES IP
>>   ARM: DRA7xx: hwmod: Add hwmod data for AES IP
>>   ARM: OMAP4: hwmod: Add hwmod data for AES IP
>>   ARM: OMAP4: hwmod: add hwmod data for DES IP
>>   ARM: OMAP: Disable POSTED mode for errata i103 and i767
>>   OMAP: AM33xx: hwmod: Correct AES module SYSC type
>>
>>  arch/arm/mach-omap2/omap_hwmod.h                   |  11 +++
>>  .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c |   1 +
>>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c         | 101 +++++++++++++++++++++
>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c          |  78 ++++++++++++++++
>>  arch/arm/mach-omap2/omap_hwmod_common_data.c       |  10 ++
>>  arch/arm/plat-omap/include/plat/dmtimer.h          |   5 +-
>>  6 files changed, 205 insertions(+), 1 deletion(-)
> 
> To me it seems we should wait on these until we have the clocks
> coming from device tree. That leaves out some parts of this
> patchset.
> 

Ok, sure. Let me see which parts can go in now till DT entries are available. If
it doesn't make sense to apply these now, I'll revise and post them again later
once clock data is merged.

thanks,

-Joel

Re: [PATCH 5/7] ARM: OMAP4: hwmod: add hwmod data for DES IP

[Joel Fernandes]

On 11/25/2013 04:11 PM, Tony Lindgren wrote:
> * Joel Fernandes <joelf@ti.com> [131125 13:45]:
>> +
>> +static struct omap_hwmod_addr_space omap4_des_addrs[] = {
>> +	{
>> +		.pa_start	= 0x480A4000,
>> +		.pa_end		= 0x481A4000,
>> +		.flags		= ADDR_TYPE_RT
>> +	},
>> +	{ }
>> +};
> 
> Let's not add new address space entries. The address
> space should be already coming from device tree.
> 
Sorry, yes. that's true - I'll drop these.

thanks,

-Joel

Re: [PATCH 6/7] ARM: OMAP: Disable POSTED mode for errata i103 and i767

[Tony Lindgren]

* Joel Fernandes <joelf@ti.com> [131125 14:18]:
> On 11/25/2013 04:14 PM, Tony Lindgren wrote:
> > * Joel Fernandes <joelf@ti.com> [131125 13:46]:
> >> Enabling of Posted mode is seen to cause problems on dmtimer modules on AM33xx
> >> (much like other OMAPs).  Reference discussions on forums [1] [2]. Earlier
> >> patch solving this on other OMAPs [3].
> >>
> >> For OMAP SoCs with this errata, the fix has been to not enable Posted mode.
> >> However, on some SoCs (atleast AM33xx) which carry this errata, Posted mode
> >> is enabled on reset. So we not only need to ignore enabling of the POSTED bit
> >> when the timer is requested, but also disable Posted mode if errata is present.
> > 
> > This could explain some occasional lost timers I saw a while back when
> > testing things.. We most likely should merge for the -rc series with cc stable.
> 
> Sure, I agree.
> 
> > 
> > Does this depend on the other patches in this series?
> > 
> 
> No it doesn't depend.

OK thanks applying into omap-for-v3.13/fixes-take4.

Tony