* [PATCH v3 1/7] pinctrl: sunxi: check clk_prepare_enable return value
2014-04-10 13:52 [PATCH v3 0/7] ARM: sunxi: add multi pin controller support Boris BREZILLON
@ 2014-04-10 13:52 ` Boris BREZILLON
2014-04-11 13:05 ` Maxime Ripard
2014-04-22 11:39 ` Linus Walleij
2014-04-10 13:52 ` [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller Boris BREZILLON
` (5 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-10 13:52 UTC (permalink / raw)
To: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Linus Walleij, Chen-Yu Tsai, Hans de Goede
Cc: Shuge, kevin, devicetree, linux-doc, linux-arm-kernel,
linux-kernel, dev, Boris BREZILLON
Check the clk_prepare_enable return value to avoid false positive probe.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
drivers/pinctrl/pinctrl-sunxi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index f9fabe9..2d9ca1c 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -884,7 +884,9 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
goto gpiochip_error;
}
- clk_prepare_enable(clk);
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ goto gpiochip_error;
pctl->irq = irq_of_parse_and_map(node, 0);
if (!pctl->irq) {
--
1.8.3.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/7] pinctrl: sunxi: check clk_prepare_enable return value
2014-04-10 13:52 ` [PATCH v3 1/7] pinctrl: sunxi: check clk_prepare_enable return value Boris BREZILLON
@ 2014-04-11 13:05 ` Maxime Ripard
2014-04-22 11:39 ` Linus Walleij
1 sibling, 0 replies; 21+ messages in thread
From: Maxime Ripard @ 2014-04-11 13:05 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Emilio López, Mike Turquette, Linus Walleij,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
[-- Attachment #1: Type: text/plain, Size: 417 bytes --]
Hi
On Thu, Apr 10, 2014 at 03:52:40PM +0200, Boris BREZILLON wrote:
> Check the clk_prepare_enable return value to avoid false positive probe.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/7] pinctrl: sunxi: check clk_prepare_enable return value
2014-04-10 13:52 ` [PATCH v3 1/7] pinctrl: sunxi: check clk_prepare_enable return value Boris BREZILLON
2014-04-11 13:05 ` Maxime Ripard
@ 2014-04-22 11:39 ` Linus Walleij
1 sibling, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2014-04-22 11:39 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
<boris.brezillon@free-electrons.com> wrote:
> Check the clk_prepare_enable return value to avoid false positive probe.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller
2014-04-10 13:52 [PATCH v3 0/7] ARM: sunxi: add multi pin controller support Boris BREZILLON
2014-04-10 13:52 ` [PATCH v3 1/7] pinctrl: sunxi: check clk_prepare_enable return value Boris BREZILLON
@ 2014-04-10 13:52 ` Boris BREZILLON
2014-04-11 13:06 ` Maxime Ripard
2014-04-22 11:40 ` Linus Walleij
2014-04-10 13:52 ` [PATCH v3 3/7] pinctrl: sunxi: add PL and PM pin definitions Boris BREZILLON
` (4 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-10 13:52 UTC (permalink / raw)
To: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Linus Walleij, Chen-Yu Tsai, Hans de Goede
Cc: Shuge, kevin, devicetree, linux-doc, linux-arm-kernel,
linux-kernel, dev, Boris BREZILLON
Disable the clk when failing to probe the pin controller device.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
drivers/pinctrl/pinctrl-sunxi.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 2d9ca1c..73d11e2 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -891,7 +891,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
pctl->irq = irq_of_parse_and_map(node, 0);
if (!pctl->irq) {
ret = -EINVAL;
- goto gpiochip_error;
+ goto clk_error;
}
pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
@@ -899,7 +899,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
if (!pctl->domain) {
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
ret = -ENOMEM;
- goto gpiochip_error;
+ goto clk_error;
}
for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
@@ -917,6 +917,8 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
return 0;
+clk_error:
+ clk_disable_unprepare(clk);
gpiochip_error:
if (gpiochip_remove(pctl->chip))
dev_err(&pdev->dev, "failed to remove gpio chip\n");
--
1.8.3.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller
2014-04-10 13:52 ` [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller Boris BREZILLON
@ 2014-04-11 13:06 ` Maxime Ripard
2014-04-22 11:40 ` Linus Walleij
1 sibling, 0 replies; 21+ messages in thread
From: Maxime Ripard @ 2014-04-11 13:06 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Emilio López, Mike Turquette, Linus Walleij,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
[-- Attachment #1: Type: text/plain, Size: 395 bytes --]
On Thu, Apr 10, 2014 at 03:52:41PM +0200, Boris BREZILLON wrote:
> Disable the clk when failing to probe the pin controller device.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller
2014-04-10 13:52 ` [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller Boris BREZILLON
2014-04-11 13:06 ` Maxime Ripard
@ 2014-04-22 11:40 ` Linus Walleij
1 sibling, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2014-04-22 11:40 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
<boris.brezillon@free-electrons.com> wrote:
> Disable the clk when failing to probe the pin controller device.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 3/7] pinctrl: sunxi: add PL and PM pin definitions
2014-04-10 13:52 [PATCH v3 0/7] ARM: sunxi: add multi pin controller support Boris BREZILLON
2014-04-10 13:52 ` [PATCH v3 1/7] pinctrl: sunxi: check clk_prepare_enable return value Boris BREZILLON
2014-04-10 13:52 ` [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller Boris BREZILLON
@ 2014-04-10 13:52 ` Boris BREZILLON
2014-04-22 11:41 ` Linus Walleij
2014-04-10 13:52 ` [PATCH v3 4/7] pinctrl: sunxi: support multiple pin controller Boris BREZILLON
` (3 subsequent siblings)
6 siblings, 1 reply; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-10 13:52 UTC (permalink / raw)
To: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Linus Walleij, Chen-Yu Tsai, Hans de Goede
Cc: Shuge, kevin, devicetree, linux-doc, linux-arm-kernel,
linux-kernel, dev, Boris BREZILLON
Define PL and PM pin macros.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/pinctrl/pinctrl-sunxi.h | 68 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index 552b0e9..ed3c4d7 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -25,6 +25,8 @@
#define PG_BASE 192
#define PH_BASE 224
#define PI_BASE 256
+#define PL_BASE 352
+#define PM_BASE 384
#define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0")
#define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1")
@@ -323,6 +325,72 @@
#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
+#define SUNXI_PINCTRL_PIN_PL0 PINCTRL_PIN(PL_BASE + 0, "PL0")
+#define SUNXI_PINCTRL_PIN_PL1 PINCTRL_PIN(PL_BASE + 1, "PL1")
+#define SUNXI_PINCTRL_PIN_PL2 PINCTRL_PIN(PL_BASE + 2, "PL2")
+#define SUNXI_PINCTRL_PIN_PL3 PINCTRL_PIN(PL_BASE + 3, "PL3")
+#define SUNXI_PINCTRL_PIN_PL4 PINCTRL_PIN(PL_BASE + 4, "PL4")
+#define SUNXI_PINCTRL_PIN_PL5 PINCTRL_PIN(PL_BASE + 5, "PL5")
+#define SUNXI_PINCTRL_PIN_PL6 PINCTRL_PIN(PL_BASE + 6, "PL6")
+#define SUNXI_PINCTRL_PIN_PL7 PINCTRL_PIN(PL_BASE + 7, "PL7")
+#define SUNXI_PINCTRL_PIN_PL8 PINCTRL_PIN(PL_BASE + 8, "PL8")
+#define SUNXI_PINCTRL_PIN_PL9 PINCTRL_PIN(PL_BASE + 9, "PL9")
+#define SUNXI_PINCTRL_PIN_PL10 PINCTRL_PIN(PL_BASE + 10, "PL10")
+#define SUNXI_PINCTRL_PIN_PL11 PINCTRL_PIN(PL_BASE + 11, "PL11")
+#define SUNXI_PINCTRL_PIN_PL12 PINCTRL_PIN(PL_BASE + 12, "PL12")
+#define SUNXI_PINCTRL_PIN_PL13 PINCTRL_PIN(PL_BASE + 13, "PL13")
+#define SUNXI_PINCTRL_PIN_PL14 PINCTRL_PIN(PL_BASE + 14, "PL14")
+#define SUNXI_PINCTRL_PIN_PL15 PINCTRL_PIN(PL_BASE + 15, "PL15")
+#define SUNXI_PINCTRL_PIN_PL16 PINCTRL_PIN(PL_BASE + 16, "PL16")
+#define SUNXI_PINCTRL_PIN_PL17 PINCTRL_PIN(PL_BASE + 17, "PL17")
+#define SUNXI_PINCTRL_PIN_PL18 PINCTRL_PIN(PL_BASE + 18, "PL18")
+#define SUNXI_PINCTRL_PIN_PL19 PINCTRL_PIN(PL_BASE + 19, "PL19")
+#define SUNXI_PINCTRL_PIN_PL20 PINCTRL_PIN(PL_BASE + 20, "PL20")
+#define SUNXI_PINCTRL_PIN_PL21 PINCTRL_PIN(PL_BASE + 21, "PL21")
+#define SUNXI_PINCTRL_PIN_PL22 PINCTRL_PIN(PL_BASE + 22, "PL22")
+#define SUNXI_PINCTRL_PIN_PL23 PINCTRL_PIN(PL_BASE + 23, "PL23")
+#define SUNXI_PINCTRL_PIN_PL24 PINCTRL_PIN(PL_BASE + 24, "PL24")
+#define SUNXI_PINCTRL_PIN_PL25 PINCTRL_PIN(PL_BASE + 25, "PL25")
+#define SUNXI_PINCTRL_PIN_PL26 PINCTRL_PIN(PL_BASE + 26, "PL26")
+#define SUNXI_PINCTRL_PIN_PL27 PINCTRL_PIN(PL_BASE + 27, "PL27")
+#define SUNXI_PINCTRL_PIN_PL28 PINCTRL_PIN(PL_BASE + 28, "PL28")
+#define SUNXI_PINCTRL_PIN_PL29 PINCTRL_PIN(PL_BASE + 29, "PL29")
+#define SUNXI_PINCTRL_PIN_PL30 PINCTRL_PIN(PL_BASE + 30, "PL30")
+#define SUNXI_PINCTRL_PIN_PL31 PINCTRL_PIN(PL_BASE + 31, "PL31")
+
+#define SUNXI_PINCTRL_PIN_PM0 PINCTRL_PIN(PM_BASE + 0, "PM0")
+#define SUNXI_PINCTRL_PIN_PM1 PINCTRL_PIN(PM_BASE + 1, "PM1")
+#define SUNXI_PINCTRL_PIN_PM2 PINCTRL_PIN(PM_BASE + 2, "PM2")
+#define SUNXI_PINCTRL_PIN_PM3 PINCTRL_PIN(PM_BASE + 3, "PM3")
+#define SUNXI_PINCTRL_PIN_PM4 PINCTRL_PIN(PM_BASE + 4, "PM4")
+#define SUNXI_PINCTRL_PIN_PM5 PINCTRL_PIN(PM_BASE + 5, "PM5")
+#define SUNXI_PINCTRL_PIN_PM6 PINCTRL_PIN(PM_BASE + 6, "PM6")
+#define SUNXI_PINCTRL_PIN_PM7 PINCTRL_PIN(PM_BASE + 7, "PM7")
+#define SUNXI_PINCTRL_PIN_PM8 PINCTRL_PIN(PM_BASE + 8, "PM8")
+#define SUNXI_PINCTRL_PIN_PM9 PINCTRL_PIN(PM_BASE + 9, "PM9")
+#define SUNXI_PINCTRL_PIN_PM10 PINCTRL_PIN(PM_BASE + 10, "PM10")
+#define SUNXI_PINCTRL_PIN_PM11 PINCTRL_PIN(PM_BASE + 11, "PM11")
+#define SUNXI_PINCTRL_PIN_PM12 PINCTRL_PIN(PM_BASE + 12, "PM12")
+#define SUNXI_PINCTRL_PIN_PM13 PINCTRL_PIN(PM_BASE + 13, "PM13")
+#define SUNXI_PINCTRL_PIN_PM14 PINCTRL_PIN(PM_BASE + 14, "PM14")
+#define SUNXI_PINCTRL_PIN_PM15 PINCTRL_PIN(PM_BASE + 15, "PM15")
+#define SUNXI_PINCTRL_PIN_PM16 PINCTRL_PIN(PM_BASE + 16, "PM16")
+#define SUNXI_PINCTRL_PIN_PM17 PINCTRL_PIN(PM_BASE + 17, "PM17")
+#define SUNXI_PINCTRL_PIN_PM18 PINCTRL_PIN(PM_BASE + 18, "PM18")
+#define SUNXI_PINCTRL_PIN_PM19 PINCTRL_PIN(PM_BASE + 19, "PM19")
+#define SUNXI_PINCTRL_PIN_PM20 PINCTRL_PIN(PM_BASE + 20, "PM20")
+#define SUNXI_PINCTRL_PIN_PM21 PINCTRL_PIN(PM_BASE + 21, "PM21")
+#define SUNXI_PINCTRL_PIN_PM22 PINCTRL_PIN(PM_BASE + 22, "PM22")
+#define SUNXI_PINCTRL_PIN_PM23 PINCTRL_PIN(PM_BASE + 23, "PM23")
+#define SUNXI_PINCTRL_PIN_PM24 PINCTRL_PIN(PM_BASE + 24, "PM24")
+#define SUNXI_PINCTRL_PIN_PM25 PINCTRL_PIN(PM_BASE + 25, "PM25")
+#define SUNXI_PINCTRL_PIN_PM26 PINCTRL_PIN(PM_BASE + 26, "PM26")
+#define SUNXI_PINCTRL_PIN_PM27 PINCTRL_PIN(PM_BASE + 27, "PM27")
+#define SUNXI_PINCTRL_PIN_PM28 PINCTRL_PIN(PM_BASE + 28, "PM28")
+#define SUNXI_PINCTRL_PIN_PM29 PINCTRL_PIN(PM_BASE + 29, "PM29")
+#define SUNXI_PINCTRL_PIN_PM30 PINCTRL_PIN(PM_BASE + 30, "PM30")
+#define SUNXI_PINCTRL_PIN_PM31 PINCTRL_PIN(PM_BASE + 31, "PM31")
+
#define SUNXI_PIN_NAME_MAX_LEN 5
#define BANK_MEM_SIZE 0x24
--
1.8.3.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/7] pinctrl: sunxi: add PL and PM pin definitions
2014-04-10 13:52 ` [PATCH v3 3/7] pinctrl: sunxi: add PL and PM pin definitions Boris BREZILLON
@ 2014-04-22 11:41 ` Linus Walleij
0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2014-04-22 11:41 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
<boris.brezillon@free-electrons.com> wrote:
> Define PL and PM pin macros.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 4/7] pinctrl: sunxi: support multiple pin controller
2014-04-10 13:52 [PATCH v3 0/7] ARM: sunxi: add multi pin controller support Boris BREZILLON
` (2 preceding siblings ...)
2014-04-10 13:52 ` [PATCH v3 3/7] pinctrl: sunxi: add PL and PM pin definitions Boris BREZILLON
@ 2014-04-10 13:52 ` Boris BREZILLON
2014-04-22 11:43 ` Linus Walleij
2014-04-10 13:52 ` [PATCH v3 5/7] pinctrl: sunxi: define A31 R_PIO pin functions Boris BREZILLON
` (2 subsequent siblings)
6 siblings, 1 reply; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-10 13:52 UTC (permalink / raw)
To: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Linus Walleij, Chen-Yu Tsai, Hans de Goede
Cc: Shuge, kevin, devicetree, linux-doc, linux-arm-kernel,
linux-kernel, dev, Boris BREZILLON
Add support for multiple pin controller instances.
First remove the static definition of the sunxi gpio chip struct and fill
the dynamically struct instead.
Then define a new pin_base field in the sunxi_pinctrl_desc which will be
used to specify the gpiochip base pin.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/pinctrl/pinctrl-sunxi.c | 30 ++++++++++++++----------------
drivers/pinctrl/pinctrl-sunxi.h | 1 +
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 73d11e2..6db1c9e 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -538,19 +538,6 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
return irq_find_mapping(pctl->domain, desc->irqnum);
}
-static struct gpio_chip sunxi_pinctrl_gpio_chip = {
- .owner = THIS_MODULE,
- .request = sunxi_pinctrl_gpio_request,
- .free = sunxi_pinctrl_gpio_free,
- .direction_input = sunxi_pinctrl_gpio_direction_input,
- .direction_output = sunxi_pinctrl_gpio_direction_output,
- .get = sunxi_pinctrl_gpio_get,
- .set = sunxi_pinctrl_gpio_set,
- .of_xlate = sunxi_pinctrl_gpio_of_xlate,
- .to_irq = sunxi_pinctrl_gpio_to_irq,
- .of_gpio_n_cells = 3,
- .can_sleep = false,
-};
static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
unsigned int type)
@@ -858,11 +845,22 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
}
last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
- pctl->chip = &sunxi_pinctrl_gpio_chip;
- pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
+ pctl->chip->owner = THIS_MODULE;
+ pctl->chip->request = sunxi_pinctrl_gpio_request,
+ pctl->chip->free = sunxi_pinctrl_gpio_free,
+ pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
+ pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
+ pctl->chip->get = sunxi_pinctrl_gpio_get,
+ pctl->chip->set = sunxi_pinctrl_gpio_set,
+ pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
+ pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
+ pctl->chip->of_gpio_n_cells = 3,
+ pctl->chip->can_sleep = false,
+ pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
+ pctl->desc->pin_base;
pctl->chip->label = dev_name(&pdev->dev);
pctl->chip->dev = &pdev->dev;
- pctl->chip->base = 0;
+ pctl->chip->base = pctl->desc->pin_base;
ret = gpiochip_add(pctl->chip);
if (ret)
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index ed3c4d7..35d15b2 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -450,6 +450,7 @@ struct sunxi_pinctrl_desc {
int npins;
struct pinctrl_gpio_range *ranges;
int nranges;
+ unsigned pin_base;
};
struct sunxi_pinctrl_function {
--
1.8.3.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 4/7] pinctrl: sunxi: support multiple pin controller
2014-04-10 13:52 ` [PATCH v3 4/7] pinctrl: sunxi: support multiple pin controller Boris BREZILLON
@ 2014-04-22 11:43 ` Linus Walleij
0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2014-04-22 11:43 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
<boris.brezillon@free-electrons.com> wrote:
> Add support for multiple pin controller instances.
>
> First remove the static definition of the sunxi gpio chip struct and fill
> the dynamically struct instead.
> Then define a new pin_base field in the sunxi_pinctrl_desc which will be
> used to specify the gpiochip base pin.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 5/7] pinctrl: sunxi: define A31 R_PIO pin functions
2014-04-10 13:52 [PATCH v3 0/7] ARM: sunxi: add multi pin controller support Boris BREZILLON
` (3 preceding siblings ...)
2014-04-10 13:52 ` [PATCH v3 4/7] pinctrl: sunxi: support multiple pin controller Boris BREZILLON
@ 2014-04-10 13:52 ` Boris BREZILLON
2014-04-22 11:47 ` Linus Walleij
2014-04-10 13:52 ` [PATCH v3 6/7] pinctrl: sunxi: add reset control support Boris BREZILLON
2014-04-10 13:52 ` [PATCH v3 7/7] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch Boris BREZILLON
6 siblings, 1 reply; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-10 13:52 UTC (permalink / raw)
To: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Linus Walleij, Chen-Yu Tsai, Hans de Goede
Cc: Shuge, kevin, devicetree, linux-doc, linux-arm-kernel,
linux-kernel, dev, Boris BREZILLON
The A31 SoC provides both PL and PM pio bank through the R_PIO block.
These pins all support gpio function and can bbe assigned to system
peripherals (like TWI, P2WI, JTAG, ...)
Add new compatible string to the DT bindings doc.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/pinctrl-sunxi-pins.h | 74 ++++++++++++++++++++++
drivers/pinctrl/pinctrl-sunxi.c | 1 +
3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index f5da7e3..d8d0656 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -11,6 +11,7 @@ Required properties:
"allwinner,sun5i-a10s-pinctrl"
"allwinner,sun5i-a13-pinctrl"
"allwinner,sun6i-a31-pinctrl"
+ "allwinner,sun6i-a31-r-pinctrl"
"allwinner,sun7i-a20-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 3d60669..51100ca 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -2820,6 +2820,74 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
};
+static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL2,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL3,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL4,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL5,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL6,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL7,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL8,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM0,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM1,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM2,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "1wire")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM3,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM4,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM5,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM6,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM7,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
+};
+
static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -3855,6 +3923,12 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
.npins = ARRAY_SIZE(sun6i_a31_pins),
};
+static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
+ .pins = sun6i_a31_r_pins,
+ .npins = ARRAY_SIZE(sun6i_a31_r_pins),
+ .pin_base = PL_BASE,
+};
+
static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
.pins = sun7i_a20_pins,
.npins = ARRAY_SIZE(sun7i_a20_pins),
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 6db1c9e..17b5f80 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -677,6 +677,7 @@ static struct of_device_id sunxi_pinctrl_match[] = {
{ .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
{ .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
{ .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
+ { .compatible = "allwinner,sun6i-a31-r-pinctrl", .data = (void *)&sun6i_a31_r_pinctrl_data },
{ .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
{}
};
--
1.8.3.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 5/7] pinctrl: sunxi: define A31 R_PIO pin functions
2014-04-10 13:52 ` [PATCH v3 5/7] pinctrl: sunxi: define A31 R_PIO pin functions Boris BREZILLON
@ 2014-04-22 11:47 ` Linus Walleij
2014-04-22 13:27 ` Boris BREZILLON
0 siblings, 1 reply; 21+ messages in thread
From: Linus Walleij @ 2014-04-22 11:47 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
<boris.brezillon@free-electrons.com> wrote:
> The A31 SoC provides both PL and PM pio bank through the R_PIO block.
>
> These pins all support gpio function and can bbe assigned to system
> peripherals (like TWI, P2WI, JTAG, ...)
>
> Add new compatible string to the DT bindings doc.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
PARTLY APPLIED.
The patch to the DT bindings apparently depend on some
patch that I do *NOT* have in my tree, please figure out what is
going on here and help me figure out what and how to apply the
changes to the bindings.
The hunk adding the docs was dropped from the patch, please
develop new series on top of my pinctrl devel branch as I
push it out.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 5/7] pinctrl: sunxi: define A31 R_PIO pin functions
2014-04-22 11:47 ` Linus Walleij
@ 2014-04-22 13:27 ` Boris BREZILLON
0 siblings, 0 replies; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-22 13:27 UTC (permalink / raw)
To: Linus Walleij
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
On 22/04/2014 13:47, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
> <boris.brezillon@free-electrons.com> wrote:
>
>> The A31 SoC provides both PL and PM pio bank through the R_PIO block.
>>
>> These pins all support gpio function and can bbe assigned to system
>> peripherals (like TWI, P2WI, JTAG, ...)
>>
>> Add new compatible string to the DT bindings doc.
>>
>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> PARTLY APPLIED.
>
> The patch to the DT bindings apparently depend on some
> patch that I do *NOT* have in my tree, please figure out what is
> going on here and help me figure out what and how to apply the
> changes to the bindings.
Oops: I dropped the patch documenting existing compatible strings in
this version ([1]).
>
> The hunk adding the docs was dropped from the patch, please
> develop new series on top of my pinctrl devel branch as I
> push it out.
Sure, I'll make a new patch listing all compatible strings (including
this new one) in the sunxi pinctrl DT bindings doc.
Thanks,
Boris
[1] https://lkml.org/lkml/2014/4/9/258
>
> Yours,
> Linus Walleij
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 6/7] pinctrl: sunxi: add reset control support
2014-04-10 13:52 [PATCH v3 0/7] ARM: sunxi: add multi pin controller support Boris BREZILLON
` (4 preceding siblings ...)
2014-04-10 13:52 ` [PATCH v3 5/7] pinctrl: sunxi: define A31 R_PIO pin functions Boris BREZILLON
@ 2014-04-10 13:52 ` Boris BREZILLON
2014-04-11 13:07 ` Maxime Ripard
2014-04-22 11:48 ` Linus Walleij
2014-04-10 13:52 ` [PATCH v3 7/7] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch Boris BREZILLON
6 siblings, 2 replies; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-10 13:52 UTC (permalink / raw)
To: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Linus Walleij, Chen-Yu Tsai, Hans de Goede
Cc: Shuge, kevin, devicetree, linux-doc, linux-arm-kernel,
linux-kernel, dev, Boris BREZILLON
The A31 SoC define a reset line for the R_PIO block which needs to be
deasserted.
Try to retrieve a reset control and deassert if one was found.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
drivers/pinctrl/pinctrl-sunxi.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 17b5f80..07af35a 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -26,6 +26,7 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include "core.h"
@@ -792,6 +793,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
const struct of_device_id *device;
struct pinctrl_pin_desc *pins;
struct sunxi_pinctrl *pctl;
+ struct reset_control *rstc;
int i, ret, last_pin;
struct clk *clk;
@@ -887,10 +889,17 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
if (ret)
goto gpiochip_error;
+ rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
+ if (!IS_ERR(rstc)) {
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ goto clk_error;
+ }
+
pctl->irq = irq_of_parse_and_map(node, 0);
if (!pctl->irq) {
ret = -EINVAL;
- goto clk_error;
+ goto rstc_error;
}
pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
@@ -898,7 +907,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
if (!pctl->domain) {
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
ret = -ENOMEM;
- goto clk_error;
+ goto rstc_error;
}
for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
@@ -916,6 +925,9 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
return 0;
+rstc_error:
+ if (!IS_ERR(rstc))
+ reset_control_assert(rstc);
clk_error:
clk_disable_unprepare(clk);
gpiochip_error:
--
1.8.3.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 6/7] pinctrl: sunxi: add reset control support
2014-04-10 13:52 ` [PATCH v3 6/7] pinctrl: sunxi: add reset control support Boris BREZILLON
@ 2014-04-11 13:07 ` Maxime Ripard
2014-04-22 11:48 ` Linus Walleij
1 sibling, 0 replies; 21+ messages in thread
From: Maxime Ripard @ 2014-04-11 13:07 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Emilio López, Mike Turquette, Linus Walleij,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
[-- Attachment #1: Type: text/plain, Size: 492 bytes --]
Hi,
On Thu, Apr 10, 2014 at 03:52:45PM +0200, Boris BREZILLON wrote:
> The A31 SoC define a reset line for the R_PIO block which needs to be
> deasserted.
>
> Try to retrieve a reset control and deassert if one was found.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 6/7] pinctrl: sunxi: add reset control support
2014-04-10 13:52 ` [PATCH v3 6/7] pinctrl: sunxi: add reset control support Boris BREZILLON
2014-04-11 13:07 ` Maxime Ripard
@ 2014-04-22 11:48 ` Linus Walleij
1 sibling, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2014-04-22 11:48 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev
On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
<boris.brezillon@free-electrons.com> wrote:
> The A31 SoC define a reset line for the R_PIO block which needs to be
> deasserted.
>
> Try to retrieve a reset control and deassert if one was found.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 7/7] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch
2014-04-10 13:52 [PATCH v3 0/7] ARM: sunxi: add multi pin controller support Boris BREZILLON
` (5 preceding siblings ...)
2014-04-10 13:52 ` [PATCH v3 6/7] pinctrl: sunxi: add reset control support Boris BREZILLON
@ 2014-04-10 13:52 ` Boris BREZILLON
2014-04-22 11:51 ` Linus Walleij
6 siblings, 1 reply; 21+ messages in thread
From: Boris BREZILLON @ 2014-04-10 13:52 UTC (permalink / raw)
To: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Linus Walleij, Chen-Yu Tsai, Hans de Goede
Cc: Shuge, kevin, devicetree, linux-doc, linux-arm-kernel,
linux-kernel, dev, Boris BREZILLON
The A31 SoC has PL and PM banks and thus increase the default ARCH_NR_GPIO.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5db05f6a..ee096bf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1644,9 +1644,9 @@ config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
+ default 416 if ARCH_SUNXI
default 392 if ARCH_U8500
default 352 if ARCH_VT8500
- default 288 if ARCH_SUNXI
default 264 if MACH_H4700
default 0
help
--
1.8.3.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 7/7] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch
2014-04-10 13:52 ` [PATCH v3 7/7] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch Boris BREZILLON
@ 2014-04-22 11:51 ` Linus Walleij
2014-04-22 14:20 ` Arnd Bergmann
0 siblings, 1 reply; 21+ messages in thread
From: Linus Walleij @ 2014-04-22 11:51 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Randy Dunlap, Maxime Ripard, Emilio López, Mike Turquette,
Chen-Yu Tsai, Hans de Goede, Shuge, kevin, devicetree, linux-doc,
linux-arm-kernel, linux-kernel, dev, Alexandre Courbot, arm
On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
<boris.brezillon@free-electrons.com> wrote:
> The A31 SoC has PL and PM banks and thus increase the default ARCH_NR_GPIO.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Patch applied, and grrrr we need to get rid of these static #gpios defines
in the long run.
ARM SoC folks: notice this hitting arch/arm/Kconfig, complain if it's
problematic.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 7/7] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch
2014-04-22 11:51 ` Linus Walleij
@ 2014-04-22 14:20 ` Arnd Bergmann
2014-04-23 13:54 ` Linus Walleij
0 siblings, 1 reply; 21+ messages in thread
From: Arnd Bergmann @ 2014-04-22 14:20 UTC (permalink / raw)
To: Linus Walleij
Cc: Boris BREZILLON, Randy Dunlap, Maxime Ripard, Emilio López,
Mike Turquette, Chen-Yu Tsai, Hans de Goede, Shuge, kevin,
devicetree, linux-doc, linux-arm-kernel, linux-kernel, dev,
Alexandre Courbot, arm
On Tuesday 22 April 2014, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 3:52 PM, Boris BREZILLON
> <boris.brezillon@free-electrons.com> wrote:
>
> > The A31 SoC has PL and PM banks and thus increase the default ARCH_NR_GPIO.
> >
> > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Patch applied, and grrrr we need to get rid of these static #gpios defines
> in the long run.
Yes, that would be nice. I guess the gpio-descriptor framework should
have solved this, but we can't move everything over to that soon, right?
> ARM SoC folks: notice this hitting arch/arm/Kconfig, complain if it's
> problematic.
Thanks for letting us know about it.
Arnd
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 7/7] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch
2014-04-22 14:20 ` Arnd Bergmann
@ 2014-04-23 13:54 ` Linus Walleij
0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2014-04-23 13:54 UTC (permalink / raw)
To: Arnd Bergmann, Alexandre Courbot
Cc: Boris BREZILLON, Randy Dunlap, Maxime Ripard, Emilio López,
Mike Turquette, Chen-Yu Tsai, Hans de Goede, Shuge, kevin,
devicetree, linux-doc, linux-arm-kernel, linux-kernel, dev, arm
On Tue, Apr 22, 2014 at 4:20 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> Patch applied, and grrrr we need to get rid of these static #gpios defines
>> in the long run.
>
> Yes, that would be nice. I guess the gpio-descriptor framework should
> have solved this, but we can't move everything over to that soon, right?
Not really, it has to happen platform by platform.
I did consider putting all the GPIO descriptors into a radix and
use that internally in gpiolib, but that wasn't easy to do
when I tried it, maybe I just thought backwards.
I would appreciate if drivers for new archs like arm64 would
use only GPIO descriptors from day one. Also if new drivers
only apply a an entirely new machine even. They should just
use descriptors.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread