[PATCH v3 0/2] ARM: sunxi: Add A31 High Speed Timer Support

[PATCH v3 0/2] ARM: sunxi: Add A31 High Speed Timer Support

[Maxime Ripard]

Hi everyone,

This patchset enables support for the High Speed Timer IP found in the
Allwinner A31 SoCs.

These timers are asserted in reset, and are not associated with any
struct device, so we also add a small helper to the reset framework
along the way to be able to retrieve the reset controller from the
device tree directly.

Thanks,
Maxime

Changes from v2:
  - Rebased on top of 3.15-rc1

Changes from v1:
  - Rebased on top of 3.14-rc1 and reset/for_3.15

Maxime Ripard (2):
  clocksource: sun5i: Add support for reset controller
  ARM: sun6i: a31: Add support for the High Speed Timers

 .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt |  4 ++++
 arch/arm/boot/dts/sun6i-a31.dtsi                              | 11 +++++++++++
 drivers/clocksource/timer-sun5i.c                             |  6 ++++++
 3 files changed, 21 insertions(+)

-- 
1.9.1

[PATCH v3 1/2] clocksource: sun5i: Add support for reset controller

[Maxime Ripard]

The Allwinner A31 that uses this timer has the timer IP asserted in reset.
Add an optional reset property to the DT, and deassert the timer from reset if
it's there.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt       | 4 ++++
 drivers/clocksource/timer-sun5i.c                                   | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
index 7c26154b8bbb..27cfc7d7ccd7 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
@@ -9,6 +9,9 @@ Required properties:
 		one)
 - clocks: phandle to the source clock (usually the AHB clock)
 
+Optionnal properties:
+- resets: phandle to a reset controller asserting the timer
+
 Example:
 
 timer@01c60000 {
@@ -19,4 +22,5 @@ timer@01c60000 {
 		     <0 53 1>,
 		     <0 54 1>;
 	clocks = <&ahb1_gates 19>;
+	resets = <&ahb1rst 19>;
 };
diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
index deebcd6469fc..02268448dc85 100644
--- a/drivers/clocksource/timer-sun5i.c
+++ b/drivers/clocksource/timer-sun5i.c
@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqreturn.h>
+#include <linux/reset.h>
 #include <linux/sched_clock.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -143,6 +144,7 @@ static u64 sun5i_timer_sched_read(void)
 
 static void __init sun5i_timer_init(struct device_node *node)
 {
+	struct reset_control *rstc;
 	unsigned long rate;
 	struct clk *clk;
 	int ret, irq;
@@ -162,6 +164,10 @@ static void __init sun5i_timer_init(struct device_node *node)
 	clk_prepare_enable(clk);
 	rate = clk_get_rate(clk);
 
+	rstc = of_reset_control_get(node, NULL);
+	if (!IS_ERR(rstc))
+		reset_control_deassert(rstc);
+
 	writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
 	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
 	       timer_base + TIMER_CTL_REG(1));
-- 
1.9.1

[PATCH v3 2/2] ARM: sun6i: a31: Add support for the High Speed Timers

[Maxime Ripard]

The Allwinner A31 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index bc46814d2ff0..2af6ca205cc2 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -428,6 +428,17 @@
 			status = "disabled";
 		};
 
+		timer@01c60000 {
+			compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
+			reg = <0x01c60000 0x1000>;
+			interrupts = <0 51 4>,
+				     <0 52 4>,
+				     <0 53 4>,
+				     <0 54 4>;
+			clocks = <&ahb1_gates 19>;
+			resets = <&ahb1_rst 19>;
+		};
+
 		spi0: spi@01c68000 {
 			compatible = "allwinner,sun6i-a31-spi";
 			reg = <0x01c68000 0x1000>;
-- 
1.9.1

Re: [PATCH v3 0/2] ARM: sunxi: Add A31 High Speed Timer Support

[Daniel Lezcano]

On 04/17/2014 11:06 AM, Maxime Ripard wrote:
> Hi everyone,
>
> This patchset enables support for the High Speed Timer IP found in the
> Allwinner A31 SoCs.
>
> These timers are asserted in reset, and are not associated with any
> struct device, so we also add a small helper to the reset framework
> along the way to be able to retrieve the reset controller from the
> device tree directly.
>
> Thanks,
> Maxime
>
> Changes from v2:
>    - Rebased on top of 3.15-rc1
>
> Changes from v1:
>    - Rebased on top of 3.14-rc1 and reset/for_3.15
>
> Maxime Ripard (2):
>    clocksource: sun5i: Add support for reset controller
>    ARM: sun6i: a31: Add support for the High Speed Timers
>
>   .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt |  4 ++++
>   arch/arm/boot/dts/sun6i-a31.dtsi                              | 11 +++++++++++
>   drivers/clocksource/timer-sun5i.c                             |  6 ++++++
>   3 files changed, 21 insertions(+)

Applied for 3.16

Thanks

   -- Daniel


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