* [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks
@ 2017-05-30 4:34 Martin Schiller
2017-06-03 15:55 ` Hauke Mehrtens
2017-11-07 22:50 ` James Hogan
0 siblings, 2 replies; 3+ messages in thread
From: Martin Schiller @ 2017-05-30 4:34 UTC (permalink / raw)
To: linux-mips, linux-kernel; +Cc: john, ralf, hauke, arnd, nbd, Martin Schiller
ASC1 is available on every Lantiq SoC (also AmazonSE) and should be
enabled like the other generic xway clocks instead of ASC0, which is
only available for AR9 and Danube.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
---
arch/mips/lantiq/xway/sysctrl.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 95bec46..cd6dbea 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -484,9 +484,9 @@ void __init ltq_soc_init(void)
/* add our generic xway clocks */
clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
- clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
+ clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
@@ -501,7 +501,6 @@ void __init ltq_soc_init(void)
}
if (!of_machine_is_compatible("lantiq,ase")) {
- clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
clkdev_add_pci();
}
--
2.1.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks
2017-05-30 4:34 [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks Martin Schiller
@ 2017-06-03 15:55 ` Hauke Mehrtens
2017-11-07 22:50 ` James Hogan
1 sibling, 0 replies; 3+ messages in thread
From: Hauke Mehrtens @ 2017-06-03 15:55 UTC (permalink / raw)
To: Martin Schiller, linux-mips, linux-kernel; +Cc: john, ralf, arnd, nbd
On 05/30/2017 06:34 AM, Martin Schiller wrote:
> ASC1 is available on every Lantiq SoC (also AmazonSE) and should be
> enabled like the other generic xway clocks instead of ASC0, which is
> only available for AR9 and Danube.
This is correct.
> Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
> arch/mips/lantiq/xway/sysctrl.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 95bec46..cd6dbea 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -484,9 +484,9 @@ void __init ltq_soc_init(void)
>
> /* add our generic xway clocks */
> clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
> - clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
> clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
> clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
> + clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
> clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
> clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
> clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
> @@ -501,7 +501,6 @@ void __init ltq_soc_init(void)
> }
>
> if (!of_machine_is_compatible("lantiq,ase")) {
> - clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
> clkdev_add_pci();
> }
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks
2017-05-30 4:34 [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks Martin Schiller
2017-06-03 15:55 ` Hauke Mehrtens
@ 2017-11-07 22:50 ` James Hogan
1 sibling, 0 replies; 3+ messages in thread
From: James Hogan @ 2017-11-07 22:50 UTC (permalink / raw)
To: Martin Schiller; +Cc: linux-mips, linux-kernel, john, ralf, hauke, arnd, nbd
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On Tue, May 30, 2017 at 06:34:34AM +0200, Martin Schiller wrote:
> ASC1 is available on every Lantiq SoC (also AmazonSE) and should be
> enabled like the other generic xway clocks instead of ASC0, which is
> only available for AR9 and Danube.
>
> Signed-off-by: Martin Schiller <ms@dev.tdt.de>
> ---
> arch/mips/lantiq/xway/sysctrl.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 95bec46..cd6dbea 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -484,9 +484,9 @@ void __init ltq_soc_init(void)
>
> /* add our generic xway clocks */
> clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
> - clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
> clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
> clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
> + clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
> clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
> clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
> clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
> @@ -501,7 +501,6 @@ void __init ltq_soc_init(void)
> }
>
> if (!of_machine_is_compatible("lantiq,ase")) {
> - clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
> clkdev_add_pci();
> }
Thanks, applied for 4.15 (and I dropped the braces here too).
Cheers
James
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2017-06-03 15:55 ` Hauke Mehrtens
2017-11-07 22:50 ` James Hogan
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