[PATCH v1 0/5] clk: gcc: Add APQ8084 Global Clock Controller support

[PATCH v1 0/5] clk: gcc: Add APQ8084 Global Clock Controller support

[Georgi Djakov]

This patchset adds support for the global clock controller found on the
APQ8084 based platforms.

It applies to the clk-next tree and the following patchset on top of it:
https://lkml.org/lkml/2014/5/16/666

Georgi Djakov (5):
  clk: qcom: Add APQ8084 Global Clock Controller documentation
  clk: qcom: Allow an override function to be passed as data
  clk: gcc: Add APQ8084 Global Clock Controller support
  ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node
  ARM: dts: qcom: Add APQ8084 serial port DT node

 .../devicetree/bindings/clock/qcom,gcc.txt         |    1 +
 arch/arm/boot/dts/qcom-apq8084.dtsi                |   17 ++
 drivers/clk/qcom/Kconfig                           |    4 +-
 drivers/clk/qcom/gcc-msm8974.c                     |  174 ++++++++++++++++++--
 include/dt-bindings/clock/qcom,gcc-msm8974.h       |    4 +
 5 files changed, 185 insertions(+), 15 deletions(-)

-- 
1.7.9.5

[PATCH v1 1/5] clk: qcom: Add APQ8084 Global Clock Controller documentation

[Georgi Djakov]

Add the compatible string for the APQ8084 global clock controller
to the clock binding documentation.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
---
 .../devicetree/bindings/clock/qcom,gcc.txt         |    1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 9cfcb4f..4f35042 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -5,6 +5,7 @@ Required properties :
 - compatible : shall contain only one of the following:
 
 			"qcom,gcc-apq8064"
+			"qcom,gcc-apq8084"
 			"qcom,gcc-msm8660"
 			"qcom,gcc-msm8960"
 			"qcom,gcc-msm8974"
-- 
1.7.9.5

[PATCH v1 2/5] clk: qcom: Allow an override function to be passed as data

[Georgi Djakov]

The APQ8084 and MSM8974 SoCs share a lot of clock data. Instead of
duplicating all the data, we can add the support for APQ8084 into
the MSM8974 code and just describe the differences by using an
override function.

This patch applies to the clk-next tree and the following patchset
on top of it: https://lkml.org/lkml/2014/5/16/666

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
---
 drivers/clk/qcom/gcc-msm8974.c |   27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 33eb051..58cb2f5 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -2674,14 +2674,6 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
 	.num_resets = ARRAY_SIZE(gcc_msm8974_resets),
 };
 
-static const struct of_device_id gcc_msm8974_match_table[] = {
-	{ .compatible = "qcom,gcc-msm8974" },
-	{ .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
-	{ .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
-	{ }
-};
-MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
-
 static void msm8974_pro_clock_override(void)
 {
 	sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
@@ -2697,20 +2689,31 @@ static void msm8974_pro_clock_override(void)
 		&gcc_sdcc1_cdccal_ff_clk.clkr;
 }
 
+static const struct of_device_id gcc_msm8974_match_table[] = {
+	{ .compatible = "qcom,gcc-msm8974" },
+	{ .compatible = "qcom,gcc-msm8974pro",
+		.data =	&msm8974_pro_clock_override },
+	{ .compatible = "qcom,gcc-msm8974pro-ac",
+		.data = &msm8974_pro_clock_override },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
+
 static int gcc_msm8974_probe(struct platform_device *pdev)
 {
 	struct clk *clk;
 	struct device *dev = &pdev->dev;
-	bool pro;
 	const struct of_device_id *id;
+	void (*overrides)(void);
 
 	id = of_match_device(gcc_msm8974_match_table, dev);
 	if (!id)
 		return -ENODEV;
-	pro = !!(id->data);
 
-	if (pro)
-		msm8974_pro_clock_override();
+	if (id->data) {
+		overrides = id->data;
+		overrides();
+	}
 
 	/* Temporary until RPM clocks supported */
 	clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
-- 
1.7.9.5

[PATCH v1 3/5] clk: gcc: Add APQ8084 Global Clock Controller support

[Georgi Djakov]

This patch adds support for the global clock controller found on
the APQ8084 based devices.

The APQ8084 and MSM8974 share a lot of clock data, so instead of
duplicating all the data, we add support to the MSM8974 code.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
---
 drivers/clk/qcom/Kconfig                     |    4 +-
 drivers/clk/qcom/gcc-msm8974.c               |  151 +++++++++++++++++++++++++-
 include/dt-bindings/clock/qcom,gcc-msm8974.h |    4 +
 3 files changed, 154 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7f696b7..00541e7 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -30,10 +30,10 @@ config MSM_MMCC_8960
 	  graphics, video encode/decode, camera, etc.
 
 config MSM_GCC_8974
-	tristate "MSM8974 Global Clock Controller"
+	tristate "APQ8084/MSM8974 Global Clock Controller"
 	depends on COMMON_CLK_QCOM
 	help
-	  Support for the global clock controller on msm8974 devices.
+	  Support for the global clock controller on apq8084/msm8974 devices.
 	  Say Y if you want to use peripheral devices such as UART, SPI,
 	  i2c, USB, SD/eMMC, SATA, PCIe, etc.
 
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 58cb2f5..c2a8d77 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -204,6 +204,12 @@ static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(50000000, P_GPLL0, 12, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 	.cmd_rcgr = 0x0660,
 	.hid_width = 5,
@@ -768,6 +774,27 @@ static struct clk_rcg2 ce2_clk_src = {
 	},
 };
 
+static const struct freq_tbl ftbl_gcc_ce3_clk_apq8084[] = {
+	F(50000000, P_GPLL0, 12, 0, 0),
+	F(85710000, P_GPLL0, 7, 0, 0),
+	F(100000000, P_GPLL0, 6, 0, 0),
+	F(171430000, P_GPLL0, 3.5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 ce3_clk_src_apq8084 = {
+	.cmd_rcgr = 0x1d10,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.freq_tbl = ftbl_gcc_ce3_clk_apq8084,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "ce3_clk_src",
+		.parent_names = gcc_xo_gpll0,
+		.num_parents = 2,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 	F(4800000, P_XO, 4, 0, 0),
 	F(6000000, P_GPLL0, 10, 1, 10),
@@ -780,6 +807,12 @@ static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gcc_gp_clk_apq8084[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(100000000, P_GPLL0, 6, 0, 0),
+	F(200000000, P_GPLL0, 3, 0, 0),
+	{ }
+};
 
 static struct clk_rcg2 gp1_clk_src = {
 	.cmd_rcgr = 0x1904,
@@ -966,6 +999,11 @@ static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gcc_usb_hs_system_clk_apq8084[] = {
+	F(75000000, P_GPLL0, 8, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 usb_hs_system_clk_src = {
 	.cmd_rcgr = 0x0490,
 	.hid_width = 5,
@@ -1029,6 +1067,11 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk_apq8084[] = {
+	F(75000000, P_GPLL0, 8, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 usb_hsic_system_clk_src = {
 	.cmd_rcgr = 0x041c,
 	.hid_width = 5,
@@ -1838,6 +1881,58 @@ static struct clk_branch gcc_ce2_clk = {
 	},
 };
 
+static struct clk_branch gcc_ce3_ahb_clk_apq8084 = {
+	.halt_reg = 0x1d0c,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1d0c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_ce3_ahb_clk",
+			.parent_names = (const char *[]){
+				"config_noc_clk_src",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_ce3_axi_clk_apq8084 = {
+	.halt_reg = 0x1088,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1d08,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_ce3_axi_clk",
+			.parent_names = (const char *[]){
+				"system_noc_clk_src",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_ce3_clk_apq8084 = {
+	.halt_reg = 0x1090,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1d04,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_ce3_clk",
+			.parent_names = (const char *[]){
+				"ce3_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_gp1_clk = {
 	.halt_reg = 0x1900,
 	.clkr = {
@@ -2575,6 +2670,10 @@ static struct clk_regmap *gcc_msm8974_clocks[] = {
 	[GPLL4_VOTE] = NULL,
 	[GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
 	[GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
+	[CE3_CLK_SRC] = NULL,
+	[GCC_CE3_AHB_CLK] = NULL,
+	[GCC_CE3_AXI_CLK] = NULL,
+	[GCC_CE3_CLK] = NULL,
 };
 
 static const struct qcom_reset_map gcc_msm8974_resets[] = {
@@ -2689,12 +2788,58 @@ static void msm8974_pro_clock_override(void)
 		&gcc_sdcc1_cdccal_ff_clk.clkr;
 }
 
+static void apq8084_clock_override(void)
+{
+	sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
+	sdcc1_apps_clk_src_init.num_parents = 3;
+	sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
+	sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
+
+	gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
+	gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
+	gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
+		&gcc_sdcc1_cdccal_sleep_clk.clkr;
+	gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
+		&gcc_sdcc1_cdccal_ff_clk.clkr;
+
+	blsp1_qup1_i2c_apps_clk_src.freq_tbl =
+		ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084;
+	blsp1_qup2_i2c_apps_clk_src.freq_tbl =
+		ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084;
+	blsp1_qup3_i2c_apps_clk_src.freq_tbl =
+		ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084;
+	blsp1_qup4_i2c_apps_clk_src.freq_tbl =
+		ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084;
+	blsp1_qup5_i2c_apps_clk_src.freq_tbl =
+		ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084;
+	blsp1_qup6_i2c_apps_clk_src.freq_tbl =
+		ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084;
+	blsp2_qup1_i2c_apps_clk_src.freq_tbl =
+		ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084;
+	usb_hsic_system_clk_src.freq_tbl =
+		ftbl_gcc_usb_hsic_system_clk_apq8084;
+	usb_hs_system_clk_src.freq_tbl = ftbl_gcc_usb_hs_system_clk_apq8084;
+
+	gcc_msm8974_clocks[CE3_CLK_SRC] = &ce3_clk_src_apq8084.clkr,
+	gcc_msm8974_clocks[GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk_apq8084.clkr,
+	gcc_msm8974_clocks[GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk_apq8084.clkr,
+	gcc_msm8974_clocks[GCC_CE3_CLK] = &gcc_ce3_clk_apq8084.clkr,
+
+	gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_apq8084;
+	gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_apq8084;
+	gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_apq8084;
+
+	gcc_msm8974_clocks[GCC_LPASS_Q6_AXI_CLK] = NULL;
+}
+
 static const struct of_device_id gcc_msm8974_match_table[] = {
 	{ .compatible = "qcom,gcc-msm8974" },
 	{ .compatible = "qcom,gcc-msm8974pro",
-		.data =	&msm8974_pro_clock_override },
+		.data =	msm8974_pro_clock_override },
 	{ .compatible = "qcom,gcc-msm8974pro-ac",
-		.data = &msm8974_pro_clock_override },
+		.data = msm8974_pro_clock_override },
+	{ .compatible = "qcom,gcc-apq8084",
+		.data = apq8084_clock_override },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
index 51e51c8..01f8863 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -320,5 +320,9 @@
 #define GPLL4_VOTE						303
 #define GCC_SDCC1_CDCCAL_SLEEP_CLK				304
 #define GCC_SDCC1_CDCCAL_FF_CLK					305
+#define CE3_CLK_SRC                             306
+#define GCC_CE3_CLK                             307
+#define GCC_CE3_AHB_CLK                         308
+#define GCC_CE3_AXI_CLK                         309
 
 #endif
-- 
1.7.9.5

Re: [PATCH v1 3/5] clk: gcc: Add APQ8084 Global Clock Controller support

[Kumar Gala]

On May 22, 2014, at 11:24 AM, Georgi Djakov <gdjakov@mm-sol.com> wrote:

> This patch adds support for the global clock controller found on
> the APQ8084 based devices.
> 
> The APQ8084 and MSM8974 share a lot of clock data, so instead of
> duplicating all the data, we add support to the MSM8974 code.
> 
> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
> ---
> drivers/clk/qcom/Kconfig                     |    4 +-
> drivers/clk/qcom/gcc-msm8974.c               |  151 +++++++++++++++++++++++++-
> include/dt-bindings/clock/qcom,gcc-msm8974.h |    4 +
> 3 files changed, 154 insertions(+), 5 deletions(-)

What about differences in reset?

- k

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v1 3/5] clk: gcc: Add APQ8084 Global Clock Controller support

[Georgi Djakov]

On 05/22/2014 07:38 PM, Kumar Gala wrote:
>
> On May 22, 2014, at 11:24 AM, Georgi Djakov <gdjakov@mm-sol.com> wrote:
>
>> This patch adds support for the global clock controller found on
>> the APQ8084 based devices.
>>
>> The APQ8084 and MSM8974 share a lot of clock data, so instead of
>> duplicating all the data, we add support to the MSM8974 code.
>>
>> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
>> ---
>> drivers/clk/qcom/Kconfig                     |    4 +-
>> drivers/clk/qcom/gcc-msm8974.c               |  151 +++++++++++++++++++++++++-
>> include/dt-bindings/clock/qcom,gcc-msm8974.h |    4 +
>> 3 files changed, 154 insertions(+), 5 deletions(-)
>
> What about differences in reset?

Oops, will add this too. Thanks!

BR,
Georgi

Re: [PATCH v1 3/5] clk: gcc: Add APQ8084 Global Clock Controller support

[Stephen Boyd]

On 05/22/14 09:24, Georgi Djakov wrote:
> diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
> index 58cb2f5..c2a8d77 100644
> --- a/drivers/clk/qcom/gcc-msm8974.c
> +++ b/drivers/clk/qcom/gcc-msm8974.c
> @@ -204,6 +204,12 @@ static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
>  	{ }
>  };
>  
> +static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084[] = {
> +	F(19200000, P_XO, 1, 0, 0),
> +	F(50000000, P_GPLL0, 12, 0, 0),
> +	{ }
> +};
> +

Just merge this with the other blsp1_2_qup table.

>  static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>  	.cmd_rcgr = 0x0660,
>  	.hid_width = 5,
> @@ -768,6 +774,27 @@ static struct clk_rcg2 ce2_clk_src = {
>  	},
>  };
>  
> +static const struct freq_tbl ftbl_gcc_ce3_clk_apq8084[] = {
> +	F(50000000, P_GPLL0, 12, 0, 0),
> +	F(85710000, P_GPLL0, 7, 0, 0),
> +	F(100000000, P_GPLL0, 6, 0, 0),
> +	F(171430000, P_GPLL0, 3.5, 0, 0),
> +	{ }
> +};
> +

Ditto.

> +static struct clk_rcg2 ce3_clk_src_apq8084 = {

Please drop all the _apq8084 stuff. I imagine if we support other chips
in this same driver this won't make any sense.

> +	.cmd_rcgr = 0x1d10,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.freq_tbl = ftbl_gcc_ce3_clk_apq8084,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "ce3_clk_src",
> +		.parent_names = gcc_xo_gpll0,
> +		.num_parents = 2,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
>  static const struct freq_tbl ftbl_gcc_gp_clk[] = {
>  	F(4800000, P_XO, 4, 0, 0),
>  	F(6000000, P_GPLL0, 10, 1, 10),
> @@ -780,6 +807,12 @@ static const struct freq_tbl ftbl_gcc_gp_clk[] = {
>  	{ }
>  };
>  
> +static const struct freq_tbl ftbl_gcc_gp_clk_apq8084[] = {
> +	F(19200000, P_XO, 1, 0, 0),
> +	F(100000000, P_GPLL0, 6, 0, 0),
> +	F(200000000, P_GPLL0, 3, 0, 0),
> +	{ }
> +};

Merge with other GP table?

>  
>  static struct clk_rcg2 gp1_clk_src = {
>  	.cmd_rcgr = 0x1904,
> @@ -966,6 +999,11 @@ static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
>  	{ }
>  };
>  
> +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk_apq8084[] = {
> +	F(75000000, P_GPLL0, 8, 0, 0),
> +	{ }
> +};
> +

ditto.

>  static struct clk_rcg2 usb_hs_system_clk_src = {
>  	.cmd_rcgr = 0x0490,
>  	.hid_width = 5,
> @@ -1029,6 +1067,11 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
>  	{ }
>  };
>  
> +static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk_apq8084[] = {
> +	F(75000000, P_GPLL0, 8, 0, 0),
> +	{ }
> +};
> +

ditto.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

Re: [PATCH v1 3/5] clk: gcc: Add APQ8084 Global Clock Controller support

[Georgi Djakov]

On 05/22/2014 08:22 PM, Stephen Boyd wrote:
> On 05/22/14 09:24, Georgi Djakov wrote:
>> diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
>> index 58cb2f5..c2a8d77 100644
>> --- a/drivers/clk/qcom/gcc-msm8974.c
>> +++ b/drivers/clk/qcom/gcc-msm8974.c
>> @@ -204,6 +204,12 @@ static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
>>   	{ }
>>   };
>>
>> +static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084[] = {
>> +	F(19200000, P_XO, 1, 0, 0),
>> +	F(50000000, P_GPLL0, 12, 0, 0),
>> +	{ }
>> +};
>> +
>
> Just merge this with the other blsp1_2_qup table.
>
>>   static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>>   	.cmd_rcgr = 0x0660,
>>   	.hid_width = 5,
>> @@ -768,6 +774,27 @@ static struct clk_rcg2 ce2_clk_src = {
>>   	},
>>   };
>>
>> +static const struct freq_tbl ftbl_gcc_ce3_clk_apq8084[] = {
>> +	F(50000000, P_GPLL0, 12, 0, 0),
>> +	F(85710000, P_GPLL0, 7, 0, 0),
>> +	F(100000000, P_GPLL0, 6, 0, 0),
>> +	F(171430000, P_GPLL0, 3.5, 0, 0),
>> +	{ }
>> +};
>> +
>
> Ditto.
>
>> +static struct clk_rcg2 ce3_clk_src_apq8084 = {
>
> Please drop all the _apq8084 stuff. I imagine if we support other chips
> in this same driver this won't make any sense.
>
>> +	.cmd_rcgr = 0x1d10,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.freq_tbl = ftbl_gcc_ce3_clk_apq8084,
>> +	.clkr.hw.init = &(struct clk_init_data){
>> +		.name = "ce3_clk_src",
>> +		.parent_names = gcc_xo_gpll0,
>> +		.num_parents = 2,
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>>   static const struct freq_tbl ftbl_gcc_gp_clk[] = {
>>   	F(4800000, P_XO, 4, 0, 0),
>>   	F(6000000, P_GPLL0, 10, 1, 10),
>> @@ -780,6 +807,12 @@ static const struct freq_tbl ftbl_gcc_gp_clk[] = {
>>   	{ }
>>   };
>>
>> +static const struct freq_tbl ftbl_gcc_gp_clk_apq8084[] = {
>> +	F(19200000, P_XO, 1, 0, 0),
>> +	F(100000000, P_GPLL0, 6, 0, 0),
>> +	F(200000000, P_GPLL0, 3, 0, 0),
>> +	{ }
>> +};
>
> Merge with other GP table?
>
>>
>>   static struct clk_rcg2 gp1_clk_src = {
>>   	.cmd_rcgr = 0x1904,
>> @@ -966,6 +999,11 @@ static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
>>   	{ }
>>   };
>>
>> +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk_apq8084[] = {
>> +	F(75000000, P_GPLL0, 8, 0, 0),
>> +	{ }
>> +};
>> +
>
> ditto.
>
>>   static struct clk_rcg2 usb_hs_system_clk_src = {
>>   	.cmd_rcgr = 0x0490,
>>   	.hid_width = 5,
>> @@ -1029,6 +1067,11 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
>>   	{ }
>>   };
>>
>> +static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk_apq8084[] = {
>> +	F(75000000, P_GPLL0, 8, 0, 0),
>> +	{ }
>> +};
>> +
>
> ditto.
>

Thanks for all the comments, Stephen. I will make the appropriate changes.

BR,
Georgi

[PATCH v1 4/5] ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node

[Georgi Djakov]

This patch adds the necessary node to probe the global clock
controller on APQ8084 platforms.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index e3e009a..2dcd11e 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -2,6 +2,8 @@
 
 #include "skeleton.dtsi"
 
+#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+
 / {
 	model = "Qualcomm APQ 8084";
 	compatible = "qcom,apq8084";
@@ -175,5 +177,13 @@
 			compatible = "qcom,pshold";
 			reg = <0xfc4ab000 0x4>;
 		};
+
+		gcc: clock-controller@fc400000 {
+			compatible = "qcom,gcc-apq8084";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			reg = <0xfc400000 0x4000>;
+		};
+
 	};
 };
-- 
1.7.9.5

[PATCH v1 5/5] ARM: dts: qcom: Add APQ8084 serial port DT node

[Georgi Djakov]

Add the necessary DT node to probe the serial driver on
APQ8084 platforms.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 2dcd11e..c346549 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -185,5 +185,12 @@
 			reg = <0xfc400000 0x4000>;
 		};
 
+		serial@f995e000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0xf995e000 0x1000>;
+			interrupts = <0 114 0x0>;
+			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+		};
 	};
 };
-- 
1.7.9.5

Re: [PATCH v1 5/5] ARM: dts: qcom: Add APQ8084 serial port DT node

[Kumar Gala]

On May 22, 2014, at 11:24 AM, Georgi Djakov <gdjakov@mm-sol.com> wrote:

> Add the necessary DT node to probe the serial driver on
> APQ8084 platforms.
> 
> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
> ---
> arch/arm/boot/dts/qcom-apq8084.dtsi |    7 +++++++
> 1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
> index 2dcd11e..c346549 100644
> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
> @@ -185,5 +185,12 @@
> 			reg = <0xfc400000 0x4000>;
> 		};
> 
> +		serial@f995e000 {

Mark it disabled in the soc.dtsi and “ok” in the board.

> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +			reg = <0xf995e000 0x1000>;
> +			interrupts = <0 114 0x0>;
> +			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
> +			clock-names = "core", "iface";
> +		};
> 	};
> };
> -- 
> 1.7.9.5
> 

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v1 5/5] ARM: dts: qcom: Add APQ8084 serial port DT node

[Georgi Djakov]

On 05/22/2014 07:32 PM, Kumar Gala wrote:
>
> On May 22, 2014, at 11:24 AM, Georgi Djakov <gdjakov@mm-sol.com> wrote:
>
>> Add the necessary DT node to probe the serial driver on
>> APQ8084 platforms.
>>
>> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
>> ---
>> arch/arm/boot/dts/qcom-apq8084.dtsi |    7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
>> index 2dcd11e..c346549 100644
>> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
>> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
>> @@ -185,5 +185,12 @@
>> 			reg = <0xfc400000 0x4000>;
>> 		};
>>
>> +		serial@f995e000 {
>
> Mark it disabled in the soc.dtsi and “ok” in the board.
>

Oh, of course!

Thanks,
Georgi