From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
To: <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pm@vger.kernel.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Paul Walmsley <pwalmsley@nvidia.com>,
<devicetree@vger.kernel.org>,
Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Subject: [PATCH v2 03/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource
Date: Mon, 21 Jul 2014 18:38:49 +0300 [thread overview]
Message-ID: <1405957142-19416-4-git-send-email-ttynkkynen@nvidia.com> (raw)
In-Reply-To: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com>
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the device tree.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
---
v2 changes:
- dropped most of the I2C properties, as they are now queried from
the regulator framework
- s/vdd_cpu-supply/vdd-cpu-supply/ to better match what other Tegra
bindings do
.../bindings/clock/nvidia,tegra124-dfll.txt | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
new file mode 100644
index 0000000..54c62ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
@@ -0,0 +1,69 @@
+NVIDIA Tegra124 DFLL FCPU clocksource
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The DFLL IP block on Tegra is a root clocksource designed for clocking
+the fast CPU cluster. It consists of a free-running voltage controlled
+oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
+control module that will automatically adjust the VDD_CPU voltage by
+communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
+
+Required properties:
+- compatible : should be "nvidia,tegra124-dfll-fcpu"
+- reg : Defines the following set of registers, in the order listed:
+ - registers for the DFLL control logic.
+ - registers for the I2C output logic.
+ - registers for the integrated I2C master controller.
+ - look-up table RAM for voltage register values.
+- interrupts: Should contain the DFLL block interrupt.
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - soc: Clock source for the DFLL control logic.
+ - ref: The closed loop reference clock
+ - i2c: Clock source for the integrated I2C master.
+- #clock-cells: Must be 0.
+- clock-output-names: Name of the clock output.
+- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
+ hardware will start controlling.
+
+Required properties for the control loop parameters:
+- nvidia,sample-rate: Sample rate of the DFLL control loop.
+- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
+- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
+- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
+- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
+- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
+- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
+
+Required properties for I2C mode:
+- nvidia,i2c-fs-rate: I2C transfer rate, if using FS mode.
+
+Example:
+
+dfll@0,70110000 {
+ compatible = "nvidia,tegra124-dfll";
+ reg = <0 0x70110000 0 0x100>, /* DFLL control */
+ <0 0x70110000 0 0x100>, /* I2C output control */
+ <0 0x70110100 0 0x100>, /* Integrated I2C controller */
+ <0 0x70110200 0 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA124_CLK_DFLL_REF>,
+ <&tegra_car TEGRA124_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ vdd-cpu-supply = <&vdd_cpu>;
+ status = "okay";
+
+ nvidia,sample-rate = <12500>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,cf = <10>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+
+ nvidia,i2c-fs-rate = <400000>;
+};
--
1.8.1.5
next prev parent reply other threads:[~2014-07-21 15:44 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-21 15:38 [PATCH v2 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 01/16] regmap: Add regmap_get_device Tuomas Tynkkynen
2014-07-25 17:34 ` Mark Brown
2014-07-25 17:43 ` Mark Brown
2014-07-21 15:38 ` [PATCH v2 02/16] regulator: Add helpers for low-level register access Tuomas Tynkkynen
2014-07-25 17:48 ` Mark Brown
2014-07-21 15:38 ` Tuomas Tynkkynen [this message]
2014-07-21 15:38 ` [PATCH v2 04/16] clk: tegra: Add library for the DFLL clock source (open-loop mode) Tuomas Tynkkynen
2014-08-18 6:05 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 05/16] clk: tegra: Add closed loop support for the DFLL Tuomas Tynkkynen
2014-08-18 6:08 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 06/16] clk: tegra: Add functions for parsing CVB tables Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 07/16] clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 08/16] clk: tegra: Add Tegra124 DFLL clocksource platform driver Tuomas Tynkkynen
2014-08-12 10:37 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 09/16] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 10/16] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 11/16] ARM: tegra: Add the DFLL to Tegra124 device tree Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 12/16] ARM: tegra: Enable the DFLL on the Jetson TK1 Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 13/16] cpufreq: tegra124: Add device tree bindings Tuomas Tynkkynen
2014-07-21 15:39 ` [PATCH v2 14/16] cpufreq: Add cpufreq driver for Tegra124 Tuomas Tynkkynen
2014-07-22 0:49 ` Rafael J. Wysocki
2014-07-23 4:44 ` Viresh Kumar
2014-07-23 6:54 ` Thierry Reding
2014-07-23 6:58 ` Viresh Kumar
2014-07-23 7:24 ` Thierry Reding
2014-07-23 8:25 ` Viresh Kumar
2014-07-23 13:51 ` Thierry Reding
2014-07-23 11:57 ` Tuomas Tynkkynen
2014-07-23 16:50 ` Viresh Kumar
2014-07-23 19:17 ` Tuomas Tynkkynen
2014-07-24 0:13 ` Viresh Kumar
2014-07-24 9:10 ` Thierry Reding
2014-07-23 7:09 ` Thierry Reding
2014-07-23 12:35 ` Tuomas Tynkkynen
2014-07-23 13:59 ` Thierry Reding
2014-07-23 7:21 ` pramod gurav
2014-07-21 15:39 ` [PATCH v2 15/16] ARM: tegra: Add entries for cpufreq on Tegra124 Tuomas Tynkkynen
2014-07-21 15:39 ` [PATCH v2 16/16] ARM: tegra: Update defconfig for tegra124-cpufreq Tuomas Tynkkynen
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