From: Vince Hsu <vinceh@nvidia.com>
To: Tuomas Tynkkynen <ttynkkynen@nvidia.com>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Paul Walmsley <pwalmsley@nvidia.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 04/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)
Date: Mon, 18 Aug 2014 14:05:55 +0800 [thread overview]
Message-ID: <53F197C3.5010002@nvidia.com> (raw)
In-Reply-To: <1405957142-19416-5-git-send-email-ttynkkynen@nvidia.com>
Hi,
On 07/21/2014 11:38 PM, Tuomas Tynkkynen wrote:
> Add shared code to support the Tegra DFLL clocksource in open-loop
> mode. This root clocksource is present on the Tegra124 SoCs. The
> DFLL is the intended primary clock source for the fast CPU cluster.
>
> This code is very closely based on a patch by Paul Walmsley from
> December (http://comments.gmane.org/gmane.linux.ports.tegra/15273),
> which in turn comes from the internal driver by originally created
> by Aleksandr Frid <afrid@nvidia.com>.
>
> Subsequent patches will add support for closed loop mode and drivers
> for the Tegra124 fast CPU cluster DFLL devices, which rely on this
> code.
>
> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
> Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
> ---
> v2 changes:
> - minor, moved the devm_regulator_get here
>
> drivers/clk/tegra/Makefile | 1 +
> drivers/clk/tegra/clk-dfll.c | 1085 ++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-dfll.h | 55 +++
> 3 files changed, 1141 insertions(+)
> create mode 100644 drivers/clk/tegra/clk-dfll.c
> create mode 100644 drivers/clk/tegra/clk-dfll.h
...
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-dfll.c
...
> +
> +/*
> + * Output clock scaler helpers
> + */
> +
> +/**
> + * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
> + * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field)
> + * @dvco_rate: the DVCO rate
> + *
> + * Apply the same scaling formula that the DFLL hardware uses to scale
> + * the DVCO rate.
> + */
> +static unsigned long dfll_scale_dvco_rate(int scale_bits,
> + unsigned long dvco_rate)
> +{
> + return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
> +}
...
> +static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
> +{
> + u32 v, s;
> + u64 pre_scaler_rate, post_scaler_rate;
> +
> + if (!dfll_is_running(td))
> + return 0;
> +
> + v = dfll_readl(td, DFLL_MONITOR_DATA);
> + v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
> + pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
> +
> + s = dfll_readl(td, DFLL_FREQ_REQ);
> + s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
> + post_scaler_rate = dfll_scale_dvco_rate(pre_scaler_rate, s);
Should be dfll_scale_dvco_rate(s, pre_scaler_rate);
Thanks,
Vince
next prev parent reply other threads:[~2014-08-18 6:04 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-21 15:38 [PATCH v2 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 01/16] regmap: Add regmap_get_device Tuomas Tynkkynen
2014-07-25 17:34 ` Mark Brown
2014-07-25 17:43 ` Mark Brown
2014-07-21 15:38 ` [PATCH v2 02/16] regulator: Add helpers for low-level register access Tuomas Tynkkynen
2014-07-25 17:48 ` Mark Brown
2014-07-21 15:38 ` [PATCH v2 03/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 04/16] clk: tegra: Add library for the DFLL clock source (open-loop mode) Tuomas Tynkkynen
2014-08-18 6:05 ` Vince Hsu [this message]
2014-07-21 15:38 ` [PATCH v2 05/16] clk: tegra: Add closed loop support for the DFLL Tuomas Tynkkynen
2014-08-18 6:08 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 06/16] clk: tegra: Add functions for parsing CVB tables Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 07/16] clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 08/16] clk: tegra: Add Tegra124 DFLL clocksource platform driver Tuomas Tynkkynen
2014-08-12 10:37 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 09/16] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 10/16] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 11/16] ARM: tegra: Add the DFLL to Tegra124 device tree Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 12/16] ARM: tegra: Enable the DFLL on the Jetson TK1 Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 13/16] cpufreq: tegra124: Add device tree bindings Tuomas Tynkkynen
2014-07-21 15:39 ` [PATCH v2 14/16] cpufreq: Add cpufreq driver for Tegra124 Tuomas Tynkkynen
2014-07-22 0:49 ` Rafael J. Wysocki
2014-07-23 4:44 ` Viresh Kumar
2014-07-23 6:54 ` Thierry Reding
2014-07-23 6:58 ` Viresh Kumar
2014-07-23 7:24 ` Thierry Reding
2014-07-23 8:25 ` Viresh Kumar
2014-07-23 13:51 ` Thierry Reding
2014-07-23 11:57 ` Tuomas Tynkkynen
2014-07-23 16:50 ` Viresh Kumar
2014-07-23 19:17 ` Tuomas Tynkkynen
2014-07-24 0:13 ` Viresh Kumar
2014-07-24 9:10 ` Thierry Reding
2014-07-23 7:09 ` Thierry Reding
2014-07-23 12:35 ` Tuomas Tynkkynen
2014-07-23 13:59 ` Thierry Reding
2014-07-23 7:21 ` pramod gurav
2014-07-21 15:39 ` [PATCH v2 15/16] ARM: tegra: Add entries for cpufreq on Tegra124 Tuomas Tynkkynen
2014-07-21 15:39 ` [PATCH v2 16/16] ARM: tegra: Update defconfig for tegra124-cpufreq Tuomas Tynkkynen
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