* [PATCH 0/2] Add clock binding id for rk3288
@ 2014-09-24 13:36 Kever Yang
2014-09-24 13:36 ` [PATCH 1/2] clk: rockchip: add some needed " Kever Yang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Kever Yang @ 2014-09-24 13:36 UTC (permalink / raw)
To: heiko, Mike Turquette
Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao,
linux-rockchip, Kever Yang, devicetree, Kumar Gala, linux-kernel,
Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Kever Yang (2):
clk: rockchip: add some needed clock binding id for rk3288
clk: rockchip: use the clock id for nodes init
drivers/clk/rockchip/clk-rk3288.c | 79 +++++++++++++++++++---------------
include/dt-bindings/clock/rk3288-cru.h | 38 +++++++++++++++-
2 files changed, 82 insertions(+), 35 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] clk: rockchip: add some needed clock binding id for rk3288
2014-09-24 13:36 [PATCH 0/2] Add clock binding id for rk3288 Kever Yang
@ 2014-09-24 13:36 ` Kever Yang
2014-09-24 14:06 ` Heiko Stübner
2014-09-24 13:36 ` [PATCH 2/2] clk: rockchip: use the clock id for nodes init Kever Yang
2014-09-25 22:01 ` [PATCH 0/2] Add clock binding id for rk3288 Mike Turquette
2 siblings, 1 reply; 6+ messages in thread
From: Kever Yang @ 2014-09-24 13:36 UTC (permalink / raw)
To: heiko, Mike Turquette
Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao,
linux-rockchip, Kever Yang, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree, linux-kernel
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
include/dt-bindings/clock/rk3288-cru.h | 38 +++++++++++++++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index ebcb460..ee579ff 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -61,6 +61,15 @@
#define SCLK_LCDC_PWM1 101
#define SCLK_MAC_RX 102
#define SCLK_MAC_TX 103
+#define SCLK_EDP_24M 104
+#define SCLK_EDP 105
+#define SCLK_RGA 106
+#define SCLK_ISP 107
+#define SCLK_ISP_JPE 108
+#define SCLK_HDMI_HDCP 109
+#define SCLK_HDMI_CEC 110
+#define SCLK_HEVC_CABAC 111
+#define SCLK_HEVC_CORE 112
#define DCLK_VOP0 190
#define DCLK_VOP1 191
@@ -75,6 +84,16 @@
#define ACLK_VOP1 198
#define ACLK_CRYPTO 199
#define ACLK_RGA 200
+#define ACLK_RGA_NIU 201
+#define ACLK_IEP 202
+#define ACLK_VIO0_NIU 203
+#define ACLK_VIP 204
+#define ACLK_ISP 205
+#define ACLK_VIO1_NIU 206
+#define ACLK_HEVC 207
+#define ACLK_VCODEC 208
+#define ACLK_CPU 209
+#define ACLK_PERI 210
/* pclk gates */
#define PCLK_GPIO0 320
@@ -112,6 +131,15 @@
#define PCLK_PS2C 352
#define PCLK_TIMER 353
#define PCLK_TZPC 354
+#define PCLK_EDP_CTRL 355
+#define PCLK_MIPI_DSI0 356
+#define PCLK_MIPI_DSI1 357
+#define PCLK_MIPI_CSI 358
+#define PCLK_LVDS_PHY 359
+#define PCLK_HDMI_CTRL 360
+#define PCLK_VIO2_H2P 361
+#define PCLK_CPU 362
+#define PCLK_PERI 363
/* hclk gates */
#define HCLK_GPS 448
@@ -137,8 +165,16 @@
#define HCLK_IEP 468
#define HCLK_ISP 469
#define HCLK_RGA 470
+#define HCLK_VIO_AHB_ARBI 471
+#define HCLK_VIO_NIU 472
+#define HCLK_VIP 473
+#define HCLK_VIO2_H2P 474
+#define HCLK_HEVC 475
+#define HCLK_VCODEC 476
+#define HCLK_CPU 477
+#define HCLK_PERI 478
-#define CLK_NR_CLKS (HCLK_RGA + 1)
+#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0 0
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: rockchip: use the clock id for nodes init
2014-09-24 13:36 [PATCH 0/2] Add clock binding id for rk3288 Kever Yang
2014-09-24 13:36 ` [PATCH 1/2] clk: rockchip: add some needed " Kever Yang
@ 2014-09-24 13:36 ` Kever Yang
2014-09-24 14:13 ` Heiko Stübner
2014-09-25 22:01 ` [PATCH 0/2] Add clock binding id for rk3288 Mike Turquette
2 siblings, 1 reply; 6+ messages in thread
From: Kever Yang @ 2014-09-24 13:36 UTC (permalink / raw)
To: heiko, Mike Turquette
Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao,
linux-rockchip, Kever Yang, linux-arm-kernel, linux-kernel
This patch use the new defined clock ID to initial the clock nodes.
This patch also add the clock nodes in PD_VIDEO.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3288.c | 79 ++++++++++++++++++++++-----------------
1 file changed, 45 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 8ea885b..9268818 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -219,12 +219,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
- GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
+ GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
RK3288_CLKGATE_CON(0), 3, GFLAGS),
- COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0,
+ COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
RK3288_CLKGATE_CON(0), 5, GFLAGS),
- COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0,
+ COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
RK3288_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "c2c_host", "aclk_cpu_src", 0,
@@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 11, GFLAGS),
+ /*
+ * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
+ * so we ignore the mux and make clocks nodes as following,
+ * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre.
+ * */
+ GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
+ RK3288_CLKGATE_CON(9), 0, GFLAGS),
+ GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0,
+ RK3288_CLKGATE_CON(3), 10, GFLAGS),
+ GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
+ RK3288_CLKGATE_CON(9), 1, GFLAGS),
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
@@ -309,7 +320,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 5, GFLAGS),
- COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
+ COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
@@ -320,35 +331,35 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 3, GFLAGS),
- COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0,
+ COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
RK3288_CLKGATE_CON(3), 12, GFLAGS),
- COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 13, GFLAGS),
- COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 14, GFLAGS),
- COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 15, GFLAGS),
- GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
+ GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
RK3288_CLKGATE_CON(5), 12, GFLAGS),
- GATE(0, "sclk_hdmi_cec", "xin32k", 0,
+ GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3288_CLKGATE_CON(5), 11, GFLAGS),
- COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 13, GFLAGS),
- DIV(0, "hclk_hevc", "aclk_hevc", 0,
+ DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
- COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 14, GFLAGS),
- COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 15, GFLAGS),
@@ -371,13 +382,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(2), 0, GFLAGS),
- COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0,
+ COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKGATE_CON(2), 3, GFLAGS),
- COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0,
+ COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKGATE_CON(2), 2, GFLAGS),
- GATE(0, "aclk_peri", "aclk_peri_src", 0,
+ GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
RK3288_CLKGATE_CON(2), 1, GFLAGS),
/*
@@ -643,34 +654,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
- GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
- GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
- GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
+ GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
+ GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
+ GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
- GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
- GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
- GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
- GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
- GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
- GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
- GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
- GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
+ GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
+ GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
+ GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
+ GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
+ GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
+ GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
+ GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
+ GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
/* aclk_vio0 gates */
GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
- GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
- GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
- GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
+ GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
+ GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
+ GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
/* aclk_vio1 gates */
GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
- GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
- GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
+ GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
+ GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
/* aclk_rga_pre gates */
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
- GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
+ GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
/*
* Other ungrouped clocks.
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] clk: rockchip: add some needed clock binding id for rk3288
2014-09-24 13:36 ` [PATCH 1/2] clk: rockchip: add some needed " Kever Yang
@ 2014-09-24 14:06 ` Heiko Stübner
0 siblings, 0 replies; 6+ messages in thread
From: Heiko Stübner @ 2014-09-24 14:06 UTC (permalink / raw)
To: Kever Yang
Cc: Mike Turquette, dianders, sonnyrao, addy.ke, cf, xjq, hj,
huangtao, linux-rockchip, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, devicetree, linux-kernel
Am Mittwoch, 24. September 2014, 21:36:34 schrieb Kever Yang:
> This patch add some clock binding id for different modules
> that under development and going to send upstream.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
>
> include/dt-bindings/clock/rk3288-cru.h | 38
> +++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1
> deletion(-)
>
> diff --git a/include/dt-bindings/clock/rk3288-cru.h
> b/include/dt-bindings/clock/rk3288-cru.h index ebcb460..ee579ff 100644
> --- a/include/dt-bindings/clock/rk3288-cru.h
> +++ b/include/dt-bindings/clock/rk3288-cru.h
> @@ -61,6 +61,15 @@
> #define SCLK_LCDC_PWM1 101
> #define SCLK_MAC_RX 102
> #define SCLK_MAC_TX 103
> +#define SCLK_EDP_24M 104
> +#define SCLK_EDP 105
> +#define SCLK_RGA 106
> +#define SCLK_ISP 107
> +#define SCLK_ISP_JPE 108
> +#define SCLK_HDMI_HDCP 109
> +#define SCLK_HDMI_CEC 110
> +#define SCLK_HEVC_CABAC 111
> +#define SCLK_HEVC_CORE 112
>
> #define DCLK_VOP0 190
> #define DCLK_VOP1 191
> @@ -75,6 +84,16 @@
> #define ACLK_VOP1 198
> #define ACLK_CRYPTO 199
> #define ACLK_RGA 200
> +#define ACLK_RGA_NIU 201
> +#define ACLK_IEP 202
> +#define ACLK_VIO0_NIU 203
> +#define ACLK_VIP 204
> +#define ACLK_ISP 205
> +#define ACLK_VIO1_NIU 206
> +#define ACLK_HEVC 207
> +#define ACLK_VCODEC 208
> +#define ACLK_CPU 209
> +#define ACLK_PERI 210
>
> /* pclk gates */
> #define PCLK_GPIO0 320
> @@ -112,6 +131,15 @@
> #define PCLK_PS2C 352
> #define PCLK_TIMER 353
> #define PCLK_TZPC 354
> +#define PCLK_EDP_CTRL 355
> +#define PCLK_MIPI_DSI0 356
> +#define PCLK_MIPI_DSI1 357
> +#define PCLK_MIPI_CSI 358
> +#define PCLK_LVDS_PHY 359
> +#define PCLK_HDMI_CTRL 360
> +#define PCLK_VIO2_H2P 361
> +#define PCLK_CPU 362
> +#define PCLK_PERI 363
>
> /* hclk gates */
> #define HCLK_GPS 448
> @@ -137,8 +165,16 @@
> #define HCLK_IEP 468
> #define HCLK_ISP 469
> #define HCLK_RGA 470
> +#define HCLK_VIO_AHB_ARBI 471
> +#define HCLK_VIO_NIU 472
> +#define HCLK_VIP 473
> +#define HCLK_VIO2_H2P 474
> +#define HCLK_HEVC 475
> +#define HCLK_VCODEC 476
> +#define HCLK_CPU 477
> +#define HCLK_PERI 478
>
> -#define CLK_NR_CLKS (HCLK_RGA + 1)
> +#define CLK_NR_CLKS (HCLK_PERI + 1)
>
> /* soft-reset indices */
> #define SRST_CORE0 0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] clk: rockchip: use the clock id for nodes init
2014-09-24 13:36 ` [PATCH 2/2] clk: rockchip: use the clock id for nodes init Kever Yang
@ 2014-09-24 14:13 ` Heiko Stübner
0 siblings, 0 replies; 6+ messages in thread
From: Heiko Stübner @ 2014-09-24 14:13 UTC (permalink / raw)
To: Kever Yang
Cc: Mike Turquette, dianders, sonnyrao, addy.ke, cf, xjq, hj,
huangtao, linux-rockchip, linux-arm-kernel, linux-kernel
Am Mittwoch, 24. September 2014, 21:36:35 schrieb Kever Yang:
> This patch use the new defined clock ID to initial the clock nodes.
>
> This patch also add the clock nodes in PD_VIDEO.
Commit messages like this [two things the patch does, connected by
"and"/"also"] are normally a good indicator that it should be split into two
patches.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
apart from one style-nit below
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
>
> drivers/clk/rockchip/clk-rk3288.c | 79
> ++++++++++++++++++++++----------------- 1 file changed, 45 insertions(+),
> 34 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index 8ea885b..9268818 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -219,12 +219,12 @@ static struct rockchip_clk_branch
> rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(1), 15, 1, MFLAGS,
> 3, 5, DFLAGS),
> DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
> RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
> - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
> + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
> RK3288_CLKGATE_CON(0), 3, GFLAGS),
> - COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0,
> + COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
> RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
> RK3288_CLKGATE_CON(0), 5, GFLAGS),
> - COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0,
> + COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
> RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
> RK3288_CLKGATE_CON(0), 4, GFLAGS),
> GATE(0, "c2c_host", "aclk_cpu_src", 0,
> @@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = { COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p,
> 0,
> RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
> RK3288_CLKGATE_CON(3), 11, GFLAGS),
> + /*
> + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
> + * so we ignore the mux and make clocks nodes as following,
> + * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre.
> + * */
comment ending is off, i.e. "* */" should be simple "*/" instead
> + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
> + RK3288_CLKGATE_CON(9), 0, GFLAGS),
> + GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0,
> + RK3288_CLKGATE_CON(3), 10, GFLAGS),
> + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
> + RK3288_CLKGATE_CON(9), 1, GFLAGS),
>
> COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
> RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
> @@ -309,7 +320,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = { COMPOSITE(0, "aclk_rga_pre",
> mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0,
> 5, DFLAGS,
> RK3288_CLKGATE_CON(3), 5, GFLAGS),
> - COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
> + COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
> RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
> RK3288_CLKGATE_CON(3), 4, GFLAGS),
>
> @@ -320,35 +331,35 @@ static struct rockchip_clk_branch
> rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(29), 6, 2, MFLAGS,
> 8, 8, DFLAGS,
> RK3288_CLKGATE_CON(3), 3, GFLAGS),
>
> - COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0,
> + COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
> RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
> RK3288_CLKGATE_CON(3), 12, GFLAGS),
> - COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
> + COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
> RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
> RK3288_CLKGATE_CON(3), 13, GFLAGS),
>
> - COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
> + COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
> RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
> RK3288_CLKGATE_CON(3), 14, GFLAGS),
> - COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
> + COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
> RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
> RK3288_CLKGATE_CON(3), 15, GFLAGS),
>
> - GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
> + GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
> RK3288_CLKGATE_CON(5), 12, GFLAGS),
> - GATE(0, "sclk_hdmi_cec", "xin32k", 0,
> + GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
> RK3288_CLKGATE_CON(5), 11, GFLAGS),
>
> - COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
> + COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
> RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
> RK3288_CLKGATE_CON(13), 13, GFLAGS),
> - DIV(0, "hclk_hevc", "aclk_hevc", 0,
> + DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
> RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
>
> - COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
> + COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac",
> mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5,
> DFLAGS,
> RK3288_CLKGATE_CON(13), 14, GFLAGS),
> - COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
> + COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p,
> 0, RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
> RK3288_CLKGATE_CON(13), 15, GFLAGS),
>
> @@ -371,13 +382,13 @@ static struct rockchip_clk_branch
> rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_peri_src",
> mux_pll_src_cpll_gpll_p, 0,
> RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
> RK3288_CLKGATE_CON(2), 0, GFLAGS),
> - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0,
> + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
> RK3288_CLKSEL_CON(10), 12, 2, DFLAGS |
CLK_DIVIDER_POWER_OF_TWO,
> RK3288_CLKGATE_CON(2), 3, GFLAGS),
> - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0,
> + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
> RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
> RK3288_CLKGATE_CON(2), 2, GFLAGS),
> - GATE(0, "aclk_peri", "aclk_peri_src", 0,
> + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
> RK3288_CLKGATE_CON(2), 1, GFLAGS),
>
> /*
> @@ -643,34 +654,34 @@ static struct rockchip_clk_branch
> rk3288_clk_branches[] __initdata = { GATE(HCLK_RGA, "hclk_rga", "hclk_vio",
> 0, RK3288_CLKGATE_CON(15), 1, GFLAGS), GATE(HCLK_VOP0, "hclk_vop0",
> "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), GATE(HCLK_VOP1,
> "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), - GATE(0,
> "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
> - GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10,
> GFLAGS), - GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15,
> GFLAGS), + GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0,
> RK3288_CLKGATE_CON(15), 9, GFLAGS), + GATE(HCLK_VIO_NIU, "hclk_vio_niu",
> "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), + GATE(HCLK_VIP,
> "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
> GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3,
> GFLAGS), GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16),
> 1, GFLAGS), - GATE(0, "hclk_vio2_h2p", "hclk_vio", 0,
> RK3288_CLKGATE_CON(16), 10, GFLAGS), - GATE(0, "pclk_mipi_dsi0",
> "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), - GATE(0,
> "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
> - GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6,
> GFLAGS), - GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16),
> 7, GFLAGS), - GATE(0, "pclk_edp_ctrl", "hclk_vio", 0,
> RK3288_CLKGATE_CON(16), 8, GFLAGS), - GATE(0, "pclk_hdmi_ctrl",
"hclk_vio",
> 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), - GATE(0, "pclk_vio2_h2p",
> "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), + GATE(HCLK_VIO2_H2P,
> "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
> + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0,
> RK3288_CLKGATE_CON(16), 4, GFLAGS), + GATE(PCLK_MIPI_DSI1,
> "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
> + GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0,
> RK3288_CLKGATE_CON(16), 6, GFLAGS), + GATE(PCLK_LVDS_PHY, "pclk_lvds_phy",
> "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), + GATE(PCLK_EDP_CTRL,
> "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
> + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0,
> RK3288_CLKGATE_CON(16), 9, GFLAGS), + GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p",
> "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
>
> /* aclk_vio0 gates */
> GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5,
> GFLAGS), - GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2,
> GFLAGS), - GATE(0, "aclk_vio0_niu", "aclk_vio0", 0,
RK3288_CLKGATE_CON(15),
> 11, GFLAGS), - GATE(0, "aclk_vip", "aclk_vio0", 0,
RK3288_CLKGATE_CON(15),
> 14, GFLAGS), + GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0,
> RK3288_CLKGATE_CON(15), 2, GFLAGS), + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu",
> "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), + GATE(ACLK_VIP,
> "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
>
> /* aclk_vio1 gates */
> GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7,
> GFLAGS), - GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2,
> GFLAGS), - GATE(0, "aclk_vio1_niu", "aclk_vio1", 0,
RK3288_CLKGATE_CON(15),
> 12, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0,
> RK3288_CLKGATE_CON(16), 2, GFLAGS), + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu",
> "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
>
> /* aclk_rga_pre gates */
> GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0,
> GFLAGS), - GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0,
> RK3288_CLKGATE_CON(15), 13, GFLAGS), + GATE(ACLK_RGA_NIU, "aclk_rga_niu",
> "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
>
> /*
> * Other ungrouped clocks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Add clock binding id for rk3288
2014-09-24 13:36 [PATCH 0/2] Add clock binding id for rk3288 Kever Yang
2014-09-24 13:36 ` [PATCH 1/2] clk: rockchip: add some needed " Kever Yang
2014-09-24 13:36 ` [PATCH 2/2] clk: rockchip: use the clock id for nodes init Kever Yang
@ 2014-09-25 22:01 ` Mike Turquette
2 siblings, 0 replies; 6+ messages in thread
From: Mike Turquette @ 2014-09-25 22:01 UTC (permalink / raw)
To: Kever Yang, heiko
Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao,
linux-rockchip, Kever Yang, devicetree, Kumar Gala, linux-kernel,
Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel
Quoting Kever Yang (2014-09-24 06:36:33)
> This patch add some clock binding id for different modules
> that under development and going to send upstream.
>
> This patch also add the clock node in PD_VIDEO.
Applied both patches to clk-next and fixed up the comment block locally.
Regards,
Mike
>
>
> Kever Yang (2):
> clk: rockchip: add some needed clock binding id for rk3288
> clk: rockchip: use the clock id for nodes init
>
> drivers/clk/rockchip/clk-rk3288.c | 79 +++++++++++++++++++---------------
> include/dt-bindings/clock/rk3288-cru.h | 38 +++++++++++++++-
> 2 files changed, 82 insertions(+), 35 deletions(-)
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-09-25 22:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-09-24 13:36 [PATCH 0/2] Add clock binding id for rk3288 Kever Yang
2014-09-24 13:36 ` [PATCH 1/2] clk: rockchip: add some needed " Kever Yang
2014-09-24 14:06 ` Heiko Stübner
2014-09-24 13:36 ` [PATCH 2/2] clk: rockchip: use the clock id for nodes init Kever Yang
2014-09-24 14:13 ` Heiko Stübner
2014-09-25 22:01 ` [PATCH 0/2] Add clock binding id for rk3288 Mike Turquette
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