* [PATCH V5 1/4] of: Add vendor prefix for MIPS Technologies, Inc.
2014-11-12 19:43 [PATCH V5 0/4] MIPS: GIC device-tree support Andrew Bresticker
@ 2014-11-12 19:43 ` Andrew Bresticker
2014-11-14 11:25 ` Ralf Baechle
2014-11-12 19:43 ` [PATCH V5 2/4] of: Add binding document for MIPS GIC Andrew Bresticker
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Andrew Bresticker @ 2014-11-12 19:43 UTC (permalink / raw)
To: Ralf Baechle, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Thomas Gleixner, Jason Cooper,
Daniel Lezcano
Cc: Andrew Bresticker, John Crispin, David Daney, Qais Yousef,
James Hogan, Arnd Bergmann, linux-mips, devicetree, linux-kernel
Add the vendor prefix "mti" for MIPS Technologies, Inc.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
I'll update the users of the "mips" prefix to use "mti" instead once
this lands.
No changes from v2/v3/v4.
New for v2.
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 0979393..0221b49 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -98,6 +98,7 @@ mitsubishi Mitsubishi Electric Corporation
mosaixtech Mosaix Technologies, Inc.
moxa Moxa
mpl MPL AG
+mti MIPS Technologies, Inc.
mundoreader Mundo Reader S.L.
murata Murata Manufacturing Co., Ltd.
mxicy Macronix International Co., Ltd.
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V5 1/4] of: Add vendor prefix for MIPS Technologies, Inc.
2014-11-12 19:43 ` [PATCH V5 1/4] of: Add vendor prefix for MIPS Technologies, Inc Andrew Bresticker
@ 2014-11-14 11:25 ` Ralf Baechle
0 siblings, 0 replies; 11+ messages in thread
From: Ralf Baechle @ 2014-11-14 11:25 UTC (permalink / raw)
To: Andrew Bresticker
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Thomas Gleixner, Jason Cooper, Daniel Lezcano, John Crispin,
David Daney, Qais Yousef, James Hogan, Arnd Bergmann, linux-mips,
devicetree, linux-kernel
On Wed, Nov 12, 2014 at 11:43:36AM -0800, Andrew Bresticker wrote:
> Add the vendor prefix "mti" for MIPS Technologies, Inc.
>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> ---
> I'll update the users of the "mips" prefix to use "mti" instead once
> this lands.
>
> No changes from v2/v3/v4.
> New for v2.
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 0979393..0221b49 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -98,6 +98,7 @@ mitsubishi Mitsubishi Electric Corporation
> mosaixtech Mosaix Technologies, Inc.
> moxa Moxa
> mpl MPL AG
> +mti MIPS Technologies, Inc.
> mundoreader Mundo Reader S.L.
> murata Murata Manufacturing Co., Ltd.
> mxicy Macronix International Co., Ltd.
Your patch does almost the same as
https://patchwork.linux-mips.org/patch/8169/
which I already applied and which adds:
+mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V5 2/4] of: Add binding document for MIPS GIC
2014-11-12 19:43 [PATCH V5 0/4] MIPS: GIC device-tree support Andrew Bresticker
2014-11-12 19:43 ` [PATCH V5 1/4] of: Add vendor prefix for MIPS Technologies, Inc Andrew Bresticker
@ 2014-11-12 19:43 ` Andrew Bresticker
2014-11-14 11:30 ` Ralf Baechle
2014-11-12 19:43 ` [PATCH V5 3/4] irqchip: mips-gic: Add device-tree support Andrew Bresticker
2014-11-12 19:43 ` [PATCH V5 4/4] clocksource: " Andrew Bresticker
3 siblings, 1 reply; 11+ messages in thread
From: Andrew Bresticker @ 2014-11-12 19:43 UTC (permalink / raw)
To: Ralf Baechle, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Thomas Gleixner, Jason Cooper,
Daniel Lezcano
Cc: Andrew Bresticker, John Crispin, David Daney, Qais Yousef,
James Hogan, Arnd Bergmann, linux-mips, devicetree, linux-kernel
The Global Interrupt Controller (GIC) present on certain MIPS systems
can be used to route external interrupts to individual VPEs and CPU
interrupt vectors. It also supports a timer and software-generated
interrupts.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
No changes from v4.
Changes from v3:
- removed CPU name from compatible string
- removed available-cpu-vectors, added reserved-cpu-vectors
- made reg property optional
Changes from v2:
- added third cell to specify local vs. shared
- added documentation for timer sub-node
- changed compatible string to include CPU version
Changes from v1:
- moved from mips/ to interrupt-controller/
- removed interrupts and interrupt-parent properties
- added available-cpu-vectors property
- dropped third cell in interrupt specifier
---
.../bindings/interrupt-controller/mips-gic.txt | 55 ++++++++++++++++++++++
.../dt-bindings/interrupt-controller/mips-gic.h | 9 ++++
2 files changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
create mode 100644 include/dt-bindings/interrupt-controller/mips-gic.h
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
new file mode 100644
index 0000000..5a65478
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
@@ -0,0 +1,55 @@
+MIPS Global Interrupt Controller (GIC)
+
+The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+It also supports local (per-processor) interrupts and software-generated
+interrupts which can be used as IPIs. The GIC also includes a free-running
+global timer, per-CPU count/compare timers, and a watchdog.
+
+Required properties:
+- compatible : Should be "mti,gic".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt specifier. Should be 3.
+ - The first cell is the type of interrupt, local or shared.
+ See <include/dt-bindings/interrupt-controller/mips-gic.h>.
+ - The second cell is the GIC interrupt number.
+ - The third cell encodes the interrupt flags.
+ See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
+ flags.
+
+Optional properties:
+- reg : Base address and length of the GIC registers. If not present,
+ the base address reported by the hardware GCR_GIC_BASE will be used.
+- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
+ to which the GIC may not route interrupts. Valid values are 2 - 7.
+ This property is ignored if the CPU is started in EIC mode.
+
+Required properties for timer sub-node:
+- compatible : Should be "mti,gic-timer".
+- interrupts : Interrupt for the GIC local timer.
+- clock-frequency : Clock frequency at which the GIC timers operate.
+
+Example:
+
+ gic: interrupt-controller@1bdc0000 {
+ compatible = "mti,gic";
+ reg = <0x1bdc0000 0x20000>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ mti,reserved-cpu-vectors = <7>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clock-frequency = <50000000>;
+ };
+ };
+
+ uart@18101400 {
+ ...
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+ ...
+ };
diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h
new file mode 100644
index 0000000..cf35a57
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/mips-gic.h
@@ -0,0 +1,9 @@
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define GIC_SHARED 0
+#define GIC_LOCAL 1
+
+#endif
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V5 2/4] of: Add binding document for MIPS GIC
2014-11-12 19:43 ` [PATCH V5 2/4] of: Add binding document for MIPS GIC Andrew Bresticker
@ 2014-11-14 11:30 ` Ralf Baechle
0 siblings, 0 replies; 11+ messages in thread
From: Ralf Baechle @ 2014-11-14 11:30 UTC (permalink / raw)
To: Andrew Bresticker
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Thomas Gleixner, Jason Cooper, Daniel Lezcano, John Crispin,
David Daney, Qais Yousef, James Hogan, Arnd Bergmann, linux-mips,
devicetree, linux-kernel
On Wed, Nov 12, 2014 at 11:43:37AM -0800, Andrew Bresticker wrote:
Patches 2-4 queud for 3.19.
Thanks,
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V5 3/4] irqchip: mips-gic: Add device-tree support
2014-11-12 19:43 [PATCH V5 0/4] MIPS: GIC device-tree support Andrew Bresticker
2014-11-12 19:43 ` [PATCH V5 1/4] of: Add vendor prefix for MIPS Technologies, Inc Andrew Bresticker
2014-11-12 19:43 ` [PATCH V5 2/4] of: Add binding document for MIPS GIC Andrew Bresticker
@ 2014-11-12 19:43 ` Andrew Bresticker
2014-11-12 19:43 ` [PATCH V5 4/4] clocksource: " Andrew Bresticker
3 siblings, 0 replies; 11+ messages in thread
From: Andrew Bresticker @ 2014-11-12 19:43 UTC (permalink / raw)
To: Ralf Baechle, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Thomas Gleixner, Jason Cooper,
Daniel Lezcano
Cc: Andrew Bresticker, John Crispin, David Daney, Qais Yousef,
James Hogan, Arnd Bergmann, linux-mips, devicetree, linux-kernel
Add device-tree support for the MIPS GIC. Update the GIC irqdomain's
xlate() callback to handle the three-cell specifier described in the
MIPS GIC binding document.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jason Cooper <jason@lakedaemon.net>
---
No changes from v4.
Changes from v3:
- use reserved-cpu-vectors property
- read GIC base from CM if no reg property present
Changes from v2:
- rebased on GIC irqchip cleanups
- updated for change in bindings
- only parse first CPU vector
- allow platforms to use EIC mode
Changes from v1:
- updated for change in bindings
- set base address and enable bit in GCR_GIC_BASE
---
drivers/irqchip/irq-mips-gic.c | 92 +++++++++++++++++++++++++++++++++++++++---
1 file changed, 87 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 61ac482..8a9ef74 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -12,12 +12,18 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/mips-gic.h>
+#include <linux/of_address.h>
#include <linux/sched.h>
#include <linux/smp.h>
+#include <asm/mips-cm.h>
#include <asm/setup.h>
#include <asm/traps.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+#include "irqchip.h"
+
unsigned int gic_present;
struct gic_pcpu_mask {
@@ -662,14 +668,34 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
return gic_shared_irq_domain_map(d, virq, hw);
}
+static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+ const u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq,
+ unsigned int *out_type)
+{
+ if (intsize != 3)
+ return -EINVAL;
+
+ if (intspec[0] == GIC_SHARED)
+ *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
+ else if (intspec[0] == GIC_LOCAL)
+ *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
+ else
+ return -EINVAL;
+ *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
+
+ return 0;
+}
+
static struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
- .xlate = irq_domain_xlate_twocell,
+ .xlate = gic_irq_domain_xlate,
};
-void __init gic_init(unsigned long gic_base_addr,
- unsigned long gic_addrspace_size, unsigned int cpu_vec,
- unsigned int irqbase)
+static void __init __gic_init(unsigned long gic_base_addr,
+ unsigned long gic_addrspace_size,
+ unsigned int cpu_vec, unsigned int irqbase,
+ struct device_node *node)
{
unsigned int gicconfig;
@@ -695,7 +721,7 @@ void __init gic_init(unsigned long gic_base_addr,
gic_irq_dispatch);
}
- gic_irq_domain = irq_domain_add_simple(NULL, GIC_NUM_LOCAL_INTRS +
+ gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
gic_shared_intrs, irqbase,
&gic_irq_domain_ops, NULL);
if (!gic_irq_domain)
@@ -705,3 +731,59 @@ void __init gic_init(unsigned long gic_base_addr,
gic_ipi_init();
}
+
+void __init gic_init(unsigned long gic_base_addr,
+ unsigned long gic_addrspace_size,
+ unsigned int cpu_vec, unsigned int irqbase)
+{
+ __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
+}
+
+static int __init gic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct resource res;
+ unsigned int cpu_vec, i = 0, reserved = 0;
+ phys_addr_t gic_base;
+ size_t gic_len;
+
+ /* Find the first available CPU vector. */
+ while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
+ i++, &cpu_vec))
+ reserved |= BIT(cpu_vec);
+ for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
+ if (!(reserved & BIT(cpu_vec)))
+ break;
+ }
+ if (cpu_vec == 8) {
+ pr_err("No CPU vectors available for GIC\n");
+ return -ENODEV;
+ }
+
+ if (of_address_to_resource(node, 0, &res)) {
+ /*
+ * Probe the CM for the GIC base address if not specified
+ * in the device-tree.
+ */
+ if (mips_cm_present()) {
+ gic_base = read_gcr_gic_base() &
+ ~CM_GCR_GIC_BASE_GICEN_MSK;
+ gic_len = 0x20000;
+ } else {
+ pr_err("Failed to get GIC memory range\n");
+ return -ENODEV;
+ }
+ } else {
+ gic_base = res.start;
+ gic_len = resource_size(&res);
+ }
+
+ if (mips_cm_present())
+ write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
+ gic_present = true;
+
+ __gic_init(gic_base, gic_len, cpu_vec, 0, node);
+
+ return 0;
+}
+IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V5 4/4] clocksource: mips-gic: Add device-tree support
2014-11-12 19:43 [PATCH V5 0/4] MIPS: GIC device-tree support Andrew Bresticker
` (2 preceding siblings ...)
2014-11-12 19:43 ` [PATCH V5 3/4] irqchip: mips-gic: Add device-tree support Andrew Bresticker
@ 2014-11-12 19:43 ` Andrew Bresticker
2014-11-17 21:21 ` Daniel Lezcano
2014-11-17 21:28 ` Daniel Lezcano
3 siblings, 2 replies; 11+ messages in thread
From: Andrew Bresticker @ 2014-11-12 19:43 UTC (permalink / raw)
To: Ralf Baechle, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Thomas Gleixner, Jason Cooper,
Daniel Lezcano
Cc: Andrew Bresticker, John Crispin, David Daney, Qais Yousef,
James Hogan, Arnd Bergmann, linux-mips, devicetree, linux-kernel
Parse the GIC timer frequency and interrupt from the device-tree.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
Changes from v4:
- don't probe from irqchip; just warn if DT is wrong
Changes from v3:
- probe from GIC irqchip
New for v3.
---
drivers/clocksource/Kconfig | 1 +
drivers/clocksource/mips-gic-timer.c | 41 ++++++++++++++++++++++++++++++------
2 files changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cb7e7f4..89836dc 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -226,5 +226,6 @@ config CLKSRC_VERSATILE
config CLKSRC_MIPS_GIC
bool
depends on MIPS_GIC
+ select CLKSRC_OF
endmenu
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index a749c81..3bd31b1 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -11,6 +11,7 @@
#include <linux/interrupt.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/notifier.h>
+#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/time.h>
@@ -101,8 +102,6 @@ static int gic_clockevent_init(void)
if (!cpu_has_counter || !gic_frequency)
return -ENXIO;
- gic_timer_irq = MIPS_GIC_IRQ_BASE +
- GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
register_cpu_notifier(&gic_cpu_nb);
@@ -123,17 +122,45 @@ static struct clocksource gic_clocksource = {
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-void __init gic_clocksource_init(unsigned int frequency)
+static void __init __gic_clocksource_init(void)
{
- gic_frequency = frequency;
-
/* Set clocksource mask. */
gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
/* Calculate a somewhat reasonable rating value. */
- gic_clocksource.rating = 200 + frequency / 10000000;
+ gic_clocksource.rating = 200 + gic_frequency / 10000000;
- clocksource_register_hz(&gic_clocksource, frequency);
+ clocksource_register_hz(&gic_clocksource, gic_frequency);
gic_clockevent_init();
}
+
+void __init gic_clocksource_init(unsigned int frequency)
+{
+ gic_frequency = frequency;
+ gic_timer_irq = MIPS_GIC_IRQ_BASE +
+ GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
+
+ __gic_clocksource_init();
+}
+
+static void __init gic_clocksource_of_init(struct device_node *node)
+{
+ if (WARN_ON(!gic_present || !node->parent ||
+ !of_device_is_compatible(node->parent, "mti,gic")))
+ return;
+
+ if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) {
+ pr_err("GIC frequency not specified.\n");
+ return;
+ }
+ gic_timer_irq = irq_of_parse_and_map(node, 0);
+ if (!gic_timer_irq) {
+ pr_err("GIC timer IRQ not specified.\n");
+ return;
+ }
+
+ __gic_clocksource_init();
+}
+CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
+ gic_clocksource_of_init);
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V5 4/4] clocksource: mips-gic: Add device-tree support
2014-11-12 19:43 ` [PATCH V5 4/4] clocksource: " Andrew Bresticker
@ 2014-11-17 21:21 ` Daniel Lezcano
2014-11-17 21:26 ` Andrew Bresticker
2014-11-17 21:28 ` Daniel Lezcano
1 sibling, 1 reply; 11+ messages in thread
From: Daniel Lezcano @ 2014-11-17 21:21 UTC (permalink / raw)
To: Andrew Bresticker, Ralf Baechle, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Thomas Gleixner,
Jason Cooper
Cc: John Crispin, David Daney, Qais Yousef, James Hogan,
Arnd Bergmann, linux-mips, devicetree, linux-kernel
On 11/12/2014 08:43 PM, Andrew Bresticker wrote:
> Parse the GIC timer frequency and interrupt from the device-tree.
>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
Hi Andrew,
through which tree is this patch supposed to go ?
Is there any dependency ?
> ---
> Changes from v4:
> - don't probe from irqchip; just warn if DT is wrong
> Changes from v3:
> - probe from GIC irqchip
> New for v3.
> ---
> drivers/clocksource/Kconfig | 1 +
> drivers/clocksource/mips-gic-timer.c | 41 ++++++++++++++++++++++++++++++------
> 2 files changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index cb7e7f4..89836dc 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -226,5 +226,6 @@ config CLKSRC_VERSATILE
> config CLKSRC_MIPS_GIC
> bool
> depends on MIPS_GIC
> + select CLKSRC_OF
>
> endmenu
> diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
> index a749c81..3bd31b1 100644
> --- a/drivers/clocksource/mips-gic-timer.c
> +++ b/drivers/clocksource/mips-gic-timer.c
> @@ -11,6 +11,7 @@
> #include <linux/interrupt.h>
> #include <linux/irqchip/mips-gic.h>
> #include <linux/notifier.h>
> +#include <linux/of_irq.h>
> #include <linux/percpu.h>
> #include <linux/smp.h>
> #include <linux/time.h>
> @@ -101,8 +102,6 @@ static int gic_clockevent_init(void)
> if (!cpu_has_counter || !gic_frequency)
> return -ENXIO;
>
> - gic_timer_irq = MIPS_GIC_IRQ_BASE +
> - GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
> setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
>
> register_cpu_notifier(&gic_cpu_nb);
> @@ -123,17 +122,45 @@ static struct clocksource gic_clocksource = {
> .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> };
>
> -void __init gic_clocksource_init(unsigned int frequency)
> +static void __init __gic_clocksource_init(void)
> {
> - gic_frequency = frequency;
> -
> /* Set clocksource mask. */
> gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
>
> /* Calculate a somewhat reasonable rating value. */
> - gic_clocksource.rating = 200 + frequency / 10000000;
> + gic_clocksource.rating = 200 + gic_frequency / 10000000;
>
> - clocksource_register_hz(&gic_clocksource, frequency);
> + clocksource_register_hz(&gic_clocksource, gic_frequency);
>
> gic_clockevent_init();
> }
> +
> +void __init gic_clocksource_init(unsigned int frequency)
> +{
> + gic_frequency = frequency;
> + gic_timer_irq = MIPS_GIC_IRQ_BASE +
> + GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
> +
> + __gic_clocksource_init();
> +}
> +
> +static void __init gic_clocksource_of_init(struct device_node *node)
> +{
> + if (WARN_ON(!gic_present || !node->parent ||
> + !of_device_is_compatible(node->parent, "mti,gic")))
> + return;
> +
> + if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) {
> + pr_err("GIC frequency not specified.\n");
> + return;
> + }
> + gic_timer_irq = irq_of_parse_and_map(node, 0);
> + if (!gic_timer_irq) {
> + pr_err("GIC timer IRQ not specified.\n");
> + return;
> + }
> +
> + __gic_clocksource_init();
> +}
> +CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
> + gic_clocksource_of_init);
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V5 4/4] clocksource: mips-gic: Add device-tree support
2014-11-17 21:21 ` Daniel Lezcano
@ 2014-11-17 21:26 ` Andrew Bresticker
2014-11-17 21:29 ` Daniel Lezcano
0 siblings, 1 reply; 11+ messages in thread
From: Andrew Bresticker @ 2014-11-17 21:26 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Ralf Baechle, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Thomas Gleixner, Jason Cooper,
John Crispin, David Daney, Qais Yousef, James Hogan,
Arnd Bergmann, Linux-MIPS, devicetree, linux-kernel
On Mon, Nov 17, 2014 at 1:21 PM, Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
> On 11/12/2014 08:43 PM, Andrew Bresticker wrote:
>>
>> Parse the GIC timer frequency and interrupt from the device-tree.
>>
>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
>
> Hi Andrew,
>
> through which tree is this patch supposed to go ?
>
> Is there any dependency ?
There are quite a few dependencies, so this series and all the other
MIPS GIC stuff is going through the MIPS tree.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V5 4/4] clocksource: mips-gic: Add device-tree support
2014-11-17 21:26 ` Andrew Bresticker
@ 2014-11-17 21:29 ` Daniel Lezcano
0 siblings, 0 replies; 11+ messages in thread
From: Daniel Lezcano @ 2014-11-17 21:29 UTC (permalink / raw)
To: Andrew Bresticker
Cc: Ralf Baechle, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Thomas Gleixner, Jason Cooper,
John Crispin, David Daney, Qais Yousef, James Hogan,
Arnd Bergmann, Linux-MIPS, devicetree, linux-kernel
On 11/17/2014 10:26 PM, Andrew Bresticker wrote:
> On Mon, Nov 17, 2014 at 1:21 PM, Daniel Lezcano
> <daniel.lezcano@linaro.org> wrote:
>> On 11/12/2014 08:43 PM, Andrew Bresticker wrote:
>>>
>>> Parse the GIC timer frequency and interrupt from the device-tree.
>>>
>>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>>
>>
>> Hi Andrew,
>>
>> through which tree is this patch supposed to go ?
>>
>> Is there any dependency ?
>
> There are quite a few dependencies, so this series and all the other
> MIPS GIC stuff is going through the MIPS tree.
Ok thanks.
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V5 4/4] clocksource: mips-gic: Add device-tree support
2014-11-12 19:43 ` [PATCH V5 4/4] clocksource: " Andrew Bresticker
2014-11-17 21:21 ` Daniel Lezcano
@ 2014-11-17 21:28 ` Daniel Lezcano
1 sibling, 0 replies; 11+ messages in thread
From: Daniel Lezcano @ 2014-11-17 21:28 UTC (permalink / raw)
To: Andrew Bresticker, Ralf Baechle, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Thomas Gleixner,
Jason Cooper
Cc: John Crispin, David Daney, Qais Yousef, James Hogan,
Arnd Bergmann, linux-mips, devicetree, linux-kernel
On 11/12/2014 08:43 PM, Andrew Bresticker wrote:
> Parse the GIC timer frequency and interrupt from the device-tree.
>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
> Changes from v4:
> - don't probe from irqchip; just warn if DT is wrong
> Changes from v3:
> - probe from GIC irqchip
> New for v3.
> ---
> drivers/clocksource/Kconfig | 1 +
> drivers/clocksource/mips-gic-timer.c | 41 ++++++++++++++++++++++++++++++------
> 2 files changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index cb7e7f4..89836dc 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -226,5 +226,6 @@ config CLKSRC_VERSATILE
> config CLKSRC_MIPS_GIC
> bool
> depends on MIPS_GIC
> + select CLKSRC_OF
>
> endmenu
> diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
> index a749c81..3bd31b1 100644
> --- a/drivers/clocksource/mips-gic-timer.c
> +++ b/drivers/clocksource/mips-gic-timer.c
> @@ -11,6 +11,7 @@
> #include <linux/interrupt.h>
> #include <linux/irqchip/mips-gic.h>
> #include <linux/notifier.h>
> +#include <linux/of_irq.h>
> #include <linux/percpu.h>
> #include <linux/smp.h>
> #include <linux/time.h>
> @@ -101,8 +102,6 @@ static int gic_clockevent_init(void)
> if (!cpu_has_counter || !gic_frequency)
> return -ENXIO;
>
> - gic_timer_irq = MIPS_GIC_IRQ_BASE +
> - GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
> setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
>
> register_cpu_notifier(&gic_cpu_nb);
> @@ -123,17 +122,45 @@ static struct clocksource gic_clocksource = {
> .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> };
>
> -void __init gic_clocksource_init(unsigned int frequency)
> +static void __init __gic_clocksource_init(void)
> {
> - gic_frequency = frequency;
> -
> /* Set clocksource mask. */
> gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
>
> /* Calculate a somewhat reasonable rating value. */
> - gic_clocksource.rating = 200 + frequency / 10000000;
> + gic_clocksource.rating = 200 + gic_frequency / 10000000;
>
> - clocksource_register_hz(&gic_clocksource, frequency);
> + clocksource_register_hz(&gic_clocksource, gic_frequency);
>
> gic_clockevent_init();
> }
> +
> +void __init gic_clocksource_init(unsigned int frequency)
> +{
> + gic_frequency = frequency;
> + gic_timer_irq = MIPS_GIC_IRQ_BASE +
> + GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
> +
> + __gic_clocksource_init();
> +}
> +
> +static void __init gic_clocksource_of_init(struct device_node *node)
> +{
> + if (WARN_ON(!gic_present || !node->parent ||
> + !of_device_is_compatible(node->parent, "mti,gic")))
> + return;
> +
> + if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) {
> + pr_err("GIC frequency not specified.\n");
> + return;
> + }
> + gic_timer_irq = irq_of_parse_and_map(node, 0);
> + if (!gic_timer_irq) {
> + pr_err("GIC timer IRQ not specified.\n");
> + return;
> + }
> +
> + __gic_clocksource_init();
> +}
> +CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
> + gic_clocksource_of_init);
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 11+ messages in thread