From: James Hogan <james.hogan@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>, James Hogan <james.hogan@imgtec.com>
Subject: [PATCH 2/9] MIPS: Use CAUSEF_TI, CAUSEF_PCI constants
Date: Tue, 27 Jan 2015 21:45:48 +0000 [thread overview]
Message-ID: <1422395155-16511-3-git-send-email-james.hogan@imgtec.com> (raw)
In-Reply-To: <1422395155-16511-1-git-send-email-james.hogan@imgtec.com>
Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than
the magic values (1 << 30) and (1 << 26).
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/kernel/cevt-r4k.c | 2 +-
arch/mips/oprofile/op_model_mipsxx.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 02dd77955a6f..d68a678b7e4e 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -76,7 +76,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
* above we now know that the reason we got here must be a timer
* interrupt. Being the paranoiacs we are we check anyway.
*/
- if (!r2 || (read_c0_cause() & (1 << 30))) {
+ if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
/* Clear Count/Compare Interrupt */
write_c0_compare(read_c0_compare());
cd = &per_cpu(mips_clockevent_device, cpu);
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 01f721a85c5b..faf0d4ad0cc2 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -246,7 +246,7 @@ static int mipsxx_perfcount_handler(void)
unsigned int counter;
int handled = IRQ_NONE;
- if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+ if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
return handled;
switch (counters) {
--
2.0.5
next prev parent reply other threads:[~2015-01-27 21:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-27 21:45 [PATCH 0/9] MIPS: Allow shared IRQ for timer & perf counter James Hogan
2015-01-27 21:45 ` [PATCH 1/9] MIPS: cevt-r4k: Move handle_perf_irq() out of header James Hogan
2015-01-27 21:45 ` James Hogan [this message]
2015-01-27 21:45 ` [PATCH 3/9] MIPS: Remove redundant IPTI==IPPCI logic James Hogan
2015-01-27 21:45 ` [PATCH 4/9] irqchip: mips-gic: Fix typo in comment James Hogan
2015-01-28 10:48 ` Andrew Bresticker
2015-01-27 21:45 ` [PATCH 5/9] irqchip: mips-gic: Add missing definitions for FDC IRQ James Hogan
2015-01-28 10:49 ` Andrew Bresticker
2015-01-27 21:45 ` [PATCH 6/9] MIPS: cevt-r4k: Make interrupt handler shared James Hogan
2015-01-27 21:45 ` [PATCH 7/9] MIPS: perf: Allow sharing IRQ with timer James Hogan
2015-01-27 21:45 ` [PATCH 8/9] MIPS: OProfile: " James Hogan
2015-01-27 21:45 ` [PATCH 9/9] MIPS: Allow shared IRQ for timer & perf counter James Hogan
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