From: James Hogan <james.hogan@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>,
James Hogan <james.hogan@imgtec.com>,
Andrew Bresticker <abrestic@chromium.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Subject: [PATCH 5/9] irqchip: mips-gic: Add missing definitions for FDC IRQ
Date: Tue, 27 Jan 2015 21:45:51 +0000 [thread overview]
Message-ID: <1422395155-16511-6-git-send-email-james.hogan@imgtec.com> (raw)
In-Reply-To: <1422395155-16511-1-git-send-email-james.hogan@imgtec.com>
Add missing VPE_PEND, VPE_RMASK and VPE_SMASK definitions for the local
FDC interrupt.
These local interrupt definitions aren't directly used, but if they
exist they should be complete.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
---
include/linux/irqchip/mips-gic.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index 420f77b34d02..ff0e75f40ef5 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -165,6 +165,8 @@
#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
#define GIC_VPE_PEND_SWINT1_SHF 5
#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
+#define GIC_VPE_PEND_FDC_SHF 6
+#define GIC_VPE_PEND_FDC_MSK (MSK(1) << GIC_VPE_PEND_FDC_SHF)
/* GIC_VPE_RMASK Masks */
#define GIC_VPE_RMASK_WD_SHF 0
@@ -179,6 +181,8 @@
#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
#define GIC_VPE_RMASK_SWINT1_SHF 5
#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
+#define GIC_VPE_RMASK_FDC_SHF 6
+#define GIC_VPE_RMASK_FDC_MSK (MSK(1) << GIC_VPE_RMASK_FDC_SHF)
/* GIC_VPE_SMASK Masks */
#define GIC_VPE_SMASK_WD_SHF 0
@@ -193,6 +197,8 @@
#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
#define GIC_VPE_SMASK_SWINT1_SHF 5
#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
+#define GIC_VPE_SMASK_FDC_SHF 6
+#define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF)
/* GIC nomenclature for Core Interrupt Pins. */
#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
--
2.0.5
next prev parent reply other threads:[~2015-01-27 21:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-27 21:45 [PATCH 0/9] MIPS: Allow shared IRQ for timer & perf counter James Hogan
2015-01-27 21:45 ` [PATCH 1/9] MIPS: cevt-r4k: Move handle_perf_irq() out of header James Hogan
2015-01-27 21:45 ` [PATCH 2/9] MIPS: Use CAUSEF_TI, CAUSEF_PCI constants James Hogan
2015-01-27 21:45 ` [PATCH 3/9] MIPS: Remove redundant IPTI==IPPCI logic James Hogan
2015-01-27 21:45 ` [PATCH 4/9] irqchip: mips-gic: Fix typo in comment James Hogan
2015-01-28 10:48 ` Andrew Bresticker
2015-01-27 21:45 ` James Hogan [this message]
2015-01-28 10:49 ` [PATCH 5/9] irqchip: mips-gic: Add missing definitions for FDC IRQ Andrew Bresticker
2015-01-27 21:45 ` [PATCH 6/9] MIPS: cevt-r4k: Make interrupt handler shared James Hogan
2015-01-27 21:45 ` [PATCH 7/9] MIPS: perf: Allow sharing IRQ with timer James Hogan
2015-01-27 21:45 ` [PATCH 8/9] MIPS: OProfile: " James Hogan
2015-01-27 21:45 ` [PATCH 9/9] MIPS: Allow shared IRQ for timer & perf counter James Hogan
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