From: Philipp Zabel <p.zabel@pengutronix.de>
To: Liu Ying <Ying.Liu@freescale.com>
Cc: stefan.wahren@i2se.com, devicetree@vger.kernel.org,
linux@arm.linux.org.uk, andyshrk@gmail.com,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
a.hajda@samsung.com, kernel@pengutronix.de,
mturquette@linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
Date: Wed, 11 Feb 2015 14:00:48 +0100 [thread overview]
Message-ID: <1423659648.4680.18.camel@pengutronix.de> (raw)
In-Reply-To: <20150211072128.GA13301@victor>
Hi Liu,
Am Mittwoch, den 11.02.2015, 15:21 +0800 schrieb Liu Ying:
[...]
> Our internal MIPI DSI SoC owner gave me some feedbacks on the clock sources.
> According to him, the Synopsys DesignWare MIPI DSI host controller needs four
> clock sources from an application platform - pclk, refclk, cfg_clk and dpipclk.
> These clocks are mentioned in the "DesignWare Cores MIPI DSI Host Controller
> Databook, 1.01a1.30a.pdf" documentation.
>
> Quote some words from the documentation:
> pclk - APB clock signal.
> refclk - D-PHY reference clock used for Master-side serial clock generation in
> clock multiplying unit(PLL).
> cfg_clk - D-PHY Configuration clock used for the initialization of the PHY. It
> is also used for exiting ULPS state.
> dpipclk - Input Pixel clock signal.
>
> The below table reflects how does i.MX6Q/DL provide the pclk, refclk and cfg_clk
> for the DesignWare MIPI DSI host controller, according to the SoC owner.
> ----------------------------------------------------------------------------
> | Synopsys | i.MX6Q/DL MIPI DSI |
> | DesignWare |------------------------------------------------------------|
> | documentation | clock | clock root | CCM_CCGR bits |
> |---------------|------------|--------------------|--------------------------|
> | pclk | ips_clk | ipg_clk_root | mipi_core_cfg_clk_enable |
> |---------------|------------|--------------------|--------------------------|
> | refclk | pll_refclk | video_27m_clk_root | mipi_core_cfg_clk_enable |
> |---------------|------------|--------------------|--------------------------|
> | cfg_clk | cfg_clk | video_27m_clk_root | mipi_core_cfg_clk_enable |
> ----------------------------------------------------------------------------
>
> I think we should add a new clock "IMX6QDL_CLK_MIPI_IPG" as a shared clock gate
> clock.
That would be necessary if the pclk clock rate mattered or would be set
anywhere.
> And, the clock-names property should exactly contain "pclk", "refclk"
> and "cfg_clk", right?
My personal preference would be to drop the superfluous "clk" prefix if
the resulting clock name is still clearly relatable to the official
name. Existing clock naming for the pclk is a bit mixed -
The "snps,dw-apb-timer" binding uses "pclk", which seems to be quite
common in other places, too. The "snps,dw-apb-uart" bindings use
"apb_pclk". "snps,dw-hdmi-tx" uses "iahb" and "isfr" without the clk
suffix.
How about "pclk", "ref" and "cfg"?
regards
Philipp
next prev parent reply other threads:[~2015-02-11 13:01 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-31 8:23 [PATCH RFC v8 00/21] Add support for i.MX MIPI DSI DRM driver Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 01/21] clk: divider: Correct parent clk round rate if no bestdiv is normally found Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 02/21] of: Add vendor prefix for Himax Technologies Inc Liu Ying
2015-02-04 16:02 ` Rob Herring
2015-02-05 2:20 ` Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 03/21] of: Add vendor prefix for Truly Semiconductors Limited Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 04/21] ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 05/21] ARM: imx6q: clk: Add the video_27m clock Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 06/21] ARM: imx6q: clk: Change hdmi_isfr clock's parent to be " Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 07/21] ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 08/21] ARM: imx6q: clk: Add support for mipi_core_cfg clock as " Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 09/21] ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 10/21] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Liu Ying
2015-02-05 10:10 ` Philipp Zabel
2015-02-06 8:13 ` Liu Ying
2015-02-11 7:21 ` Liu Ying
2015-02-11 13:00 ` Philipp Zabel [this message]
2015-02-11 14:09 ` Liu Ying
2015-02-11 15:23 ` Philipp Zabel
2015-02-12 2:14 ` Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 12/21] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 13/21] Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 14/21] drm: imx: Support Synopsys DesignWare MIPI DSI host controller Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 15/21] Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 16/21] drm: panel: Add support for Himax HX8369A MIPI DSI panel Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 17/21] ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 18/21] ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 19/21] ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 20/21] ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller Liu Ying
2014-12-31 8:23 ` [PATCH RFC v8 21/21] ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel Liu Ying
2015-02-02 2:17 ` [PATCH RFC v8 00/21] Add support for i.MX MIPI DSI DRM driver Liu Ying
2015-02-02 5:34 ` Liu Ying
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