* [PATCH 1/2] phy: Add binding document for Pistachio USB2.0 PHY
2015-04-01 20:16 [PATCH 0/2] Pistachio USB2.0 PHY Andrew Bresticker
@ 2015-04-01 20:16 ` Andrew Bresticker
2015-04-01 20:16 ` [PATCH 2/2] phy: Add driver " Andrew Bresticker
1 sibling, 0 replies; 4+ messages in thread
From: Andrew Bresticker @ 2015-04-01 20:16 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Ralf Baechle
Cc: devicetree, linux-mips, linux-kernel, Andrew Bresticker,
James Hartley, Damien Horsley, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala
Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
---
.../devicetree/bindings/phy/pistachio-usb-phy.txt | 29 ++++++++++++++++++++++
include/dt-bindings/phy/phy-pistachio-usb.h | 16 ++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
new file mode 100644
index 0000000..afbc7e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
@@ -0,0 +1,29 @@
+IMG Pistachio USB PHY
+=====================
+
+Required properties:
+--------------------
+ - compatible: Must be "img,pistachio-usb-phy".
+ - #phy-cells: Must be 0. See ./phy-bindings.txt for details.
+ - clocks: Must contain an entry for each entry in clock-names.
+ See ../clock/clock-bindings.txt for details.
+ - clock-names: Must include "usb_phy".
+ - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
+ - img,refclk: Indicates the reference clock source for the USB PHY.
+ See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
+
+Optional properties:
+--------------------
+ - phy-supply: USB VBUS supply. Must supply 5.0V.
+
+Example:
+--------
+usb_phy: usb-phy {
+ compatible = "img,pistachio-usb-phy";
+ clocks = <&clk_core CLK_USB_PHY>;
+ clock-names = "usb_phy";
+ phy-supply = <&usb_vbus>;
+ img,refclk = <REFCLK_CLK_CORE>;
+ img,cr-top = <&cr_top>;
+ #phy-cells = <0>;
+};
diff --git a/include/dt-bindings/phy/phy-pistachio-usb.h b/include/dt-bindings/phy/phy-pistachio-usb.h
new file mode 100644
index 0000000..d1877aa
--- /dev/null
+++ b/include/dt-bindings/phy/phy-pistachio-usb.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PHY_PISTACHIO
+#define _DT_BINDINGS_PHY_PISTACHIO
+
+#define REFCLK_XO_CRYSTAL 0x0
+#define REFCLK_X0_EXT_CLK 0x1
+#define REFCLK_CLK_CORE 0x2
+
+#endif /* _DT_BINDINGS_PHY_PISTACHIO */
--
2.2.0.rc0.207.ga3a616c
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] phy: Add driver for Pistachio USB2.0 PHY
2015-04-01 20:16 [PATCH 0/2] Pistachio USB2.0 PHY Andrew Bresticker
2015-04-01 20:16 ` [PATCH 1/2] phy: Add binding document for " Andrew Bresticker
@ 2015-04-01 20:16 ` Andrew Bresticker
2015-04-01 20:38 ` Joe Perches
1 sibling, 1 reply; 4+ messages in thread
From: Andrew Bresticker @ 2015-04-01 20:16 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Ralf Baechle
Cc: devicetree, linux-mips, linux-kernel, Andrew Bresticker,
James Hartley, Damien Horsley
Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-pistachio-usb.c | 206 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 214 insertions(+)
create mode 100644 drivers/phy/phy-pistachio-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2962de2..717f30d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -225,6 +225,13 @@ config PHY_EXYNOS5_USBDRD
This driver provides PHY interface for USB 3.0 DRD controller
present on Exynos5 SoC series.
+config PHY_PISTACHIO_USB
+ tristate "IMG Pistachio USB2.0 PHY driver"
+ depends on MACH_PISTACHIO
+ select GENERIC_PHY
+ help
+ Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+
config PHY_QCOM_APQ8064_SATA
tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
depends on ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f080e1b..e561708 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
+obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
diff --git a/drivers/phy/phy-pistachio-usb.c b/drivers/phy/phy-pistachio-usb.c
new file mode 100644
index 0000000..84cb760
--- /dev/null
+++ b/drivers/phy/phy-pistachio-usb.c
@@ -0,0 +1,206 @@
+/*
+ * IMG Pistachio USB PHY driver
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy-pistachio-usb.h>
+
+#define USB_PHY_CONTROL1 0x04
+#define USB_PHY_CONTROL1_FSEL_SHIFT 2
+#define USB_PHY_CONTROL1_FSEL_MASK 0x7
+
+#define USB_PHY_STRAP_CONTROL 0x10
+#define USB_PHY_STRAP_CONTROL_REFCLK_SHIFT 4
+#define USB_PHY_STRAP_CONTROL_REFCLK_MASK 0x3
+
+#define USB_PHY_STATUS 0x14
+#define USB_PHY_STATUS_RX_PHY_CLK BIT(9)
+#define USB_PHY_STATUS_RX_UTMI_CLK BIT(8)
+#define USB_PHY_STATUS_VBUS_FAULT BIT(7)
+
+struct pistachio_usb_phy {
+ struct device *dev;
+ struct regmap *cr_top;
+ struct clk *phy_clk;
+ unsigned int refclk;
+};
+
+static const unsigned long fsel_rate_map[] = {
+ 9600000,
+ 10000000,
+ 12000000,
+ 19200000,
+ 20000000,
+ 24000000,
+ 0,
+ 50000000,
+};
+
+static int pistachio_usb_phy_power_on(struct phy *phy)
+{
+ struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
+ unsigned long timeout, rate;
+ unsigned int i;
+ int ret;
+
+ ret = clk_prepare_enable(p_phy->phy_clk);
+ if (ret < 0) {
+ dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
+ return ret;
+ }
+
+ regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL,
+ USB_PHY_STRAP_CONTROL_REFCLK_MASK <<
+ USB_PHY_STRAP_CONTROL_REFCLK_SHIFT,
+ p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT);
+
+ rate = clk_get_rate(p_phy->phy_clk);
+ if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) {
+ dev_err(p_phy->dev, "Unspported rate for XO crystal: %ld\n",
+ rate);
+ ret = -EINVAL;
+ goto disable_clk;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(fsel_rate_map); i++) {
+ if (rate == fsel_rate_map[i])
+ break;
+ }
+ if (i == ARRAY_SIZE(fsel_rate_map)) {
+ dev_err(p_phy->dev, "Unspported clock rate: %lu\n", rate);
+ ret = -EINVAL;
+ goto disable_clk;
+ }
+
+ regmap_update_bits(p_phy->cr_top, USB_PHY_CONTROL1,
+ USB_PHY_CONTROL1_FSEL_MASK <<
+ USB_PHY_CONTROL1_FSEL_SHIFT,
+ i << USB_PHY_CONTROL1_FSEL_SHIFT);
+
+ timeout = jiffies + msecs_to_jiffies(200);
+ while (time_before(jiffies, timeout)) {
+ unsigned int val;
+
+ regmap_read(p_phy->cr_top, USB_PHY_STATUS, &val);
+ if (val & USB_PHY_STATUS_VBUS_FAULT) {
+ dev_err(p_phy->dev, "VBUS fault detected\n");
+ ret = -EIO;
+ goto disable_clk;
+ }
+ if ((val & USB_PHY_STATUS_RX_PHY_CLK) &&
+ (val & USB_PHY_STATUS_RX_UTMI_CLK))
+ return 0;
+ usleep_range(1000, 1500);
+ }
+
+ dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
+ ret = -ETIMEDOUT;
+
+disable_clk:
+ clk_disable_unprepare(p_phy->phy_clk);
+ return ret;
+}
+
+static int pistachio_usb_phy_power_off(struct phy *phy)
+{
+ struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
+
+ clk_disable_unprepare(p_phy->phy_clk);
+
+ return 0;
+}
+
+static const struct phy_ops pistachio_usb_phy_ops = {
+ .power_on = pistachio_usb_phy_power_on,
+ .power_off = pistachio_usb_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int pistachio_usb_phy_probe(struct platform_device *pdev)
+{
+ struct pistachio_usb_phy *p_phy;
+ struct phy_provider *provider;
+ struct phy *phy;
+ int ret;
+
+ p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
+ if (!p_phy)
+ return -ENOMEM;
+ p_phy->dev = &pdev->dev;
+ platform_set_drvdata(pdev, p_phy);
+
+ p_phy->cr_top = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node,
+ "img,cr-top");
+ if (IS_ERR(p_phy->cr_top)) {
+ dev_err(p_phy->dev, "Failed to get CR_TOP registers: %ld\n",
+ PTR_ERR(p_phy->cr_top));
+ return PTR_ERR(p_phy->cr_top);
+ }
+
+ p_phy->phy_clk = devm_clk_get(p_phy->dev, "usb_phy");
+ if (IS_ERR(p_phy->phy_clk)) {
+ dev_err(p_phy->dev, "Failed to get usb_phy clock: %ld\n",
+ PTR_ERR(p_phy->phy_clk));
+ return PTR_ERR(p_phy->phy_clk);
+ }
+
+ ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk",
+ &p_phy->refclk);
+ if (ret < 0) {
+ dev_err(p_phy->dev, "No reference clock selector specified\n");
+ return ret;
+ }
+
+ phy = devm_phy_create(p_phy->dev, NULL, &pistachio_usb_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(p_phy->dev, "Failed to create PHY: %ld\n",
+ PTR_ERR(phy));
+ return PTR_ERR(phy);
+ }
+ phy_set_drvdata(phy, p_phy);
+
+ provider = devm_of_phy_provider_register(p_phy->dev,
+ of_phy_simple_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(p_phy->dev, "Failed to register PHY provider: %ld\n",
+ PTR_ERR(provider));
+ return PTR_ERR(provider);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id pistachio_usb_phy_of_match[] = {
+ { .compatible = "img,pistachio-usb-phy", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, pistachio_usb_phy_of_match);
+
+static struct platform_driver pistachio_usb_phy_driver = {
+ .probe = pistachio_usb_phy_probe,
+ .driver = {
+ .name = "pistachio-usb-phy",
+ .of_match_table = pistachio_usb_phy_of_match,
+ },
+};
+module_platform_driver(pistachio_usb_phy_driver);
+
+MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
+MODULE_DESCRIPTION("IMG Pistachio USB2.0 PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.2.0.rc0.207.ga3a616c
^ permalink raw reply related [flat|nested] 4+ messages in thread