[PATCH V7 0/9] Tegra xHCI support

[PATCH V7 0/9] Tegra xHCI support

[Andrew Bresticker]

This series adds support for xHCI on NVIDIA Tegra SoCs.  This includes:
 - patches 1, 2, and 3: minor cleanups for mailbox framework and xHCI,
 - patches 4 and 5: adding an MFD driver for the XUSB cmoplex,
 - patches 6 and 7: adding a driver for the mailbox used to communicate
   with the xHCI controller's firmware, and
 - patches 8 and 9: adding a xHCI host-controller driver.

The addition of USB PHY support to the XUSB padctl driver has been dropped
from v7.  Thierry will be posting those patches later.

Given the many compile and run-time dependencies in this series, it is probably
best if the first 3 patches are picked up by the relevant maintainers in topic
branches so that the remainder of the series can go through the Tegra tree.

Tested on Jetson TK1 and Nyan-Big with a variety of USB2.0 and USB3.0 memory
sticks and ethernet dongles.  This has also been tested, with additional
out-of-tree patches, on a Tegra132-based board.

Based on v4.1-rc1.  A branch with the entire series is available at:
  https://github.com/abrestic/linux/tree/tegra-xhci-v7

Changes from v6:
 - Dropped PHY changes from series.  Will be posted later by Thierry.
 - Added an MFD device with the mailbox and xHCI host as sub-devices.

Changes from v5:
 - Addressed review comments from Jassi and Felipe.

Changes from v4:
 - Made USB support optional in padctl driver.
 - Made usb3-port a pinconfig property again.
 - Cleaned up mbox_request_channel() error handling and allowed it to defer
   probing (patch 3).
 - Minor xHCI (patch 1) and mailbox framework (patch 2) cleanups suggested
   by Thierry.
 - Addressed Thierry's review comments.

Changes from v3:
 - Fixed USB2.0 flakiness on Jetson-TK1.
 - Switched to 32-bit DMA mask for host.
 - Addressed Stephen's review comments.

Chagnes from v2:
 - Dropped mailbox channel specifier.  The mailbox driver allocates virtual
   channels backed by the single physical channel.
 - Added support for HS_CURR_LEVEL adjustment pinconfig property, which
   will be required for the Blaze board.
 - Addressed Stephen's review comments.

Changes from v1:
 - Converted mailbox driver to use the common mailbox framework.
 - Fixed up host driver so that it can now be built and used as a module.
 - Addressed Stephen's review comments.
 - Misc. cleanups.

Andrew Bresticker (8):
  xhci: Set shared HCD's hcd_priv in xhci_gen_setup
  mailbox: Make struct mbox_controller's ops field const
  mfd: Add binding document for NVIDIA Tegra XUSB
  mfd: Add driver for NVIDIA Tegra XUSB
  mailbox: Add NVIDIA Tegra XUSB mailbox binding
  mailbox: Add NVIDIA Tegra XUSB mailbox driver
  usb: Add NVIDIA Tegra xHCI controller binding
  usb: xhci: Add NVIDIA Tegra xHCI host-controller driver

Benson Leung (1):
  mailbox: Fix up error handling in mbox_request_channel()

 .../bindings/mailbox/nvidia,tegra124-xusb-mbox.txt |  30 +
 .../bindings/mfd/nvidia,tegra124-xusb.txt          |  46 +
 .../bindings/usb/nvidia,tegra124-xhci.txt          |  90 ++
 drivers/mailbox/Kconfig                            |   8 +
 drivers/mailbox/Makefile                           |   2 +
 drivers/mailbox/mailbox.c                          |  11 +-
 drivers/mailbox/omap-mailbox.c                     |   6 +-
 drivers/mailbox/tegra-xusb-mailbox.c               | 275 ++++++
 drivers/mfd/Kconfig                                |   7 +
 drivers/mfd/Makefile                               |   1 +
 drivers/mfd/tegra-xusb.c                           | 167 ++++
 drivers/usb/host/Kconfig                           |  10 +
 drivers/usb/host/Makefile                          |   1 +
 drivers/usb/host/xhci-pci.c                        |   5 -
 drivers/usb/host/xhci-plat.c                       |   5 -
 drivers/usb/host/xhci-tegra.c                      | 946 +++++++++++++++++++++
 drivers/usb/host/xhci.c                            |   6 +-
 include/linux/mailbox_controller.h                 |   2 +-
 include/soc/tegra/xusb.h                           |  49 ++
 19 files changed, 1647 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt
 create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
 create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
 create mode 100644 drivers/mailbox/tegra-xusb-mailbox.c
 create mode 100644 drivers/mfd/tegra-xusb.c
 create mode 100644 drivers/usb/host/xhci-tegra.c
 create mode 100644 include/soc/tegra/xusb.h

-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 1/9] xhci: Set shared HCD's hcd_priv in xhci_gen_setup

[Andrew Bresticker]

xhci_gen_setup() sets the hcd_priv field for the primary HCD, but not
for the shared HCD, requiring xHCI host-controller drivers to set it
between usb_create_shared_hcd() and usb_add_hcd().  There's no reason
xhci_gen_setup() can't set the shared HCD's hcd_priv as well, so move
that bit out of the host-controller drivers and into xhci_gen_setup().

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Cc: Mathias Nyman <mathias.nyman@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
No changes from v5/v6.
New for v5.
Peviously posted here: https://lkml.org/lkml/2014/10/30/726
---
 drivers/usb/host/xhci-pci.c  | 5 -----
 drivers/usb/host/xhci-plat.c | 5 -----
 drivers/usb/host/xhci.c      | 6 +++---
 3 files changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 2af32e2..f9ce741 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -247,11 +247,6 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 		goto dealloc_usb2_hcd;
 	}
 
-	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
-	 * is called by usb_add_hcd().
-	 */
-	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
-
 	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 			IRQF_SHARED);
 	if (retval)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 783e819..852b1e9 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -147,11 +147,6 @@ static int xhci_plat_probe(struct platform_device *pdev)
 	if ((node && of_property_read_bool(node, "usb3-lpm-capable")) ||
 			(pdata && pdata->usb3_lpm_capable))
 		xhci->quirks |= XHCI_LPM_SUPPORT;
-	/*
-	 * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
-	 * is called by usb_add_hcd().
-	 */
-	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
 
 	if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
 		xhci->shared_hcd->can_do_streams = 1;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index ec8ac16..2901a67 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -4849,9 +4849,9 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
 		 */
 		hcd->has_tt = 1;
 	} else {
-		/* xHCI private pointer was set in xhci_pci_probe for the second
-		 * registered roothub.
-		 */
+		xhci = hcd_to_xhci(hcd->primary_hcd);
+		*((struct xhci_hcd **) hcd->hcd_priv) = xhci;
+
 		return 0;
 	}
 
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 2/9] mailbox: Make struct mbox_controller's ops field const

[Andrew Bresticker]

The mailbox controller's channel ops ought to be read-only.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Jassi Brar <jassisinghbrar@gmail.com>
---
No changes from v5/v6.
New for v5.
---
 include/linux/mailbox_controller.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h
index d4cf96f..68c4245 100644
--- a/include/linux/mailbox_controller.h
+++ b/include/linux/mailbox_controller.h
@@ -72,7 +72,7 @@ struct mbox_chan_ops {
  */
 struct mbox_controller {
 	struct device *dev;
-	struct mbox_chan_ops *ops;
+	const struct mbox_chan_ops *ops;
 	struct mbox_chan *chans;
 	int num_chans;
 	bool txdone_irq;
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 3/9] mailbox: Fix up error handling in mbox_request_channel()

[Andrew Bresticker]

From: Benson Leung <bleung@chromium.org>

mbox_request_channel() currently returns EBUSY in the event the controller
is not present or if of_xlate() fails, but in neither case is EBUSY really
appropriate.  Return EPROBE_DEFER if the controller is not yet present
and change of_xlate() to return an ERR_PTR instead of NULL so that the
error can be propagated back to the caller of mbox_request_channel().

Signed-off-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Suman Anna <s-anna@ti.com>
---
Changes from v6:
 - Update omap-mailbox's xlate() to return error codes.
No changes from v5.
New for v5.
---
 drivers/mailbox/mailbox.c      | 11 ++++++++---
 drivers/mailbox/omap-mailbox.c |  6 +++---
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
index 19b491d..c3c42d4 100644
--- a/drivers/mailbox/mailbox.c
+++ b/drivers/mailbox/mailbox.c
@@ -318,7 +318,7 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index)
 		return ERR_PTR(-ENODEV);
 	}
 
-	chan = NULL;
+	chan = ERR_PTR(-EPROBE_DEFER);
 	list_for_each_entry(mbox, &mbox_cons, node)
 		if (mbox->dev->of_node == spec.np) {
 			chan = mbox->of_xlate(mbox, &spec);
@@ -327,7 +327,12 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index)
 
 	of_node_put(spec.np);
 
-	if (!chan || chan->cl || !try_module_get(mbox->dev->driver->owner)) {
+	if (IS_ERR(chan)) {
+		mutex_unlock(&con_mutex);
+		return chan;
+	}
+
+	if (chan->cl || !try_module_get(mbox->dev->driver->owner)) {
 		dev_dbg(dev, "%s: mailbox not free\n", __func__);
 		mutex_unlock(&con_mutex);
 		return ERR_PTR(-EBUSY);
@@ -390,7 +395,7 @@ of_mbox_index_xlate(struct mbox_controller *mbox,
 	int ind = sp->args[0];
 
 	if (ind >= mbox->num_chans)
-		return NULL;
+		return ERR_PTR(-EINVAL);
 
 	return &mbox->chans[ind];
 }
diff --git a/drivers/mailbox/omap-mailbox.c b/drivers/mailbox/omap-mailbox.c
index 0f332c1..e0df27b 100644
--- a/drivers/mailbox/omap-mailbox.c
+++ b/drivers/mailbox/omap-mailbox.c
@@ -639,18 +639,18 @@ static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
 
 	mdev = container_of(controller, struct omap_mbox_device, controller);
 	if (WARN_ON(!mdev))
-		return NULL;
+		return ERR_PTR(-EINVAL);
 
 	node = of_find_node_by_phandle(phandle);
 	if (!node) {
 		pr_err("%s: could not find node phandle 0x%x\n",
 		       __func__, phandle);
-		return NULL;
+		return ERR_PTR(-ENODEV);
 	}
 
 	mbox = omap_mbox_device_find(mdev, node->name);
 	of_node_put(node);
-	return mbox ? mbox->chan : NULL;
+	return mbox ? mbox->chan : ERR_PTR(-ENOENT);
 }
 
 static int omap_mbox_probe(struct platform_device *pdev)
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB

[Andrew Bresticker]

Add a binding document for the XUSB host complex on NVIDIA Tegra124
and later SoCs.  The XUSB host complex includes a mailbox for
communication with the XUSB micro-controller and an xHCI host-controller.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Lee Jones <lee.jones@linaro.org>
---
New for v7.
---
 .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt

diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
new file mode 100644
index 0000000..6a46680
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
@@ -0,0 +1,46 @@
+NVIDIA Tegra XUSB host copmlex
+==============================
+
+The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
+controller and a mailbox for communication with the XUSB micro-controller.
+
+Required properties:
+--------------------
+ - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
+   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
+   where <chip> is tegra132.
+ - reg: Must contain register base and length for each register set listed
+   in reg-names.
+ - reg-names: Must include the following entries:
+   - xhci
+   - fpci
+   - ipfs
+ - interrupts: Must contain an interrupt for each entry in interrupt-names.
+ - interrupt-names: Must include the following entries:
+   - host
+   - smi
+   - pme
+
+Example:
+--------
+	usb@0,70090000 {
+		compatible = "nvidia,tegra124-xusb";
+		reg = <0x0 0x70090000 0x0 0x8000>,
+		      <0x0 0x70098000 0x0 0x1000>,
+		      <0x0 0x70099000 0x0 0x1000>;
+		reg-names = "xhci", "fpci", "ipfs";
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HGIH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host", "smi", "pme";
+
+		usb-host {
+			compatible = "nvidia,tegra124-xhci";
+			...
+		};
+
+		mailbox {
+			compatible = "nvidia,tegra124-xusb-mbox";
+			...
+		};
+	};
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 5/9] mfd: Add driver for NVIDIA Tegra XUSB

[Andrew Bresticker]

Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
and later SoCs.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Lee Jones <lee.jones@linaro.org>
---
New for v7.
---
 drivers/mfd/Kconfig      |   7 ++
 drivers/mfd/Makefile     |   1 +
 drivers/mfd/tegra-xusb.c | 167 +++++++++++++++++++++++++++++++++++++++++++++++
 include/soc/tegra/xusb.h |  19 ++++++
 4 files changed, 194 insertions(+)
 create mode 100644 drivers/mfd/tegra-xusb.c
 create mode 100644 include/soc/tegra/xusb.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index d5ad04d..61872b4 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1430,6 +1430,13 @@ config MFD_STW481X
 	  in various ST Microelectronics and ST-Ericsson embedded
 	  Nomadik series.
 
+config MFD_TEGRA_XUSB
+	tristate "NVIDIA Tegra XUSB"
+	depends on ARCH_TEGRA
+	select MFD_CORE
+	help
+	  Support for the XUSB complex found on NVIDIA Tegra124 and later SoCs.
+
 menu "Multimedia Capabilities Port drivers"
 	depends on ARCH_SA1100
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 0e5cfeb..7588caf 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -181,6 +181,7 @@ obj-$(CONFIG_MFD_HI6421_PMIC)	+= hi6421-pmic-core.o
 obj-$(CONFIG_MFD_DLN2)		+= dln2.o
 obj-$(CONFIG_MFD_RT5033)	+= rt5033.o
 obj-$(CONFIG_MFD_SKY81452)	+= sky81452.o
+obj-$(CONFIG_MFD_TEGRA_XUSB)	+= tegra-xusb.o
 
 intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
 obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
diff --git a/drivers/mfd/tegra-xusb.c b/drivers/mfd/tegra-xusb.c
new file mode 100644
index 0000000..d30d259
--- /dev/null
+++ b/drivers/mfd/tegra-xusb.c
@@ -0,0 +1,167 @@
+/*
+ * NVIDIA Tegra XUSB MFD driver
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mfd/core.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <soc/tegra/xusb.h>
+
+struct tegra_xusb_soc_data {
+	struct mfd_cell *devs;
+	unsigned int num_devs;
+};
+
+static struct resource tegra_xhci_resources[] = {
+	{
+		.name = "host",
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.name = "xhci",
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.name = "ipfs",
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource tegra_xusb_mbox_resources[] = {
+	{
+		.name = "smi",
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct mfd_cell tegra124_xusb_devs[] = {
+	{
+		.name = "tegra-xhci",
+		.of_compatible = "nvidia,tegra124-xhci",
+	},
+	{
+		.name = "tegra-xusb-mbox",
+		.of_compatible = "nvidia,tegra124-xusb-mbox",
+	},
+};
+
+static const struct tegra_xusb_soc_data tegra124_xusb_data = {
+	.devs = tegra124_xusb_devs,
+	.num_devs = ARRAY_SIZE(tegra124_xusb_devs),
+};
+
+static const struct of_device_id tegra_xusb_of_match[] = {
+	{ .compatible = "nvidia,tegra124-xusb", .data = &tegra124_xusb_data },
+	{},
+};
+MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
+
+static struct regmap_config tegra_fpci_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int tegra_xusb_probe(struct platform_device *pdev)
+{
+	const struct tegra_xusb_soc_data *soc;
+	const struct of_device_id *match;
+	struct tegra_xusb *xusb;
+	struct resource *res;
+	void __iomem *fpci_base;
+	int irq, ret;
+
+	xusb = devm_kzalloc(&pdev->dev, sizeof(*xusb), GFP_KERNEL);
+	if (!xusb)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, xusb);
+
+	match = of_match_node(tegra_xusb_of_match, pdev->dev.of_node);
+	soc = match->data;
+
+	irq = platform_get_irq_byname(pdev, "host");
+	if (irq < 0)
+		return irq;
+	tegra_xhci_resources[0].start = irq;
+	tegra_xhci_resources[0].end = irq;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci");
+	if (!res)
+		return -ENODEV;
+	tegra_xhci_resources[1].start = res->start;
+	tegra_xhci_resources[1].end = res->end;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipfs");
+	if (!res)
+		return -ENODEV;
+	tegra_xhci_resources[2].start = res->start;
+	tegra_xhci_resources[2].end = res->end;
+
+	soc->devs[0].resources = tegra_xhci_resources;
+	soc->devs[0].num_resources = ARRAY_SIZE(tegra_xhci_resources);
+
+	irq = platform_get_irq_byname(pdev, "smi");
+	if (irq < 0)
+		return irq;
+	tegra_xusb_mbox_resources[0].start = irq;
+	tegra_xusb_mbox_resources[0].end = irq;
+
+	soc->devs[1].resources = tegra_xusb_mbox_resources;
+	soc->devs[1].num_resources = ARRAY_SIZE(tegra_xusb_mbox_resources);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fpci");
+	fpci_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(fpci_base))
+		return PTR_ERR(fpci_base);
+
+	tegra_fpci_regmap_config.max_register = res->end - res->start - 3;
+	xusb->fpci_regs = devm_regmap_init_mmio(&pdev->dev, fpci_base,
+						&tegra_fpci_regmap_config);
+	if (IS_ERR(xusb->fpci_regs)) {
+		ret = PTR_ERR(xusb->fpci_regs);
+		dev_err(&pdev->dev, "Failed to init regmap: %d\n", ret);
+		return ret;
+	}
+
+	ret = mfd_add_devices(&pdev->dev, -1, soc->devs, soc->num_devs,
+			      NULL, 0, NULL);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to add MFD devices: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int tegra_xusb_remove(struct platform_device *pdev)
+{
+	mfd_remove_devices(&pdev->dev);
+
+	return 0;
+}
+
+static struct platform_driver tegra_xusb_driver = {
+	.probe = tegra_xusb_probe,
+	.remove = tegra_xusb_remove,
+	.driver = {
+		.name = "tegra-xusb",
+		.of_match_table = tegra_xusb_of_match,
+	},
+};
+module_platform_driver(tegra_xusb_driver);
+
+MODULE_DESCRIPTION("NVIDIA Tegra XUSB MFD");
+MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/soc/tegra/xusb.h b/include/soc/tegra/xusb.h
new file mode 100644
index 0000000..9d28d90
--- /dev/null
+++ b/include/soc/tegra/xusb.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_TEGRA_XUSB_H__
+#define __SOC_TEGRA_XUSB_H__
+
+struct regmap;
+
+struct tegra_xusb {
+	struct regmap *fpci_regs;
+};
+
+#endif /* __SOC_TEGRA_XUSB_H__ */
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 6/9] mailbox: Add NVIDIA Tegra XUSB mailbox binding

[Andrew Bresticker]

Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra xHCI controller's firmware and the
host processor.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Jassi Brar <jassisinghbrar@gmail.com>
---
Changes from v6:
 - Removed reg/interrupts properties.
No changes from v3/v4/v5.
Changes from v2:
 - Dropped channel specifier.
 - Added pointer to mailbox documentation.
Changes from v1:
 - Updated to use common mailbox bindings.
---
 .../bindings/mailbox/nvidia,tegra124-xusb-mbox.txt | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt

diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt
new file mode 100644
index 0000000..9d89afa
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt
@@ -0,0 +1,30 @@
+NVIDIA Tegra XUSB mailbox
+=========================
+
+The Tegra XUSB mailbox is used by the Tegra xHCI controller's firmware to
+communicate requests to the host and PHY drivers.
+
+Refer to ./mailbox.txt for generic information about mailbox device-tree
+bindings.
+
+Required properties:
+--------------------
+ - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-mbox".
+   Otherwise, must contain '"nvidia,<chip>-xusb-mbox",
+   "nvidia,tegra124-xusb-mbox"' where <chip> is tegra132.
+ - #mbox-cells: Should be 0.  There is only one physical channel.
+
+Example:
+--------
+	mailbox {
+		compatible = "nvidia,tegra124-xusb-mbox";
+
+		#mbox-cells = <0>;
+	};
+
+	usb-host {
+		...
+		mboxes = <&xusb_mbox>;
+		mbox-names = "xusb";
+		...
+	};
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 7/9] mailbox: Add NVIDIA Tegra XUSB mailbox driver

[Andrew Bresticker]

The Tegra xHCI controller's firmware communicates requests to the host
processor through a mailbox interface.  While there is only a single
physical channel, messages sent by the controller can be divided
into two groups: those intended for the PHY driver and those intended
for the host-controller driver.  The requesting driver is assigned
one of two virtual channels when the single physical channel is
requested.  All incoming messages are sent to both virtual channels.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Jassi Brar <jassisinghbrar@gmail.com>
---
Changes from v6:
 - Access FPCI registers using parent MFD's regmap.
Changes from v5:
 - Poll for TX completion using MBOX_OWNER field.
Changes from v4:
 - Use chan->cl to indicate channel allocation status
 - Addressed review comments from Thierry
No changes from v3.
Changes from v2:
 - Fixed mailbox IRQ vs. channel alloc/free race.
 - Renamed defines to match TRM.
 - Dropped channel specifier and instead allocated virtual channels as they
   were requested.
 - Removed MODULE_ALIAS.
Changes from v1:
 - Converted to common mailbox framework.
 - Removed useless polling sequences in TX path.
 - Moved xusb include from linux/ to soc/tegra/
---
 drivers/mailbox/Kconfig              |   8 +
 drivers/mailbox/Makefile             |   2 +
 drivers/mailbox/tegra-xusb-mailbox.c | 275 +++++++++++++++++++++++++++++++++++
 include/soc/tegra/xusb.h             |  30 ++++
 4 files changed, 315 insertions(+)
 create mode 100644 drivers/mailbox/tegra-xusb-mailbox.c

diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 84b0a2d..37da641 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -60,4 +60,12 @@ config ALTERA_MBOX
 	  An implementation of the Altera Mailbox soft core. It is used
 	  to send message between processors. Say Y here if you want to use the
 	  Altera mailbox support.
+
+config TEGRA_XUSB_MBOX
+	tristate "NVIDIA Tegra XUSB Mailbox"
+	depends on MFD_TEGRA_XUSB
+	help
+	  Mailbox driver for the XUSB complex found on NVIDIA Tegra124 and
+	  later SoCs.  The XUSB mailbox is used to communicate between the
+	  XUSB microcontroller and the host processor.
 endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index b18201e..d77012a 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_OMAP2PLUS_MBOX)	+= omap-mailbox.o
 obj-$(CONFIG_PCC)		+= pcc.o
 
 obj-$(CONFIG_ALTERA_MBOX)	+= mailbox-altera.o
+
+obj-$(CONFIG_TEGRA_XUSB_MBOX)	+= tegra-xusb-mailbox.o
diff --git a/drivers/mailbox/tegra-xusb-mailbox.c b/drivers/mailbox/tegra-xusb-mailbox.c
new file mode 100644
index 0000000..f0cac4d
--- /dev/null
+++ b/drivers/mailbox/tegra-xusb-mailbox.c
@@ -0,0 +1,275 @@
+/*
+ * NVIDIA Tegra XUSB mailbox driver
+ *
+ * Copyright (C) 2014 NVIDIA Corporation
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <soc/tegra/xusb.h>
+
+#define XUSB_MBOX_NUM_CHANS			2 /* Host + PHY */
+
+#define XUSB_CFG_ARU_MBOX_CMD			0xe4
+#define  MBOX_DEST_FALC				BIT(27)
+#define  MBOX_DEST_PME				BIT(28)
+#define  MBOX_DEST_SMI				BIT(29)
+#define  MBOX_DEST_XHCI				BIT(30)
+#define  MBOX_INT_EN				BIT(31)
+#define XUSB_CFG_ARU_MBOX_DATA_IN		0xe8
+#define  CMD_DATA_SHIFT				0
+#define  CMD_DATA_MASK				0xffffff
+#define  CMD_TYPE_SHIFT				24
+#define  CMD_TYPE_MASK				0xff
+#define XUSB_CFG_ARU_MBOX_DATA_OUT		0xec
+#define XUSB_CFG_ARU_MBOX_OWNER			0xf0
+#define  MBOX_OWNER_NONE			0
+#define  MBOX_OWNER_FW				1
+#define  MBOX_OWNER_SW				2
+#define XUSB_CFG_ARU_SMI_INTR			0x428
+#define  MBOX_SMI_INTR_FW_HANG			BIT(1)
+#define  MBOX_SMI_INTR_EN			BIT(3)
+
+struct tegra_xusb_mbox {
+	struct mbox_controller mbox;
+	struct tegra_xusb *xusb;
+	spinlock_t lock;
+};
+
+static inline u32 mbox_readl(struct tegra_xusb_mbox *mbox, unsigned long offset)
+{
+	u32 val;
+
+	regmap_read(mbox->xusb->fpci_regs, offset, &val);
+
+	return val;
+}
+
+static inline void mbox_writel(struct tegra_xusb_mbox *mbox, u32 val,
+			       unsigned long offset)
+{
+	regmap_write(mbox->xusb->fpci_regs, offset, val);
+}
+
+static inline struct tegra_xusb_mbox *to_tegra_mbox(struct mbox_controller *c)
+{
+	return container_of(c, struct tegra_xusb_mbox, mbox);
+}
+
+static inline u32 mbox_pack_msg(struct tegra_xusb_mbox_msg *msg)
+{
+	u32 val;
+
+	val = (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT;
+	val |= (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
+
+	return val;
+}
+
+static inline void mbox_unpack_msg(u32 val, struct tegra_xusb_mbox_msg *msg)
+{
+	msg->cmd = (val >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
+	msg->data = (val >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
+}
+
+static int tegra_xusb_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+	struct tegra_xusb_mbox *mbox = to_tegra_mbox(chan->mbox);
+	struct tegra_xusb_mbox_msg *msg = data;
+	unsigned long flags;
+	u32 reg, owner;
+
+	dev_dbg(mbox->mbox.dev, "TX message %#x:%#x\n", msg->cmd, msg->data);
+
+	/* ACK/NAK must be sent with the controller as the mailbox owner */
+	if (msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)
+		owner = MBOX_OWNER_FW;
+	else
+		owner = MBOX_OWNER_SW;
+
+	spin_lock_irqsave(&mbox->lock, flags);
+
+	/* Acquire mailbox */
+	if (mbox_readl(mbox, XUSB_CFG_ARU_MBOX_OWNER) != MBOX_OWNER_NONE) {
+		dev_err(mbox->mbox.dev, "Mailbox not idle\n");
+		goto busy;
+	}
+	mbox_writel(mbox, owner, XUSB_CFG_ARU_MBOX_OWNER);
+	if (mbox_readl(mbox, XUSB_CFG_ARU_MBOX_OWNER) != owner) {
+		dev_err(mbox->mbox.dev, "Failed to acquire mailbox");
+		goto busy;
+	}
+
+	mbox_writel(mbox, mbox_pack_msg(msg), XUSB_CFG_ARU_MBOX_DATA_IN);
+	reg = mbox_readl(mbox, XUSB_CFG_ARU_MBOX_CMD);
+	reg |= MBOX_INT_EN | MBOX_DEST_FALC;
+	mbox_writel(mbox, reg, XUSB_CFG_ARU_MBOX_CMD);
+
+	spin_unlock_irqrestore(&mbox->lock, flags);
+
+	return 0;
+busy:
+	spin_unlock_irqrestore(&mbox->lock, flags);
+	return -EBUSY;
+}
+
+static int tegra_xusb_mbox_startup(struct mbox_chan *chan)
+{
+	return 0;
+}
+
+static void tegra_xusb_mbox_shutdown(struct mbox_chan *chan)
+{
+}
+
+static bool tegra_xusb_mbox_last_tx_done(struct mbox_chan *chan)
+{
+	struct tegra_xusb_mbox *mbox = to_tegra_mbox(chan->mbox);
+
+	return mbox_readl(mbox, XUSB_CFG_ARU_MBOX_OWNER) == MBOX_OWNER_NONE;
+}
+
+static const struct mbox_chan_ops tegra_xusb_mbox_chan_ops = {
+	.send_data = tegra_xusb_mbox_send_data,
+	.startup = tegra_xusb_mbox_startup,
+	.shutdown = tegra_xusb_mbox_shutdown,
+	.last_tx_done = tegra_xusb_mbox_last_tx_done,
+};
+
+static irqreturn_t tegra_xusb_mbox_irq(int irq, void *p)
+{
+	struct tegra_xusb_mbox *mbox = p;
+	struct tegra_xusb_mbox_msg msg;
+	unsigned int i;
+	u32 reg;
+
+	spin_lock(&mbox->lock);
+
+	/* Clear mbox interrupts */
+	reg = mbox_readl(mbox, XUSB_CFG_ARU_SMI_INTR);
+	if (reg & MBOX_SMI_INTR_FW_HANG)
+		dev_err(mbox->mbox.dev, "Controller firmware hang\n");
+	mbox_writel(mbox, reg, XUSB_CFG_ARU_SMI_INTR);
+
+	reg = mbox_readl(mbox, XUSB_CFG_ARU_MBOX_DATA_OUT);
+	mbox_unpack_msg(reg, &msg);
+
+	/*
+	 * Set the mailbox back to idle.  The recipient of the message is
+	 * responsible for sending an ACK/NAK, if necessary.
+	 */
+	reg = mbox_readl(mbox, XUSB_CFG_ARU_MBOX_CMD);
+	reg &= ~MBOX_DEST_SMI;
+	mbox_writel(mbox, reg, XUSB_CFG_ARU_MBOX_CMD);
+	mbox_writel(mbox, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
+
+	dev_dbg(mbox->mbox.dev, "RX message %#x:%#x\n", msg.cmd, msg.data);
+	for (i = 0; i < XUSB_MBOX_NUM_CHANS; i++) {
+		if (mbox->mbox.chans[i].cl)
+			mbox_chan_received_data(&mbox->mbox.chans[i], &msg);
+	}
+
+	spin_unlock(&mbox->lock);
+
+	return IRQ_HANDLED;
+}
+
+static struct mbox_chan *tegra_xusb_mbox_of_xlate(struct mbox_controller *ctlr,
+					const struct of_phandle_args *sp)
+{
+	struct tegra_xusb_mbox *mbox = to_tegra_mbox(ctlr);
+	struct mbox_chan *chan = ERR_PTR(-EINVAL);
+	unsigned long flags;
+	unsigned int i;
+
+	/* Pick the first available (virtual) channel. */
+	spin_lock_irqsave(&mbox->lock, flags);
+	for (i = 0; XUSB_MBOX_NUM_CHANS; i++) {
+		if (!ctlr->chans[i].cl) {
+			chan = &ctlr->chans[i];
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&mbox->lock, flags);
+
+	return chan;
+}
+
+static const struct of_device_id tegra_xusb_mbox_of_match[] = {
+	{ .compatible = "nvidia,tegra124-xusb-mbox" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, tegra_xusb_mbox_of_match);
+
+static int tegra_xusb_mbox_probe(struct platform_device *pdev)
+{
+	struct tegra_xusb_mbox *mbox;
+	int irq, ret;
+
+	mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
+	if (!mbox)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, mbox);
+	spin_lock_init(&mbox->lock);
+	mbox->xusb = dev_get_drvdata(pdev->dev.parent);
+
+	mbox->mbox.dev = &pdev->dev;
+	mbox->mbox.chans = devm_kcalloc(&pdev->dev, XUSB_MBOX_NUM_CHANS,
+					sizeof(*mbox->mbox.chans), GFP_KERNEL);
+	if (!mbox->mbox.chans)
+		return -ENOMEM;
+	mbox->mbox.num_chans = XUSB_MBOX_NUM_CHANS;
+	mbox->mbox.ops = &tegra_xusb_mbox_chan_ops;
+	mbox->mbox.txdone_poll = true;
+	mbox->mbox.txpoll_period = 1;
+	mbox->mbox.of_xlate = tegra_xusb_mbox_of_xlate;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+	ret = devm_request_irq(&pdev->dev, irq, tegra_xusb_mbox_irq, 0,
+			       dev_name(&pdev->dev), mbox);
+	if (ret < 0)
+		return ret;
+
+	ret = mbox_controller_register(&mbox->mbox);
+	if (ret < 0)
+		dev_err(&pdev->dev, "failed to register mailbox: %d\n", ret);
+
+	return ret;
+}
+
+static int tegra_xusb_mbox_remove(struct platform_device *pdev)
+{
+	struct tegra_xusb_mbox *mbox = platform_get_drvdata(pdev);
+
+	mbox_controller_unregister(&mbox->mbox);
+
+	return 0;
+}
+
+static struct platform_driver tegra_xusb_mbox_driver = {
+	.probe = tegra_xusb_mbox_probe,
+	.remove = tegra_xusb_mbox_remove,
+	.driver = {
+		.name = "tegra-xusb-mbox",
+		.of_match_table = tegra_xusb_mbox_of_match,
+	},
+};
+module_platform_driver(tegra_xusb_mbox_driver);
+
+MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
+MODULE_DESCRIPTION("NVIDIA Tegra XUSB mailbox driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/soc/tegra/xusb.h b/include/soc/tegra/xusb.h
index 9d28d90..d815bc1 100644
--- a/include/soc/tegra/xusb.h
+++ b/include/soc/tegra/xusb.h
@@ -16,4 +16,34 @@ struct tegra_xusb {
 	struct regmap *fpci_regs;
 };
 
+/* Command requests from the firmware */
+enum tegra_xusb_mbox_cmd {
+	MBOX_CMD_MSG_ENABLED = 1,
+	MBOX_CMD_INC_FALC_CLOCK,
+	MBOX_CMD_DEC_FALC_CLOCK,
+	MBOX_CMD_INC_SSPI_CLOCK,
+	MBOX_CMD_DEC_SSPI_CLOCK,
+	MBOX_CMD_SET_BW, /* no ACK/NAK required */
+	MBOX_CMD_SET_SS_PWR_GATING,
+	MBOX_CMD_SET_SS_PWR_UNGATING,
+	MBOX_CMD_SAVE_DFE_CTLE_CTX,
+	MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
+	MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
+	MBOX_CMD_START_HSIC_IDLE,
+	MBOX_CMD_STOP_HSIC_IDLE,
+	MBOX_CMD_DBC_WAKE_STACK, /* unused */
+	MBOX_CMD_HSIC_PRETEND_CONNECT,
+
+	MBOX_CMD_MAX,
+
+	/* Response message to above commands */
+	MBOX_CMD_ACK = 128,
+	MBOX_CMD_NAK
+};
+
+struct tegra_xusb_mbox_msg {
+	u32 cmd;
+	u32 data;
+};
+
 #endif /* __SOC_TEGRA_XUSB_H__ */
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 8/9] usb: Add NVIDIA Tegra xHCI controller binding

[Andrew Bresticker]

Add device-tree binding documentation for the xHCI controller present
on Tegra124 and later SoCs.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Mathias Nyman <mathias.nyman@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
Changes from v6:
 - Removed XUSB_DEV related clocks/resets.  They will be consumed by
   a separate driver and binding.
 - Removed reg/interrupts properties.
No changes from v5.
Changes from v4:
 - Updated regulator names, as suggested by Thierry.
No changes from v3.
Changes from v2:
 - Added mbox-names property.
Changes from v1:
 - Updated to use common mailbox bindings.
 - Added remaining XUSB-related clocks and resets.
 - Updated list of power supplies to be more accurate wrt to the hardware.
---
 .../bindings/usb/nvidia,tegra124-xhci.txt          | 90 ++++++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt

diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
new file mode 100644
index 0000000..5c980b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
@@ -0,0 +1,90 @@
+NVIDIA Tegra xHCI controller
+============================
+
+The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed
+by the Tegra XUSB pad controller.
+
+Required properties:
+--------------------
+ - compatible: For Tegra124, must contain "nvidia,tegra124-xhci".
+   Otherwise, must contain '"nvidia,<chip>-xhci", "nvidia,tegra124-xhci"'
+   where <chip> is tegra132.
+ - clocks: Must contain an entry for each entry in clock-names.
+   See ../clock/clock-bindings.txt for details.
+ - clock-names: Must include the following entries:
+    - xusb_host
+    - xusb_host_src
+    - xusb_falcon_src
+    - xusb_ss
+    - xusb_ss_src
+    - xusb_ss_div2
+    - xusb_hs_src
+    - xusb_fs_src
+    - pll_u_480m
+    - clk_m
+    - pll_e
+ - resets: Must contain an entry for each entry in reset-names.
+   See ../reset/reset.txt for details.
+ - reset-names: Must include the following entries:
+   - xusb_host
+   - xusb_ss
+   - xusb_src
+   Note that xusb_src is the shared reset for xusb_{ss,hs,fs,falcon,host}_src.
+ - mboxes: Must contain an entry for the XUSB mailbox channel.
+   See ../mailbox/mailbox.txt for details.
+ - mbox-names: Must include the following entries:
+   - xusb
+ - avddio-pex-supply: PCIe/USB3 analog logic power supply.  Must supply 1.05V.
+ - dvddio-pex-supply: PCIe/USB3 digital logic power supply.  Must supply 1.05V.
+ - avdd-usb-supply: USB controller power supply.  Must supply 3.3V.
+ - avdd-pll-utmip-supply: UTMI PLL power supply.  Must supply 1.8V.
+ - avdd-pll-erefe-supply: PLLE reference PLL power supply.  Must supply 1.05V.
+ - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply.  Must supply 1.05V.
+ - hvdd-usb-ss-supply: High-voltage PCIe/USB3 power supply.  Must supply 3.3V.
+ - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply.  Must supply 3.3V.
+
+Optional properties:
+--------------------
+ - phys: Must contain an entry for each entry in phy-names.
+   See ../phy/phy-bindings.txt for details.
+ - phy-names: Should include an entry for each PHY used by the controller.
+   Names must be of the form "<type>-<number>" where <type> is one of "utmi",
+   "hsic", or "usb3" and <number> is a 0-based index.  On Tegra124, there may
+   be up to 3 UTMI, 2 HSIC, and 2 USB3 PHYs.
+
+Example:
+--------
+	usb-host {
+		compatible = "nvidia,tegra124-xhci";
+		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
+			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
+			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
+			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
+			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
+			 <&tegra_car TEGRA124_CLK_CLK_M>,
+			 <&tegra_car TEGRA124_CLK_PLL_E>;
+		clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src",
+			      "xusb_ss", "xusb_ss_div2", "xusb_ss_src",
+			      "xusb_hs_src", "xusb_fs_src", "pll_u_480m",
+			      "clk_m", "pll_e";
+		resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>;
+		reset-names = "xusb_host", "xusb_ss", "xusb_src";
+		mboxes = <&xusb_mbox>;
+		mbox-names = "xusb";
+		phys = <&padctl TEGRA_XUSB_PADCTL_UTMI_P1>, /* mini-PCIe USB */
+		       <&padctl TEGRA_XUSB_PADCTL_UTMI_P2>, /* USB A */
+		       <&padctl TEGRA_XUSB_PADCTL_USB3_P0>; /* USB A */
+		phy-names = "utmi-1", "utmi-2", "usb3-0";
+		avddio-pex-supply = <&vdd_1v05_run>;
+		dvddio-pex-supply = <&vdd_1v05_run>;
+		avdd-usb-supply = <&vdd_3v3_lp0>;
+		avdd-pll-utmip-supply = <&vddio_1v8>;
+		avdd-pll-erefe-supply = <&avdd_1v05_run>;
+		avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
+		hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
+		hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
+	};
-- 
2.2.0.rc0.207.ga3a616c

[PATCH V7 9/9] usb: xhci: Add NVIDIA Tegra xHCI host-controller driver

[Andrew Bresticker]

Add support for the on-chip xHCI host controller present on Tegra SoCs.
The controller requires external firmware which must be loaded before
using the controller.  This driver loads the firmware, starts the
controller, and is able to service host-specific messages sent by
the controller's firmware.

The controller also supports USB device mode as well as powergating
of the SuperSpeed and host-controller logic when not in use, but
support for these is not yet implemented.

Based on work by:
  Ajay Gupta <ajayg@nvidia.com>
  Bharath Yadav <byadav@nvidia.com>

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mathias Nyman <mathias.nyman@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
Changes from v6:
 - Access FPCI registers using parent MFD's regmap.
 - Made regulator names and PHY types part of the SoC-specific data
   since they will be different on Tegra210.
 - Other cosmetic cleanups.
Changes from v5:
 - Added dependency on COMPILE_TEST and MAILBOX.
 - Added TODO about powergating support.
Changes from v4:
 - Poll for controller to finish booting.
 - Addressed review comments from Thierry.
Changes from v3:
 - Used 32-bit DMA mask (platforms may have > 32-bit physical address space
   and < 64-bit dma_addr_t).
 - Moved comment about SET_BW command.
Changes from v2:
 - Added filtering out of non-host mailbox messages.
 - Removed MODULE_ALIAS.
Changes from v1:
 - Updated to use common mailbox API.
 - Fixed up so that the driver can be built and used as a module.
 - Incorporated review feedback from Stephen.
 - Misc. cleanups.
---
 drivers/usb/host/Kconfig      |  10 +
 drivers/usb/host/Makefile     |   1 +
 drivers/usb/host/xhci-tegra.c | 946 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 957 insertions(+)
 create mode 100644 drivers/usb/host/xhci-tegra.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 197a6a3..22601d0 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -50,6 +50,16 @@ config USB_XHCI_RCAR
 	  Say 'Y' to enable the support for the xHCI host controller
 	  found in Renesas R-Car ARM SoCs.
 
+config USB_XHCI_TEGRA
+	tristate "xHCI support for NVIDIA Tegra SoCs"
+	depends on MFD_TEGRA_XUSB || COMPILE_TEST
+	depends on MAILBOX
+	depends on RESET_CONTROLLER
+	select FW_LOADER
+	---help---
+	  Say 'Y' to enable the support for the xHCI host controller
+	  found in NVIDIA Tegra124 and later SoCs.
+
 endif # USB_XHCI_HCD
 
 config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 65b0b6a..1b98107 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCI)		+= pci-quirks.o
 
 obj-$(CONFIG_USB_XHCI_PCI)	+= xhci-pci.o
 obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
+obj-$(CONFIG_USB_XHCI_TEGRA)	+= xhci-tegra.o
 
 obj-$(CONFIG_USB_EHCI_HCD)	+= ehci-hcd.o
 obj-$(CONFIG_USB_EHCI_PCI)	+= ehci-pci.o
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
new file mode 100644
index 0000000..6230a2d
--- /dev/null
+++ b/drivers/usb/host/xhci-tegra.c
@@ -0,0 +1,946 @@
+/*
+ * NVIDIA Tegra xHCI host controller driver
+ *
+ * Copyright (C) 2014 NVIDIA Corporation
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_client.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+
+#include <soc/tegra/xusb.h>
+
+#include "xhci.h"
+
+#define TEGRA_XHCI_SS_CLK_HIGH_SPEED 120000000
+#define TEGRA_XHCI_SS_CLK_LOW_SPEED 12000000
+
+/* FPCI CFG registers */
+#define XUSB_CFG_1				0x004
+#define  XUSB_IO_SPACE_EN			BIT(0)
+#define  XUSB_MEM_SPACE_EN			BIT(1)
+#define  XUSB_BUS_MASTER_EN			BIT(2)
+#define XUSB_CFG_4				0x010
+#define  XUSB_BASE_ADDR_SHIFT			15
+#define  XUSB_BASE_ADDR_MASK			0x1ffff
+#define XUSB_CFG_ARU_C11_CSBRANGE		0x41c
+#define XUSB_CFG_CSB_BASE_ADDR			0x800
+
+/* IPFS registers */
+#define IPFS_XUSB_HOST_CONFIGURATION_0		0x180
+#define  IPFS_EN_FPCI				BIT(0)
+#define IPFS_XUSB_HOST_INTR_MASK_0		0x188
+#define  IPFS_IP_INT_MASK			BIT(16)
+#define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0	0x1bc
+
+#define CSB_PAGE_SELECT_MASK			0x7fffff
+#define CSB_PAGE_SELECT_SHIFT			9
+#define CSB_PAGE_OFFSET_MASK			0x1ff
+#define CSB_PAGE_SELECT(addr)	((addr) >> (CSB_PAGE_SELECT_SHIFT) &	\
+				 CSB_PAGE_SELECT_MASK)
+#define CSB_PAGE_OFFSET(addr)	((addr) & CSB_PAGE_OFFSET_MASK)
+
+/* Falcon CSB registers */
+#define XUSB_FALC_CPUCTL			0x100
+#define  CPUCTL_STARTCPU			BIT(1)
+#define  CPUCTL_STATE_HALTED			BIT(4)
+#define  CPUCTL_STATE_STOPPED			BIT(5)
+#define XUSB_FALC_BOOTVEC			0x104
+#define XUSB_FALC_DMACTL			0x10c
+#define XUSB_FALC_IMFILLRNG1			0x154
+#define  IMFILLRNG1_TAG_MASK			0xffff
+#define  IMFILLRNG1_TAG_LO_SHIFT		0
+#define  IMFILLRNG1_TAG_HI_SHIFT		16
+#define XUSB_FALC_IMFILLCTL			0x158
+
+/* MP CSB registers */
+#define XUSB_CSB_MP_ILOAD_ATTR			0x101a00
+#define XUSB_CSB_MP_ILOAD_BASE_LO		0x101a04
+#define XUSB_CSB_MP_ILOAD_BASE_HI		0x101a08
+#define XUSB_CSB_MP_L2IMEMOP_SIZE		0x101a10
+#define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT		8
+#define  L2IMEMOP_SIZE_SRC_OFFSET_MASK		0x3ff
+#define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT		24
+#define  L2IMEMOP_SIZE_SRC_COUNT_MASK		0xff
+#define XUSB_CSB_MP_L2IMEMOP_TRIG		0x101a14
+#define  L2IMEMOP_ACTION_SHIFT			24
+#define  L2IMEMOP_INVALIDATE_ALL		(0x40 << L2IMEMOP_ACTION_SHIFT)
+#define  L2IMEMOP_LOAD_LOCKED_RESULT		(0x11 << L2IMEMOP_ACTION_SHIFT)
+#define XUSB_CSB_MP_APMAP			0x10181c
+#define  APMAP_BOOTPATH				BIT(31)
+
+#define IMEM_BLOCK_SIZE				256
+
+struct tegra_xhci_fw_cfgtbl {
+	u32 boot_loadaddr_in_imem;
+	u32 boot_codedfi_offset;
+	u32 boot_codetag;
+	u32 boot_codesize;
+	u32 phys_memaddr;
+	u16 reqphys_memsize;
+	u16 alloc_phys_memsize;
+	u32 rodata_img_offset;
+	u32 rodata_section_start;
+	u32 rodata_section_end;
+	u32 main_fnaddr;
+	u32 fwimg_cksum;
+	u32 fwimg_created_time;
+	u32 imem_resident_start;
+	u32 imem_resident_end;
+	u32 idirect_start;
+	u32 idirect_end;
+	u32 l2_imem_start;
+	u32 l2_imem_end;
+	u32 version_id;
+	u8 init_ddirect;
+	u8 reserved[3];
+	u32 phys_addr_log_buffer;
+	u32 total_log_entries;
+	u32 dequeue_ptr;
+	u32 dummy_var[2];
+	u32 fwimg_len;
+	u8 magic[8];
+	u32 ss_low_power_entry_timeout;
+	u8 num_hsic_port;
+	u8 padding[139]; /* Pad to 256 bytes */
+};
+
+struct tegra_xhci_phy_type {
+	const char *name;
+	unsigned int num;
+};
+
+struct tegra_xhci_soc_data {
+	const char *firmware_file;
+	const char * const *supply_names;
+	unsigned int num_supplies;
+	const struct tegra_xhci_phy_type *phy_types;
+	unsigned int num_types;
+};
+
+struct tegra_xhci_hcd {
+	struct device *dev;
+	struct usb_hcd *hcd;
+	struct tegra_xusb *xusb;
+
+	int irq;
+
+	void __iomem *ipfs_base;
+
+	const struct tegra_xhci_soc_data *soc;
+
+	struct regulator_bulk_data *supplies;
+
+	struct clk *host_clk;
+	struct clk *falc_clk;
+	struct clk *ss_clk;
+	struct clk *ss_src_clk;
+	struct clk *hs_src_clk;
+	struct clk *fs_src_clk;
+	struct clk *pll_u_480m;
+	struct clk *clk_m;
+	struct clk *pll_e;
+
+	struct reset_control *host_rst;
+	struct reset_control *ss_rst;
+
+	struct phy **phys;
+	unsigned int num_phys;
+
+	struct work_struct mbox_req_work;
+	struct tegra_xusb_mbox_msg mbox_req;
+	struct mbox_client mbox_client;
+	struct mbox_chan *mbox_chan;
+
+	/* Firmware loading related */
+	void *fw_data;
+	size_t fw_size;
+	dma_addr_t fw_dma_addr;
+	bool fw_loaded;
+};
+
+static struct hc_driver __read_mostly tegra_xhci_hc_driver;
+
+static inline struct tegra_xhci_hcd *
+mbox_work_to_tegra(struct work_struct *work)
+{
+	return container_of(work, struct tegra_xhci_hcd, mbox_req_work);
+}
+
+static inline u32 fpci_readl(struct tegra_xhci_hcd *tegra, u32 addr)
+{
+	u32 val;
+
+	regmap_read(tegra->xusb->fpci_regs, addr, &val);
+
+	return val;
+}
+
+static inline void fpci_writel(struct tegra_xhci_hcd *tegra, u32 val, u32 addr)
+{
+	regmap_write(tegra->xusb->fpci_regs, addr, val);
+}
+
+static inline u32 ipfs_readl(struct tegra_xhci_hcd *tegra, u32 addr)
+{
+	return readl(tegra->ipfs_base + addr);
+}
+
+static inline void ipfs_writel(struct tegra_xhci_hcd *tegra, u32 val, u32 addr)
+{
+	writel(val, tegra->ipfs_base + addr);
+}
+
+static u32 csb_readl(struct tegra_xhci_hcd *tegra, u32 addr)
+{
+	u32 page, offset;
+
+	page = CSB_PAGE_SELECT(addr);
+	offset = CSB_PAGE_OFFSET(addr);
+	fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
+	return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + offset);
+}
+
+static void csb_writel(struct tegra_xhci_hcd *tegra, u32 val, u32 addr)
+{
+	u32 page, offset;
+
+	page = CSB_PAGE_SELECT(addr);
+	offset = CSB_PAGE_OFFSET(addr);
+	fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
+	fpci_writel(tegra, val, XUSB_CFG_CSB_BASE_ADDR + offset);
+}
+
+static void tegra_xhci_ipfs_config(struct tegra_xhci_hcd *tegra)
+{
+	u32 reg;
+
+	reg = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
+	reg |= IPFS_EN_FPCI;
+	ipfs_writel(tegra, reg, IPFS_XUSB_HOST_CONFIGURATION_0);
+	udelay(10);
+
+	/* Program BAR0 space */
+	reg = fpci_readl(tegra, XUSB_CFG_4);
+	reg &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
+	reg |= tegra->hcd->rsrc_start & (XUSB_BASE_ADDR_MASK <<
+					 XUSB_BASE_ADDR_SHIFT);
+	fpci_writel(tegra, reg, XUSB_CFG_4);
+	usleep_range(100, 200);
+
+	/* Enable bus master */
+	reg = fpci_readl(tegra, XUSB_CFG_1);
+	reg |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
+	fpci_writel(tegra, reg, XUSB_CFG_1);
+
+	/* Enable interrupt assertion */
+	reg = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
+	reg |= IPFS_IP_INT_MASK;
+	ipfs_writel(tegra, reg, IPFS_XUSB_HOST_INTR_MASK_0);
+
+	/* Set hysteresis */
+	ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
+}
+
+static int tegra_xhci_load_firmware(struct tegra_xhci_hcd *tegra)
+{
+	struct device *dev = tegra->dev;
+	struct tegra_xhci_fw_cfgtbl *cfg_tbl;
+	struct tm fw_tm;
+	u32 val, code_tag_blocks, code_size_blocks;
+	u64 fw_base;
+	time_t fw_time;
+	unsigned long timeout;
+
+	if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
+		dev_info(dev, "Firmware already loaded, Falcon state 0x%x\n",
+			 csb_readl(tegra, XUSB_FALC_CPUCTL));
+		return 0;
+	}
+
+	cfg_tbl = (struct tegra_xhci_fw_cfgtbl *)tegra->fw_data;
+
+	/* Program the size of DFI into ILOAD_ATTR. */
+	csb_writel(tegra, tegra->fw_size, XUSB_CSB_MP_ILOAD_ATTR);
+
+	/*
+	 * Boot code of the firmware reads the ILOAD_BASE registers
+	 * to get to the start of the DFI in system memory.
+	 */
+	fw_base = tegra->fw_dma_addr + sizeof(*cfg_tbl);
+	csb_writel(tegra, fw_base, XUSB_CSB_MP_ILOAD_BASE_LO);
+	csb_writel(tegra, fw_base >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
+
+	/* Set BOOTPATH to 1 in APMAP. */
+	csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
+
+	/* Invalidate L2IMEM. */
+	csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
+
+	/*
+	 * Initiate fetch of bootcode from system memory into L2IMEM.
+	 * Program bootcode location and size in system memory.
+	 */
+	code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(cfg_tbl->boot_codetag),
+				       IMEM_BLOCK_SIZE);
+	code_size_blocks = DIV_ROUND_UP(le32_to_cpu(cfg_tbl->boot_codesize),
+					IMEM_BLOCK_SIZE);
+	val = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
+	       L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
+	      ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
+	       L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
+	csb_writel(tegra, val, XUSB_CSB_MP_L2IMEMOP_SIZE);
+
+	/* Trigger L2IMEM load operation. */
+	csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
+		   XUSB_CSB_MP_L2IMEMOP_TRIG);
+
+	/* Setup Falcon auto-fill. */
+	csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
+
+	val = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
+	       IMFILLRNG1_TAG_LO_SHIFT) |
+	      (((code_size_blocks + code_tag_blocks) & IMFILLRNG1_TAG_MASK) <<
+	       IMFILLRNG1_TAG_HI_SHIFT);
+	csb_writel(tegra, val, XUSB_FALC_IMFILLRNG1);
+
+	csb_writel(tegra, 0, XUSB_FALC_DMACTL);
+	msleep(50);
+
+	csb_writel(tegra, le32_to_cpu(cfg_tbl->boot_codetag),
+		   XUSB_FALC_BOOTVEC);
+
+	/* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
+	timeout = jiffies + msecs_to_jiffies(5);
+	csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
+	while (time_before(jiffies, timeout)) {
+		if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
+			break;
+		usleep_range(100, 200);
+	}
+	if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
+		dev_err(dev, "Falcon failed to start, state: %#x\n",
+			csb_readl(tegra, XUSB_FALC_CPUCTL));
+		return -EIO;
+	}
+
+	fw_time = le32_to_cpu(cfg_tbl->fwimg_created_time);
+	time_to_tm(fw_time, 0, &fw_tm);
+	dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
+		 fw_tm.tm_year + 1900, fw_tm.tm_mon + 1, fw_tm.tm_mday,
+		 fw_tm.tm_hour, fw_tm.tm_min, fw_tm.tm_sec);
+
+	return 0;
+}
+
+static int tegra_xhci_set_ss_clk(struct tegra_xhci_hcd *tegra,
+				 unsigned long rate)
+{
+	struct clk *clk = tegra->ss_src_clk;
+	unsigned long new_parent_rate, old_parent_rate;
+	int ret, div;
+
+	if (clk_get_rate(clk) == rate)
+		return 0;
+
+	switch (rate) {
+	case TEGRA_XHCI_SS_CLK_HIGH_SPEED:
+		/*
+		 * Reparent to PLLU_480M. Set divider first to avoid
+		 * overclocking.
+		 */
+		old_parent_rate = clk_get_rate(clk_get_parent(clk));
+		new_parent_rate = clk_get_rate(tegra->pll_u_480m);
+		div = new_parent_rate / rate;
+		ret = clk_set_rate(clk, old_parent_rate / div);
+		if (ret)
+			return ret;
+		ret = clk_set_parent(clk, tegra->pll_u_480m);
+		if (ret)
+			return ret;
+		/*
+		 * The rate should already be correct, but set it again just
+		 * to be sure.
+		 */
+		ret = clk_set_rate(clk, rate);
+		if (ret)
+			return ret;
+		break;
+	case TEGRA_XHCI_SS_CLK_LOW_SPEED:
+		/* Reparent to CLK_M */
+		ret = clk_set_parent(clk, tegra->clk_m);
+		if (ret)
+			return ret;
+		ret = clk_set_rate(clk, rate);
+		if (ret)
+			return ret;
+		break;
+	default:
+		dev_err(tegra->dev, "Invalid SS rate: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	if (clk_get_rate(clk) != rate) {
+		dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int tegra_xhci_clk_enable(struct tegra_xhci_hcd *tegra)
+{
+	int ret;
+
+	ret = clk_prepare_enable(tegra->pll_e);
+	if (ret < 0)
+		return ret;
+	ret = clk_prepare_enable(tegra->host_clk);
+	if (ret < 0)
+		goto disable_plle;
+	ret = clk_prepare_enable(tegra->ss_clk);
+	if (ret < 0)
+		goto disable_host;
+	ret = clk_prepare_enable(tegra->falc_clk);
+	if (ret < 0)
+		goto disable_ss;
+	ret = clk_prepare_enable(tegra->fs_src_clk);
+	if (ret < 0)
+		goto disable_falc;
+	ret = clk_prepare_enable(tegra->hs_src_clk);
+	if (ret < 0)
+		goto disable_fs_src;
+	ret = tegra_xhci_set_ss_clk(tegra, TEGRA_XHCI_SS_CLK_HIGH_SPEED);
+	if (ret < 0)
+		goto disable_hs_src;
+
+	return 0;
+
+disable_hs_src:
+	clk_disable_unprepare(tegra->hs_src_clk);
+disable_fs_src:
+	clk_disable_unprepare(tegra->fs_src_clk);
+disable_falc:
+	clk_disable_unprepare(tegra->falc_clk);
+disable_ss:
+	clk_disable_unprepare(tegra->ss_clk);
+disable_host:
+	clk_disable_unprepare(tegra->host_clk);
+disable_plle:
+	clk_disable_unprepare(tegra->pll_e);
+	return ret;
+}
+
+static void tegra_xhci_clk_disable(struct tegra_xhci_hcd *tegra)
+{
+	clk_disable_unprepare(tegra->pll_e);
+	clk_disable_unprepare(tegra->host_clk);
+	clk_disable_unprepare(tegra->ss_clk);
+	clk_disable_unprepare(tegra->falc_clk);
+	clk_disable_unprepare(tegra->fs_src_clk);
+	clk_disable_unprepare(tegra->hs_src_clk);
+}
+
+static int tegra_xhci_phy_enable(struct tegra_xhci_hcd *tegra)
+{
+	unsigned int i;
+	int ret;
+
+	for (i = 0; i < tegra->num_phys; i++) {
+		ret = phy_init(tegra->phys[i]);
+		if (ret)
+			goto disable_phy;
+		ret = phy_power_on(tegra->phys[i]);
+		if (ret) {
+			phy_exit(tegra->phys[i]);
+			goto disable_phy;
+		}
+	}
+
+	return 0;
+disable_phy:
+	for (; i > 0; i--) {
+		phy_power_off(tegra->phys[i - 1]);
+		phy_exit(tegra->phys[i - 1]);
+	}
+	return ret;
+}
+
+static void tegra_xhci_phy_disable(struct tegra_xhci_hcd *tegra)
+{
+	unsigned int i;
+
+	for (i = 0; i < tegra->num_phys; i++) {
+		phy_power_off(tegra->phys[i]);
+		phy_exit(tegra->phys[i]);
+	}
+}
+
+static bool is_host_mbox_message(u32 cmd)
+{
+	switch (cmd) {
+	case MBOX_CMD_INC_SSPI_CLOCK:
+	case MBOX_CMD_DEC_SSPI_CLOCK:
+	case MBOX_CMD_INC_FALC_CLOCK:
+	case MBOX_CMD_DEC_FALC_CLOCK:
+	case MBOX_CMD_SET_BW:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void tegra_xhci_mbox_work(struct work_struct *work)
+{
+	struct tegra_xhci_hcd *tegra = mbox_work_to_tegra(work);
+	struct tegra_xusb_mbox_msg *msg = &tegra->mbox_req;
+	struct tegra_xusb_mbox_msg resp;
+	int ret;
+
+	resp.cmd = 0;
+	switch (msg->cmd) {
+	case MBOX_CMD_INC_SSPI_CLOCK:
+	case MBOX_CMD_DEC_SSPI_CLOCK:
+		ret = tegra_xhci_set_ss_clk(tegra, msg->data * 1000);
+		resp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
+		if (ret)
+			resp.cmd = MBOX_CMD_NAK;
+		else
+			resp.cmd = MBOX_CMD_ACK;
+		break;
+	case MBOX_CMD_INC_FALC_CLOCK:
+	case MBOX_CMD_DEC_FALC_CLOCK:
+		resp.data = clk_get_rate(tegra->falc_clk) / 1000;
+		if (resp.data != msg->data)
+			resp.cmd = MBOX_CMD_NAK;
+		else
+			resp.cmd = MBOX_CMD_ACK;
+		break;
+	case MBOX_CMD_SET_BW:
+		/*
+		 * TODO: Request bandwidth once EMC scaling is supported.
+		 * Ignore for now since ACK/NAK is not required for SET_BW
+		 * messages.
+		 */
+		break;
+	default:
+		break;
+	}
+
+	if (resp.cmd)
+		mbox_send_message(tegra->mbox_chan, &resp);
+}
+
+static void tegra_xhci_mbox_rx(struct mbox_client *cl, void *data)
+{
+	struct tegra_xhci_hcd *tegra = dev_get_drvdata(cl->dev);
+	struct tegra_xusb_mbox_msg *msg = data;
+
+	if (is_host_mbox_message(msg->cmd)) {
+		tegra->mbox_req = *msg;
+		schedule_work(&tegra->mbox_req_work);
+	}
+}
+
+static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
+{
+	xhci->quirks |= XHCI_PLAT;
+}
+
+static int tegra_xhci_setup(struct usb_hcd *hcd)
+{
+	return xhci_gen_setup(hcd, tegra_xhci_quirks);
+}
+
+static const char * const tegra124_supply_names[] = {
+	"avddio-pex",
+	"dvddio-pex",
+	"avdd-usb",
+	"avdd-pll-utmip",
+	"avdd-pll-erefe",
+	"avdd-usb-ss-pll",
+	"hvdd-usb-ss",
+	"hvdd-usb-ss-pll-e",
+};
+
+static const struct tegra_xhci_phy_type tegra124_phy_types[] = {
+	{ .name = "usb3", .num = 2, },
+	{ .name = "utmi", .num = 3, },
+	{ .name = "hsic", .num = 2, },
+};
+
+static const struct tegra_xhci_soc_data tegra124_soc_data = {
+	.firmware_file = "nvidia/tegra124/xusb.bin",
+	.supply_names = tegra124_supply_names,
+	.num_supplies = ARRAY_SIZE(tegra124_supply_names),
+	.phy_types = tegra124_phy_types,
+	.num_types = ARRAY_SIZE(tegra124_phy_types),
+};
+MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
+
+static const struct of_device_id tegra_xhci_of_match[] = {
+	{ .compatible = "nvidia,tegra124-xhci", .data = &tegra124_soc_data },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, tegra_xhci_of_match);
+
+static void tegra_xhci_probe_finish(const struct firmware *fw, void *context)
+{
+	struct tegra_xhci_hcd *tegra = context;
+	struct device *dev = tegra->dev;
+	struct xhci_hcd *xhci = NULL;
+	struct tegra_xhci_fw_cfgtbl *cfg_tbl;
+	struct tegra_xusb_mbox_msg msg;
+	int ret;
+
+	if (!fw)
+		goto put_usb2_hcd;
+
+	/* Load Falcon controller with its firmware. */
+	cfg_tbl = (struct tegra_xhci_fw_cfgtbl *)fw->data;
+	tegra->fw_size = le32_to_cpu(cfg_tbl->fwimg_len);
+	tegra->fw_data = dma_alloc_coherent(dev, tegra->fw_size,
+					    &tegra->fw_dma_addr,
+					    GFP_KERNEL);
+	if (!tegra->fw_data)
+		goto put_usb2_hcd;
+	memcpy(tegra->fw_data, fw->data, tegra->fw_size);
+
+	ret = tegra_xhci_load_firmware(tegra);
+	if (ret < 0)
+		goto put_usb2_hcd;
+
+	ret = usb_add_hcd(tegra->hcd, tegra->irq, IRQF_SHARED);
+	if (ret < 0)
+		goto put_usb2_hcd;
+	device_wakeup_enable(tegra->hcd->self.controller);
+
+	/*
+	 * USB 2.0 roothub is stored in drvdata now. Swap it with the Tegra HCD.
+	 */
+	tegra->hcd = dev_get_drvdata(dev);
+	dev_set_drvdata(dev, tegra);
+	xhci = hcd_to_xhci(tegra->hcd);
+	xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
+						 dev, dev_name(dev),
+						 tegra->hcd);
+	if (!xhci->shared_hcd)
+		goto dealloc_usb2_hcd;
+
+	ret = usb_add_hcd(xhci->shared_hcd, tegra->irq, IRQF_SHARED);
+	if (ret < 0)
+		goto put_usb3_hcd;
+
+	/* Enable firmware messages from controller. */
+	msg.cmd = MBOX_CMD_MSG_ENABLED;
+	msg.data = 0;
+	ret = mbox_send_message(tegra->mbox_chan, &msg);
+	if (ret < 0)
+		goto dealloc_usb3_hcd;
+
+	tegra->fw_loaded = true;
+	release_firmware(fw);
+	return;
+
+	/* Free up as much as we can and wait to be unbound. */
+dealloc_usb3_hcd:
+	usb_remove_hcd(xhci->shared_hcd);
+put_usb3_hcd:
+	usb_put_hcd(xhci->shared_hcd);
+dealloc_usb2_hcd:
+	usb_remove_hcd(tegra->hcd);
+	kfree(xhci);
+put_usb2_hcd:
+	usb_put_hcd(tegra->hcd);
+	tegra->hcd = NULL;
+	release_firmware(fw);
+}
+
+static int tegra_xhci_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct tegra_xhci_hcd *tegra;
+	struct resource *res;
+	struct usb_hcd *hcd;
+	struct phy *phy;
+	unsigned int i, j, k;
+	int ret;
+
+	BUILD_BUG_ON(sizeof(struct tegra_xhci_fw_cfgtbl) != 256);
+
+	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
+	if (!tegra)
+		return -ENOMEM;
+	tegra->dev = &pdev->dev;
+	tegra->xusb = dev_get_drvdata(pdev->dev.parent);
+	platform_set_drvdata(pdev, tegra);
+
+	match = of_match_device(tegra_xhci_of_match, &pdev->dev);
+	tegra->soc = match->data;
+
+	hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
+			     dev_name(&pdev->dev));
+	if (!hcd)
+		return -ENOMEM;
+	tegra->hcd = hcd;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci");
+	hcd->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(hcd->regs)) {
+		ret = PTR_ERR(hcd->regs);
+		goto put_hcd;
+	}
+	hcd->rsrc_start = res->start;
+	hcd->rsrc_len = resource_size(res);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipfs");
+	tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(tegra->ipfs_base)) {
+		ret = PTR_ERR(tegra->ipfs_base);
+		goto put_hcd;
+	}
+
+	tegra->irq = platform_get_irq(pdev, 0);
+	if (tegra->irq < 0) {
+		ret = tegra->irq;
+		goto put_hcd;
+	}
+
+	tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host");
+	if (IS_ERR(tegra->host_rst)) {
+		ret = PTR_ERR(tegra->host_rst);
+		goto put_hcd;
+	}
+	tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
+	if (IS_ERR(tegra->ss_rst)) {
+		ret = PTR_ERR(tegra->ss_rst);
+		goto put_hcd;
+	}
+
+	tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
+	if (IS_ERR(tegra->host_clk)) {
+		ret = PTR_ERR(tegra->host_clk);
+		goto put_hcd;
+	}
+	tegra->falc_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
+	if (IS_ERR(tegra->falc_clk)) {
+		ret = PTR_ERR(tegra->falc_clk);
+		goto put_hcd;
+	}
+	tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
+	if (IS_ERR(tegra->ss_clk)) {
+		ret = PTR_ERR(tegra->ss_clk);
+		goto put_hcd;
+	}
+	tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
+	if (IS_ERR(tegra->ss_src_clk)) {
+		ret = PTR_ERR(tegra->ss_src_clk);
+		goto put_hcd;
+	}
+	tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
+	if (IS_ERR(tegra->hs_src_clk)) {
+		ret = PTR_ERR(tegra->hs_src_clk);
+		goto put_hcd;
+	}
+	tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
+	if (IS_ERR(tegra->fs_src_clk)) {
+		ret = PTR_ERR(tegra->fs_src_clk);
+		goto put_hcd;
+	}
+	tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
+	if (IS_ERR(tegra->pll_u_480m)) {
+		ret = PTR_ERR(tegra->pll_u_480m);
+		goto put_hcd;
+	}
+	tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
+	if (IS_ERR(tegra->clk_m)) {
+		ret = PTR_ERR(tegra->clk_m);
+		goto put_hcd;
+	}
+	tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
+	if (IS_ERR(tegra->pll_e)) {
+		ret = PTR_ERR(tegra->pll_e);
+		goto put_hcd;
+	}
+	ret = tegra_xhci_clk_enable(tegra);
+	if (ret)
+		goto put_hcd;
+
+	tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
+				       sizeof(*tegra->supplies), GFP_KERNEL);
+	if (!tegra->supplies) {
+		ret = -ENOMEM;
+		goto put_hcd;
+	}
+	for (i = 0; i < tegra->soc->num_supplies; i++)
+		tegra->supplies[i].supply = tegra->soc->supply_names[i];
+	ret = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
+				      tegra->supplies);
+	if (ret)
+		goto disable_clk;
+	ret = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
+	if (ret)
+		goto disable_clk;
+
+	INIT_WORK(&tegra->mbox_req_work, tegra_xhci_mbox_work);
+	tegra->mbox_client.dev = &pdev->dev;
+	tegra->mbox_client.tx_block = true;
+	tegra->mbox_client.tx_tout = 0;
+	tegra->mbox_client.rx_callback = tegra_xhci_mbox_rx;
+	tegra->mbox_chan = mbox_request_channel(&tegra->mbox_client, 0);
+	if (IS_ERR(tegra->mbox_chan)) {
+		ret = PTR_ERR(tegra->mbox_chan);
+		goto disable_regulator;
+	}
+
+	for (i = 0; i < tegra->soc->num_types; i++)
+		tegra->num_phys += tegra->soc->phy_types[i].num;
+	tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
+				   sizeof(*tegra->phys), GFP_KERNEL);
+	if (!tegra->phys) {
+		ret = -ENOMEM;
+		goto put_mbox;
+	}
+	for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
+		char prop[8];
+
+		for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
+			snprintf(prop, sizeof(prop), "%s-%d",
+				 tegra->soc->phy_types[i].name, j);
+			phy = devm_phy_optional_get(&pdev->dev, prop);
+			if (IS_ERR(phy)) {
+				ret = PTR_ERR(phy);
+				goto put_mbox;
+			}
+			tegra->phys[k++] = phy;
+		}
+	}
+
+	tegra_xhci_ipfs_config(tegra);
+
+	ret = tegra_xhci_phy_enable(tegra);
+	if (ret < 0)
+		goto put_mbox;
+
+	ret = request_firmware_nowait(THIS_MODULE, true,
+				      tegra->soc->firmware_file,
+				      tegra->dev, GFP_KERNEL, tegra,
+				      tegra_xhci_probe_finish);
+	if (ret < 0)
+		goto disable_phy;
+
+	return 0;
+
+disable_phy:
+	tegra_xhci_phy_disable(tegra);
+put_mbox:
+	mbox_free_channel(tegra->mbox_chan);
+disable_regulator:
+	regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
+disable_clk:
+	tegra_xhci_clk_disable(tegra);
+put_hcd:
+	usb_put_hcd(hcd);
+	return ret;
+}
+
+static int tegra_xhci_remove(struct platform_device *pdev)
+{
+	struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
+	struct usb_hcd *hcd = tegra->hcd;
+	struct xhci_hcd *xhci;
+
+	if (tegra->fw_loaded) {
+		xhci = hcd_to_xhci(hcd);
+		usb_remove_hcd(xhci->shared_hcd);
+		usb_put_hcd(xhci->shared_hcd);
+		usb_remove_hcd(hcd);
+		usb_put_hcd(hcd);
+		kfree(xhci);
+	} else if (hcd) {
+		/* Unbound after probe(), but before firmware loading. */
+		usb_put_hcd(hcd);
+	}
+
+	if (tegra->fw_data)
+		dma_free_coherent(tegra->dev, tegra->fw_size, tegra->fw_data,
+				  tegra->fw_dma_addr);
+
+	cancel_work_sync(&tegra->mbox_req_work);
+	mbox_free_channel(tegra->mbox_chan);
+	tegra_xhci_phy_disable(tegra);
+	regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
+	tegra_xhci_clk_disable(tegra);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_xhci_suspend(struct device *dev)
+{
+	struct tegra_xhci_hcd *tegra = dev_get_drvdata(dev);
+	struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
+	bool wakeup = device_may_wakeup(dev);
+
+	/* TODO: Powergate controller across suspend/resume. */
+	return xhci_suspend(xhci, wakeup);
+}
+
+static int tegra_xhci_resume(struct device *dev)
+{
+	struct tegra_xhci_hcd *tegra = dev_get_drvdata(dev);
+	struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
+
+	return xhci_resume(xhci, 0);
+}
+#endif
+
+static const struct dev_pm_ops tegra_xhci_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(tegra_xhci_suspend, tegra_xhci_resume)
+};
+
+static struct platform_driver tegra_xhci_driver = {
+	.probe = tegra_xhci_probe,
+	.remove = tegra_xhci_remove,
+	.driver = {
+		.name = "tegra-xhci",
+		.pm = &tegra_xhci_pm_ops,
+		.of_match_table = tegra_xhci_of_match,
+	},
+};
+
+static int __init tegra_xhci_init(void)
+{
+	xhci_init_driver(&tegra_xhci_hc_driver, tegra_xhci_setup);
+	return platform_driver_register(&tegra_xhci_driver);
+}
+module_init(tegra_xhci_init);
+
+static void __exit tegra_xhci_exit(void)
+{
+	platform_driver_unregister(&tegra_xhci_driver);
+}
+module_exit(tegra_xhci_exit);
+
+MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
+MODULE_DESCRIPTION("NVIDIA Tegra xHCI host-controller driver");
+MODULE_LICENSE("GPL v2");
-- 
2.2.0.rc0.207.ga3a616c

Re: [PATCH V7 3/9] mailbox: Fix up error handling in mbox_request_channel()

[Suman Anna]

On 04/27/2015 05:37 PM, Andrew Bresticker wrote:
> From: Benson Leung <bleung@chromium.org>
> 
> mbox_request_channel() currently returns EBUSY in the event the controller
> is not present or if of_xlate() fails, but in neither case is EBUSY really
> appropriate.  Return EPROBE_DEFER if the controller is not yet present
> and change of_xlate() to return an ERR_PTR instead of NULL so that the
> error can be propagated back to the caller of mbox_request_channel().
> 
> Signed-off-by: Benson Leung <bleung@chromium.org>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Cc: Jassi Brar <jassisinghbrar@gmail.com>
> Cc: Suman Anna <s-anna@ti.com>
> ---
> Changes from v6:
>  - Update omap-mailbox's xlate() to return error codes.
> No changes from v5.
> New for v5.
> ---
>  drivers/mailbox/mailbox.c      | 11 ++++++++---
>  drivers/mailbox/omap-mailbox.c |  6 +++---

For the OMAP mailbox portion,
Acked-by: Suman Anna <s-anna@ti.com>

>  2 files changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
> index 19b491d..c3c42d4 100644
> --- a/drivers/mailbox/mailbox.c
> +++ b/drivers/mailbox/mailbox.c
> @@ -318,7 +318,7 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index)
>  		return ERR_PTR(-ENODEV);
>  	}
>  
> -	chan = NULL;
> +	chan = ERR_PTR(-EPROBE_DEFER);
>  	list_for_each_entry(mbox, &mbox_cons, node)
>  		if (mbox->dev->of_node == spec.np) {
>  			chan = mbox->of_xlate(mbox, &spec);
> @@ -327,7 +327,12 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index)
>  
>  	of_node_put(spec.np);
>  
> -	if (!chan || chan->cl || !try_module_get(mbox->dev->driver->owner)) {
> +	if (IS_ERR(chan)) {
> +		mutex_unlock(&con_mutex);
> +		return chan;
> +	}
> +
> +	if (chan->cl || !try_module_get(mbox->dev->driver->owner)) {
>  		dev_dbg(dev, "%s: mailbox not free\n", __func__);
>  		mutex_unlock(&con_mutex);
>  		return ERR_PTR(-EBUSY);
> @@ -390,7 +395,7 @@ of_mbox_index_xlate(struct mbox_controller *mbox,
>  	int ind = sp->args[0];
>  
>  	if (ind >= mbox->num_chans)
> -		return NULL;
> +		return ERR_PTR(-EINVAL);
>  
>  	return &mbox->chans[ind];
>  }
> diff --git a/drivers/mailbox/omap-mailbox.c b/drivers/mailbox/omap-mailbox.c
> index 0f332c1..e0df27b 100644
> --- a/drivers/mailbox/omap-mailbox.c
> +++ b/drivers/mailbox/omap-mailbox.c
> @@ -639,18 +639,18 @@ static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
>  
>  	mdev = container_of(controller, struct omap_mbox_device, controller);
>  	if (WARN_ON(!mdev))
> -		return NULL;
> +		return ERR_PTR(-EINVAL);
>  
>  	node = of_find_node_by_phandle(phandle);
>  	if (!node) {
>  		pr_err("%s: could not find node phandle 0x%x\n",
>  		       __func__, phandle);
> -		return NULL;
> +		return ERR_PTR(-ENODEV);
>  	}
>  
>  	mbox = omap_mbox_device_find(mdev, node->name);
>  	of_node_put(node);
> -	return mbox ? mbox->chan : NULL;
> +	return mbox ? mbox->chan : ERR_PTR(-ENOENT);
>  }
>  
>  static int omap_mbox_probe(struct platform_device *pdev)
> 

Re: [PATCH V7 2/9] mailbox: Make struct mbox_controller's ops field const

[Suman Anna]

Hi Andrew,

On 04/27/2015 05:37 PM, Andrew Bresticker wrote:
> The mailbox controller's channel ops ought to be read-only.

We ought to change this on all the existing controllers as well.

regards
Suman

> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Cc: Jassi Brar <jassisinghbrar@gmail.com>
> ---
> No changes from v5/v6.
> New for v5.
> ---
>  include/linux/mailbox_controller.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h
> index d4cf96f..68c4245 100644
> --- a/include/linux/mailbox_controller.h
> +++ b/include/linux/mailbox_controller.h
> @@ -72,7 +72,7 @@ struct mbox_chan_ops {
>   */
>  struct mbox_controller {
>  	struct device *dev;
> -	struct mbox_chan_ops *ops;
> +	const struct mbox_chan_ops *ops;
>  	struct mbox_chan *chans;
>  	int num_chans;
>  	bool txdone_irq;
> 

Re: [PATCH V7 5/9] mfd: Add driver for NVIDIA Tegra XUSB

[Lee Jones]

On Mon, 27 Apr 2015, Andrew Bresticker wrote:

> Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
> and later SoCs.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Cc: Samuel Ortiz <sameo@linux.intel.com>
> Cc: Lee Jones <lee.jones@linaro.org>
> ---
> New for v7.
> ---
>  drivers/mfd/Kconfig      |   7 ++
>  drivers/mfd/Makefile     |   1 +
>  drivers/mfd/tegra-xusb.c | 167 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/soc/tegra/xusb.h |  19 ++++++
>  4 files changed, 194 insertions(+)
>  create mode 100644 drivers/mfd/tegra-xusb.c
>  create mode 100644 include/soc/tegra/xusb.h
> 
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index d5ad04d..61872b4 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1430,6 +1430,13 @@ config MFD_STW481X
>  	  in various ST Microelectronics and ST-Ericsson embedded
>  	  Nomadik series.
>  
> +config MFD_TEGRA_XUSB
> +	tristate "NVIDIA Tegra XUSB"
> +	depends on ARCH_TEGRA
> +	select MFD_CORE
> +	help
> +	  Support for the XUSB complex found on NVIDIA Tegra124 and later SoCs.
> +
>  menu "Multimedia Capabilities Port drivers"
>  	depends on ARCH_SA1100
>  
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 0e5cfeb..7588caf 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -181,6 +181,7 @@ obj-$(CONFIG_MFD_HI6421_PMIC)	+= hi6421-pmic-core.o
>  obj-$(CONFIG_MFD_DLN2)		+= dln2.o
>  obj-$(CONFIG_MFD_RT5033)	+= rt5033.o
>  obj-$(CONFIG_MFD_SKY81452)	+= sky81452.o
> +obj-$(CONFIG_MFD_TEGRA_XUSB)	+= tegra-xusb.o
>  
>  intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
>  obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
> diff --git a/drivers/mfd/tegra-xusb.c b/drivers/mfd/tegra-xusb.c
> new file mode 100644
> index 0000000..d30d259
> --- /dev/null
> +++ b/drivers/mfd/tegra-xusb.c
> @@ -0,0 +1,167 @@
> +/*
> + * NVIDIA Tegra XUSB MFD driver
> + *
> + * Copyright (C) 2015 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mfd/core.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +
> +#include <soc/tegra/xusb.h>
> +
> +struct tegra_xusb_soc_data {
> +	struct mfd_cell *devs;
> +	unsigned int num_devs;
> +};
> +
> +static struct resource tegra_xhci_resources[] = {
> +	{
> +		.name = "host",
> +		.flags = IORESOURCE_IRQ,
> +	},
> +	{
> +		.name = "xhci",
> +		.flags = IORESOURCE_MEM,
> +	},
> +	{
> +		.name = "ipfs",
> +		.flags = IORESOURCE_MEM,
> +	},
> +};
> +
> +static struct resource tegra_xusb_mbox_resources[] = {
> +	{
> +		.name = "smi",
> +		.flags = IORESOURCE_IRQ,
> +	},
> +};

DEFINE_RES_IRQ_NAMED()

> +static struct mfd_cell tegra124_xusb_devs[] = {
> +	{
> +		.name = "tegra-xhci",
> +		.of_compatible = "nvidia,tegra124-xhci",
> +	},
> +	{
> +		.name = "tegra-xusb-mbox",
> +		.of_compatible = "nvidia,tegra124-xusb-mbox",
> +	},
> +};
> +
> +static const struct tegra_xusb_soc_data tegra124_xusb_data = {
> +	.devs = tegra124_xusb_devs,
> +	.num_devs = ARRAY_SIZE(tegra124_xusb_devs),
> +};
> +
> +static const struct of_device_id tegra_xusb_of_match[] = {
> +	{ .compatible = "nvidia,tegra124-xusb", .data = &tegra124_xusb_data },

Yuk!  Why are you mixing platform data and DT in this way?

Why can't you just stick all of this in DT?

> +	{},
> +};
> +
> +MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
> +static struct regmap_config tegra_fpci_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +};
> +
> +static int tegra_xusb_probe(struct platform_device *pdev)
> +{
> +	const struct tegra_xusb_soc_data *soc;
> +	const struct of_device_id *match;
> +	struct tegra_xusb *xusb;
> +	struct resource *res;
> +	void __iomem *fpci_base;
> +	int irq, ret;
> +
> +	xusb = devm_kzalloc(&pdev->dev, sizeof(*xusb), GFP_KERNEL);
> +	if (!xusb)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, xusb);
> +
> +	match = of_match_node(tegra_xusb_of_match, pdev->dev.of_node);
> +	soc = match->data;
> +
> +	irq = platform_get_irq_byname(pdev, "host");
> +	if (irq < 0)
> +		return irq;
> +	tegra_xhci_resources[0].start = irq;
> +	tegra_xhci_resources[0].end = irq;
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci");
> +	if (!res)
> +		return -ENODEV;
> +	tegra_xhci_resources[1].start = res->start;
> +	tegra_xhci_resources[1].end = res->end;
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipfs");
> +	if (!res)
> +		return -ENODEV;
> +	tegra_xhci_resources[2].start = res->start;
> +	tegra_xhci_resources[2].end = res->end;
> +
> +	soc->devs[0].resources = tegra_xhci_resources;
> +	soc->devs[0].num_resources = ARRAY_SIZE(tegra_xhci_resources);
> +
> +	irq = platform_get_irq_byname(pdev, "smi");
> +	if (irq < 0)
> +		return irq;
> +	tegra_xusb_mbox_resources[0].start = irq;
> +	tegra_xusb_mbox_resources[0].end = irq;
> +
> +	soc->devs[1].resources = tegra_xusb_mbox_resources;
> +	soc->devs[1].num_resources = ARRAY_SIZE(tegra_xusb_mbox_resources);
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fpci");
> +	fpci_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(fpci_base))
> +		return PTR_ERR(fpci_base);

This stuff is not good.

Either let MFD handle it with mfd_cells or stick all of this stuff in
DT and parse it from the child devices.

> +	tegra_fpci_regmap_config.max_register = res->end - res->start - 3;
> +	xusb->fpci_regs = devm_regmap_init_mmio(&pdev->dev, fpci_base,
> +						&tegra_fpci_regmap_config);
> +	if (IS_ERR(xusb->fpci_regs)) {
> +		ret = PTR_ERR(xusb->fpci_regs);
> +		dev_err(&pdev->dev, "Failed to init regmap: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = mfd_add_devices(&pdev->dev, -1, soc->devs, soc->num_devs,
> +			      NULL, 0, NULL);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to add MFD devices: %d\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int tegra_xusb_remove(struct platform_device *pdev)
> +{
> +	mfd_remove_devices(&pdev->dev);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver tegra_xusb_driver = {
> +	.probe = tegra_xusb_probe,
> +	.remove = tegra_xusb_remove,
> +	.driver = {
> +		.name = "tegra-xusb",
> +		.of_match_table = tegra_xusb_of_match,
> +	},
> +};
> +module_platform_driver(tegra_xusb_driver);
> +
> +MODULE_DESCRIPTION("NVIDIA Tegra XUSB MFD");
> +MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/soc/tegra/xusb.h b/include/soc/tegra/xusb.h
> new file mode 100644
> index 0000000..9d28d90
> --- /dev/null
> +++ b/include/soc/tegra/xusb.h
> @@ -0,0 +1,19 @@
> +/*
> + * Copyright (C) 2014 NVIDIA Corporation
> + * Copyright (C) 2014 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + */
> +
> +#ifndef __SOC_TEGRA_XUSB_H__
> +#define __SOC_TEGRA_XUSB_H__
> +
> +struct regmap;
> +
> +struct tegra_xusb {
> +	struct regmap *fpci_regs;

Are you going to add to this?

> +};
> +
> +#endif /* __SOC_TEGRA_XUSB_H__ */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB

[Lee Jones]

On Mon, 27 Apr 2015, Andrew Bresticker wrote:

> Add a binding document for the XUSB host complex on NVIDIA Tegra124
> and later SoCs.  The XUSB host complex includes a mailbox for
> communication with the XUSB micro-controller and an xHCI host-controller.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: Kumar Gala <galak@codeaurora.org>
> Cc: Samuel Ortiz <sameo@linux.intel.com>
> Cc: Lee Jones <lee.jones@linaro.org>
> ---
> New for v7.
> ---
>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> 
> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> new file mode 100644
> index 0000000..6a46680
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> @@ -0,0 +1,46 @@
> +NVIDIA Tegra XUSB host copmlex
> +==============================
> +
> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
> +controller and a mailbox for communication with the XUSB micro-controller.
> +
> +Required properties:
> +--------------------
> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
> +   where <chip> is tegra132.

Okay.  Why?

> + - reg: Must contain register base and length for each register set listed
> +   in reg-names.

You've mentioned 2 of the cells, what about the remaining 2?

> + - reg-names: Must include the following entries:
> +   - xhci
> +   - fpci
> +   - ipfs
> + - interrupts: Must contain an interrupt for each entry in interrupt-names.
> + - interrupt-names: Must include the following entries:
> +   - host
> +   - smi
> +   - pme
> +
> +Example:
> +--------
> +	usb@0,70090000 {
> +		compatible = "nvidia,tegra124-xusb";
> +		reg = <0x0 0x70090000 0x0 0x8000>,
> +		      <0x0 0x70098000 0x0 0x1000>,
> +		      <0x0 0x70099000 0x0 0x1000>;
> +		reg-names = "xhci", "fpci", "ipfs";
> +		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HGIH>,
> +			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "host", "smi", "pme";

Are these resources used by both children?

If not, place them into the children and ioremap() them from the
associated child drivers.

Using an MFD driver to pull all of this out an disseminate it is a bit
bonkers.

> +		usb-host {
> +			compatible = "nvidia,tegra124-xhci";
> +			...
> +		};
> +
> +		mailbox {
> +			compatible = "nvidia,tegra124-xusb-mbox";
> +			...
> +		};
> +	};

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB

[Andrew Bresticker]

Lee,

On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones@linaro.org> wrote:
> On Mon, 27 Apr 2015, Andrew Bresticker wrote:
>
>> Add a binding document for the XUSB host complex on NVIDIA Tegra124
>> and later SoCs.  The XUSB host complex includes a mailbox for
>> communication with the XUSB micro-controller and an xHCI host-controller.
>>
>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Pawel Moll <pawel.moll@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> Cc: Samuel Ortiz <sameo@linux.intel.com>
>> Cc: Lee Jones <lee.jones@linaro.org>
>> ---
>> New for v7.
>> ---
>>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> new file mode 100644
>> index 0000000..6a46680
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> @@ -0,0 +1,46 @@
>> +NVIDIA Tegra XUSB host copmlex
>> +==============================
>> +
>> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
>> +controller and a mailbox for communication with the XUSB micro-controller.
>> +
>> +Required properties:
>> +--------------------
>> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
>> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
>> +   where <chip> is tegra132.
>
> Okay.  Why?

Why what?  This is the convention used for Tegra bindings and is also
documented in Documentation/devicetree/bindings/submitting-patches.txt.
See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
examples of this.

>> + - reg: Must contain register base and length for each register set listed
>> +   in reg-names.
>
> You've mentioned 2 of the cells, what about the remaining 2?

The example given was for Tegra124, where there are two address cells
and two size cells.

>> + - reg-names: Must include the following entries:
>> +   - xhci
>> +   - fpci
>> +   - ipfs
>> + - interrupts: Must contain an interrupt for each entry in interrupt-names.
>> + - interrupt-names: Must include the following entries:
>> +   - host
>> +   - smi
>> +   - pme
>> +
>> +Example:
>> +--------
>> +     usb@0,70090000 {
>> +             compatible = "nvidia,tegra124-xusb";
>> +             reg = <0x0 0x70090000 0x0 0x8000>,
>> +                   <0x0 0x70098000 0x0 0x1000>,
>> +                   <0x0 0x70099000 0x0 0x1000>;
>> +             reg-names = "xhci", "fpci", "ipfs";
>> +             interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
>> +                          <GIC_SPI 40 IRQ_TYPE_LEVEL_HGIH>,
>> +                          <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> +             interrupt-names = "host", "smi", "pme";
>
> Are these resources used by both children?

Only the FPCI register set is shared.

> If not, place them into the children and ioremap() them from the
> associated child drivers.

Ok.

-Andrew

Re: [PATCH V7 5/9] mfd: Add driver for NVIDIA Tegra XUSB

[Andrew Bresticker]

Lee,

On Wed, Apr 29, 2015 at 2:23 AM, Lee Jones <lee.jones@linaro.org> wrote:
> On Mon, 27 Apr 2015, Andrew Bresticker wrote:
>
>> Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
>> and later SoCs.
>>
>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> Cc: Samuel Ortiz <sameo@linux.intel.com>
>> Cc: Lee Jones <lee.jones@linaro.org>

>> --- /dev/null
>> +++ b/drivers/mfd/tegra-xusb.c

>> +struct tegra_xusb_soc_data {
>> +     struct mfd_cell *devs;
>> +     unsigned int num_devs;
>> +};
>> +
>> +static struct resource tegra_xhci_resources[] = {
>> +     {
>> +             .name = "host",
>> +             .flags = IORESOURCE_IRQ,
>> +     },
>> +     {
>> +             .name = "xhci",
>> +             .flags = IORESOURCE_MEM,
>> +     },
>> +     {
>> +             .name = "ipfs",
>> +             .flags = IORESOURCE_MEM,
>> +     },
>> +};
>> +
>> +static struct resource tegra_xusb_mbox_resources[] = {
>> +     {
>> +             .name = "smi",
>> +             .flags = IORESOURCE_IRQ,
>> +     },
>> +};
>
> DEFINE_RES_IRQ_NAMED()
>
>> +static struct mfd_cell tegra124_xusb_devs[] = {
>> +     {
>> +             .name = "tegra-xhci",
>> +             .of_compatible = "nvidia,tegra124-xhci",
>> +     },
>> +     {
>> +             .name = "tegra-xusb-mbox",
>> +             .of_compatible = "nvidia,tegra124-xusb-mbox",
>> +     },
>> +};
>> +
>> +static const struct tegra_xusb_soc_data tegra124_xusb_data = {
>> +     .devs = tegra124_xusb_devs,
>> +     .num_devs = ARRAY_SIZE(tegra124_xusb_devs),
>> +};
>> +
>> +static const struct of_device_id tegra_xusb_of_match[] = {
>> +     { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_xusb_data },
>
> Yuk!  Why are you mixing platform data and DT in this way?
>
> Why can't you just stick all of this in DT?

I assume you mean the resources?  The compatible strings will at least
need to be SoC-specific since they will change from SoC to SoC.

>> +     {},
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
>> +static struct regmap_config tegra_fpci_regmap_config = {
>> +     .reg_bits = 32,
>> +     .val_bits = 32,
>> +     .reg_stride = 4,
>> +};
>> +
>> +static int tegra_xusb_probe(struct platform_device *pdev)
>> +{
>> +     const struct tegra_xusb_soc_data *soc;
>> +     const struct of_device_id *match;
>> +     struct tegra_xusb *xusb;
>> +     struct resource *res;
>> +     void __iomem *fpci_base;
>> +     int irq, ret;
>> +
>> +     xusb = devm_kzalloc(&pdev->dev, sizeof(*xusb), GFP_KERNEL);
>> +     if (!xusb)
>> +             return -ENOMEM;
>> +     platform_set_drvdata(pdev, xusb);
>> +
>> +     match = of_match_node(tegra_xusb_of_match, pdev->dev.of_node);
>> +     soc = match->data;
>> +
>> +     irq = platform_get_irq_byname(pdev, "host");
>> +     if (irq < 0)
>> +             return irq;
>> +     tegra_xhci_resources[0].start = irq;
>> +     tegra_xhci_resources[0].end = irq;
>> +
>> +     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci");
>> +     if (!res)
>> +             return -ENODEV;
>> +     tegra_xhci_resources[1].start = res->start;
>> +     tegra_xhci_resources[1].end = res->end;
>> +
>> +     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipfs");
>> +     if (!res)
>> +             return -ENODEV;
>> +     tegra_xhci_resources[2].start = res->start;
>> +     tegra_xhci_resources[2].end = res->end;
>> +
>> +     soc->devs[0].resources = tegra_xhci_resources;
>> +     soc->devs[0].num_resources = ARRAY_SIZE(tegra_xhci_resources);
>> +
>> +     irq = platform_get_irq_byname(pdev, "smi");
>> +     if (irq < 0)
>> +             return irq;
>> +     tegra_xusb_mbox_resources[0].start = irq;
>> +     tegra_xusb_mbox_resources[0].end = irq;
>> +
>> +     soc->devs[1].resources = tegra_xusb_mbox_resources;
>> +     soc->devs[1].num_resources = ARRAY_SIZE(tegra_xusb_mbox_resources);
>> +
>> +     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fpci");
>> +     fpci_base = devm_ioremap_resource(&pdev->dev, res);
>> +     if (IS_ERR(fpci_base))
>> +             return PTR_ERR(fpci_base);
>
> This stuff is not good.
>
> Either let MFD handle it with mfd_cells or stick all of this stuff in
> DT and parse it from the child devices.

I'm not sure what exactly you mean by "let MFD handle it with
mfd_cells" here - is that not what I'm doing now?  Anyway I think that
leaves two ways of representing this in DT.

Either have the MFD take a single IOMEM resource and divide it up
statically within the driver:

usb@0,70090000 {
        compatible = "nvidia,tegra124-xusb";
        reg = <0x0 0x70090000 0x0 0xa000>;

        usb-host {
                compatible = "nvidia,tegra124-xhci";
                interrupts = <...>;
                ...
        }:

        mailbox {
                compatible = "nvidia,tegra124-xusb-mbox";
                interrupts = <...>;
                ...
        };
};

... or have the MFD take only the shared FPCI resource and have the
sub-devices parse the rest from DT:

usb@0,70098000 {
        compatible = "nvidia,tegra124-xusb";
        reg = <0x0 0x70098000 0x0 0x1000>;
        ranges;

        usb-host@0,70090000 {
                compatible = "nvidia,tegra124-xhci";
                reg = <0x0 0x70090000 0x0 0x8000>,
                        <0x0 0x70099000 0x0 0x1000>;
                interrupts = <...>;
                ...
        }:

        mailbox {
                compatible = "nvidia,tegra124-xusb-mbox";
                interrupts = <...>;
                ...
        };
};

I don't have a strong preference here, but I think the former more
accurately represents the resource hierarchy.  Since Thierry requested
the use of an MFD, I'd like him to weigh in on this - Thierry?

>> +     tegra_fpci_regmap_config.max_register = res->end - res->start - 3;
>> +     xusb->fpci_regs = devm_regmap_init_mmio(&pdev->dev, fpci_base,
>> +                                             &tegra_fpci_regmap_config);
>> +     if (IS_ERR(xusb->fpci_regs)) {
>> +             ret = PTR_ERR(xusb->fpci_regs);
>> +             dev_err(&pdev->dev, "Failed to init regmap: %d\n", ret);
>> +             return ret;
>> +     }
>> +
>> +     ret = mfd_add_devices(&pdev->dev, -1, soc->devs, soc->num_devs,
>> +                           NULL, 0, NULL);
>> +     if (ret) {
>> +             dev_err(&pdev->dev, "Failed to add MFD devices: %d\n", ret);
>> +             return ret;
>> +     }
>> +
>> +     return 0;
>> +}

>> --- /dev/null
>> +++ b/include/soc/tegra/xusb.h

>> +struct tegra_xusb {
>> +     struct regmap *fpci_regs;
>
> Are you going to add to this?

No, I don't have any plans to add to this struct.

-Andrew

Re: [PATCH V7 5/9] mfd: Add driver for NVIDIA Tegra XUSB

[Lee Jones]

On Wed, 29 Apr 2015, Andrew Bresticker wrote:

> Lee,
> 
> On Wed, Apr 29, 2015 at 2:23 AM, Lee Jones <lee.jones@linaro.org> wrote:
> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
> >
> >> Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
> >> and later SoCs.
> >>
> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> >> Cc: Samuel Ortiz <sameo@linux.intel.com>
> >> Cc: Lee Jones <lee.jones@linaro.org>
> 
> >> --- /dev/null
> >> +++ b/drivers/mfd/tegra-xusb.c
> 
> >> +struct tegra_xusb_soc_data {
> >> +     struct mfd_cell *devs;
> >> +     unsigned int num_devs;
> >> +};
> >> +
> >> +static struct resource tegra_xhci_resources[] = {
> >> +     {
> >> +             .name = "host",
> >> +             .flags = IORESOURCE_IRQ,
> >> +     },
> >> +     {
> >> +             .name = "xhci",
> >> +             .flags = IORESOURCE_MEM,
> >> +     },
> >> +     {
> >> +             .name = "ipfs",
> >> +             .flags = IORESOURCE_MEM,
> >> +     },
> >> +};
> >> +
> >> +static struct resource tegra_xusb_mbox_resources[] = {
> >> +     {
> >> +             .name = "smi",
> >> +             .flags = IORESOURCE_IRQ,
> >> +     },
> >> +};
> >
> > DEFINE_RES_IRQ_NAMED()
> >
> >> +static struct mfd_cell tegra124_xusb_devs[] = {
> >> +     {
> >> +             .name = "tegra-xhci",
> >> +             .of_compatible = "nvidia,tegra124-xhci",
> >> +     },
> >> +     {
> >> +             .name = "tegra-xusb-mbox",
> >> +             .of_compatible = "nvidia,tegra124-xusb-mbox",
> >> +     },
> >> +};
> >> +
> >> +static const struct tegra_xusb_soc_data tegra124_xusb_data = {
> >> +     .devs = tegra124_xusb_devs,
> >> +     .num_devs = ARRAY_SIZE(tegra124_xusb_devs),
> >> +};
> >> +
> >> +static const struct of_device_id tegra_xusb_of_match[] = {
> >> +     { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_xusb_data },
> >
> > Yuk!  Why are you mixing platform data and DT in this way?
> >
> > Why can't you just stick all of this in DT?
> 
> I assume you mean the resources?  The compatible strings will at least
> need to be SoC-specific since they will change from SoC to SoC.
> 
> >> +     {},
> >> +};
> >> +
> >> +MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
> >> +static struct regmap_config tegra_fpci_regmap_config = {
> >> +     .reg_bits = 32,
> >> +     .val_bits = 32,
> >> +     .reg_stride = 4,
> >> +};
> >> +
> >> +static int tegra_xusb_probe(struct platform_device *pdev)
> >> +{
> >> +     const struct tegra_xusb_soc_data *soc;
> >> +     const struct of_device_id *match;
> >> +     struct tegra_xusb *xusb;
> >> +     struct resource *res;
> >> +     void __iomem *fpci_base;
> >> +     int irq, ret;
> >> +
> >> +     xusb = devm_kzalloc(&pdev->dev, sizeof(*xusb), GFP_KERNEL);
> >> +     if (!xusb)
> >> +             return -ENOMEM;
> >> +     platform_set_drvdata(pdev, xusb);
> >> +
> >> +     match = of_match_node(tegra_xusb_of_match, pdev->dev.of_node);
> >> +     soc = match->data;
> >> +
> >> +     irq = platform_get_irq_byname(pdev, "host");
> >> +     if (irq < 0)
> >> +             return irq;
> >> +     tegra_xhci_resources[0].start = irq;
> >> +     tegra_xhci_resources[0].end = irq;
> >> +
> >> +     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci");
> >> +     if (!res)
> >> +             return -ENODEV;
> >> +     tegra_xhci_resources[1].start = res->start;
> >> +     tegra_xhci_resources[1].end = res->end;
> >> +
> >> +     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipfs");
> >> +     if (!res)
> >> +             return -ENODEV;
> >> +     tegra_xhci_resources[2].start = res->start;
> >> +     tegra_xhci_resources[2].end = res->end;
> >> +
> >> +     soc->devs[0].resources = tegra_xhci_resources;
> >> +     soc->devs[0].num_resources = ARRAY_SIZE(tegra_xhci_resources);
> >> +
> >> +     irq = platform_get_irq_byname(pdev, "smi");
> >> +     if (irq < 0)
> >> +             return irq;
> >> +     tegra_xusb_mbox_resources[0].start = irq;
> >> +     tegra_xusb_mbox_resources[0].end = irq;
> >> +
> >> +     soc->devs[1].resources = tegra_xusb_mbox_resources;
> >> +     soc->devs[1].num_resources = ARRAY_SIZE(tegra_xusb_mbox_resources);
> >> +
> >> +     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fpci");
> >> +     fpci_base = devm_ioremap_resource(&pdev->dev, res);
> >> +     if (IS_ERR(fpci_base))
> >> +             return PTR_ERR(fpci_base);
> >
> > This stuff is not good.
> >
> > Either let MFD handle it with mfd_cells or stick all of this stuff in
> > DT and parse it from the child devices.
> 
> I'm not sure what exactly you mean by "let MFD handle it with
> mfd_cells" here - is that not what I'm doing now?  Anyway I think that
> leaves two ways of representing this in DT.
> 
> Either have the MFD take a single IOMEM resource and divide it up
> statically within the driver:
> 
> usb@0,70090000 {
>         compatible = "nvidia,tegra124-xusb";
>         reg = <0x0 0x70090000 0x0 0xa000>;
> 
>         usb-host {
>                 compatible = "nvidia,tegra124-xhci";
>                 interrupts = <...>;
>                 ...
>         }:
> 
>         mailbox {
>                 compatible = "nvidia,tegra124-xusb-mbox";
>                 interrupts = <...>;
>                 ...
>         };
> };
> 
> ... or have the MFD take only the shared FPCI resource and have the
> sub-devices parse the rest from DT:
> 
> usb@0,70098000 {
>         compatible = "nvidia,tegra124-xusb";
>         reg = <0x0 0x70098000 0x0 0x1000>;
>         ranges;
> 
>         usb-host@0,70090000 {
>                 compatible = "nvidia,tegra124-xhci";
>                 reg = <0x0 0x70090000 0x0 0x8000>,
>                         <0x0 0x70099000 0x0 0x1000>;
>                 interrupts = <...>;
>                 ...
>         }:
> 
>         mailbox {
>                 compatible = "nvidia,tegra124-xusb-mbox";
>                 interrupts = <...>;
>                 ...
>         };
> };
> 
> I don't have a strong preference here, but I think the former more
> accurately represents the resource hierarchy.  Since Thierry requested
> the use of an MFD, I'd like him to weigh in on this - Thierry?

The latter is what I had in mind.

> >> +     tegra_fpci_regmap_config.max_register = res->end - res->start - 3;
> >> +     xusb->fpci_regs = devm_regmap_init_mmio(&pdev->dev, fpci_base,
> >> +                                             &tegra_fpci_regmap_config);
> >> +     if (IS_ERR(xusb->fpci_regs)) {
> >> +             ret = PTR_ERR(xusb->fpci_regs);
> >> +             dev_err(&pdev->dev, "Failed to init regmap: %d\n", ret);
> >> +             return ret;
> >> +     }
> >> +
> >> +     ret = mfd_add_devices(&pdev->dev, -1, soc->devs, soc->num_devs,
> >> +                           NULL, 0, NULL);
> >> +     if (ret) {
> >> +             dev_err(&pdev->dev, "Failed to add MFD devices: %d\n", ret);
> >> +             return ret;
> >> +     }
> >> +
> >> +     return 0;
> >> +}
> 
> >> --- /dev/null
> >> +++ b/include/soc/tegra/xusb.h
> 
> >> +struct tegra_xusb {
> >> +     struct regmap *fpci_regs;
> >
> > Are you going to add to this?
> 
> No, I don't have any plans to add to this struct.

Then you don't require a struct.  :)

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB

[Lee Jones]

On Wed, 29 Apr 2015, Andrew Bresticker wrote:

> Lee,
> 
> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones@linaro.org> wrote:
> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
> >
> >> Add a binding document for the XUSB host complex on NVIDIA Tegra124
> >> and later SoCs.  The XUSB host complex includes a mailbox for
> >> communication with the XUSB micro-controller and an xHCI host-controller.
> >>
> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> >> Cc: Rob Herring <robh+dt@kernel.org>
> >> Cc: Pawel Moll <pawel.moll@arm.com>
> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> >> Cc: Kumar Gala <galak@codeaurora.org>
> >> Cc: Samuel Ortiz <sameo@linux.intel.com>
> >> Cc: Lee Jones <lee.jones@linaro.org>
> >> ---
> >> New for v7.
> >> ---
> >>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
> >>  1 file changed, 46 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> new file mode 100644
> >> index 0000000..6a46680
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> @@ -0,0 +1,46 @@
> >> +NVIDIA Tegra XUSB host copmlex
> >> +==============================
> >> +
> >> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
> >> +controller and a mailbox for communication with the XUSB micro-controller.
> >> +
> >> +Required properties:
> >> +--------------------
> >> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
> >> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
> >> +   where <chip> is tegra132.
> >
> > Okay.  Why?
> 
> Why what?  This is the convention used for Tegra bindings and is also
> documented in Documentation/devicetree/bindings/submitting-patches.txt.
> See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
> examples of this.

It seems strange to me that you'd mention two specific chips in one
compatible string.  What's the purpose of that?

> >> + - reg: Must contain register base and length for each register set listed
> >> +   in reg-names.
> >
> > You've mentioned 2 of the cells, what about the remaining 2?
> 
> The example given was for Tegra124, where there are two address cells
> and two size cells.

I don't get that.  How does that work?

> >> + - reg-names: Must include the following entries:
> >> +   - xhci
> >> +   - fpci
> >> +   - ipfs
> >> + - interrupts: Must contain an interrupt for each entry in interrupt-names.
> >> + - interrupt-names: Must include the following entries:
> >> +   - host
> >> +   - smi
> >> +   - pme
> >> +
> >> +Example:
> >> +--------
> >> +     usb@0,70090000 {
> >> +             compatible = "nvidia,tegra124-xusb";
> >> +             reg = <0x0 0x70090000 0x0 0x8000>,
> >> +                   <0x0 0x70098000 0x0 0x1000>,
> >> +                   <0x0 0x70099000 0x0 0x1000>;
> >> +             reg-names = "xhci", "fpci", "ipfs";
> >> +             interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> >> +                          <GIC_SPI 40 IRQ_TYPE_LEVEL_HGIH>,
> >> +                          <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> >> +             interrupt-names = "host", "smi", "pme";
> >
> > Are these resources used by both children?
> 
> Only the FPCI register set is shared.
> 
> > If not, place them into the children and ioremap() them from the
> > associated child drivers.
> 
> Ok.

Great.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB

[Andrew Bresticker]

On Wed, Apr 29, 2015 at 11:34 AM, Lee Jones <lee.jones@linaro.org> wrote:
> On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>
>> Lee,
>>
>> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones@linaro.org> wrote:
>> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
>> >
>> >> Add a binding document for the XUSB host complex on NVIDIA Tegra124
>> >> and later SoCs.  The XUSB host complex includes a mailbox for
>> >> communication with the XUSB micro-controller and an xHCI host-controller.
>> >>
>> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> >> Cc: Rob Herring <robh+dt@kernel.org>
>> >> Cc: Pawel Moll <pawel.moll@arm.com>
>> >> Cc: Mark Rutland <mark.rutland@arm.com>
>> >> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> >> Cc: Kumar Gala <galak@codeaurora.org>
>> >> Cc: Samuel Ortiz <sameo@linux.intel.com>
>> >> Cc: Lee Jones <lee.jones@linaro.org>
>> >> ---
>> >> New for v7.
>> >> ---
>> >>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
>> >>  1 file changed, 46 insertions(+)
>> >>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> >> new file mode 100644
>> >> index 0000000..6a46680
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> >> @@ -0,0 +1,46 @@
>> >> +NVIDIA Tegra XUSB host copmlex
>> >> +==============================
>> >> +
>> >> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
>> >> +controller and a mailbox for communication with the XUSB micro-controller.
>> >> +
>> >> +Required properties:
>> >> +--------------------
>> >> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
>> >> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
>> >> +   where <chip> is tegra132.
>> >
>> > Okay.  Why?
>>
>> Why what?  This is the convention used for Tegra bindings and is also
>> documented in Documentation/devicetree/bindings/submitting-patches.txt.
>> See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
>> examples of this.
>
> It seems strange to me that you'd mention two specific chips in one
> compatible string.  What's the purpose of that?

The Tegra maintainers can correct me if I'm wrong here, but the point
is, I think, to future-proof the binding.  There are currently no
differences between Tegra124 and Tegra132 that need to be accounted
for in the driver, so the driver need only match against
"nvidia,tegra124-xusb".  If a Tegra132-specific quirk comes about
later all Tegra132 device-trees will also include the
"nvidia,tegra132-*" compatible string, so we can simply update the
driver without breaking DT backwards-compatibility.

>> >> + - reg: Must contain register base and length for each register set listed
>> >> +   in reg-names.
>> >
>> > You've mentioned 2 of the cells, what about the remaining 2?
>>
>> The example given was for Tegra124, where there are two address cells
>> and two size cells.
>
> I don't get that.  How does that work?

Tegra124 has a physical address space of > 4GB because of LPAE, thus a
single cell each for address and size is not sufficient.  The arm64
Tegra SoCs will obviously also use two address and size cells.  Take a
look at arch/arm/boot/dts/tegra124.dtsi.

-Andrew

Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB

[Lee Jones]

On Wed, 29 Apr 2015, Andrew Bresticker wrote:

> On Wed, Apr 29, 2015 at 11:34 AM, Lee Jones <lee.jones@linaro.org> wrote:
> > On Wed, 29 Apr 2015, Andrew Bresticker wrote:
> >
> >> Lee,
> >>
> >> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones@linaro.org> wrote:
> >> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
> >> >
> >> >> Add a binding document for the XUSB host complex on NVIDIA Tegra124
> >> >> and later SoCs.  The XUSB host complex includes a mailbox for
> >> >> communication with the XUSB micro-controller and an xHCI host-controller.
> >> >>
> >> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> >> >> Cc: Rob Herring <robh+dt@kernel.org>
> >> >> Cc: Pawel Moll <pawel.moll@arm.com>
> >> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> >> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> >> >> Cc: Kumar Gala <galak@codeaurora.org>
> >> >> Cc: Samuel Ortiz <sameo@linux.intel.com>
> >> >> Cc: Lee Jones <lee.jones@linaro.org>
> >> >> ---
> >> >> New for v7.
> >> >> ---
> >> >>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
> >> >>  1 file changed, 46 insertions(+)
> >> >>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> >>
> >> >> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> >> new file mode 100644
> >> >> index 0000000..6a46680
> >> >> --- /dev/null
> >> >> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> >> @@ -0,0 +1,46 @@
> >> >> +NVIDIA Tegra XUSB host copmlex
> >> >> +==============================
> >> >> +
> >> >> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
> >> >> +controller and a mailbox for communication with the XUSB micro-controller.
> >> >> +
> >> >> +Required properties:
> >> >> +--------------------
> >> >> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
> >> >> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
> >> >> +   where <chip> is tegra132.
> >> >
> >> > Okay.  Why?
> >>
> >> Why what?  This is the convention used for Tegra bindings and is also
> >> documented in Documentation/devicetree/bindings/submitting-patches.txt.
> >> See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
> >> examples of this.
> >
> > It seems strange to me that you'd mention two specific chips in one
> > compatible string.  What's the purpose of that?
> 
> The Tegra maintainers can correct me if I'm wrong here, but the point
> is, I think, to future-proof the binding.  There are currently no
> differences between Tegra124 and Tegra132 that need to be accounted
> for in the driver, so the driver need only match against
> "nvidia,tegra124-xusb".  If a Tegra132-specific quirk comes about
> later all Tegra132 device-trees will also include the
> "nvidia,tegra132-*" compatible string, so we can simply update the
> driver without breaking DT backwards-compatibility.

I still don't understand why you need to use them both at the same
time.  Why don't you use nvidia,tegra124-* for Tegra124 and
nvidia,tegra132-* for Tegra132?

> >> >> + - reg: Must contain register base and length for each register set listed
> >> >> +   in reg-names.
> >> >
> >> > You've mentioned 2 of the cells, what about the remaining 2?
> >>
> >> The example given was for Tegra124, where there are two address cells
> >> and two size cells.
> >
> > I don't get that.  How does that work?
> 
> Tegra124 has a physical address space of > 4GB because of LPAE, thus a
> single cell each for address and size is not sufficient.  The arm64
> Tegra SoCs will obviously also use two address and size cells.  Take a
> look at arch/arm/boot/dts/tegra124.dtsi.

Okay, so these get shifted and &'ed into posstible 64bit addresses?

I guess I just thought ARM64 addresses would look like:

  0xXXXXXXXXXXXXXXXX 0xXXXX

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB

[Andrew Bresticker]

On Thu, Apr 30, 2015 at 3:06 AM, Lee Jones <lee.jones@linaro.org> wrote:
> On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>
>> On Wed, Apr 29, 2015 at 11:34 AM, Lee Jones <lee.jones@linaro.org> wrote:
>> > On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>> >
>> >> Lee,
>> >>
>> >> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones@linaro.org> wrote:
>> >> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
>> >> >
>> >> >> Add a binding document for the XUSB host complex on NVIDIA Tegra124
>> >> >> and later SoCs.  The XUSB host complex includes a mailbox for
>> >> >> communication with the XUSB micro-controller and an xHCI host-controller.
>> >> >>
>> >> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> >> >> Cc: Rob Herring <robh+dt@kernel.org>
>> >> >> Cc: Pawel Moll <pawel.moll@arm.com>
>> >> >> Cc: Mark Rutland <mark.rutland@arm.com>
>> >> >> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> >> >> Cc: Kumar Gala <galak@codeaurora.org>
>> >> >> Cc: Samuel Ortiz <sameo@linux.intel.com>
>> >> >> Cc: Lee Jones <lee.jones@linaro.org>
>> >> >> ---
>> >> >> New for v7.
>> >> >> ---
>> >> >>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
>> >> >>  1 file changed, 46 insertions(+)
>> >> >>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> >> >>
>> >> >> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> >> >> new file mode 100644
>> >> >> index 0000000..6a46680
>> >> >> --- /dev/null
>> >> >> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
>> >> >> @@ -0,0 +1,46 @@
>> >> >> +NVIDIA Tegra XUSB host copmlex
>> >> >> +==============================
>> >> >> +
>> >> >> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
>> >> >> +controller and a mailbox for communication with the XUSB micro-controller.
>> >> >> +
>> >> >> +Required properties:
>> >> >> +--------------------
>> >> >> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
>> >> >> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
>> >> >> +   where <chip> is tegra132.
>> >> >
>> >> > Okay.  Why?
>> >>
>> >> Why what?  This is the convention used for Tegra bindings and is also
>> >> documented in Documentation/devicetree/bindings/submitting-patches.txt.
>> >> See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
>> >> examples of this.
>> >
>> > It seems strange to me that you'd mention two specific chips in one
>> > compatible string.  What's the purpose of that?
>>
>> The Tegra maintainers can correct me if I'm wrong here, but the point
>> is, I think, to future-proof the binding.  There are currently no
>> differences between Tegra124 and Tegra132 that need to be accounted
>> for in the driver, so the driver need only match against
>> "nvidia,tegra124-xusb".  If a Tegra132-specific quirk comes about
>> later all Tegra132 device-trees will also include the
>> "nvidia,tegra132-*" compatible string, so we can simply update the
>> driver without breaking DT backwards-compatibility.
>
> I still don't understand why you need to use them both at the same
> time.  Why don't you use nvidia,tegra124-* for Tegra124 and
> nvidia,tegra132-* for Tegra132?

The XUSB block on Tegra132 is identical to the one on Tegra124, so the
Tegra132 XUSB is 'compatible' with the Tegra124 XUSB.  Again, I'm just
following the convention the other Tegra bindings are using...

>> >> >> + - reg: Must contain register base and length for each register set listed
>> >> >> +   in reg-names.
>> >> >
>> >> > You've mentioned 2 of the cells, what about the remaining 2?
>> >>
>> >> The example given was for Tegra124, where there are two address cells
>> >> and two size cells.
>> >
>> > I don't get that.  How does that work?
>>
>> Tegra124 has a physical address space of > 4GB because of LPAE, thus a
>> single cell each for address and size is not sufficient.  The arm64
>> Tegra SoCs will obviously also use two address and size cells.  Take a
>> look at arch/arm/boot/dts/tegra124.dtsi.
>
> Okay, so these get shifted and &'ed into posstible 64bit addresses?

Yup.

-Andrew