[PATCH] clk: tegra: Fix comments for structure definitions

[PATCH] clk: tegra: Fix comments for structure definitions

[Rhyland Klein]

Some fields moved from the tegra_clk_pll struct to
the tegra_pll_params struct. Update the struct comments
to reflect where the fields really are.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
---
 drivers/clk/tegra/clk.h |   74 +++++++++++++++++++++++------------------------
 1 file changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 751a97966354..4eae99a4f32e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -171,6 +171,30 @@ struct div_nmp {
  * @lock_bit_idx:		Bit index for PLL lock status
  * @lock_enable_bit_idx:	Bit index to enable PLL lock
  * @lock_delay:			Delay in us if PLL lock is not used
+ * @freq_table:			array of frequencies supported by PLL
+ * @fixed_rate:			PLL rate if it is fixed
+ * @flags:			PLL flags
+ *
+ * Flags:
+ * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
+ *     PLL locking. If not set it will use lock_delay value to wait.
+ * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
+ *     to be programmed to change output frequency of the PLL.
+ * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
+ *     to be programmed to change output frequency of the PLL.
+ * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
+ *     to be programmed to change output frequency of the PLL.
+ * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
+ *     that it is PLLU and invert post divider value.
+ * TEGRA_PLLM - PLLM has additional override settings in PMC. This
+ *     flag indicates that it is PLLM and use override settings.
+ * TEGRA_PLL_FIXED - We are not supposed to change output frequency
+ *     of some plls.
+ * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
+ * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
+ *     base register.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
+ * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
  */
 struct tegra_clk_pll_params {
 	unsigned long	input_min;
@@ -203,38 +227,26 @@ struct tegra_clk_pll_params {
 	unsigned long	fixed_rate;
 };
 
+#define TEGRA_PLL_USE_LOCK BIT(0)
+#define TEGRA_PLL_HAS_CPCON BIT(1)
+#define TEGRA_PLL_SET_LFCON BIT(2)
+#define TEGRA_PLL_SET_DCCON BIT(3)
+#define TEGRA_PLLU BIT(4)
+#define TEGRA_PLLM BIT(5)
+#define TEGRA_PLL_FIXED BIT(6)
+#define TEGRA_PLLE_CONFIGURE BIT(7)
+#define TEGRA_PLL_LOCK_MISC BIT(8)
+#define TEGRA_PLL_BYPASS BIT(9)
+#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
+
 /**
  * struct tegra_clk_pll - Tegra PLL clock
  *
  * @hw:		handle between common and hardware-specifix interfaces
  * @clk_base:	address of CAR controller
  * @pmc:	address of PMC, required to read override bits
- * @freq_table:	array of frequencies supported by PLL
- * @params:	PLL parameters
- * @flags:	PLL flags
- * @fixed_rate:	PLL rate if it is fixed
  * @lock:	register lock
- *
- * Flags:
- * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
- *     PLL locking. If not set it will use lock_delay value to wait.
- * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
- *     to be programmed to change output frequency of the PLL.
- * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
- *     to be programmed to change output frequency of the PLL.
- * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
- *     to be programmed to change output frequency of the PLL.
- * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
- *     that it is PLLU and invert post divider value.
- * TEGRA_PLLM - PLLM has additional override settings in PMC. This
- *     flag indicates that it is PLLM and use override settings.
- * TEGRA_PLL_FIXED - We are not supposed to change output frequency
- *     of some plls.
- * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
- * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
- *     base register.
- * TEGRA_PLL_BYPASS - PLL has bypass bit
- * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
+ * @params:	PLL parameters
  */
 struct tegra_clk_pll {
 	struct clk_hw	hw;
@@ -246,18 +258,6 @@ struct tegra_clk_pll {
 
 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
 
-#define TEGRA_PLL_USE_LOCK BIT(0)
-#define TEGRA_PLL_HAS_CPCON BIT(1)
-#define TEGRA_PLL_SET_LFCON BIT(2)
-#define TEGRA_PLL_SET_DCCON BIT(3)
-#define TEGRA_PLLU BIT(4)
-#define TEGRA_PLLM BIT(5)
-#define TEGRA_PLL_FIXED BIT(6)
-#define TEGRA_PLLE_CONFIGURE BIT(7)
-#define TEGRA_PLL_LOCK_MISC BIT(8)
-#define TEGRA_PLL_BYPASS BIT(9)
-#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
-
 extern const struct clk_ops tegra_clk_pll_ops;
 extern const struct clk_ops tegra_clk_plle_ops;
 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
-- 
1.7.9.5

Re: [PATCH] clk: tegra: Fix comments for structure definitions

[Peter De Schrijver]

On Mon, Apr 13, 2015 at 12:38:17PM -0400, Rhyland Klein wrote:
> Some fields moved from the tegra_clk_pll struct to
> the tegra_pll_params struct. Update the struct comments
> to reflect where the fields really are.
> 

Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>

> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
>  drivers/clk/tegra/clk.h |   74 +++++++++++++++++++++++------------------------
>  1 file changed, 37 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 751a97966354..4eae99a4f32e 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -171,6 +171,30 @@ struct div_nmp {
>   * @lock_bit_idx:		Bit index for PLL lock status
>   * @lock_enable_bit_idx:	Bit index to enable PLL lock
>   * @lock_delay:			Delay in us if PLL lock is not used
> + * @freq_table:			array of frequencies supported by PLL
> + * @fixed_rate:			PLL rate if it is fixed
> + * @flags:			PLL flags
> + *
> + * Flags:
> + * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
> + *     PLL locking. If not set it will use lock_delay value to wait.
> + * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
> + *     to be programmed to change output frequency of the PLL.
> + * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
> + *     to be programmed to change output frequency of the PLL.
> + * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
> + *     to be programmed to change output frequency of the PLL.
> + * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
> + *     that it is PLLU and invert post divider value.
> + * TEGRA_PLLM - PLLM has additional override settings in PMC. This
> + *     flag indicates that it is PLLM and use override settings.
> + * TEGRA_PLL_FIXED - We are not supposed to change output frequency
> + *     of some plls.
> + * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
> + * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
> + *     base register.
> + * TEGRA_PLL_BYPASS - PLL has bypass bit
> + * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
>   */
>  struct tegra_clk_pll_params {
>  	unsigned long	input_min;
> @@ -203,38 +227,26 @@ struct tegra_clk_pll_params {
>  	unsigned long	fixed_rate;
>  };
>  
> +#define TEGRA_PLL_USE_LOCK BIT(0)
> +#define TEGRA_PLL_HAS_CPCON BIT(1)
> +#define TEGRA_PLL_SET_LFCON BIT(2)
> +#define TEGRA_PLL_SET_DCCON BIT(3)
> +#define TEGRA_PLLU BIT(4)
> +#define TEGRA_PLLM BIT(5)
> +#define TEGRA_PLL_FIXED BIT(6)
> +#define TEGRA_PLLE_CONFIGURE BIT(7)
> +#define TEGRA_PLL_LOCK_MISC BIT(8)
> +#define TEGRA_PLL_BYPASS BIT(9)
> +#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
> +
>  /**
>   * struct tegra_clk_pll - Tegra PLL clock
>   *
>   * @hw:		handle between common and hardware-specifix interfaces
>   * @clk_base:	address of CAR controller
>   * @pmc:	address of PMC, required to read override bits
> - * @freq_table:	array of frequencies supported by PLL
> - * @params:	PLL parameters
> - * @flags:	PLL flags
> - * @fixed_rate:	PLL rate if it is fixed
>   * @lock:	register lock
> - *
> - * Flags:
> - * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
> - *     PLL locking. If not set it will use lock_delay value to wait.
> - * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
> - *     to be programmed to change output frequency of the PLL.
> - * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
> - *     to be programmed to change output frequency of the PLL.
> - * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
> - *     to be programmed to change output frequency of the PLL.
> - * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
> - *     that it is PLLU and invert post divider value.
> - * TEGRA_PLLM - PLLM has additional override settings in PMC. This
> - *     flag indicates that it is PLLM and use override settings.
> - * TEGRA_PLL_FIXED - We are not supposed to change output frequency
> - *     of some plls.
> - * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
> - * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
> - *     base register.
> - * TEGRA_PLL_BYPASS - PLL has bypass bit
> - * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
> + * @params:	PLL parameters
>   */
>  struct tegra_clk_pll {
>  	struct clk_hw	hw;
> @@ -246,18 +258,6 @@ struct tegra_clk_pll {
>  
>  #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
>  
> -#define TEGRA_PLL_USE_LOCK BIT(0)
> -#define TEGRA_PLL_HAS_CPCON BIT(1)
> -#define TEGRA_PLL_SET_LFCON BIT(2)
> -#define TEGRA_PLL_SET_DCCON BIT(3)
> -#define TEGRA_PLLU BIT(4)
> -#define TEGRA_PLLM BIT(5)
> -#define TEGRA_PLL_FIXED BIT(6)
> -#define TEGRA_PLLE_CONFIGURE BIT(7)
> -#define TEGRA_PLL_LOCK_MISC BIT(8)
> -#define TEGRA_PLL_BYPASS BIT(9)
> -#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
> -
>  extern const struct clk_ops tegra_clk_pll_ops;
>  extern const struct clk_ops tegra_clk_plle_ops;
>  struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
> -- 
> 1.7.9.5
> 

Re: [PATCH] clk: tegra: Fix comments for structure definitions

[Benson Leung]

On Mon, Apr 13, 2015 at 9:38 AM, Rhyland Klein <rklein@nvidia.com> wrote:
> Some fields moved from the tegra_clk_pll struct to
> the tegra_pll_params struct. Update the struct comments
> to reflect where the fields really are.
>
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>

-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@chromium.org

Re: [PATCH] clk: tegra: Fix comments for structure definitions

[Benson Leung]

On Mon, Apr 13, 2015 at 9:38 AM, Rhyland Klein <rklein@nvidia.com> wrote:
> Some fields moved from the tegra_clk_pll struct to
> the tegra_pll_params struct. Update the struct comments
> to reflect where the fields really are.
>
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
>  drivers/clk/tegra/clk.h |   74 +++++++++++++++++++++++------------------------
>  1 file changed, 37 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 751a97966354..4eae99a4f32e 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -171,6 +171,30 @@ struct div_nmp {
>   * @lock_bit_idx:              Bit index for PLL lock status


By the way,

It looks like the kernel doc for this structure hasn't been updated
for some of the fields added or modified since. lock_bit_idx is
actually no longer here (now lock_mask), and the bunch added for 114
(including ext_misc_reg) aren't documented.

-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@chromium.org

Re: [PATCH] clk: tegra: Fix comments for structure definitions

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 478 bytes --]

On Mon, Apr 13, 2015 at 12:38:17PM -0400, Rhyland Klein wrote:
> Some fields moved from the tegra_clk_pll struct to
> the tegra_pll_params struct. Update the struct comments
> to reflect where the fields really are.
> 
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
>  drivers/clk/tegra/clk.h |   74 +++++++++++++++++++++++------------------------
>  1 file changed, 37 insertions(+), 37 deletions(-)

Applied to the for-4.2/clk branch.

Thanks,
Thierry

[-- Attachment #2: Type: application/pgp-signature, Size: 819 bytes --]

[PATCH] clk: tegra: Update struct tegra_clk_pll_params kerneldoc

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Benson Leung pointed out that the kerneldoc for this structure has
become stale. Update the field descriptions to match the structure
content.

Reported-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/clk/tegra/clk.h | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index f3782dedbdfb..c47e633616be 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -157,7 +157,7 @@ struct div_nmp {
 };
 
 /**
- * struct clk_pll_params - PLL parameters
+ * struct tegra_clk_pll_params - PLL parameters
  *
  * @input_min:			Minimum input frequency
  * @input_max:			Maximum input frequency
@@ -168,12 +168,22 @@ struct div_nmp {
  * @base_reg:			PLL base reg offset
  * @misc_reg:			PLL misc reg offset
  * @lock_reg:			PLL lock reg offset
- * @lock_bit_idx:		Bit index for PLL lock status
+ * @lock_mask:			Bitmask for PLL lock status
  * @lock_enable_bit_idx:	Bit index to enable PLL lock
+ * @iddq_reg:			PLL IDDQ register offset
+ * @iddq_bit_idx:		Bit index to enable PLL IDDQ
+ * @aux_reg:			AUX register offset
+ * @dyn_ramp_reg:		Dynamic ramp control register offset
+ * @ext_misc_reg:		Miscellaneous control register offsets
+ * @pmc_divnm_reg:		n, m divider PMC override register offset (PLLM)
+ * @pmc_divp_reg:		p divider PMC override register offset (PLLM)
+ * @flags:			PLL flags
+ * @stepa_shift:		Dynamic ramp step A field shift
+ * @stepb_shift:		Dynamic ramp step B field shift
  * @lock_delay:			Delay in us if PLL lock is not used
+ * @div_nmp:			offsets and widths on n, m and p fields
  * @freq_table:			array of frequencies supported by PLL
  * @fixed_rate:			PLL rate if it is fixed
- * @flags:			PLL flags
  *
  * Flags:
  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
-- 
2.3.5

Re: [PATCH] clk: tegra: Update struct tegra_clk_pll_params kerneldoc

[Rhyland Klein]

On 5/6/2015 9:43 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Benson Leung pointed out that the kerneldoc for this structure has
> become stale. Update the field descriptions to match the structure
> content.
> 
> Reported-by: Benson Leung <bleung@chromium.org>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  drivers/clk/tegra/clk.h | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index f3782dedbdfb..c47e633616be 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -157,7 +157,7 @@ struct div_nmp {
>  };
>  
>  /**
> - * struct clk_pll_params - PLL parameters
> + * struct tegra_clk_pll_params - PLL parameters
>   *
>   * @input_min:			Minimum input frequency
>   * @input_max:			Maximum input frequency
> @@ -168,12 +168,22 @@ struct div_nmp {
>   * @base_reg:			PLL base reg offset
>   * @misc_reg:			PLL misc reg offset
>   * @lock_reg:			PLL lock reg offset
> - * @lock_bit_idx:		Bit index for PLL lock status
> + * @lock_mask:			Bitmask for PLL lock status
>   * @lock_enable_bit_idx:	Bit index to enable PLL lock
> + * @iddq_reg:			PLL IDDQ register offset
> + * @iddq_bit_idx:		Bit index to enable PLL IDDQ
> + * @aux_reg:			AUX register offset
> + * @dyn_ramp_reg:		Dynamic ramp control register offset
> + * @ext_misc_reg:		Miscellaneous control register offsets
> + * @pmc_divnm_reg:		n, m divider PMC override register offset (PLLM)
> + * @pmc_divp_reg:		p divider PMC override register offset (PLLM)
> + * @flags:			PLL flags
> + * @stepa_shift:		Dynamic ramp step A field shift
> + * @stepb_shift:		Dynamic ramp step B field shift
>   * @lock_delay:			Delay in us if PLL lock is not used
> + * @div_nmp:			offsets and widths on n, m and p fields
>   * @freq_table:			array of frequencies supported by PLL
>   * @fixed_rate:			PLL rate if it is fixed
> - * @flags:			PLL flags
>   *
>   * Flags:
>   * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
> 

Acked-by: Rhyland Klein <rklein@nvidia.com>

-rhyland

-- 
nvpublic

Re: [PATCH] clk: tegra: Update struct tegra_clk_pll_params kerneldoc

[Benson Leung]

On Wed, May 6, 2015 at 6:43 AM, Thierry Reding <thierry.reding@gmail.com> wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Benson Leung pointed out that the kerneldoc for this structure has
> become stale. Update the field descriptions to match the structure
> content.
>
> Reported-by: Benson Leung <bleung@chromium.org>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  drivers/clk/tegra/clk.h | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index f3782dedbdfb..c47e633616be 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -157,7 +157,7 @@ struct div_nmp {
>  };
>
>  /**
> - * struct clk_pll_params - PLL parameters
> + * struct tegra_clk_pll_params - PLL parameters
>   *
>   * @input_min:                 Minimum input frequency
>   * @input_max:                 Maximum input frequency
> @@ -168,12 +168,22 @@ struct div_nmp {
>   * @base_reg:                  PLL base reg offset
>   * @misc_reg:                  PLL misc reg offset
>   * @lock_reg:                  PLL lock reg offset
> - * @lock_bit_idx:              Bit index for PLL lock status
> + * @lock_mask:                 Bitmask for PLL lock status
>   * @lock_enable_bit_idx:       Bit index to enable PLL lock
> + * @iddq_reg:                  PLL IDDQ register offset
> + * @iddq_bit_idx:              Bit index to enable PLL IDDQ
> + * @aux_reg:                   AUX register offset
> + * @dyn_ramp_reg:              Dynamic ramp control register offset
> + * @ext_misc_reg:              Miscellaneous control register offsets
> + * @pmc_divnm_reg:             n, m divider PMC override register offset (PLLM)
> + * @pmc_divp_reg:              p divider PMC override register offset (PLLM)
> + * @flags:                     PLL flags
> + * @stepa_shift:               Dynamic ramp step A field shift
> + * @stepb_shift:               Dynamic ramp step B field shift
>   * @lock_delay:                        Delay in us if PLL lock is not used


Missed a couple -

@max_p:
@pdiv_tohw:

Thanks!

-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@chromium.org

[PATCH v2] clk: tegra: Update struct tegra_clk_pll_params kerneldoc

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Benson Leung pointed out that the kerneldoc for this structure has
become stale. Update the field descriptions to match the structure
content.

Reported-by: Benson Leung <bleung@chromium.org>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- document max_p and pdiv_tohw fields

 drivers/clk/tegra/clk.h | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index f3782dedbdfb..b76b786e15f6 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -157,7 +157,7 @@ struct div_nmp {
 };
 
 /**
- * struct clk_pll_params - PLL parameters
+ * struct tegra_clk_pll_params - PLL parameters
  *
  * @input_min:			Minimum input frequency
  * @input_max:			Maximum input frequency
@@ -168,12 +168,24 @@ struct div_nmp {
  * @base_reg:			PLL base reg offset
  * @misc_reg:			PLL misc reg offset
  * @lock_reg:			PLL lock reg offset
- * @lock_bit_idx:		Bit index for PLL lock status
+ * @lock_mask:			Bitmask for PLL lock status
  * @lock_enable_bit_idx:	Bit index to enable PLL lock
+ * @iddq_reg:			PLL IDDQ register offset
+ * @iddq_bit_idx:		Bit index to enable PLL IDDQ
+ * @aux_reg:			AUX register offset
+ * @dyn_ramp_reg:		Dynamic ramp control register offset
+ * @ext_misc_reg:		Miscellaneous control register offsets
+ * @pmc_divnm_reg:		n, m divider PMC override register offset (PLLM)
+ * @pmc_divp_reg:		p divider PMC override register offset (PLLM)
+ * @flags:			PLL flags
+ * @stepa_shift:		Dynamic ramp step A field shift
+ * @stepb_shift:		Dynamic ramp step B field shift
  * @lock_delay:			Delay in us if PLL lock is not used
+ * @max_p:			maximum value for the p divider
+ * @pdiv_tohw:			mapping of p divider to register values
+ * @div_nmp:			offsets and widths on n, m and p fields
  * @freq_table:			array of frequencies supported by PLL
  * @fixed_rate:			PLL rate if it is fixed
- * @flags:			PLL flags
  *
  * Flags:
  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
-- 
2.3.5

Re: [PATCH v2] clk: tegra: Update struct tegra_clk_pll_params kerneldoc

[Benson Leung]

On Thu, May 7, 2015 at 8:23 AM, Thierry Reding <thierry.reding@gmail.com> wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Benson Leung pointed out that the kerneldoc for this structure has
> become stale. Update the field descriptions to match the structure
> content.
>
> Reported-by: Benson Leung <bleung@chromium.org>
> Acked-by: Rhyland Klein <rklein@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>


Reviewed-by: Benson Leung <bleung@chromium.org>

Thanks!

-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@chromium.org

Re: [PATCH v2] clk: tegra: Update struct tegra_clk_pll_params kerneldoc

[Michael Turquette]

Quoting Thierry Reding (2015-05-07 08:23:39)
> From: Thierry Reding <treding@nvidia.com>
> 
> Benson Leung pointed out that the kerneldoc for this structure has
> become stale. Update the field descriptions to match the structure
> content.
> 
> Reported-by: Benson Leung <bleung@chromium.org>
> Acked-by: Rhyland Klein <rklein@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Looks good to me.

Regards,
Mike

> ---
> Changes in v2:
> - document max_p and pdiv_tohw fields
> 
>  drivers/clk/tegra/clk.h | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index f3782dedbdfb..b76b786e15f6 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -157,7 +157,7 @@ struct div_nmp {
>  };
>  
>  /**
> - * struct clk_pll_params - PLL parameters
> + * struct tegra_clk_pll_params - PLL parameters
>   *
>   * @input_min:                 Minimum input frequency
>   * @input_max:                 Maximum input frequency
> @@ -168,12 +168,24 @@ struct div_nmp {
>   * @base_reg:                  PLL base reg offset
>   * @misc_reg:                  PLL misc reg offset
>   * @lock_reg:                  PLL lock reg offset
> - * @lock_bit_idx:              Bit index for PLL lock status
> + * @lock_mask:                 Bitmask for PLL lock status
>   * @lock_enable_bit_idx:       Bit index to enable PLL lock
> + * @iddq_reg:                  PLL IDDQ register offset
> + * @iddq_bit_idx:              Bit index to enable PLL IDDQ
> + * @aux_reg:                   AUX register offset
> + * @dyn_ramp_reg:              Dynamic ramp control register offset
> + * @ext_misc_reg:              Miscellaneous control register offsets
> + * @pmc_divnm_reg:             n, m divider PMC override register offset (PLLM)
> + * @pmc_divp_reg:              p divider PMC override register offset (PLLM)
> + * @flags:                     PLL flags
> + * @stepa_shift:               Dynamic ramp step A field shift
> + * @stepb_shift:               Dynamic ramp step B field shift
>   * @lock_delay:                        Delay in us if PLL lock is not used
> + * @max_p:                     maximum value for the p divider
> + * @pdiv_tohw:                 mapping of p divider to register values
> + * @div_nmp:                   offsets and widths on n, m and p fields
>   * @freq_table:                        array of frequencies supported by PLL
>   * @fixed_rate:                        PLL rate if it is fixed
> - * @flags:                     PLL flags
>   *
>   * Flags:
>   * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
> -- 
> 2.3.5
>