* [PATCH v2 0/3] ARM: rockchip: fix the SMP
@ 2015-06-05 11:39 Caesar Wang
2015-06-05 11:39 ` [PATCH v2 1/3] ARM: rockchip: fix the CPU soft reset Caesar Wang
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Caesar Wang @ 2015-06-05 11:39 UTC (permalink / raw)
To: Heiko Stuebner
Cc: dianders, Dmitry Torokhov, linux-rockchip, Caesar Wang,
Russell King, linux-arm-kernel, linux-kernel
Verified on url =
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.14
Caesar Wang (3):
ARM: rockchip: fix the CPU soft reset
ARM: rockchip: ensure CPU to enter WFI/WFE state
ARM: rockchip: fix the SMP code style
arch/arm/mach-rockchip/platsmp.c | 56 +++++++++++++++++++++++++++-------------
1 file changed, 38 insertions(+), 18 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2 1/3] ARM: rockchip: fix the CPU soft reset
2015-06-05 11:39 [PATCH v2 0/3] ARM: rockchip: fix the SMP Caesar Wang
@ 2015-06-05 11:39 ` Caesar Wang
2015-06-05 11:39 ` [PATCH v2 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state Caesar Wang
2015-06-05 11:39 ` [PATCH v2 3/3] ARM: rockchip: fix the SMP code style Caesar Wang
2 siblings, 0 replies; 4+ messages in thread
From: Caesar Wang @ 2015-06-05 11:39 UTC (permalink / raw)
To: Heiko Stuebner
Cc: dianders, Dmitry Torokhov, linux-rockchip, Caesar Wang,
Russell King, linux-arm-kernel, linux-kernel
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 1000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000" ]]; do
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducile log:
[34466.186812] PM: noirq suspend of devices complete after 0.669
msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing: Watchdog detected hard
LOCKUP on cpu 0
.......
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
arch/arm/mach-rockchip/platsmp.c | 46 +++++++++++++++++++++++++++-------------
1 file changed, 31 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 5b4ca3c..1d4659e 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -88,28 +88,44 @@ static int pmu_set_power_domain(int pd, bool on)
return PTR_ERR(rstc);
}
- if (on)
- reset_control_deassert(rstc);
- else
+ if (!on)
reset_control_assert(rstc);
- reset_control_put(rstc);
- }
+ ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
+ if (ret < 0) {
+ pr_err("%s: could not update power domain\n", __func__);
+ reset_control_put(rstc);
+ return ret;
+ }
- ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
- if (ret < 0) {
- pr_err("%s: could not update power domain\n", __func__);
- return ret;
- }
+ ret = -1;
+ while (ret != on) {
+ ret = pmu_power_domain_is_on(pd);
+ if (ret < 0) {
+ pr_err("%s: could not read power domain state\n",
+ __func__);
+ return ret;
+ }
+ }
- ret = -1;
- while (ret != on) {
- ret = pmu_power_domain_is_on(pd);
+ if (on)
+ reset_control_deassert(rstc);
+ } else {
+ ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
if (ret < 0) {
- pr_err("%s: could not read power domain state\n",
- __func__);
+ pr_err("%s: could not update power domain\n", __func__);
return ret;
}
+
+ ret = -1;
+ while (ret != on) {
+ ret = pmu_power_domain_is_on(pd);
+ if (ret < 0) {
+ pr_err("%s: could not read power domain state\n",
+ __func__);
+ return ret;
+ }
+ }
}
return 0;
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state
2015-06-05 11:39 [PATCH v2 0/3] ARM: rockchip: fix the SMP Caesar Wang
2015-06-05 11:39 ` [PATCH v2 1/3] ARM: rockchip: fix the CPU soft reset Caesar Wang
@ 2015-06-05 11:39 ` Caesar Wang
2015-06-05 11:39 ` [PATCH v2 3/3] ARM: rockchip: fix the SMP code style Caesar Wang
2 siblings, 0 replies; 4+ messages in thread
From: Caesar Wang @ 2015-06-05 11:39 UTC (permalink / raw)
To: Heiko Stuebner
Cc: dianders, Dmitry Torokhov, linux-rockchip, Caesar Wang,
Russell King, linux-arm-kernel, linux-kernel
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI/WFE state.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 1d4659e..17b3473 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -335,6 +335,9 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
#ifdef CONFIG_HOTPLUG_CPU
static int rockchip_cpu_kill(unsigned int cpu)
{
+ /* ensure CPU can enter the WFI/WFE state */
+ mdelay(1);
+
pmu_set_power_domain(0 + cpu, false);
return 1;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 3/3] ARM: rockchip: fix the SMP code style
2015-06-05 11:39 [PATCH v2 0/3] ARM: rockchip: fix the SMP Caesar Wang
2015-06-05 11:39 ` [PATCH v2 1/3] ARM: rockchip: fix the CPU soft reset Caesar Wang
2015-06-05 11:39 ` [PATCH v2 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state Caesar Wang
@ 2015-06-05 11:39 ` Caesar Wang
2 siblings, 0 replies; 4+ messages in thread
From: Caesar Wang @ 2015-06-05 11:39 UTC (permalink / raw)
To: Heiko Stuebner
Cc: dianders, Dmitry Torokhov, linux-rockchip, Caesar Wang,
Russell King, linux-arm-kernel, linux-kernel
Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c
Although there is a check, it's no matter.
CHECK: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
+167udelay(10);
total: 0 errors, 0 warnings, 1 checks, 362 lines checked
Changes in v2:
- As Kever points out, Fix the subject typo WIF/WFI in PATCH [2/3].
- As Heiko suggestion, re-adjust the cpu on/off flow in PATCH [1/3].
- Use the checkpatch.pl -f --subjective to check in PATCH [3/3].
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
arch/arm/mach-rockchip/platsmp.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 17b3473..fc50e1f 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -147,7 +147,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
if (cpu >= ncores) {
pr_err("%s: cpu %d outside maximum number of cpus %d\n",
- __func__, cpu, ncores);
+ __func__, cpu, ncores);
return -ENXIO;
}
@@ -166,7 +166,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
* */
udelay(10);
writel(virt_to_phys(rockchip_secondary_startup),
- sram_base_addr + 8);
+ sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev();
}
@@ -345,7 +345,7 @@ static int rockchip_cpu_kill(unsigned int cpu)
static void rockchip_cpu_die(unsigned int cpu)
{
v7_exit_coherency_flush(louis);
- while(1)
+ while (1)
cpu_do_idle();
}
#endif
@@ -358,4 +358,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
.cpu_die = rockchip_cpu_die,
#endif
};
+
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-06-05 11:40 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2015-06-05 11:39 [PATCH v2 0/3] ARM: rockchip: fix the SMP Caesar Wang
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2015-06-05 11:39 ` [PATCH v2 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state Caesar Wang
2015-06-05 11:39 ` [PATCH v2 3/3] ARM: rockchip: fix the SMP code style Caesar Wang
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