[PATCH 0/5] Add support for A53 CPU clock

[PATCH 0/5] Add support for A53 CPU clock

[Georgi Djakov]

This patchset adds support for the A53 CPU clock to allow CPU
frequency scaling. It is used on platforms like Qualcomm's msm8916.

Georgi Djakov (4):
  clk: qcom: Add support for SR2 PLLs
  clk: qcom: Add support for regmap mux-div clocks
  clk: qcom: Add A53 clock driver
  arm64: dts: qcom: msm8916: Add A53 DT node

Stephen Boyd (1):
  clk: Add safe switch hook

 Documentation/devicetree/bindings/clock/qcom,a53cc |   22 ++
 arch/arm64/boot/dts/qcom/msm8916.dtsi              |   12 +
 drivers/clk/clk.c                                  |   76 ++++-
 drivers/clk/qcom/Kconfig                           |    8 +
 drivers/clk/qcom/Makefile                          |    2 +
 drivers/clk/qcom/clk-a53.c                         |  195 +++++++++++++
 drivers/clk/qcom/clk-pll.c                         |   75 +++++
 drivers/clk/qcom/clk-pll.h                         |    1 +
 drivers/clk/qcom/clk-regmap-mux-div.c              |  297 ++++++++++++++++++++
 drivers/clk/qcom/clk-regmap-mux-div.h              |   63 +++++
 include/linux/clk-provider.h                       |    2 +
 11 files changed, 745 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc
 create mode 100644 drivers/clk/qcom/clk-a53.c
 create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c
 create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h

[PATCH 1/5] clk: qcom: Add support for SR2 PLLs

[Georgi Djakov]

Add support for SR2 type pll operations. SR2 is optimized for Time Interval
Error (TIE) or absolute jitter.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/clk-pll.c |   75 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-pll.h |    1 +
 2 files changed, 76 insertions(+)

diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 245d5063a385..017eede87237 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -292,3 +292,78 @@ void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
 		clk_pll_set_fsm_mode(pll, regmap, 0);
 }
 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
+
+static int clk_pll_sr2_enable(struct clk_hw *hw)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	int ret;
+	u32 mode;
+
+	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
+	if (ret)
+		return ret;
+
+	/* Disable PLL bypass mode. */
+	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
+				 PLL_BYPASSNL);
+	if (ret)
+		return ret;
+
+	/*
+	 * H/W requires a 5us delay between disabling the bypass and
+	 * de-asserting the reset. Delay 10us just to be safe.
+	 */
+	udelay(10);
+
+	/* De-assert active-low PLL reset. */
+	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
+				 PLL_RESET_N);
+	if (ret)
+		return ret;
+
+	ret = wait_for_pll(pll);
+	if (ret)
+		return ret;
+
+	/* Enable PLL output. */
+	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
+				 PLL_OUTCTRL);
+}
+
+static int
+clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	const struct pll_freq_tbl *f;
+	bool enabled;
+	u32 mode;
+	u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
+
+	f = find_freq(pll->freq_tbl, rate);
+	if (!f)
+		return -EINVAL;
+
+	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
+	enabled = (mode & enable_mask) == enable_mask;
+
+	if (enabled)
+		clk_pll_disable(hw);
+
+	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
+	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
+	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
+
+	if (enabled)
+		clk_pll_sr2_enable(hw);
+
+	return 0;
+}
+
+const struct clk_ops clk_pll_sr2_ops = {
+	.enable = clk_pll_sr2_enable,
+	.disable = clk_pll_disable,
+	.set_rate = clk_pll_sr2_set_rate,
+	.recalc_rate = clk_pll_recalc_rate,
+	.determine_rate = clk_pll_determine_rate,
+};
+EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index c9c0cda306d0..ffd0c63bddbc 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -62,6 +62,7 @@ struct clk_pll {
 
 extern const struct clk_ops clk_pll_ops;
 extern const struct clk_ops clk_pll_vote_ops;
+extern const struct clk_ops clk_pll_sr2_ops;
 
 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
 

[PATCH 2/5] clk: Add safe switch hook

[Georgi Djakov]

From: Stephen Boyd <sboyd@codeaurora.org>

Sometimes clocks can't accept their parent source turning off
while the source is reprogrammed to a different rate. Most
notably CPU clocks require a way to switch away from the current
PLL they're running on, reprogram that PLL to a new rate, and
then switch back to the PLL with the new rate once they're done.
Add a hook that drivers can implement allowing them to return a
'safe parent' and 'safe frequency' that they can switch their
parent to while the upstream source is reprogrammed to support
this.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[georgi: updated patch to support safe frequency]
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/clk.c            |   76 +++++++++++++++++++++++++++++++++++++-----
 include/linux/clk-provider.h |    2 ++
 2 files changed, 70 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 1cf479b9f3b4..7ec74833612a 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -50,9 +50,13 @@ struct clk_core {
 	struct clk_core		**parents;
 	u8			num_parents;
 	u8			new_parent_index;
+	u8			safe_parent_index;
 	unsigned long		rate;
 	unsigned long		req_rate;
+	unsigned long		old_rate;
 	unsigned long		new_rate;
+	unsigned long		safe_freq;
+	struct clk_core		*safe_parent;
 	struct clk_core		*new_parent;
 	struct clk_core		*new_child;
 	unsigned long		flags;
@@ -1224,7 +1228,9 @@ out:
 static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
 			     struct clk_core *new_parent, u8 p_index)
 {
-	struct clk_core *child;
+	struct clk_core *child, *parent;
+	struct clk_hw *parent_hw;
+	unsigned long safe_freq;
 
 	core->new_rate = new_rate;
 	core->new_parent = new_parent;
@@ -1234,6 +1240,23 @@ static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
 	if (new_parent && new_parent != core->parent)
 		new_parent->new_child = core;
 
+	if (core->ops->get_safe_parent) {
+		parent_hw = core->ops->get_safe_parent(core->hw, &safe_freq);
+		if (parent_hw) {
+			parent = parent_hw->core;
+			p_index = clk_fetch_parent_index(core, parent);
+			core->safe_parent_index = p_index;
+			core->safe_parent = parent;
+			if (safe_freq)
+				core->safe_freq = safe_freq;
+			else
+				core->safe_freq = 0;
+		}
+	} else {
+		core->safe_parent = NULL;
+		core->safe_freq = 0;
+	}
+
 	hlist_for_each_entry(child, &core->children, child_node) {
 		child->new_rate = clk_recalc(child, new_rate);
 		clk_calc_subtree(child, child->new_rate, NULL, 0);
@@ -1338,14 +1361,51 @@ static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
 						  unsigned long event)
 {
 	struct clk_core *child, *tmp_clk, *fail_clk = NULL;
+	struct clk_core *old_parent;
 	int ret = NOTIFY_DONE;
 
-	if (core->rate == core->new_rate)
+	if (core->rate == core->new_rate && event != POST_RATE_CHANGE)
 		return NULL;
 
+	switch (event) {
+	case PRE_RATE_CHANGE:
+		if (core->safe_parent) {
+			if (core->safe_freq)
+				core->ops->set_rate_and_parent(core->hw,
+						core->safe_freq,
+						core->safe_parent->rate,
+						core->safe_parent_index);
+			else
+				core->ops->set_parent(core->hw,
+						core->safe_parent_index);
+		}
+		core->old_rate = core->rate;
+		break;
+	case POST_RATE_CHANGE:
+		if (core->safe_parent) {
+			old_parent = __clk_set_parent_before(core,
+							     core->new_parent);
+			if (core->ops->set_rate_and_parent) {
+				core->ops->set_rate_and_parent(core->hw,
+						core->new_rate,
+						core->new_parent ?
+						core->new_parent->rate : 0,
+						core->new_parent_index);
+			} else if (core->ops->set_parent) {
+				core->ops->set_parent(core->hw,
+						core->new_parent_index);
+			}
+			__clk_set_parent_after(core, core->new_parent,
+					       old_parent);
+		}
+		break;
+	}
+
 	if (core->notifier_count) {
-		ret = __clk_notify(core, event, core->rate, core->new_rate);
-		if (ret & NOTIFY_STOP_MASK)
+		if (event != POST_RATE_CHANGE || core->old_rate != core->rate)
+			ret = __clk_notify(core, event, core->old_rate,
+					   core->new_rate);
+		if (ret & NOTIFY_STOP_MASK && event != POST_RATE_CHANGE)
 			fail_clk = core;
 	}
 
@@ -1388,7 +1448,8 @@ static void clk_change_rate(struct clk_core *core)
 	else if (core->parent)
 		best_parent_rate = core->parent->rate;
 
-	if (core->new_parent && core->new_parent != core->parent) {
+	if (core->new_parent && core->new_parent != core->parent &&
+	    !core->safe_parent) {
 		old_parent = __clk_set_parent_before(core, core->new_parent);
 		trace_clk_set_parent(core, core->new_parent);
 
@@ -1414,9 +1475,6 @@ static void clk_change_rate(struct clk_core *core)
 
 	core->rate = clk_recalc(core, best_parent_rate);
 
-	if (core->notifier_count && old_rate != core->rate)
-		__clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
-
 	/*
 	 * Use safe iteration, as change_rate can actually swap parents
 	 * for certain clock types.
@@ -1469,6 +1527,8 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
 
 	core->req_rate = req_rate;
 
+	clk_propagate_rate_change(top, POST_RATE_CHANGE);
+
 	return ret;
 }
 
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 4a943d13625b..a1b1c1c74056 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -183,6 +183,8 @@ struct clk_ops {
 					  struct clk_hw **best_parent_hw);
 	int		(*set_parent)(struct clk_hw *hw, u8 index);
 	u8		(*get_parent)(struct clk_hw *hw);
+	struct clk_hw	*(*get_safe_parent)(struct clk_hw *hw,
+					    unsigned long *safe_freq);
 	int		(*set_rate)(struct clk_hw *hw, unsigned long rate,
 				    unsigned long parent_rate);
 	int		(*set_rate_and_parent)(struct clk_hw *hw,

[PATCH 3/5] clk: qcom: Add support for regmap mux-div clocks

[Georgi Djakov]

Add support for hardware that support switching both parent clocks and the
divider at the same time. This avoids generating intermediate frequencies
from either the old parent clock and new divider or new parent clock and
old divider combinations.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/Makefile             |    1 +
 drivers/clk/qcom/clk-regmap-mux-div.c |  297 +++++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-regmap-mux-div.h |   63 +++++++
 3 files changed, 361 insertions(+)
 create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c
 create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h

diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 50b337a24a87..38b02a7f2da3 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o
 clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
+clk-qcom-y += clk-regmap-mux-div.o
 clk-qcom-y += reset.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.c b/drivers/clk/qcom/clk-regmap-mux-div.c
new file mode 100644
index 000000000000..fe4664d8bcf3
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux-div.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap-mux-div.h"
+
+#define CMD_RCGR			0x0
+#define CMD_RCGR_UPDATE			BIT(0)
+#define CMD_RCGR_DIRTY_CFG		BIT(4)
+#define CMD_RCGR_ROOT_OFF		BIT(31)
+#define CFG_RCGR			0x4
+
+static int __mux_div_update_config(struct clk_regmap_mux_div *md)
+{
+	int ret;
+	u32 val, count;
+	const char *name = __clk_get_name(md->clkr.hw.clk);
+
+	ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,
+				 CMD_RCGR_UPDATE, CMD_RCGR_UPDATE);
+	if (ret)
+		return ret;
+
+	/* Wait for update to take effect */
+	for (count = 500; count > 0; count--) {
+		ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,
+				  &val);
+		if (ret)
+			return ret;
+		if (!(val & CMD_RCGR_UPDATE))
+			return 0;
+		udelay(1);
+	}
+
+	pr_err("%s: rcg did not update its configuration.", name);
+	return -EBUSY;
+}
+
+static int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src_sel,
+				 u32 src_div)
+{
+	int ret;
+	u32 val, mask;
+
+	val = (src_div << md->hid_shift) | (src_sel << md->src_shift);
+	mask = ((BIT(md->hid_width) - 1) << md->hid_shift) |
+		((BIT(md->src_width) - 1) << md->src_shift);
+
+	ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,
+				 mask, val);
+	if (ret)
+		return ret;
+
+	ret = __mux_div_update_config(md);
+	return ret;
+}
+
+static void __mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src_sel,
+				  u32 *src_div)
+{
+	u32 val, div, src;
+	const char *name = __clk_get_name(md->clkr.hw.clk);
+
+	regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
+
+	if (val & CMD_RCGR_DIRTY_CFG) {
+		pr_err("%s: rcg configuration is pending.\n", name);
+		return;
+	}
+
+	regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
+	src = (val >> md->src_shift);
+	src &= BIT(md->src_width) - 1;
+	*src_sel = src;
+
+	div = (val >> md->hid_shift);
+	div &= BIT(md->hid_width) - 1;
+	*src_div = div;
+}
+
+static int mux_div_enable(struct clk_hw *hw)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+	return __mux_div_set_src_div(md, md->src_sel, md->div);
+}
+
+static inline bool is_better_rate(unsigned long req, unsigned long best,
+				  unsigned long new)
+{
+	return (req <= new && new < best) || (best < req && best < new);
+}
+
+static long mux_div_determine_rate(struct clk_hw *hw, unsigned long rate,
+				   unsigned long min_rate,
+				   unsigned long max_rate,
+				   unsigned long *best_parent_rate,
+				   struct clk_hw **best_parent_hw)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+	unsigned int i, div, max_div;
+	unsigned long actual_rate, rrate = 0;
+
+	for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
+		struct clk *parent = clk_get_parent_by_index(hw->clk, i);
+		unsigned long parent_rate = __clk_get_rate(parent);
+
+		max_div = BIT(md->hid_width) - 1;
+		for (div = 1; div < max_div; div++) {
+			parent_rate = mult_frac(rate, div, 2);
+			parent_rate = __clk_round_rate(parent, parent_rate);
+			actual_rate = mult_frac(parent_rate, 2, div);
+
+			if (is_better_rate(rate, rrate, actual_rate)) {
+				rrate = actual_rate;
+				*best_parent_rate = parent_rate;
+				*best_parent_hw = __clk_get_hw(parent);
+			}
+
+			if (actual_rate < rate || rrate <= rate)
+				break;
+		}
+	}
+
+	if (!rrate)
+		return -EINVAL;
+
+	return rrate;
+}
+
+static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+					 unsigned long prate, u32 src_sel)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+	int ret, i;
+	u32 div, max_div, best_src = 0, best_div = 0;
+	unsigned long actual_rate = 0, rrate = 0;
+
+	for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
+		struct clk *parent = clk_get_parent_by_index(hw->clk, i);
+		unsigned long parent_rate = __clk_get_rate(parent);
+
+		max_div = BIT(md->hid_width) - 1;
+		for (div = 1; div < max_div; div++) {
+			parent_rate = mult_frac(rate, div, 2);
+			parent_rate = __clk_round_rate(parent, parent_rate);
+			actual_rate = mult_frac(parent_rate, 2, div);
+
+			if (is_better_rate(rate, rrate, actual_rate)) {
+				rrate = actual_rate;
+				best_src = md->parent_map[i].cfg;
+				best_div = div - 1;
+			}
+
+			if (actual_rate < rate || rrate <= rate)
+				break;
+		}
+	}
+
+	ret = __mux_div_set_src_div(md, best_src, best_div);
+	if (!ret) {
+		md->div = best_div;
+		md->src_sel = best_src;
+	}
+
+	return ret;
+}
+
+static u8 mux_div_get_parent(struct clk_hw *hw)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+	int num_parents = __clk_get_num_parents(hw->clk);
+	const char *name = __clk_get_name(hw->clk);
+	u32 i, div, src;
+
+	__mux_div_get_src_div(md, &src, &div);
+
+	for (i = 0; i < num_parents; i++)
+		if (src == md->parent_map[i].cfg)
+			return i;
+
+	pr_err("%s: Can't find parent %d\n", name, src);
+	return 0;
+}
+
+static int mux_div_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+	return __mux_div_set_src_div(md, md->parent_map[index].cfg, md->div);
+}
+
+static int mux_div_set_rate(struct clk_hw *hw,
+			    unsigned long rate, unsigned long prate)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+	u8 pindex = mux_div_get_parent(hw);
+	struct clk *parent = clk_get_parent_by_index(hw->clk, pindex);
+	unsigned long current_prate = __clk_get_rate(parent);
+
+	if (rate > current_prate)
+		return -EINVAL;
+
+	return __mux_div_set_rate_and_parent(hw, rate, prate, md->src_sel);
+}
+
+static int mux_div_set_rate_and_parent(struct clk_hw *hw,  unsigned long rate,
+				       unsigned long prate, u8 index)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+	return __mux_div_set_rate_and_parent(hw, rate, prate,
+					     md->parent_map[index].cfg);
+}
+
+static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+	u32 div, src;
+	int i, num_parents = __clk_get_num_parents(hw->clk);
+	const char *name = __clk_get_name(hw->clk);
+
+	__mux_div_get_src_div(md, &src, &div);
+	for (i = 0; i < num_parents; i++)
+		if (src == md->parent_map[i].cfg) {
+			struct clk *p = clk_get_parent_by_index(hw->clk, i);
+			unsigned long parent_rate = __clk_get_rate(p);
+
+			return mult_frac(parent_rate, 2, div + 1);
+		}
+
+	pr_err("%s: Can't find parent %d\n", name, src);
+	return 0;
+}
+
+static struct clk_hw *mux_div_get_safe_parent(struct clk_hw *hw,
+					      unsigned long *safe_freq)
+{
+	int i;
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+	int num_parents = __clk_get_num_parents(hw->clk);
+
+	if (md->safe_freq)
+		*safe_freq = md->safe_freq;
+
+	for (i = 0; i < num_parents; i++)
+		if (md->safe_src == md->parent_map[i].cfg)
+			break;
+
+	return __clk_get_hw(clk_get_parent_by_index(hw->clk, i));
+}
+
+static void mux_div_disable(struct clk_hw *hw)
+{
+	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+	struct clk_hw *parent;
+	u32 div;
+
+	if (!md->safe_freq || !md->safe_src)
+		return;
+
+	parent = mux_div_get_safe_parent(hw, &md->safe_freq);
+	div = divider_get_val(md->safe_freq, clk_get_rate(parent->clk), NULL,
+			      md->hid_width, CLK_DIVIDER_ROUND_CLOSEST);
+	div = 2 * div + 1;
+
+	__mux_div_set_src_div(md, md->safe_src, div);
+}
+
+const struct clk_ops clk_regmap_mux_div_ops = {
+	.enable = mux_div_enable,
+	.disable = mux_div_disable,
+	.get_parent = mux_div_get_parent,
+	.set_parent = mux_div_set_parent,
+	.set_rate = mux_div_set_rate,
+	.set_rate_and_parent = mux_div_set_rate_and_parent,
+	.determine_rate = mux_div_determine_rate,
+	.recalc_rate = mux_div_recalc_rate,
+	.get_safe_parent = mux_div_get_safe_parent,
+};
+EXPORT_SYMBOL_GPL(clk_regmap_mux_div_ops);
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.h b/drivers/clk/qcom/clk-regmap-mux-div.h
new file mode 100644
index 000000000000..b887a900ad89
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux-div.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__
+#define __QCOM_CLK_REGMAP_MUX_DIV_H__
+
+#include <linux/clk-provider.h>
+#include "clk-regmap.h"
+#include "clk-rcg.h"
+
+/**
+ * struct mux_div_clk - combined mux/divider clock
+ * @reg_offset: offset of the mux/divider register
+ * @hid_width:	number of bits in half integer divider
+ * @hid_shift:	lowest bit of hid value field
+ * @src_width:	number of bits in source select
+ * @src_shift:	lowest bit of source select field
+ * @div:	the divider configuration value
+ * @src_sel:	the mux index which will be used if the clock is enabled
+ * @safe_src:	value for safe source
+ * @safe_freq:	When switching rates from A to B, the mux div clock will
+ *		instead switch from A -> safe_freq -> B. This allows the
+ *		mux_div clock to change rates while enabled, even if this
+ *		behavior is not supported by the parent clocks.
+ *		If changing the rate of parent A also causes the rate of
+ *		parent B to change, then safe_freq must be defined.
+ *		safe_freq is expected to have a source clock which is always
+ *		on and runs at only one rate.
+ * @parent_map:	pointer to parent_map struct
+ * @clkr:	handle between common and hardware-specific interfaces
+ */
+
+struct clk_regmap_mux_div {
+	u32				reg_offset;
+	u32				hid_width;
+	u32				hid_shift;
+	u32				src_width;
+	u32				src_shift;
+	u32				div;
+	u32				src_sel;
+	u32				safe_src;
+	unsigned long			safe_freq;
+	const struct parent_map		*parent_map;
+	struct clk_regmap		clkr;
+};
+
+#define to_clk_regmap_mux_div(_hw) \
+	container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
+
+extern const struct clk_ops clk_regmap_mux_div_ops;
+
+#endif

[PATCH 4/5] clk: qcom: Add A53 clock driver

[Georgi Djakov]

Add a driver for the A53 subsystem PLL, so that we can provide higher
frequency clocks for use by the system.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 Documentation/devicetree/bindings/clock/qcom,a53cc |   22 +++
 drivers/clk/qcom/Kconfig                           |    8 +
 drivers/clk/qcom/Makefile                          |    1 +
 drivers/clk/qcom/clk-a53.c                         |  195 ++++++++++++++++++++
 4 files changed, 226 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc
 create mode 100644 drivers/clk/qcom/clk-a53.c

diff --git a/Documentation/devicetree/bindings/clock/qcom,a53cc b/Documentation/devicetree/bindings/clock/qcom,a53cc
new file mode 100644
index 000000000000..209cae8afc1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,a53cc
@@ -0,0 +1,22 @@
+A53 Clock Controller
+
+Required properties :
+- compatible : shall contain:
+			"qcom,a53cc"
+- reg : shall contain base register location and length
+	of the A53 PLL
+- #clock-cells : shall contain 1
+- qcom,apcs : phandle of apcs syscon node
+
+Example:
+	apcs: syscon@b011000 {
+		compatible = "syscon";
+		reg = <0x0b011000 0x1000>;
+	};
+
+	a53cc: clock-controller@0b016000 {
+		compatible = "qcom,clock-a53-msm8916";
+		reg = <0x0b016000 0x40>;
+		#clock-cells = <1>;
+		qcom,apcs = <&apcs>;
+	};
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 59d16668bdf5..82a03260011e 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -97,3 +97,11 @@ config MSM_MMCC_8974
 	  Support for the multimedia clock controller on msm8974 devices.
 	  Say Y if you want to support multimedia devices such as display,
 	  graphics, video encode/decode, camera, etc.
+
+config QCOM_A53
+	tristate "A53 Clock Controller"
+	depends on COMMON_CLK_QCOM
+	help
+	  Support for the A53 clock controller on Qualcomm devices.
+	  Say Y if you want to support CPU frequency scaling on devices
+	  such as MSM8916.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 38b02a7f2da3..b462a3f7551a 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
+obj-$(CONFIG_QCOM_A53) += clk-a53.o
diff --git a/drivers/clk/qcom/clk-a53.c b/drivers/clk/qcom/clk-a53.c
new file mode 100644
index 000000000000..2d4d3f8b2116
--- /dev/null
+++ b/drivers/clk/qcom/clk-a53.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/cpu.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "clk-regmap-mux-div.h"
+
+#define F_APCS_PLL(f, l, m, n) { (f), (l), (m), (n), 0 }
+
+static struct pll_freq_tbl apcs_pll_freq[] = {
+	F_APCS_PLL( 998400000, 52, 0x0, 0x1),
+	F_APCS_PLL(1094400000, 57, 0x0, 0x1),
+	F_APCS_PLL(1152000000, 62, 0x0, 0x1),
+	F_APCS_PLL(1209600000, 65, 0x0, 0x1),
+	F_APCS_PLL(1401600000, 73, 0x0, 0x1),
+};
+
+static struct clk_pll a53sspll = {
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.config_reg = 0x14,
+	.mode_reg = 0x00,
+	.status_reg = 0x1c,
+	.status_bit = 16,
+	.freq_tbl = apcs_pll_freq,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "a53sspll",
+		.parent_names = (const char *[]){ "xo" },
+		.num_parents = 1,
+		.flags = CLK_GET_RATE_NOCACHE,
+		.ops = &clk_pll_sr2_ops,
+	},
+};
+
+static const struct regmap_config a53sspll_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x40,
+	.fast_io	= true,
+};
+
+static struct clk *a53ss_add_pll(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	void __iomem *base;
+	struct regmap *regmap;
+	struct clk_pll *pll;
+
+	pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base))
+		return base;
+
+	pll = &a53sspll;
+
+	regmap = devm_regmap_init_mmio(dev, base, &a53sspll_regmap_config);
+	if (IS_ERR(regmap))
+		return ERR_CAST(regmap);
+
+	return devm_clk_register_regmap(dev, &pll->clkr);
+}
+
+enum {
+	P_GPLL0,
+	P_A53SSPLL,
+};
+
+static const struct parent_map gpll0_a53sspll_map[] = {
+	{ P_GPLL0, 4 },
+	{ P_A53SSPLL, 5 },
+};
+
+static const char * const gpll0_a53sspll[] = {
+	"gpll0_vote",
+	"a53sspll",
+};
+
+static struct clk_regmap_mux_div a53ssmux = {
+	.reg_offset = 0x50,
+	.hid_width = 5,
+	.hid_shift = 0,
+	.src_width = 3,
+	.src_shift = 8,
+	.safe_src = 4,
+	.safe_freq = 400000000,
+	.parent_map = gpll0_a53sspll_map,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "a53ssmux",
+		.parent_names = gpll0_a53sspll,
+		.num_parents = 2,
+		.ops = &clk_regmap_mux_div_ops,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk *a53ss_add_mux(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regmap *regmap;
+	struct clk_regmap_mux_div *mux;
+
+	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return ERR_PTR(-ENOMEM);
+
+	mux = &a53ssmux;
+
+	regmap = syscon_regmap_lookup_by_phandle(np,  "qcom,apcs");
+	if (IS_ERR(regmap))
+		return ERR_CAST(regmap);
+
+	mux->clkr.regmap = regmap;
+	return devm_clk_register(dev, &mux->clkr.hw);
+}
+
+static const struct of_device_id qcom_a53_match_table[] = {
+	{ .compatible = "qcom,clock-a53-msm8916" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, qcom_a53_match_table);
+
+static int qcom_a53_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct clk *clk_pll, *clk_mux;
+	struct clk_onecell_data *data;
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->clks = devm_kcalloc(dev, 2, sizeof(struct clk *), GFP_KERNEL);
+	if (!data->clks)
+		return -ENOMEM;
+
+	clk_pll = a53ss_add_pll(pdev);
+	if (IS_ERR(clk_pll))
+		return PTR_ERR(clk_pll);
+
+	clk_mux = a53ss_add_mux(pdev);
+	if (IS_ERR(clk_mux))
+		return PTR_ERR(clk_mux);
+
+	data->clks[0] = clk_pll;
+	data->clks[1] = clk_mux;
+	data->clk_num = 2;
+
+	clk_prepare_enable(clk_pll);
+
+	return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
+}
+
+static struct platform_driver qcom_a53_driver = {
+	.probe = qcom_a53_probe,
+	.driver = {
+		.name = "qcom-a53",
+		.of_match_table = qcom_a53_match_table,
+	},
+};
+
+static int __init qcom_a53_init(void)
+{
+	return platform_driver_register(&qcom_a53_driver);
+}
+arch_initcall(qcom_a53_init);
+
+MODULE_DESCRIPTION("Qualcomm A53 Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-a53");

[PATCH 5/5] arm64: dts: qcom: msm8916: Add A53 DT node

[Georgi Djakov]

Add nodes for the A53 clocks and apcs, so that the driver
can probe and register the clocks.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index f212b8303d04..9b63a8fddf42 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -118,6 +118,18 @@
 			reg = <0x1800000 0x80000>;
 		};
 
+		apcs: syscon@b011000 {
+			compatible = "syscon";
+			reg = <0x0b011000 0x1000>;
+		};
+
+		a53cc: qcom,a53cc@0b016000 {
+			compatible = "qcom,clock-a53-msm8916";
+			reg = <0x0b016000 0x40>;
+			#clock-cells = <1>;
+			qcom,apcs = <&apcs>;
+		};
+
 		blsp1_uart2: serial@78b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x78b0000 0x200>;

Re: [PATCH 4/5] clk: qcom: Add A53 clock driver

[Paul Bolle]

On Fri, 2015-06-12 at 11:41 +0300, Georgi Djakov wrote:
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-a53.c

> +static int __init qcom_a53_init(void)
> +{
> +	return platform_driver_register(&qcom_a53_driver);
> +}
> +arch_initcall(qcom_a53_init);

There's no function that's, well, called by module_exit() that undoes
the above. So one can build this as a module, load that module, but not
unload it. That's by design?


Paul Bolle

Re: [PATCH 4/5] clk: qcom: Add A53 clock driver

[Georgi Djakov]

On 06/15/2015 04:58 PM, Paul Bolle wrote:
> On Fri, 2015-06-12 at 11:41 +0300, Georgi Djakov wrote:
>> --- /dev/null
>> +++ b/drivers/clk/qcom/clk-a53.c
> 
>> +static int __init qcom_a53_init(void)
>> +{
>> +	return platform_driver_register(&qcom_a53_driver);
>> +}
>> +arch_initcall(qcom_a53_init);
> 
> There's no function that's, well, called by module_exit() that undoes
> the above. So one can build this as a module, load that module, but not
> unload it. That's by design?
> 
> 

In general, it is not expected to unload it as this is for the
main CPU clock, but i will add a module_exit() call to make it
correct. Thanks for the comment!

BR,
Georgi

Re: [PATCH 4/5] clk: qcom: Add A53 clock driver

[Paul Bolle]

On Mon, 2015-06-15 at 18:36 +0300, Georgi Djakov wrote:
> In general, it is not expected to unload it as this is for the
> main CPU clock, but i will add a module_exit() call to make it
> correct.

It's not incorrect to not have a module_exit() call. But not having it
means you can't (easily and cleanly) unload this module. Which is
uncommon enough for me to inquire whether that was by design.

Thanks,


Paul Bolle

Re: [PATCH 1/5] clk: qcom: Add support for SR2 PLLs

[Stephen Boyd]

On 06/12, Georgi Djakov wrote:
> Add support for SR2 type pll operations. SR2 is optimized for Time Interval
> Error (TIE) or absolute jitter.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---

Applied to clk-next

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