From: Robert Richter <rric@kernel.org>
To: Marc Zygnier <marc.zyngier@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Robert Richter <rrichter@cavium.com>
Subject: [PATCH v2 5/5] irqchip, gicv3-its: Workaround for Cavium ThunderX errata 22375, 24313
Date: Thu, 13 Aug 2015 16:47:57 +0200 [thread overview]
Message-ID: <1439477277-6157-6-git-send-email-rric@kernel.org> (raw)
In-Reply-To: <1439477277-6157-1-git-send-email-rric@kernel.org>
From: Robert Richter <rrichter@cavium.com>
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization and basically ignore memory access
type and table size provided by the TYPER and BASER registers.
Signed-off-by: Robert Richter <rrichter@cavium.com>
---
drivers/irqchip/irq-gic-v3-its.c | 39 +++++++++++++++++++++++++++++++++++----
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index bf0659821683..d629e0e03322 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -39,7 +39,8 @@
#include "irq-gic-common.h"
#include "irqchip.h"
-#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0)
+#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
+#define ITS_FLAGS_CAVIUM_THUNDERX (1ULL << 1)
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
@@ -803,9 +804,22 @@ static int its_alloc_tables(struct its_node *its)
int i;
int psz = SZ_64K;
u64 shr = GITS_BASER_InnerShareable;
- u64 cache = GITS_BASER_WaWb;
- u64 typer = readq_relaxed(its->base + GITS_TYPER);
- u32 ids = GITS_TYPER_DEVBITS(typer);
+ u64 cache;
+ u64 typer;
+ u32 ids;
+
+ if (its->flags & ITS_FLAGS_CAVIUM_THUNDERX) {
+ /*
+ * erratum 22375: only alloc 8MB table size
+ * erratum 24313: ignore memory access type
+ */
+ cache = 0;
+ ids = 0x13; /* 20 bits, 8MB */
+ } else {
+ cache = GITS_BASER_WaWb;
+ typer = readq_relaxed(its->base + GITS_TYPER);
+ ids = GITS_TYPER_DEVBITS(typer);
+ }
for (i = 0; i < GITS_BASER_NR_REGS; i++) {
u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
@@ -1391,8 +1405,25 @@ static int its_force_quiescent(void __iomem *base)
}
}
+static void its_enable_cavium_thunderx(void *data)
+{
+ struct its_node *its = data;
+
+ its->flags |= ITS_FLAGS_CAVIUM_THUNDERX;
+}
+
static const struct gic_capabilities its_errata[] = {
{
+ /*
+ * Need to be applied in guests too, thus use midr as
+ * iidr is emulated with different vendor id.
+ */
+ .desc = "ITS: Cavium errata 22375, 24313",
+ .midr = 0x43000a10, /* ThunderX pass 1.x */
+ .midr_mask = 0xfff0fff0,
+ .init = its_enable_cavium_thunderx,
+ },
+ {
}
};
--
2.1.1
prev parent reply other threads:[~2015-08-13 14:48 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-13 14:47 [PATCH v2 0/5] irqchip, gicv3: Updates and Cavium ThunderX errata workarounds Robert Richter
2015-08-13 14:47 ` [PATCH v2 1/5] arm64: gicv3: its: Add range check for number of allocated pages Robert Richter
2015-08-13 14:47 ` [PATCH v2 2/5] irqchip, gicv3: Add HW revision detection and configuration Robert Richter
2015-08-13 15:06 ` Marc Zyngier
2015-08-13 14:47 ` [PATCH v2 3/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154 Robert Richter
2015-08-13 15:11 ` Marc Zyngier
2015-08-13 16:17 ` Robert Richter
2015-08-13 16:54 ` Marc Zyngier
2015-08-13 17:11 ` Robert Richter
2015-08-14 8:28 ` Marc Zyngier
2015-08-14 11:47 ` Robert Richter
2015-08-13 14:47 ` [PATCH v2 4/5] irqchip, gicv3-its: Read typer register outside the loop Robert Richter
2015-08-13 14:47 ` Robert Richter [this message]
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