* [PATCH 0/5] mtd: Qualcomm NAND controller driver
@ 2015-01-16 14:48 Archit Taneja
2015-01-16 14:48 ` [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x Archit Taneja
` (7 more replies)
0 siblings, 8 replies; 71+ messages in thread
From: Archit Taneja @ 2015-01-16 14:48 UTC (permalink / raw)
To: linux-mtd, linux-arm-msm; +Cc: linux-kernel, agross, galak, Archit Taneja
Add support for the NAND controller driver for SoC's that contain EBI2. For now,
the only SoC upstream that has EBI2 is IPQ806x.
The patchset requires the ADM dmaengine patches posted by Andy:
http://thread.gmane.org/gmane.linux.ports.arm.msm/11136
Archit Taneja (5):
clk: qcom: Add EBI2 clocks for IPQ806x
mtd: nand: Add qcom nand controller driver
Documentaion: dt: add DT bindings for Qualcomm NAND controller
arm: qcom: dts: Add NAND controller node for ipq806x
arm: qcom: dts: Enale NAND node on IPQ8064 AP148 pplatform
.../devicetree/bindings/mtd/qcom_nandc.txt | 48 +
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 32 +
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +-
drivers/clk/qcom/gcc-ipq806x.c | 34 +
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qcom_nandc.c | 1995 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 +
8 files changed, 2136 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
create mode 100644 drivers/mtd/nand/qcom_nandc.c
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
@ 2015-01-16 14:48 ` Archit Taneja
2015-01-16 21:56 ` Stephen Boyd
2015-01-29 22:21 ` Stephen Boyd
2015-01-16 14:48 ` [PATCH 2/5] mtd: nand: Add qcom nand controller driver Archit Taneja
` (6 subsequent siblings)
7 siblings, 2 replies; 71+ messages in thread
From: Archit Taneja @ 2015-01-16 14:48 UTC (permalink / raw)
To: linux-mtd, linux-arm-msm
Cc: linux-kernel, agross, galak, Archit Taneja, Stephen Boyd
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks.
Create structs for these clocks so that they can be used by the NAND controller
driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 34 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index afed5eb..7db54c8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -2159,6 +2159,38 @@ static struct clk_branch usb_fs1_h_clk = {
},
};
+static struct clk_branch ebi2_clk = {
+ .hwcg_reg = 0x3b00,
+ .hwcg_bit = 6,
+ .halt_reg = 0x2fcc,
+ .halt_bit = 1,
+ .clkr = {
+ .enable_reg = 0x3b00,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ebi2_clk",
+ .ops = &clk_branch_ops,
+ .flags = CLK_IS_ROOT,
+ },
+ },
+};
+
+static struct clk_branch ebi2_aon_clk = {
+ .hwcg_reg = 0x3b00,
+ .hwcg_bit = 6,
+ .halt_reg = 0x2fcc,
+ .halt_bit = 0,
+ .clkr = {
+ .enable_reg = 0x3b00,
+ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data){
+ .name = "ebi2_always_on_clk",
+ .ops = &clk_branch_ops,
+ .flags = CLK_IS_ROOT,
+ },
+ },
+};
+
static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
@@ -2261,6 +2293,8 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
+ [EBI2_CLK] = &ebi2_clk.clkr,
+ [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index b857cad..858a47f 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -289,5 +289,6 @@
#define UBI32_CORE2_CLK_SRC 278
#define UBI32_CORE1_CLK 279
#define UBI32_CORE2_CLK 280
+#define EBI2_AON_CLK 281
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 2/5] mtd: nand: Add qcom nand controller driver
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-01-16 14:48 ` [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x Archit Taneja
@ 2015-01-16 14:48 ` Archit Taneja
2015-01-21 0:54 ` Daniel Ehrenberg
2015-01-16 14:48 ` [PATCH 3/5] Documentaion: dt: add DT bindings for Qualcomm NAND controller Archit Taneja
` (5 subsequent siblings)
7 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-01-16 14:48 UTC (permalink / raw)
To: linux-mtd, linux-arm-msm; +Cc: linux-kernel, agross, galak, Archit Taneja
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15
series.
It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) and
QPIC (Qualcomm Parallel Interface Controller). These IPs provide a broader
interface for external slow peripheral devices such as LCD and NAND/NOR flash
memory or SRAM like interfaces.
We add support for the NAND controller found within EBI2. For the SoCs of our
interest, we only use the NAND controller within EBI2. Therefore, it's safe for
us to assume that the NAND controller is a standalone block within the SoC.
The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND flash
devices. It contains a HW ECC block that supports BCH ECC (4, 8 and 16 bit
correction/step) and RS ECC(4 bit correction/step) that covers main and spare
data. The controller contains an internal 512 byte page buffer to which we
read/write via DMA. The EBI2 type NAND controller uses ADM DMA for register
read/write and data transfers. The controller performs page reads and writes at
a codeword/step level of 512 bytes. It can support up to 2 external chips of
different configurations.
The driver prepares register read and write configuraton descriptors for each
codeword, followed by data descriptors to read or write data from the
controller's internal buffer. It uses a single ADM DMA channel that we get via
dmaengine API. The controller requires 2 ADM CRCIs for command and data flow
control. These are passed via DT.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qcom_nandc.c | 1995 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 2003 insertions(+)
create mode 100644 drivers/mtd/nand/qcom_nandc.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7d0150d..03ad13d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -524,4 +524,11 @@ config MTD_NAND_SUNXI
help
Enables support for NAND Flash chips on Allwinner SoCs.
+config MTD_NAND_QCOM
+ tristate "Support for NAND on QCOM SoCs"
+ depends on ARCH_QCOM && QCOM_ADM
+ help
+ Enables support for NAND flash chips on SoCs containing the EBI2 NAND
+ controller. This controller is found on IPQ806x SoC.
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index bd38f21..bdf82a9 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -51,5 +51,6 @@ obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
+obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
new file mode 100644
index 0000000..18b4280
--- /dev/null
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -0,0 +1,1995 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_mtd.h>
+#include <linux/delay.h>
+
+/* NANDc reg offsets */
+#define NAND_FLASH_CMD 0x00
+#define NAND_ADDR0 0x04
+#define NAND_ADDR1 0x08
+#define NAND_FLASH_CHIP_SELECT 0x0c
+#define NAND_EXEC_CMD 0x10
+#define NAND_FLASH_STATUS 0x14
+#define NAND_BUFFER_STATUS 0x18
+#define NAND_DEV0_CFG0 0x20
+#define NAND_DEV0_CFG1 0x24
+#define NAND_DEV0_ECC_CFG 0x28
+#define NAND_DEV1_ECC_CFG 0x2c
+#define NAND_DEV1_CFG0 0x30
+#define NAND_DEV1_CFG1 0x34
+#define NAND_READ_ID 0x40
+#define NAND_READ_STATUS 0x44
+#define NAND_DEV_CMD0 0xa0
+#define NAND_DEV_CMD1 0xa4
+#define NAND_DEV_CMD2 0xa8
+#define NAND_DEV_CMD_VLD 0xac
+#define SFLASHC_BURST_CFG 0xe0
+#define NAND_ERASED_CW_DETECT_CFG 0xe8
+#define NAND_ERASED_CW_DETECT_STATUS 0xec
+#define NAND_EBI2_ECC_BUF_CFG 0xf0
+#define FLASH_BUF_ACC 0x100
+
+#define NAND_CTRL 0xf00
+#define NAND_VERSION 0xf08
+#define NAND_READ_LOCATION_0 0xf20
+#define NAND_READ_LOCATION_1 0xf24
+
+/* NAND_FLASH_CMD bits */
+#define PAGE_ACC BIT(4)
+#define LAST_PAGE BIT(5)
+
+/* NAND_FLASH_CHIP_SELECT bits */
+#define NAND_DEV_SEL 0
+#define DM_EN BIT(2)
+
+/* NAND_FLASH_STATUS bits */
+#define FS_OP_ERR BIT(4)
+#define FS_READY_BSY_N BIT(5)
+#define FS_MPU_ERR BIT(8)
+#define FS_DEVICE_STS_ERR BIT(16)
+#define FS_DEVICE_WP BIT(23)
+
+/* NAND_BUFFER_STATUS bits */
+#define BS_UNCORRECTABLE_BIT BIT(8)
+#define BS_CORRECTABLE_ERR_MSK 0x1f
+
+/* NAND_DEVn_CFG0 bits */
+#define DISABLE_STATUS_AFTER_WRITE 4
+#define CW_PER_PAGE 6
+#define UD_SIZE_BYTES 9
+#define ECC_PARITY_SIZE_BYTES_RS 19
+#define SPARE_SIZE_BYTES 23
+#define NUM_ADDR_CYCLES 27
+#define STATUS_BFR_READ 30
+#define SET_RD_MODE_AFTER_STATUS 31
+
+/* NAND_DEVn_CFG0 bits */
+#define DEV0_CFG1_ECC_DISABLE 0
+#define WIDE_FLASH 1
+#define NAND_RECOVERY_CYCLES 2
+#define CS_ACTIVE_BSY 5
+#define BAD_BLOCK_BYTE_NUM 6
+#define BAD_BLOCK_IN_SPARE_AREA 16
+#define WR_RD_BSY_GAP 17
+#define ENABLE_BCH_ECC 27
+
+/* NAND_DEV0_ECC_CFG bits */
+#define ECC_CFG_ECC_DISABLE 0
+#define ECC_SW_RESET 1
+#define ECC_MODE 4
+#define ECC_PARITY_SIZE_BYTES_BCH 8
+#define ECC_NUM_DATA_BYTES 16
+#define ECC_FORCE_CLK_OPEN 30
+
+/* NAND_DEV_CMD1 bits */
+#define READ_ADDR 0
+
+/* NAND_DEV_CMD_VLD bits */
+#define READ_START_VLD 0
+
+/* NAND_EBI2_ECC_BUF_CFG bits */
+#define NUM_STEPS 0
+
+/* NAND_ERASED_CW_DETECT_CFG bits */
+#define ERASED_CW_ECC_MASK 1
+#define AUTO_DETECT_RES 0
+#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
+#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
+#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
+#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
+#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
+
+/* NAND_ERASED_CW_DETECT_STATUS bits */
+#define PAGE_ALL_ERASED BIT(7)
+#define CODEWORD_ALL_ERASED BIT(6)
+#define PAGE_ERASED BIT(5)
+#define CODEWORD_ERASED BIT(4)
+#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
+#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
+
+/* Version Mask */
+#define NAND_VERSION_MAJOR_MASK 0xf0000000
+#define NAND_VERSION_MAJOR_SHIFT 28
+#define NAND_VERSION_MINOR_MASK 0x0fff0000
+#define NAND_VERSION_MINOR_SHIFT 16
+
+/* NAND OP_CMDs */
+#define PAGE_READ 0x2
+#define PAGE_READ_WITH_ECC 0x3
+#define PAGE_READ_WITH_ECC_SPARE 0x4
+#define PROGRAM_PAGE 0x6
+#define PAGE_PROGRAM_WITH_ECC 0x7
+#define PROGRAM_PAGE_SPARE 0x9
+#define BLOCK_ERASE 0xa
+#define FETCH_ID 0xb
+#define RESET_DEVICE 0xd
+
+/*
+ * the NAND controller performs reads/writes with ECC in 512 byte chunks.
+ * the driver calls the chunks 'step' or 'codeword' interchangeably
+ */
+#define NANDC_STEP_SIZE 512
+
+/*
+ * the largest page size we support is 8K, this will have 16 steps/codewords
+ * of 512 bytes each
+ */
+#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
+
+/* we read at most 3 registers per codeword scan */
+#define MAX_REG_RD (3 * MAX_NUM_STEPS)
+
+/* ECC modes */
+#define ECC_NONE BIT(0)
+#define ECC_RS_4BIT BIT(1)
+#define ECC_BCH_4BIT BIT(2)
+#define ECC_BCH_8BIT BIT(3)
+
+struct desc_info {
+ struct list_head list;
+
+ enum dma_transfer_direction dir;
+ struct scatterlist sgl;
+ struct dma_async_tx_descriptor *dma_desc;
+
+ bool mapped;
+};
+
+/*
+ * holds the current register values that we want to write. acts as a contiguous
+ * chunk of memory which we use to write the controller registers through DMA.
+ */
+struct nandc_regs {
+ u32 cmd;
+ u32 addr0;
+ u32 addr1;
+ u32 chip_sel;
+ u32 exec;
+
+ u32 cfg0;
+ u32 cfg1;
+ u32 ecc_bch_cfg;
+
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+
+ u32 cmd1;
+ u32 vld;
+
+ u32 orig_cmd1;
+ u32 orig_vld;
+
+ u32 ecc_buf_cfg;
+};
+
+/*
+ * @data_buffer: DMA buffer for page read/writes
+ * @buf_size/count/start: markers for chip->read_buf/write_buf functions
+ * @data_pos/oob_pos: DMA address offset markers for data/oob within
+ * the data_buffer
+ * @reg_read_buf: buffer for reading register data via DMA
+ * @reg_read_pos: marker for data read in reg_read_buf
+ * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
+ * ecc/non-ecc mode for the current nand flash
+ * device
+ * @regs: a contiguous chunk of memory for DMA register
+ * writes
+ * @list: DMA descriptor list
+ * @ecc_strength: 4 bit or 8 bit ecc, received via DT
+ * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
+ * @cmd_crci: ADM DMA CRCI for command flow control
+ * @data_crci: ADM DMA CRCI for data flow control
+ * @ecc_modes: supported ECC modes by the current controller,
+ * initialized via DT match data
+ * @cw_size: the number of bytes in a single step/codeword
+ * of a page, consisting of all data, ecc, spare
+ * and reserved bytes
+ * @cw_data: the number of bytes within a codeword protected
+ * by ECC
+ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
+ * @page: current page in use by the controller
+ * @erased_page: tracker to tell if last page was erased or not
+ * @status: value to be returned if NAND_CMD_STATUS command
+ * is executed
+ * @dma_done: completion param to denote end of last
+ * descriptor in the list
+ */
+struct qcom_nandc_data {
+ struct platform_device *pdev;
+ struct device *dev;
+
+ void __iomem *base;
+ struct resource *res;
+
+ struct clk *core_clk;
+ struct clk *aon_clk;
+
+ struct dma_chan *chan;
+ struct dma_slave_config slave_conf;
+
+ struct nand_chip chip;
+ struct mtd_info mtd;
+
+ u8 *data_buffer;
+ dma_addr_t data_buffer_paddr;
+ int buf_size;
+ int buf_count;
+ int buf_start;
+ int data_pos;
+ int oob_pos;
+
+ u32 *reg_read_buf;
+ dma_addr_t reg_read_paddr;
+ int reg_read_pos;
+
+ u32 cfg0, cfg1;
+ u32 cfg0_raw, cfg1_raw;
+ u32 ecc_buf_cfg;
+ u32 ecc_bch_cfg;
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+ u32 sflashc_burst_cfg;
+ u32 cmd1, vld;
+
+ struct nandc_regs *regs;
+
+ struct list_head list;
+
+ int ecc_strength;
+ int bus_width;
+ unsigned int cmd_crci;
+ unsigned int data_crci;
+
+ u32 ecc_modes;
+
+ int cw_size;
+ int cw_data;
+ bool use_ecc;
+ bool bch_enabled;
+ int page;
+ bool erased_page;
+ u8 status;
+ int last_command;
+ struct completion dma_done;
+};
+
+static inline unsigned int nandc_read(struct qcom_nandc_data *this, int offset)
+{
+ return ioread32(this->base + offset);
+}
+
+static inline void nandc_write(struct qcom_nandc_data *this, int offset,
+ unsigned int val)
+{
+ iowrite32(val, this->base + offset);
+}
+
+static void set_address(struct qcom_nandc_data *this, u16 column, int page)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nandc_regs *regs = this->regs;
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ column >>= 1;
+
+ regs->addr0 = page << 16 | column;
+ regs->addr1 = page >> 16 & 0xff;
+}
+
+static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
+{
+ struct nandc_regs *regs = this->regs;
+
+ if (this->use_ecc) {
+ if (read)
+ regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
+ else
+ regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
+
+ regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ regs->cfg1 = this->cfg1;
+ regs->ecc_bch_cfg = this->ecc_bch_cfg;
+ } else {
+ if (read)
+ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ else
+ regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
+
+ regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ regs->cfg1 = this->cfg1_raw;
+ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ }
+
+ regs->ecc_buf_cfg = this->ecc_buf_cfg;
+ regs->clrflashstatus = this->clrflashstatus;
+ regs->clrreadstatus = this->clrreadstatus;
+ regs->exec = 1;
+}
+
+/*
+ * write_reg_dma: prepares a descriptor to write a given number of
+ * contiguous registers
+ *
+ * @first: offset of the first register in the contiguous block
+ * @reg: starting address containing the reg values to write
+ * @num_regs: number of registers to write
+ * @flow_control: flow control enabled/disabled
+ */
+static int write_reg_dma(struct qcom_nandc_data *this, int first,
+ u32 *reg, int num_regs, bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ int size;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ size = num_regs * sizeof(u32);
+
+ sg_init_one(sgl, reg, size);
+
+ desc->dir = DMA_MEM_TO_DEV;
+
+ dma_map_sg(this->dev, sgl, 1, desc->dir);
+
+ this->slave_conf.device_fc = flow_control ? 1 : 0;
+ this->slave_conf.dst_addr = this->res->start + first;
+ this->slave_conf.dst_maxburst = 16;
+ this->slave_conf.slave_id = this->cmd_crci;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare register write desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ desc->mapped = true;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * read_reg_dma: prepares a descriptor to read a given number of
+ * contiguous registers to the reg_read_buf pointer
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to read
+ * @flow_control: flow control enabled/disabled
+ */
+static int read_reg_dma(struct qcom_nandc_data *this, int first,
+ int num_regs, bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ int size;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ size = num_regs * sizeof(u32);
+
+ sg_init_one(sgl, this->reg_read_buf + this->reg_read_pos, size);
+
+ desc->dir = DMA_DEV_TO_MEM;
+
+ dma_map_sg(this->dev, sgl, 1, desc->dir);
+
+ this->slave_conf.device_fc = flow_control ? 1 : 0;
+ this->slave_conf.src_addr = this->res->start + first;
+ this->slave_conf.src_maxburst = 16;
+ this->slave_conf.slave_id = this->data_crci;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare register read desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ desc->mapped = true;
+
+ this->reg_read_pos += num_regs;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * read_data_dma: prepares a DMA descriptor to transfer data from the
+ * controller's internal buffer to data_buffer
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @buf_off: offset in data_buffer where we want to write the data
+ * read from the controller
+ * @size: DMA transaction size in bytes
+ */
+static int read_data_dma(struct qcom_nandc_data *this, int reg_off,
+ int *buf_off, int size)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ void *vaddr;
+ dma_addr_t address;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ vaddr = this->data_buffer + *buf_off;
+ address = this->data_buffer_paddr + *buf_off;
+
+ sg_init_one(sgl, vaddr, size);
+ sgl->dma_address = address;
+
+ desc->dir = DMA_DEV_TO_MEM;
+
+ this->slave_conf.device_fc = 0;
+ this->slave_conf.src_addr = this->res->start + reg_off;
+ this->slave_conf.src_maxburst = 16;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare data read desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ *buf_off += size;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * write_data_dma: prepares a DMA descriptor to transfer data from
+ * data_buffer to the controller's internal buffer
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @buf_off: offset in data_buffer where we want to read the data to
+ * be written to the controller
+ * @size: DMA transaction size in bytes
+ */
+static int write_data_dma(struct qcom_nandc_data *this, int reg_off,
+ int *buf_off, int size)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ void *vaddr;
+ dma_addr_t address;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ vaddr = this->data_buffer + *buf_off;
+ address = this->data_buffer_paddr + *buf_off;
+
+ sg_init_one(sgl, vaddr, size);
+ sgl->dma_address = address;
+
+ desc->dir = DMA_MEM_TO_DEV;
+
+ this->slave_conf.device_fc = 0;
+ this->slave_conf.dst_addr = this->res->start + reg_off;
+ this->slave_conf.dst_maxburst = 16;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare data write desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ *buf_off += size;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/* read_cw: helper to prepare descriptors to read one codeword
+ *
+ * @data_size: data bytes to be fetched
+ * @oob_size: oob bytes to be fetched
+ */
+static int read_cw(struct qcom_nandc_data *this, int data_size, int oob_size)
+{
+ struct nandc_regs *regs = this->regs;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
+ write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
+ 1, false);
+
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 2, true);
+ read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1, false);
+
+ if (data_size)
+ read_data_dma(this, FLASH_BUF_ACC, &this->data_pos, data_size);
+
+ if (oob_size)
+ read_data_dma(this, FLASH_BUF_ACC + data_size, &this->oob_pos,
+ oob_size);
+
+ return 0;
+}
+
+/*
+ * write_cw: helper to prepare descriptors to write one codeword
+ *
+ * @data_size: data bytes to be written to NANDc internal buffer
+ * @oob_size: oob bytes to be written to NANDc internal buffer
+ */
+static int write_cw(struct qcom_nandc_data *this, int data_size, int oob_size)
+{
+ struct nandc_regs *regs = this->regs;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
+ write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
+ 1, false);
+
+ write_data_dma(this, FLASH_BUF_ACC, &this->data_pos, data_size);
+
+ /* oob */
+ if (oob_size)
+ write_data_dma(this, FLASH_BUF_ACC + data_size, &this->oob_pos,
+ oob_size);
+
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, ®s->clrflashstatus, 1, false);
+ write_reg_dma(this, NAND_READ_STATUS, ®s->clrreadstatus, 1, false);
+
+ return 0;
+}
+
+/*
+ * the following functions are used within chip->cmdfunc() to perform different
+ * NAND_CMD_* commands
+ */
+
+/* nandc_param: sets up descriptors for NAND_CMD_PARAM */
+static int nandc_param(struct qcom_nandc_data *this)
+{
+ int size;
+ struct nandc_regs *regs = this->regs;
+
+ /*
+ * NAND_CMD_PARAM is called before we know much about the FLASH chip
+ * in use. we configure the controller to perform a raw read of 512
+ * bytes to read onfi params
+ */
+ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ regs->addr0 = 0;
+ regs->addr1 = 0;
+ regs->cfg0 = 0 << CW_PER_PAGE
+ | 512 << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ regs->cfg1 = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | 0 << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+
+ /* configure CMD1 and VLD for ONFI param probing */
+ regs->vld = (this->vld & ~(1 << READ_START_VLD))
+ | 0 << READ_START_VLD;
+
+ regs->cmd1 = (this->cmd1 & ~(0xFF << READ_ADDR))
+ | NAND_CMD_PARAM << READ_ADDR;
+
+ regs->exec = 1;
+
+ regs->orig_cmd1 = this->cmd1;
+ regs->orig_vld = this->vld;
+
+ write_reg_dma(this, NAND_DEV_CMD_VLD, ®s->vld, 1, false);
+ write_reg_dma(this, NAND_DEV_CMD1, ®s->cmd1, 1, false);
+
+ size = this->buf_count = 512;
+
+ read_cw(this, size, 0);
+
+ /* restore CMD1 and VLD regs */
+ write_reg_dma(this, NAND_DEV_CMD1, ®s->orig_cmd1, 1, false);
+ write_reg_dma(this, NAND_DEV_CMD_VLD, ®s->orig_vld, 1, false);
+
+ return 0;
+}
+
+/*
+ * read_page: sets up descriptors for NAND_CMD_READ0/NAND_CMD_READOOB
+ * @oob_only: only read oob area to data_buffer, discard data
+ */
+static int read_page(struct qcom_nandc_data *this, bool oob_only)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ int i;
+
+ /* queue cmd descs for each codeword */
+ for (i = 0; i < cwperpage; i++) {
+ int data_size, oob_size;
+
+ if (i == (cwperpage - 1)) {
+ data_size = ecc->size - ((cwperpage - 1) << 2);
+ oob_size = (cwperpage << 2) + ecc->bytes;
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+ }
+
+ read_cw(this, oob_only ? 0 : data_size, oob_size);
+ }
+
+ return 0;
+}
+
+/*
+ * write_page: sets up descriptors for NAND_CMD_PAGEPROG. this function writes
+ * the complete page along with oob data. currently, we can't
+ * configure our controller to write only oob or only data
+ */
+static int write_page(struct qcom_nandc_data *this)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ int i;
+
+ /* queue cmd descs for each word */
+ for (i = 0; i < cwperpage; i++) {
+ int data_size, oob_size;
+
+ if (i == (cwperpage - 1)) {
+ data_size = ecc->size - ((cwperpage - 1) << 2);
+ oob_size = cwperpage << 2;
+
+ /*
+ * the last codewords contains both ecc and oob,
+ * configure dma descs for both of them
+ */
+ write_cw(this, data_size, oob_size);
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+
+ /*
+ * we skip writing oob for the first n - 1 codewords as
+ * they consist of just ecc, that's written by the
+ * controller by itself, we just move our marker
+ * accordingly
+ */
+ write_cw(this, data_size, 0);
+
+ this->oob_pos += oob_size;
+ }
+ }
+
+ return 0;
+}
+
+/* erase_block: sets up descriptors for NAND_CMD_ERASE1 */
+static int erase_block(struct qcom_nandc_data *this, int page_addr)
+{
+ struct nandc_regs *regs = this->regs;
+
+ regs->cmd = BLOCK_ERASE | PAGE_ACC | LAST_PAGE;
+ regs->addr0 = page_addr;
+ regs->addr1 = 0;
+ regs->cfg0 = this->cfg0_raw & ~(7 << CW_PER_PAGE);
+ regs->cfg1 = this->cfg1_raw;
+ regs->exec = 1;
+ regs->clrflashstatus = this->clrflashstatus;
+ regs->clrreadstatus = this->clrreadstatus;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
+ write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 2, false);
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, ®s->clrflashstatus, 1, false);
+ write_reg_dma(this, NAND_READ_STATUS, ®s->clrreadstatus, 1, false);
+
+ return 0;
+}
+
+/* read_id: sets up descriptors for NAND_CMD_READID */
+static int read_id(struct qcom_nandc_data *this, int column)
+{
+ struct nandc_regs *regs = this->regs;
+
+ if (column == -1)
+ return 0;
+
+ regs->cmd = FETCH_ID;
+ regs->addr0 = column;
+ regs->addr1 = 0;
+ regs->chip_sel = DM_EN;
+ regs->exec = 1;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 4, true);
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_READ_ID, 1, true);
+
+ return 0;
+}
+
+/* reset: sets up descriptors for NAND_CMD_RESET */
+static int reset(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ regs->cmd = RESET_DEVICE;
+ regs->exec = 1;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 1, true);
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
+
+ return 0;
+}
+
+static void dma_callback(void *param)
+{
+ struct qcom_nandc_data *this = (struct qcom_nandc_data *) param;
+ struct completion *c = &this->dma_done;
+
+ complete(c);
+}
+
+static int submit_descs(struct qcom_nandc_data *this)
+{
+ struct completion *c = &this->dma_done;
+ struct desc_info *desc;
+ int r;
+
+ init_completion(c);
+
+ list_for_each_entry(desc, &this->list, list) {
+ /*
+ * we add a callback the last descriptor in our list to notify
+ * completion of command
+ */
+ if (list_is_last(&desc->list, &this->list)) {
+ desc->dma_desc->callback = dma_callback;
+ desc->dma_desc->callback_param = this;
+ }
+
+ dmaengine_submit(desc->dma_desc);
+ }
+
+ dma_async_issue_pending(this->chan);
+
+ r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
+ if (!r)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void free_descs(struct qcom_nandc_data *this)
+{
+ struct desc_info *desc, *n;
+
+ list_for_each_entry_safe(desc, n, &this->list, list) {
+ list_del(&desc->list);
+ if (desc->mapped)
+ dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir);
+ kfree(desc);
+ }
+}
+
+static void pre_command(struct qcom_nandc_data *this, int command)
+{
+ struct mtd_info *mtd = &this->mtd;
+
+ this->buf_count = 0;
+ this->buf_start = 0;
+ this->data_pos = 0;
+ this->oob_pos = mtd->writesize;
+ this->reg_read_pos = 0;
+ this->use_ecc = false;
+ this->erased_page = false;
+ this->last_command = command;
+
+ if (command == NAND_CMD_READ0 ||
+ command == NAND_CMD_READOOB ||
+ command == NAND_CMD_SEQIN ||
+ command == NAND_CMD_PARAM) {
+
+ this->buf_count = mtd->writesize + mtd->oobsize;
+ memset(this->data_buffer, 0xff, this->buf_count);
+ memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(u32));
+ }
+}
+
+/*
+ * when using RS ECC, the NAND controller flags an error when reading an
+ * erased page. however, there are special characters at certain offsets when
+ * we read the erased page. we check here if the page is really empty. if so,
+ * we replace the magic characters with 0xffs
+ */
+static void empty_page_fixup(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ int i;
+
+ /* if BCH is enabled, HW will take care of detecting erased pages */
+ if (this->bch_enabled || !this->use_ecc)
+ return;
+
+ for (i = 0; i < cwperpage; i++) {
+ u8 *empty1, *empty2;
+ u32 flash_status = this->reg_read_buf[3 * i];
+
+ /*
+ * an erased page flags an error in NAND_FLASH_STATUS, check if
+ * the page is erased by looking for 0x54s at offsets 3 and 175
+ * from the beginning of each codeword
+ */
+ if (flash_status & FS_OP_ERR) {
+ empty1 = &this->data_buffer[3 + i * this->cw_data];
+ empty2 = &this->data_buffer[175 + i * this->cw_data];
+
+ /*
+ * the error wasn't because of an erased page, bail out
+ * and let someone else do the error checking
+ */
+ if (!((*empty1 == 0x54 && *empty2 == 0xff) ||
+ (*empty1 == 0xff && *empty2 == 0x54)))
+ return;
+ }
+ }
+
+ for (i = 0; i < mtd->writesize && (this->data_buffer[i] == 0xff ||
+ (i % this->cw_data == 3 || i % this->cw_data == 175)); i++) {
+ }
+
+ if (i < mtd->writesize)
+ return;
+
+ /*
+ * the whole page is 0xffs besides the magic offsets, we replace the
+ * 0x54s with 0xffs
+ */
+ for (i = 0; i < cwperpage; i++) {
+ this->data_buffer[3 + i * this->cw_data] = 0xff;
+ this->data_buffer[175 + i * this->cw_data] = 0xff;
+ }
+
+ /*
+ * raise the erased page flag so that parse_read_errors() doesn't think
+ * it's an error
+ */
+ this->erased_page = true;
+}
+
+/*
+ * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
+ * privately maintained status byte, this status byte can be read after
+ * NAND_CMD_STATUS is called
+ */
+static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int num_cw;
+ int i;
+
+ num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
+
+ for (i = 0; i < num_cw; i++) {
+ u32 flash_status;
+
+ flash_status = this->reg_read_buf[i];
+
+ if (flash_status & FS_MPU_ERR)
+ this->status &= ~NAND_STATUS_WP;
+
+ if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
+ (flash_status & FS_DEVICE_STS_ERR)))
+ this->status |= NAND_STATUS_FAIL;
+ }
+}
+
+static void post_command(struct qcom_nandc_data *this, int command)
+{
+ switch (command) {
+ case NAND_CMD_READID:
+ memcpy(this->data_buffer, this->reg_read_buf, this->buf_count);
+ break;
+ case NAND_CMD_READ0:
+ case NAND_CMD_READ1:
+ empty_page_fixup(this);
+ break;
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_ERASE1:
+ parse_erase_write_errors(this, command);
+ break;
+ default:
+ break;
+ }
+}
+
+static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct qcom_nandc_data *this = chip->priv;
+ bool wait = true;
+ int r = 0;
+
+ pre_command(this, command);
+
+ switch (command) {
+ case NAND_CMD_RESET:
+ r = reset(this);
+ break;
+
+ case NAND_CMD_READID:
+ this->buf_count = 4;
+ r = read_id(this, column);
+ break;
+
+ case NAND_CMD_READ0:
+ case NAND_CMD_READOOB:
+ this->buf_start = column;
+ this->use_ecc = true;
+
+ if (command == NAND_CMD_READOOB)
+ this->buf_start += mtd->writesize;
+
+ /*
+ * for now, the controller always reads complete page data, we
+ * configure DMA to read data + oob or only oob from the
+ * controller's buffer into data_buffer
+ */
+ set_address(this, 0, page_addr);
+ update_rw_regs(this, ecc->steps, true);
+
+ r = read_page(this, command == NAND_CMD_READOOB);
+ break;
+
+ case NAND_CMD_PARAM:
+ r = nandc_param(this);
+ break;
+
+ case NAND_CMD_SEQIN:
+ this->buf_start = column;
+ this->page = page_addr;
+ set_address(this, 0, page_addr);
+ wait = false;
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ this->use_ecc = true;
+ update_rw_regs(this, ecc->steps, false);
+ r = write_page(this);
+ break;
+
+ case NAND_CMD_ERASE1:
+ r = erase_block(this, page_addr);
+ break;
+
+ case NAND_CMD_STATUS:
+ wait = false;
+ break;
+
+ case NAND_CMD_NONE:
+ default:
+ wait = false;
+ break;
+ }
+
+ if (r) {
+ dev_err(this->dev, "failure executing command %d\n",
+ command);
+ free_descs(this);
+ return;
+ }
+
+ if (wait) {
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev,
+ "failure submitting descs for command %d\n",
+ command);
+ }
+
+ free_descs(this);
+
+ post_command(this, command);
+}
+
+/*
+ * the bad block marker is readable only when we read the page with ECC
+ * disabled. all the read/write commands like NAND_CMD_READOOB, NAND_CMD_READ0
+ * and NAND_CMD_PAGEPROG are executed in the driver with ECC enabled. therefore,
+ * the default nand helper functions to detect a bad block or mark a bad block
+ * can't be used.
+ */
+static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+ int page, r, mark, bad = 0;
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ struct qcom_nandc_data *this = chip->priv;
+ u32 flash_status;
+
+ pre_command(this, NAND_CMD_NONE);
+
+ page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+
+ /*
+ * configure registers for a raw page read, the address is set to the
+ * beginning of the last codeword
+ */
+ this->use_ecc = false;
+ set_address(this, this->cw_size * (cwperpage - 1), page);
+
+ /* we just read one codeword that contains the bad block marker */
+ update_rw_regs(this, 1, true);
+
+ read_cw(this, this->cw_size, 0);
+
+ r = submit_descs(this);
+ if (r) {
+ dev_err(this->dev, "error submitting descs\n");
+ goto err;
+ }
+
+ flash_status = this->reg_read_buf[0];
+
+ /*
+ * unable to read the marker successfully, is that sufficient to report
+ * the block as bad?
+ */
+ if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
+ dev_warn(this->dev, "error while reading bad block mark\n");
+ goto err;
+ }
+
+ mark = mtd->writesize - (this->cw_size * (cwperpage - 1));
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ bad = this->data_buffer[mark] != 0xff ||
+ this->data_buffer[mark + 1] != 0xff;
+
+ bad = this->data_buffer[mark] != 0xff;
+err:
+ free_descs(this);
+
+ return bad;
+}
+
+static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ int page, r;
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ struct qcom_nandc_data *this = chip->priv;
+ u32 flash_status;
+
+ pre_command(this, NAND_CMD_NONE);
+
+ /* fill our internal buffer's oob area with 0's */
+ memset(this->data_buffer, 0x00, mtd->writesize + mtd->oobsize);
+
+ page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+
+ this->use_ecc = false;
+ set_address(this, this->cw_size * (cwperpage - 1), page);
+
+ /* we just write to one codeword that contains the bad block marker*/
+ update_rw_regs(this, 1, false);
+
+ /*
+ * overwrite the last codeword with 0s, this will result in setting
+ * the bad block marker to 0 too
+ */
+ write_cw(this, this->cw_size, 0);
+
+ r = submit_descs(this);
+ if (r) {
+ dev_err(this->dev, "error submitting descs\n");
+ r = -EIO;
+ goto err;
+ }
+
+ flash_status = this->reg_read_buf[0];
+
+ if (flash_status & (FS_OP_ERR | FS_MPU_ERR))
+ r = -EIO;
+
+err:
+ free_descs(this);
+
+ return r;
+}
+
+static int parse_read_errors(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ unsigned int max_bitflips = 0;
+ int i;
+
+ for (i = 0; i < cwperpage; i++) {
+ int stat;
+ u32 flash_status = this->reg_read_buf[3 * i];
+ u32 buffer_status = this->reg_read_buf[3 * i + 1];
+ u32 erased_cw_status = this->reg_read_buf[3 * i + 2];
+
+ if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
+
+ /* ignore erased codeword errors */
+ if (this->bch_enabled) {
+ if ((erased_cw_status & ERASED_CW) == ERASED_CW)
+ continue;
+ } else if (this->erased_page == true) {
+ continue;
+ }
+
+ if (buffer_status & BS_UNCORRECTABLE_BIT) {
+ mtd->ecc_stats.failed++;
+ continue;
+ }
+ }
+
+ stat = buffer_status & BS_CORRECTABLE_ERR_MSK;
+ mtd->ecc_stats.corrected += stat;
+
+ max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ }
+
+ return max_bitflips;
+}
+
+static int qcom_nandc_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+
+ chip->read_buf(mtd, buf, mtd->writesize);
+ if (oob_required)
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ return parse_read_errors(this);
+}
+
+/*
+ * the NAND controller cannot write only data or only oob within a codeword.
+ * this is because the controller can't be configured on the fly between
+ * codewords to change the amount of data that needs to be written to the
+ * nand chip. this results in a write performance drop. this can be
+ * optimized if we perform the extra read-copy-write operation only on the
+ * codeword that has spare data
+ */
+static int qcom_nandc_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf,
+ int oob_required)
+{
+ struct qcom_nandc_data *this = chip->priv;
+
+ /* it's all okay when we intend to write both data and oob */
+ if (oob_required) {
+ chip->write_buf(mtd, buf, mtd->writesize);
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+ return 0;
+ }
+
+ /*
+ * the controller will write oob even when we don't want to write to it.
+ * we read the original OOB, copy it to our buffer and do a full page
+ * write so that the OOB doesn't change
+ */
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, this->page);
+
+ this->buf_start = 0;
+
+ chip->write_buf(mtd, buf, mtd->writesize);
+
+ return 0;
+}
+
+static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ int status = 0;
+
+ /* read complete data + oob */
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+ /*
+ * override the read oob with the new oob content in oob_poi, perform
+ * a full page write
+ */
+ memcpy(this->data_buffer + mtd->writesize, chip->oob_poi,
+ mtd->oobsize);
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ uint8_t *buf = (uint8_t *) this->data_buffer;
+ uint8_t ret = 0x0;
+
+ if (this->last_command == NAND_CMD_STATUS) {
+ ret = this->status;
+
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+
+ return ret;
+ }
+
+ if (this->buf_start < this->buf_count)
+ ret = buf[this->buf_start++];
+
+ return ret;
+}
+
+/*
+ * TODO: We always copy DMA to our internal buffer. Try to use the buffer passed
+ * mtd first. Fallback to data_buffer only if the upper layer buffer can't be
+ * used
+ */
+static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(buf, this->data_buffer + this->buf_start, real_len);
+ this->buf_start += real_len;
+}
+
+static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(this->data_buffer + this->buf_start, buf, real_len);
+
+ this->buf_start += real_len;
+}
+
+/* we support only one external chip for now */
+static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+
+ if (chipnr <= 0)
+ return;
+
+ dev_warn(this->dev, "invalid chip select\n");
+}
+
+/*
+ * NAND controller page layout info
+ *
+ * |-----------------------| |---------------------------------|
+ * | xx.......xx| | *********xx.......xx|
+ * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
+ * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
+ * | xx.......xx| | *********xx.......xx|
+ * |-----------------------| |---------------------------------|
+ * codeword 1,2..n-1 codeword n
+ * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
+ *
+ * n = number of codewords in the page
+ * . = ECC bytes
+ * * = spare bytes
+ * x = unused/reserved bytes
+ *
+ * 2K page: n = 4, spare = 16 bytes
+ * 4K page: n = 8, spare = 32 bytes
+ * 8K page: n = 16, spare = 64 bytes
+ *
+ * the qcom nand controller operates at a sub page/codeword level. each
+ * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
+ * the number of ECC bytes vary based on the ECC strength and the bus width.
+ *
+ * the first n - 1 codewords contains 516 bytes of user data, the remaining
+ * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
+ * both user data and spare(oobavail) bytes that sum up to 516 bytes.
+ *
+ * the layout described above is used by the controller when the ECC block is
+ * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
+ * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
+ * layouts defined below doesn't consider the positions occupied by the reserved
+ * bytes
+ *
+ * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
+ * in the last codeword is the position of bad block marker. the bad block
+ * marker cannot be accessed when ECC is enabled.
+ *
+ */
+
+/* 2K page, 4 bit ECC */
+static struct nand_ecclayout layout_oob_64 = {
+ .eccbytes = 40,
+ .eccpos = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
+ },
+
+ .oobfree = {
+ { 30, 16 },
+ },
+};
+
+/* 4K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_128 = {
+ .eccbytes = 80,
+ .eccpos = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
+ 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
+ },
+ .oobfree = {
+ { 70, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 8 bit bus width */
+static struct nand_ecclayout layout_oob_224_x8 = {
+ .eccpos = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+ 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
+ 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
+ 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90,
+ 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
+ },
+ .oobfree = {
+ { 91, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 16 bit bus width */
+static struct nand_ecclayout layout_oob_224_x16 = {
+ .eccbytes = 112,
+ .eccpos = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
+ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
+ 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
+ 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
+ 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,
+ },
+ .oobfree = {
+ { 98, 32 },
+ },
+};
+
+/* 8K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_256 = {
+ .eccbytes = 160,
+ .eccpos = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
+ 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
+ 90, 91, 92, 93, 94, 96, 97, 98, 99, 100,
+ 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,
+ 111, 112, 113, 114, 115, 116, 117, 118, 119, 120,
+ 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,
+ 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,
+ 141, 142, 143, 144, 145, 146, 147, 148, 149, 150,
+ 215, 216, 217, 218, 219, 220, 221, 222, 223, 224,
+ },
+ .oobfree = {
+ { 151, 64 },
+ },
+};
+
+/*
+ * this is called before scan_ident, we do some minimal configurations so
+ * that reading ID and ONFI params work
+ */
+static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
+{
+ /* kill onenand */
+ nandc_write(this, SFLASHC_BURST_CFG, 0);
+
+ /* enable ADM DMA */
+ nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
+
+ /* save the original values of these registers */
+ this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
+ this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
+
+ /* initial status value */
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+}
+
+static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage;
+ bool wide_bus;
+
+ /* the nand controller fetches codewords/chunks of 512 bytes */
+ cwperpage = mtd->writesize >> 9;
+
+ /* strength is the net strength of the complete page */
+ ecc->strength = this->ecc_strength * cwperpage;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 32) {
+ /* 8 bit ECC defaults to BCH ECC on all platforms */
+ ecc->bytes = wide_bus ? 14 : 13;
+ } else {
+ /*
+ * if the controller supports BCH for 4 bit ECC, the controller
+ * uses lesser bytes for ECC. If RS is used, the ECC bytes is
+ * always 10 bytes
+ */
+ if (this->ecc_modes & ECC_BCH_4BIT)
+ ecc->bytes = wide_bus ? 8 : 7;
+ else
+ ecc->bytes = 10;
+ }
+
+ /* each step consists of 512 bytes of data */
+ ecc->size = NANDC_STEP_SIZE;
+
+ ecc->read_page = qcom_nandc_read_page_hwecc;
+ ecc->write_page = qcom_nandc_write_page_hwecc;
+ ecc->write_oob = qcom_nandc_write_oob;
+
+ switch (mtd->oobsize) {
+ case 64:
+ ecc->layout = &layout_oob_64;
+ break;
+ case 128:
+ ecc->layout = &layout_oob_128;
+ break;
+ case 224:
+ if (wide_bus)
+ ecc->layout = &layout_oob_224_x16;
+ else
+ ecc->layout = &layout_oob_224_x8;
+ break;
+ case 256:
+ ecc->layout = &layout_oob_256;
+ break;
+ default:
+ dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
+ mtd->oobsize);
+ return -ENODEV;
+ }
+
+ ecc->mode = NAND_ECC_HW;
+
+ /* enable ecc by default */
+ this->use_ecc = true;
+
+ /* free old buffer, allocate one with page data + oob size */
+ dma_free_coherent(this->dev, this->buf_size, this->data_buffer,
+ this->data_buffer_paddr);
+
+ this->buf_size = mtd->writesize + mtd->oobsize;
+
+ this->data_buffer = dma_alloc_coherent(this->dev, this->buf_size,
+ &this->data_buffer_paddr, GFP_KERNEL);
+ if (!this->data_buffer)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ int spare_bytes, bad_block_byte;
+ bool wide_bus;
+ int ecc_mode = 0;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 32) {
+ this->cw_size = 532;
+
+ spare_bytes = wide_bus ? 0 : 2;
+
+ this->bch_enabled = true;
+ ecc_mode = 1;
+ } else {
+ this->cw_size = 528;
+
+ if (this->ecc_modes & ECC_BCH_4BIT) {
+ spare_bytes = wide_bus ? 2 : 4;
+
+ this->bch_enabled = true;
+ ecc_mode = 0;
+ } else {
+ spare_bytes = wide_bus ? 0 : 1;
+ }
+ }
+
+ /*
+ * DATA_UD_BYTES varies based on whether the read/write command protects
+ * spare data with ECC too. We protect spare data by default, so we set
+ * it to main + spare data, which are 512 and 4 bytes respectively.
+ */
+ this->cw_data = 516;
+
+ bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
+
+ this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_data << UD_SIZE_BYTES
+ | 0 << DISABLE_STATUS_AFTER_WRITE
+ | 5 << NUM_ADDR_CYCLES
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
+ | 0 << STATUS_BFR_READ
+ | 1 << SET_RD_MODE_AFTER_STATUS
+ | spare_bytes << SPARE_SIZE_BYTES;
+
+ this->cfg1 = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | bad_block_byte << BAD_BLOCK_BYTE_NUM
+ | 0 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | this->bch_enabled << ENABLE_BCH_ECC;
+
+ this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_size << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
+ | 0 << ECC_SW_RESET
+ | this->cw_data << ECC_NUM_DATA_BYTES
+ | 1 << ECC_FORCE_CLK_OPEN
+ | ecc_mode << ECC_MODE
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
+
+ this->ecc_buf_cfg = 0x203 << NUM_STEPS;
+
+ this->clrflashstatus = FS_READY_BSY_N;
+ this->clrreadstatus = 0xc0;
+
+ dev_dbg(this->dev, "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x "
+ "cw_size %d cw_data %d strength %d parity_bytes %d "
+ "steps %d\n", this->cfg0, this->cfg1, this->ecc_buf_cfg,
+ this->ecc_bch_cfg, this->cw_size, this->cw_data,
+ ecc->strength, ecc->bytes, cwperpage);
+}
+
+static int qcom_nandc_alloc(struct qcom_nandc_data *this)
+{
+ int r;
+
+ r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
+ if (r) {
+ dev_err(this->dev, "failed to set DMA mask\n");
+ return r;
+ }
+
+ /*
+ * we don't know the page size of the NAND chip yet, set the buffer size
+ * to 512 bytes for now, that's sufficient for reading ID or ONFI params
+ */
+ this->buf_size = SZ_512;
+
+ this->data_buffer = dma_alloc_coherent(this->dev, this->buf_size,
+ &this->data_buffer_paddr, GFP_KERNEL);
+ if (!this->data_buffer)
+ return -ENOMEM;
+
+ this->regs = devm_kzalloc(this->dev, sizeof(struct nandc_regs),
+ GFP_KERNEL);
+ if (!this->regs)
+ return -ENOMEM;
+
+ this->reg_read_buf = devm_kzalloc(this->dev, MAX_REG_RD * sizeof(u32),
+ GFP_KERNEL);
+ if (!this->reg_read_buf)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&this->list);
+
+ this->chan = dma_request_slave_channel(this->dev, "rxtx");
+ if (!this->chan) {
+ dev_err(this->dev, "failed to request slave channel\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
+{
+ dma_free_coherent(this->dev, this->buf_size, this->data_buffer,
+ this->data_buffer_paddr);
+
+ dma_release_channel(this->chan);
+}
+
+static int qcom_nandc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct mtd_part_parser_data ppdata = {};
+ int r;
+
+ mtd->priv = chip;
+ mtd->name = "qcom-nandc";
+ mtd->owner = THIS_MODULE;
+
+ chip->priv = this;
+
+ chip->cmdfunc = qcom_nandc_command;
+ chip->select_chip = qcom_nandc_select_chip;
+ chip->read_byte = qcom_nandc_read_byte;
+ chip->read_buf = qcom_nandc_read_buf;
+ chip->write_buf = qcom_nandc_write_buf;
+ chip->block_bad = qcom_nandc_block_bad;
+ chip->block_markbad = qcom_nandc_block_markbad;
+
+ /* TODO: both can be supported, need to implement them */
+ chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN;
+
+ if (this->bus_width == 16)
+ chip->options |= NAND_BUSWIDTH_16;
+
+ qcom_nandc_pre_init(this);
+
+ r = nand_scan_ident(mtd, 1, NULL);
+ if (r)
+ return r;
+
+ r = qcom_nandc_ecc_init(this);
+ if (r)
+ return r;
+
+ r = nand_scan_tail(mtd);
+ if (r)
+ return r;
+
+ qcom_nandc_hw_post_init(this);
+
+ ppdata.of_node = this->dev->of_node;
+ r = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+ if (r)
+ return r;
+
+ return 0;
+}
+
+static int qcom_nandc_parse_dt(struct platform_device *pdev)
+{
+ struct device_node *np;
+ struct qcom_nandc_data *this;
+ int r;
+
+ np = pdev->dev.of_node;
+ if (!np)
+ return -ENODEV;
+
+ this = platform_get_drvdata(pdev);
+ if (!this)
+ return -ENODEV;
+
+ this->ecc_strength = of_get_nand_ecc_strength(np);
+ if (this->ecc_strength < 0) {
+ dev_warn(this->dev,
+ "incorrect ecc strength, setting to 4 bits/step\n");
+ this->ecc_strength = 4;
+ }
+
+ this->bus_width = of_get_nand_bus_width(np);
+ if (this->bus_width < 0) {
+ dev_warn(this->dev, "incorrect bus width, setting to 8\n");
+ this->bus_width = 8;
+ }
+
+ r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
+ if (r) {
+ dev_err(this->dev, "command CRCI unspecified\n");
+ return r;
+ }
+
+ r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
+ if (r) {
+ dev_err(this->dev, "data CRCI unspecified\n");
+ return r;
+ }
+
+ return 0;
+}
+
+#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
+
+static const struct of_device_id qcom_nandc_of_match[] = {
+ { .compatible = "qcom,ebi2-nandc",
+ .data = (void *) EBI2_NANDC_ECC_MODES,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
+
+static int qcom_nandc_probe(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this;
+ const struct of_device_id *match;
+ int r;
+
+ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
+ if (!this)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, this);
+
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+
+ match = of_match_node(qcom_nandc_of_match, pdev->dev.of_node);
+ if (!match) {
+ dev_err(&pdev->dev, "unsupported NANDc module\n");
+ return -ENODEV;
+ }
+
+ /* match->data will hold a struct pointer once we support more IPs */
+ this->ecc_modes = (u32) match->data;
+
+ this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ this->base = devm_ioremap_resource(&pdev->dev, this->res);
+ if (IS_ERR(this->base))
+ return PTR_ERR(this->base);
+
+ this->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(this->core_clk))
+ return PTR_ERR(this->core_clk);
+
+ this->aon_clk = devm_clk_get(&pdev->dev, "aon");
+ if (IS_ERR(this->aon_clk))
+ return PTR_ERR(this->aon_clk);
+
+ r = qcom_nandc_parse_dt(pdev);
+ if (r)
+ return r;
+
+ r = qcom_nandc_alloc(this);
+ if (r)
+ return r;
+
+ r = clk_prepare_enable(this->core_clk);
+ if (r)
+ goto err_core_clk;
+
+ r = clk_prepare_enable(this->aon_clk);
+ if (r)
+ goto err_aon_clk;
+
+ r = qcom_nandc_init(this);
+ if (r)
+ goto err_init;
+
+ return 0;
+
+err_init:
+ clk_disable_unprepare(this->aon_clk);
+err_aon_clk:
+ clk_disable_unprepare(this->core_clk);
+err_core_clk:
+ qcom_nandc_unalloc(this);
+
+ return r;
+}
+
+static int qcom_nandc_remove(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this;
+
+ this = platform_get_drvdata(pdev);
+ if (!this)
+ return -ENODEV;
+
+ qcom_nandc_unalloc(this);
+
+ clk_disable_unprepare(this->aon_clk);
+ clk_disable_unprepare(this->core_clk);
+
+ return 0;
+}
+
+static struct platform_driver qcom_nandc_driver = {
+ .driver = {
+ .name = "qcom-nandc",
+ .of_match_table = qcom_nandc_of_match,
+ },
+ .probe = qcom_nandc_probe,
+ .remove = qcom_nandc_remove,
+};
+module_platform_driver(qcom_nandc_driver);
+
+MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
+MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
+MODULE_LICENSE("GPL");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 3/5] Documentaion: dt: add DT bindings for Qualcomm NAND controller
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-01-16 14:48 ` [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x Archit Taneja
2015-01-16 14:48 ` [PATCH 2/5] mtd: nand: Add qcom nand controller driver Archit Taneja
@ 2015-01-16 14:48 ` Archit Taneja
2015-01-16 14:48 ` [PATCH 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
` (4 subsequent siblings)
7 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-01-16 14:48 UTC (permalink / raw)
To: linux-mtd, linux-arm-msm
Cc: linux-kernel, agross, galak, Archit Taneja, devicetree
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
new file mode 100644
index 0000000..e24c77a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -0,0 +1,48 @@
+* Qualcomm NAND controller
+
+Required properties:
+- compatible: should be "qcom,ebi2-nand" for IPQ806x
+- reg: MMIO address range
+- clocks: must contain core clock and always on clock
+- clock-names: must contain "core" for the core clock and "aon" for the
+ always on clock
+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
+ controller node and the channel number to be used for
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
+- dma-names: must be "rxtx"
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+- qcom,data-crci: must contain the ADM data type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+
+Optional properties:
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
+ as default
+
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
+ bits. If not present, 4 is chosen as default
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand@0x1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ partition@0 {
+ ...
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 4/5] arm: qcom: dts: Add NAND controller node for ipq806x
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (2 preceding siblings ...)
2015-01-16 14:48 ` [PATCH 3/5] Documentaion: dt: add DT bindings for Qualcomm NAND controller Archit Taneja
@ 2015-01-16 14:48 ` Archit Taneja
2015-01-16 14:48 ` [PATCH 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 pplatform Archit Taneja
` (3 subsequent siblings)
7 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-01-16 14:48 UTC (permalink / raw)
To: linux-mtd, linux-arm-msm
Cc: linux-kernel, agross, galak, Archit Taneja, devicetree
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 733b0f3..6ed0150 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -281,7 +281,7 @@
#reset-cells = <1>;
};
- dma@18300000 {
+ adm_dma: dma@18300000 {
compatible = "qcom,adm";
reg = <0x18300000 0x100000>;
interrupts = <0 170 0>;
@@ -300,5 +300,22 @@
status = "disabled";
};
+
+ nand@0x1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ status = "disabled";
+ };
+
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 pplatform
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (3 preceding siblings ...)
2015-01-16 14:48 ` [PATCH 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
@ 2015-01-16 14:48 ` Archit Taneja
2015-02-18 6:03 ` [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (2 subsequent siblings)
7 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-01-16 14:48 UTC (permalink / raw)
To: linux-mtd, linux-arm-msm
Cc: linux-kernel, agross, galak, Archit Taneja, devicetree
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 1e1d0d8..82878bb 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,28 @@
bias-none;
};
};
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
gsbi@16300000 {
@@ -93,5 +115,15 @@
dma@18300000 {
status = "ok";
};
+
+ nand@0x1ac00000 {
+ status = "ok";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x
2015-01-16 14:48 ` [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x Archit Taneja
@ 2015-01-16 21:56 ` Stephen Boyd
2015-01-19 10:32 ` Archit Taneja
2015-01-29 22:21 ` Stephen Boyd
1 sibling, 1 reply; 71+ messages in thread
From: Stephen Boyd @ 2015-01-16 21:56 UTC (permalink / raw)
To: Archit Taneja, linux-mtd, linux-arm-msm; +Cc: linux-kernel, agross, galak
On 01/16/2015 06:48 AM, Archit Taneja wrote:
> The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks.
> Create structs for these clocks so that they can be used by the NAND controller
> driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
Looks ok. I couldn't find this used in the downstream sources though.
Can you point me to it? I'm mostly worried that this is a shared
resource that never should be turned off, so exposing it to drivers may
not be the right idea.
> +static struct clk_branch ebi2_aon_clk = {
> + .hwcg_reg = 0x3b00,
> + .hwcg_bit = 6,
> + .halt_reg = 0x2fcc,
> + .halt_bit = 0,
> + .clkr = {
> + .enable_reg = 0x3b00,
> + .enable_mask = BIT(8),
> + .hw.init = &(struct clk_init_data){
> + .name = "ebi2_always_on_clk",
>
Can this be ebi2_aon_clk to match the macro?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x
2015-01-16 21:56 ` Stephen Boyd
@ 2015-01-19 10:32 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-01-19 10:32 UTC (permalink / raw)
To: Stephen Boyd, linux-mtd, linux-arm-msm; +Cc: galak, linux-kernel, agross
Hi,
On 01/17/2015 03:26 AM, Stephen Boyd wrote:
> On 01/16/2015 06:48 AM, Archit Taneja wrote:
>> The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks.
>> Create structs for these clocks so that they can be used by the NAND controller
>> driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
>>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>
> Looks ok. I couldn't find this used in the downstream sources though.
> Can you point me to it? I'm mostly worried that this is a shared
> resource that never should be turned off, so exposing it to drivers may
> not be the right idea.
I'll share the sources.
>
>> +static struct clk_branch ebi2_aon_clk = {
>> + .hwcg_reg = 0x3b00,
>> + .hwcg_bit = 6,
>> + .halt_reg = 0x2fcc,
>> + .halt_bit = 0,
>> + .clkr = {
>> + .enable_reg = 0x3b00,
>> + .enable_mask = BIT(8),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "ebi2_always_on_clk",
>>
>
> Can this be ebi2_aon_clk to match the macro?
>
I'll fix this.
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/5] mtd: nand: Add qcom nand controller driver
2015-01-16 14:48 ` [PATCH 2/5] mtd: nand: Add qcom nand controller driver Archit Taneja
@ 2015-01-21 0:54 ` Daniel Ehrenberg
2015-01-22 6:36 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Daniel Ehrenberg @ 2015-01-21 0:54 UTC (permalink / raw)
To: Archit Taneja; +Cc: linux-mtd, linux-arm-msm, linux-kernel, agross, galak
On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja <architt@codeaurora.org> wrote:
> +/*
> + * the bad block marker is readable only when we read the page with ECC
> + * disabled. all the read/write commands like NAND_CMD_READOOB, NAND_CMD_READ0
> + * and NAND_CMD_PAGEPROG are executed in the driver with ECC enabled. therefore,
> + * the default nand helper functions to detect a bad block or mark a bad block
> + * can't be used.
> + */
> +static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
> +{
> + int page, r, mark, bad = 0;
> + struct nand_chip *chip = mtd->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + struct qcom_nandc_data *this = chip->priv;
> + u32 flash_status;
> +
> + pre_command(this, NAND_CMD_NONE);
> +
> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
> +
> + /*
> + * configure registers for a raw page read, the address is set to the
> + * beginning of the last codeword
> + */
> + this->use_ecc = false;
> + set_address(this, this->cw_size * (cwperpage - 1), page);
> +
> + /* we just read one codeword that contains the bad block marker */
> + update_rw_regs(this, 1, true);
> +
> + read_cw(this, this->cw_size, 0);
> +
> + r = submit_descs(this);
> + if (r) {
> + dev_err(this->dev, "error submitting descs\n");
> + goto err;
> + }
> +
> + flash_status = this->reg_read_buf[0];
> +
> + /*
> + * unable to read the marker successfully, is that sufficient to report
> + * the block as bad?
> + */
> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
> + dev_warn(this->dev, "error while reading bad block mark\n");
> + goto err;
> + }
> +
> + mark = mtd->writesize - (this->cw_size * (cwperpage - 1));
> +
> + if (chip->options & NAND_BUSWIDTH_16)
> + bad = this->data_buffer[mark] != 0xff ||
> + this->data_buffer[mark + 1] != 0xff;
> +
> + bad = this->data_buffer[mark] != 0xff;
> +err:
> + free_descs(this);
> +
> + return bad;
> +}
> +
> +static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
> +{
> + int page, r;
> + struct nand_chip *chip = mtd->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + struct qcom_nandc_data *this = chip->priv;
> + u32 flash_status;
> +
> + pre_command(this, NAND_CMD_NONE);
> +
> + /* fill our internal buffer's oob area with 0's */
> + memset(this->data_buffer, 0x00, mtd->writesize + mtd->oobsize);
> +
> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
> +
> + this->use_ecc = false;
> + set_address(this, this->cw_size * (cwperpage - 1), page);
> +
> + /* we just write to one codeword that contains the bad block marker*/
> + update_rw_regs(this, 1, false);
> +
> + /*
> + * overwrite the last codeword with 0s, this will result in setting
> + * the bad block marker to 0 too
> + */
> + write_cw(this, this->cw_size, 0);
> +
> + r = submit_descs(this);
> + if (r) {
> + dev_err(this->dev, "error submitting descs\n");
> + r = -EIO;
> + goto err;
> + }
> +
> + flash_status = this->reg_read_buf[0];
> +
> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR))
> + r = -EIO;
> +
> +err:
> + free_descs(this);
> +
> + return r;
> +}
Looks like this code marks block bad and reads bad block information
based on information in the OOB area. And in qcom_nandc_init,
NAND_SKIP_BBTSCAN is set, meaning that this is the code used in
practice on the chip in the mtd_block_isbad path. Can this driver be
used with an on-flash OOB table by editing the init function's chip
flags, or would it need more significant changes to allow that?
Thanks,
Dan
On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja <architt@codeaurora.org> wrote:
> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15
> series.
>
> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) and
> QPIC (Qualcomm Parallel Interface Controller). These IPs provide a broader
> interface for external slow peripheral devices such as LCD and NAND/NOR flash
> memory or SRAM like interfaces.
>
> We add support for the NAND controller found within EBI2. For the SoCs of our
> interest, we only use the NAND controller within EBI2. Therefore, it's safe for
> us to assume that the NAND controller is a standalone block within the SoC.
>
> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND flash
> devices. It contains a HW ECC block that supports BCH ECC (4, 8 and 16 bit
> correction/step) and RS ECC(4 bit correction/step) that covers main and spare
> data. The controller contains an internal 512 byte page buffer to which we
> read/write via DMA. The EBI2 type NAND controller uses ADM DMA for register
> read/write and data transfers. The controller performs page reads and writes at
> a codeword/step level of 512 bytes. It can support up to 2 external chips of
> different configurations.
>
> The driver prepares register read and write configuraton descriptors for each
> codeword, followed by data descriptors to read or write data from the
> controller's internal buffer. It uses a single ADM DMA channel that we get via
> dmaengine API. The controller requires 2 ADM CRCIs for command and data flow
> control. These are passed via DT.
>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
> drivers/mtd/nand/Kconfig | 7 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qcom_nandc.c | 1995 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 2003 insertions(+)
> create mode 100644 drivers/mtd/nand/qcom_nandc.c
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 7d0150d..03ad13d 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -524,4 +524,11 @@ config MTD_NAND_SUNXI
> help
> Enables support for NAND Flash chips on Allwinner SoCs.
>
> +config MTD_NAND_QCOM
> + tristate "Support for NAND on QCOM SoCs"
> + depends on ARCH_QCOM && QCOM_ADM
> + help
> + Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> + controller. This controller is found on IPQ806x SoC.
> +
> endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index bd38f21..bdf82a9 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -51,5 +51,6 @@ obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
> obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
> obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
> obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
> +obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>
> nand-objs := nand_base.o nand_bbt.o nand_timings.o
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> new file mode 100644
> index 0000000..18b4280
> --- /dev/null
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -0,0 +1,1995 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/interrupt.h>
> +#include <linux/bitops.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> +#include <linux/module.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_mtd.h>
> +#include <linux/delay.h>
> +
> +/* NANDc reg offsets */
> +#define NAND_FLASH_CMD 0x00
> +#define NAND_ADDR0 0x04
> +#define NAND_ADDR1 0x08
> +#define NAND_FLASH_CHIP_SELECT 0x0c
> +#define NAND_EXEC_CMD 0x10
> +#define NAND_FLASH_STATUS 0x14
> +#define NAND_BUFFER_STATUS 0x18
> +#define NAND_DEV0_CFG0 0x20
> +#define NAND_DEV0_CFG1 0x24
> +#define NAND_DEV0_ECC_CFG 0x28
> +#define NAND_DEV1_ECC_CFG 0x2c
> +#define NAND_DEV1_CFG0 0x30
> +#define NAND_DEV1_CFG1 0x34
> +#define NAND_READ_ID 0x40
> +#define NAND_READ_STATUS 0x44
> +#define NAND_DEV_CMD0 0xa0
> +#define NAND_DEV_CMD1 0xa4
> +#define NAND_DEV_CMD2 0xa8
> +#define NAND_DEV_CMD_VLD 0xac
> +#define SFLASHC_BURST_CFG 0xe0
> +#define NAND_ERASED_CW_DETECT_CFG 0xe8
> +#define NAND_ERASED_CW_DETECT_STATUS 0xec
> +#define NAND_EBI2_ECC_BUF_CFG 0xf0
> +#define FLASH_BUF_ACC 0x100
> +
> +#define NAND_CTRL 0xf00
> +#define NAND_VERSION 0xf08
> +#define NAND_READ_LOCATION_0 0xf20
> +#define NAND_READ_LOCATION_1 0xf24
> +
> +/* NAND_FLASH_CMD bits */
> +#define PAGE_ACC BIT(4)
> +#define LAST_PAGE BIT(5)
> +
> +/* NAND_FLASH_CHIP_SELECT bits */
> +#define NAND_DEV_SEL 0
> +#define DM_EN BIT(2)
> +
> +/* NAND_FLASH_STATUS bits */
> +#define FS_OP_ERR BIT(4)
> +#define FS_READY_BSY_N BIT(5)
> +#define FS_MPU_ERR BIT(8)
> +#define FS_DEVICE_STS_ERR BIT(16)
> +#define FS_DEVICE_WP BIT(23)
> +
> +/* NAND_BUFFER_STATUS bits */
> +#define BS_UNCORRECTABLE_BIT BIT(8)
> +#define BS_CORRECTABLE_ERR_MSK 0x1f
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DISABLE_STATUS_AFTER_WRITE 4
> +#define CW_PER_PAGE 6
> +#define UD_SIZE_BYTES 9
> +#define ECC_PARITY_SIZE_BYTES_RS 19
> +#define SPARE_SIZE_BYTES 23
> +#define NUM_ADDR_CYCLES 27
> +#define STATUS_BFR_READ 30
> +#define SET_RD_MODE_AFTER_STATUS 31
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DEV0_CFG1_ECC_DISABLE 0
> +#define WIDE_FLASH 1
> +#define NAND_RECOVERY_CYCLES 2
> +#define CS_ACTIVE_BSY 5
> +#define BAD_BLOCK_BYTE_NUM 6
> +#define BAD_BLOCK_IN_SPARE_AREA 16
> +#define WR_RD_BSY_GAP 17
> +#define ENABLE_BCH_ECC 27
> +
> +/* NAND_DEV0_ECC_CFG bits */
> +#define ECC_CFG_ECC_DISABLE 0
> +#define ECC_SW_RESET 1
> +#define ECC_MODE 4
> +#define ECC_PARITY_SIZE_BYTES_BCH 8
> +#define ECC_NUM_DATA_BYTES 16
> +#define ECC_FORCE_CLK_OPEN 30
> +
> +/* NAND_DEV_CMD1 bits */
> +#define READ_ADDR 0
> +
> +/* NAND_DEV_CMD_VLD bits */
> +#define READ_START_VLD 0
> +
> +/* NAND_EBI2_ECC_BUF_CFG bits */
> +#define NUM_STEPS 0
> +
> +/* NAND_ERASED_CW_DETECT_CFG bits */
> +#define ERASED_CW_ECC_MASK 1
> +#define AUTO_DETECT_RES 0
> +#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
> +#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
> +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
> +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
> +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
> +
> +/* NAND_ERASED_CW_DETECT_STATUS bits */
> +#define PAGE_ALL_ERASED BIT(7)
> +#define CODEWORD_ALL_ERASED BIT(6)
> +#define PAGE_ERASED BIT(5)
> +#define CODEWORD_ERASED BIT(4)
> +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
> +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
> +
> +/* Version Mask */
> +#define NAND_VERSION_MAJOR_MASK 0xf0000000
> +#define NAND_VERSION_MAJOR_SHIFT 28
> +#define NAND_VERSION_MINOR_MASK 0x0fff0000
> +#define NAND_VERSION_MINOR_SHIFT 16
> +
> +/* NAND OP_CMDs */
> +#define PAGE_READ 0x2
> +#define PAGE_READ_WITH_ECC 0x3
> +#define PAGE_READ_WITH_ECC_SPARE 0x4
> +#define PROGRAM_PAGE 0x6
> +#define PAGE_PROGRAM_WITH_ECC 0x7
> +#define PROGRAM_PAGE_SPARE 0x9
> +#define BLOCK_ERASE 0xa
> +#define FETCH_ID 0xb
> +#define RESET_DEVICE 0xd
> +
> +/*
> + * the NAND controller performs reads/writes with ECC in 512 byte chunks.
> + * the driver calls the chunks 'step' or 'codeword' interchangeably
> + */
> +#define NANDC_STEP_SIZE 512
> +
> +/*
> + * the largest page size we support is 8K, this will have 16 steps/codewords
> + * of 512 bytes each
> + */
> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
> +
> +/* we read at most 3 registers per codeword scan */
> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
> +
> +/* ECC modes */
> +#define ECC_NONE BIT(0)
> +#define ECC_RS_4BIT BIT(1)
> +#define ECC_BCH_4BIT BIT(2)
> +#define ECC_BCH_8BIT BIT(3)
> +
> +struct desc_info {
> + struct list_head list;
> +
> + enum dma_transfer_direction dir;
> + struct scatterlist sgl;
> + struct dma_async_tx_descriptor *dma_desc;
> +
> + bool mapped;
> +};
> +
> +/*
> + * holds the current register values that we want to write. acts as a contiguous
> + * chunk of memory which we use to write the controller registers through DMA.
> + */
> +struct nandc_regs {
> + u32 cmd;
> + u32 addr0;
> + u32 addr1;
> + u32 chip_sel;
> + u32 exec;
> +
> + u32 cfg0;
> + u32 cfg1;
> + u32 ecc_bch_cfg;
> +
> + u32 clrflashstatus;
> + u32 clrreadstatus;
> +
> + u32 cmd1;
> + u32 vld;
> +
> + u32 orig_cmd1;
> + u32 orig_vld;
> +
> + u32 ecc_buf_cfg;
> +};
> +
> +/*
> + * @data_buffer: DMA buffer for page read/writes
> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
> + * @data_pos/oob_pos: DMA address offset markers for data/oob within
> + * the data_buffer
> + * @reg_read_buf: buffer for reading register data via DMA
> + * @reg_read_pos: marker for data read in reg_read_buf
> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
> + * ecc/non-ecc mode for the current nand flash
> + * device
> + * @regs: a contiguous chunk of memory for DMA register
> + * writes
> + * @list: DMA descriptor list
> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
> + * @cmd_crci: ADM DMA CRCI for command flow control
> + * @data_crci: ADM DMA CRCI for data flow control
> + * @ecc_modes: supported ECC modes by the current controller,
> + * initialized via DT match data
> + * @cw_size: the number of bytes in a single step/codeword
> + * of a page, consisting of all data, ecc, spare
> + * and reserved bytes
> + * @cw_data: the number of bytes within a codeword protected
> + * by ECC
> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
> + * @page: current page in use by the controller
> + * @erased_page: tracker to tell if last page was erased or not
> + * @status: value to be returned if NAND_CMD_STATUS command
> + * is executed
> + * @dma_done: completion param to denote end of last
> + * descriptor in the list
> + */
> +struct qcom_nandc_data {
> + struct platform_device *pdev;
> + struct device *dev;
> +
> + void __iomem *base;
> + struct resource *res;
> +
> + struct clk *core_clk;
> + struct clk *aon_clk;
> +
> + struct dma_chan *chan;
> + struct dma_slave_config slave_conf;
> +
> + struct nand_chip chip;
> + struct mtd_info mtd;
> +
> + u8 *data_buffer;
> + dma_addr_t data_buffer_paddr;
> + int buf_size;
> + int buf_count;
> + int buf_start;
> + int data_pos;
> + int oob_pos;
> +
> + u32 *reg_read_buf;
> + dma_addr_t reg_read_paddr;
> + int reg_read_pos;
> +
> + u32 cfg0, cfg1;
> + u32 cfg0_raw, cfg1_raw;
> + u32 ecc_buf_cfg;
> + u32 ecc_bch_cfg;
> + u32 clrflashstatus;
> + u32 clrreadstatus;
> + u32 sflashc_burst_cfg;
> + u32 cmd1, vld;
> +
> + struct nandc_regs *regs;
> +
> + struct list_head list;
> +
> + int ecc_strength;
> + int bus_width;
> + unsigned int cmd_crci;
> + unsigned int data_crci;
> +
> + u32 ecc_modes;
> +
> + int cw_size;
> + int cw_data;
> + bool use_ecc;
> + bool bch_enabled;
> + int page;
> + bool erased_page;
> + u8 status;
> + int last_command;
> + struct completion dma_done;
> +};
> +
> +static inline unsigned int nandc_read(struct qcom_nandc_data *this, int offset)
> +{
> + return ioread32(this->base + offset);
> +}
> +
> +static inline void nandc_write(struct qcom_nandc_data *this, int offset,
> + unsigned int val)
> +{
> + iowrite32(val, this->base + offset);
> +}
> +
> +static void set_address(struct qcom_nandc_data *this, u16 column, int page)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nandc_regs *regs = this->regs;
> +
> + if (chip->options & NAND_BUSWIDTH_16)
> + column >>= 1;
> +
> + regs->addr0 = page << 16 | column;
> + regs->addr1 = page >> 16 & 0xff;
> +}
> +
> +static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + if (this->use_ecc) {
> + if (read)
> + regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
> + else
> + regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
> +
> + regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
> + (num_cw - 1) << CW_PER_PAGE;
> +
> + regs->cfg1 = this->cfg1;
> + regs->ecc_bch_cfg = this->ecc_bch_cfg;
> + } else {
> + if (read)
> + regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
> + else
> + regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
> +
> + regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
> + (num_cw - 1) << CW_PER_PAGE;
> +
> + regs->cfg1 = this->cfg1_raw;
> + regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
> + }
> +
> + regs->ecc_buf_cfg = this->ecc_buf_cfg;
> + regs->clrflashstatus = this->clrflashstatus;
> + regs->clrreadstatus = this->clrreadstatus;
> + regs->exec = 1;
> +}
> +
> +/*
> + * write_reg_dma: prepares a descriptor to write a given number of
> + * contiguous registers
> + *
> + * @first: offset of the first register in the contiguous block
> + * @reg: starting address containing the reg values to write
> + * @num_regs: number of registers to write
> + * @flow_control: flow control enabled/disabled
> + */
> +static int write_reg_dma(struct qcom_nandc_data *this, int first,
> + u32 *reg, int num_regs, bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + int size;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + sgl = &desc->sgl;
> +
> + size = num_regs * sizeof(u32);
> +
> + sg_init_one(sgl, reg, size);
> +
> + desc->dir = DMA_MEM_TO_DEV;
> +
> + dma_map_sg(this->dev, sgl, 1, desc->dir);
> +
> + this->slave_conf.device_fc = flow_control ? 1 : 0;
> + this->slave_conf.dst_addr = this->res->start + first;
> + this->slave_conf.dst_maxburst = 16;
> + this->slave_conf.slave_id = this->cmd_crci;
> +
> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare register write desc\n");
> + r = PTR_ERR(dma_desc);
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + desc->mapped = true;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
> +/*
> + * read_reg_dma: prepares a descriptor to read a given number of
> + * contiguous registers to the reg_read_buf pointer
> + *
> + * @first: offset of the first register in the contiguous block
> + * @num_regs: number of registers to read
> + * @flow_control: flow control enabled/disabled
> + */
> +static int read_reg_dma(struct qcom_nandc_data *this, int first,
> + int num_regs, bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + int size;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + sgl = &desc->sgl;
> +
> + size = num_regs * sizeof(u32);
> +
> + sg_init_one(sgl, this->reg_read_buf + this->reg_read_pos, size);
> +
> + desc->dir = DMA_DEV_TO_MEM;
> +
> + dma_map_sg(this->dev, sgl, 1, desc->dir);
> +
> + this->slave_conf.device_fc = flow_control ? 1 : 0;
> + this->slave_conf.src_addr = this->res->start + first;
> + this->slave_conf.src_maxburst = 16;
> + this->slave_conf.slave_id = this->data_crci;
> +
> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare register read desc\n");
> + r = PTR_ERR(dma_desc);
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + desc->mapped = true;
> +
> + this->reg_read_pos += num_regs;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
> +/*
> + * read_data_dma: prepares a DMA descriptor to transfer data from the
> + * controller's internal buffer to data_buffer
> + *
> + * @reg_off: offset within the controller's data buffer
> + * @buf_off: offset in data_buffer where we want to write the data
> + * read from the controller
> + * @size: DMA transaction size in bytes
> + */
> +static int read_data_dma(struct qcom_nandc_data *this, int reg_off,
> + int *buf_off, int size)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + void *vaddr;
> + dma_addr_t address;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + sgl = &desc->sgl;
> +
> + vaddr = this->data_buffer + *buf_off;
> + address = this->data_buffer_paddr + *buf_off;
> +
> + sg_init_one(sgl, vaddr, size);
> + sgl->dma_address = address;
> +
> + desc->dir = DMA_DEV_TO_MEM;
> +
> + this->slave_conf.device_fc = 0;
> + this->slave_conf.src_addr = this->res->start + reg_off;
> + this->slave_conf.src_maxburst = 16;
> +
> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare data read desc\n");
> + r = PTR_ERR(dma_desc);
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + *buf_off += size;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
> +/*
> + * write_data_dma: prepares a DMA descriptor to transfer data from
> + * data_buffer to the controller's internal buffer
> + *
> + * @reg_off: offset within the controller's data buffer
> + * @buf_off: offset in data_buffer where we want to read the data to
> + * be written to the controller
> + * @size: DMA transaction size in bytes
> + */
> +static int write_data_dma(struct qcom_nandc_data *this, int reg_off,
> + int *buf_off, int size)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + void *vaddr;
> + dma_addr_t address;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + sgl = &desc->sgl;
> +
> + vaddr = this->data_buffer + *buf_off;
> + address = this->data_buffer_paddr + *buf_off;
> +
> + sg_init_one(sgl, vaddr, size);
> + sgl->dma_address = address;
> +
> + desc->dir = DMA_MEM_TO_DEV;
> +
> + this->slave_conf.device_fc = 0;
> + this->slave_conf.dst_addr = this->res->start + reg_off;
> + this->slave_conf.dst_maxburst = 16;
> +
> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare data write desc\n");
> + r = PTR_ERR(dma_desc);
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + *buf_off += size;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
> +/* read_cw: helper to prepare descriptors to read one codeword
> + *
> + * @data_size: data bytes to be fetched
> + * @oob_size: oob bytes to be fetched
> + */
> +static int read_cw(struct qcom_nandc_data *this, int data_size, int oob_size)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
> + write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
> + 1, false);
> +
> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 2, true);
> + read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1, false);
> +
> + if (data_size)
> + read_data_dma(this, FLASH_BUF_ACC, &this->data_pos, data_size);
> +
> + if (oob_size)
> + read_data_dma(this, FLASH_BUF_ACC + data_size, &this->oob_pos,
> + oob_size);
> +
> + return 0;
> +}
> +
> +/*
> + * write_cw: helper to prepare descriptors to write one codeword
> + *
> + * @data_size: data bytes to be written to NANDc internal buffer
> + * @oob_size: oob bytes to be written to NANDc internal buffer
> + */
> +static int write_cw(struct qcom_nandc_data *this, int data_size, int oob_size)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
> + write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
> + 1, false);
> +
> + write_data_dma(this, FLASH_BUF_ACC, &this->data_pos, data_size);
> +
> + /* oob */
> + if (oob_size)
> + write_data_dma(this, FLASH_BUF_ACC + data_size, &this->oob_pos,
> + oob_size);
> +
> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
> +
> + write_reg_dma(this, NAND_FLASH_STATUS, ®s->clrflashstatus, 1, false);
> + write_reg_dma(this, NAND_READ_STATUS, ®s->clrreadstatus, 1, false);
> +
> + return 0;
> +}
> +
> +/*
> + * the following functions are used within chip->cmdfunc() to perform different
> + * NAND_CMD_* commands
> + */
> +
> +/* nandc_param: sets up descriptors for NAND_CMD_PARAM */
> +static int nandc_param(struct qcom_nandc_data *this)
> +{
> + int size;
> + struct nandc_regs *regs = this->regs;
> +
> + /*
> + * NAND_CMD_PARAM is called before we know much about the FLASH chip
> + * in use. we configure the controller to perform a raw read of 512
> + * bytes to read onfi params
> + */
> + regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
> + regs->addr0 = 0;
> + regs->addr1 = 0;
> + regs->cfg0 = 0 << CW_PER_PAGE
> + | 512 << UD_SIZE_BYTES
> + | 5 << NUM_ADDR_CYCLES
> + | 0 << SPARE_SIZE_BYTES;
> +
> + regs->cfg1 = 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | 17 << BAD_BLOCK_BYTE_NUM
> + | 1 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | 0 << WIDE_FLASH
> + | 1 << DEV0_CFG1_ECC_DISABLE;
> +
> + regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
> +
> + /* configure CMD1 and VLD for ONFI param probing */
> + regs->vld = (this->vld & ~(1 << READ_START_VLD))
> + | 0 << READ_START_VLD;
> +
> + regs->cmd1 = (this->cmd1 & ~(0xFF << READ_ADDR))
> + | NAND_CMD_PARAM << READ_ADDR;
> +
> + regs->exec = 1;
> +
> + regs->orig_cmd1 = this->cmd1;
> + regs->orig_vld = this->vld;
> +
> + write_reg_dma(this, NAND_DEV_CMD_VLD, ®s->vld, 1, false);
> + write_reg_dma(this, NAND_DEV_CMD1, ®s->cmd1, 1, false);
> +
> + size = this->buf_count = 512;
> +
> + read_cw(this, size, 0);
> +
> + /* restore CMD1 and VLD regs */
> + write_reg_dma(this, NAND_DEV_CMD1, ®s->orig_cmd1, 1, false);
> + write_reg_dma(this, NAND_DEV_CMD_VLD, ®s->orig_vld, 1, false);
> +
> + return 0;
> +}
> +
> +/*
> + * read_page: sets up descriptors for NAND_CMD_READ0/NAND_CMD_READOOB
> + * @oob_only: only read oob area to data_buffer, discard data
> + */
> +static int read_page(struct qcom_nandc_data *this, bool oob_only)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + int i;
> +
> + /* queue cmd descs for each codeword */
> + for (i = 0; i < cwperpage; i++) {
> + int data_size, oob_size;
> +
> + if (i == (cwperpage - 1)) {
> + data_size = ecc->size - ((cwperpage - 1) << 2);
> + oob_size = (cwperpage << 2) + ecc->bytes;
> + } else {
> + data_size = this->cw_data;
> + oob_size = ecc->bytes;
> + }
> +
> + read_cw(this, oob_only ? 0 : data_size, oob_size);
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * write_page: sets up descriptors for NAND_CMD_PAGEPROG. this function writes
> + * the complete page along with oob data. currently, we can't
> + * configure our controller to write only oob or only data
> + */
> +static int write_page(struct qcom_nandc_data *this)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + int i;
> +
> + /* queue cmd descs for each word */
> + for (i = 0; i < cwperpage; i++) {
> + int data_size, oob_size;
> +
> + if (i == (cwperpage - 1)) {
> + data_size = ecc->size - ((cwperpage - 1) << 2);
> + oob_size = cwperpage << 2;
> +
> + /*
> + * the last codewords contains both ecc and oob,
> + * configure dma descs for both of them
> + */
> + write_cw(this, data_size, oob_size);
> + } else {
> + data_size = this->cw_data;
> + oob_size = ecc->bytes;
> +
> + /*
> + * we skip writing oob for the first n - 1 codewords as
> + * they consist of just ecc, that's written by the
> + * controller by itself, we just move our marker
> + * accordingly
> + */
> + write_cw(this, data_size, 0);
> +
> + this->oob_pos += oob_size;
> + }
> + }
> +
> + return 0;
> +}
> +
> +/* erase_block: sets up descriptors for NAND_CMD_ERASE1 */
> +static int erase_block(struct qcom_nandc_data *this, int page_addr)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + regs->cmd = BLOCK_ERASE | PAGE_ACC | LAST_PAGE;
> + regs->addr0 = page_addr;
> + regs->addr1 = 0;
> + regs->cfg0 = this->cfg0_raw & ~(7 << CW_PER_PAGE);
> + regs->cfg1 = this->cfg1_raw;
> + regs->exec = 1;
> + regs->clrflashstatus = this->clrflashstatus;
> + regs->clrreadstatus = this->clrreadstatus;
> +
> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
> + write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 2, false);
> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
> +
> + write_reg_dma(this, NAND_FLASH_STATUS, ®s->clrflashstatus, 1, false);
> + write_reg_dma(this, NAND_READ_STATUS, ®s->clrreadstatus, 1, false);
> +
> + return 0;
> +}
> +
> +/* read_id: sets up descriptors for NAND_CMD_READID */
> +static int read_id(struct qcom_nandc_data *this, int column)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + if (column == -1)
> + return 0;
> +
> + regs->cmd = FETCH_ID;
> + regs->addr0 = column;
> + regs->addr1 = 0;
> + regs->chip_sel = DM_EN;
> + regs->exec = 1;
> +
> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 4, true);
> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
> +
> + read_reg_dma(this, NAND_READ_ID, 1, true);
> +
> + return 0;
> +}
> +
> +/* reset: sets up descriptors for NAND_CMD_RESET */
> +static int reset(struct qcom_nandc_data *this)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + regs->cmd = RESET_DEVICE;
> + regs->exec = 1;
> +
> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 1, true);
> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
> +
> + return 0;
> +}
> +
> +static void dma_callback(void *param)
> +{
> + struct qcom_nandc_data *this = (struct qcom_nandc_data *) param;
> + struct completion *c = &this->dma_done;
> +
> + complete(c);
> +}
> +
> +static int submit_descs(struct qcom_nandc_data *this)
> +{
> + struct completion *c = &this->dma_done;
> + struct desc_info *desc;
> + int r;
> +
> + init_completion(c);
> +
> + list_for_each_entry(desc, &this->list, list) {
> + /*
> + * we add a callback the last descriptor in our list to notify
> + * completion of command
> + */
> + if (list_is_last(&desc->list, &this->list)) {
> + desc->dma_desc->callback = dma_callback;
> + desc->dma_desc->callback_param = this;
> + }
> +
> + dmaengine_submit(desc->dma_desc);
> + }
> +
> + dma_async_issue_pending(this->chan);
> +
> + r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
> + if (!r)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static void free_descs(struct qcom_nandc_data *this)
> +{
> + struct desc_info *desc, *n;
> +
> + list_for_each_entry_safe(desc, n, &this->list, list) {
> + list_del(&desc->list);
> + if (desc->mapped)
> + dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir);
> + kfree(desc);
> + }
> +}
> +
> +static void pre_command(struct qcom_nandc_data *this, int command)
> +{
> + struct mtd_info *mtd = &this->mtd;
> +
> + this->buf_count = 0;
> + this->buf_start = 0;
> + this->data_pos = 0;
> + this->oob_pos = mtd->writesize;
> + this->reg_read_pos = 0;
> + this->use_ecc = false;
> + this->erased_page = false;
> + this->last_command = command;
> +
> + if (command == NAND_CMD_READ0 ||
> + command == NAND_CMD_READOOB ||
> + command == NAND_CMD_SEQIN ||
> + command == NAND_CMD_PARAM) {
> +
> + this->buf_count = mtd->writesize + mtd->oobsize;
> + memset(this->data_buffer, 0xff, this->buf_count);
> + memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(u32));
> + }
> +}
> +
> +/*
> + * when using RS ECC, the NAND controller flags an error when reading an
> + * erased page. however, there are special characters at certain offsets when
> + * we read the erased page. we check here if the page is really empty. if so,
> + * we replace the magic characters with 0xffs
> + */
> +static void empty_page_fixup(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + int i;
> +
> + /* if BCH is enabled, HW will take care of detecting erased pages */
> + if (this->bch_enabled || !this->use_ecc)
> + return;
> +
> + for (i = 0; i < cwperpage; i++) {
> + u8 *empty1, *empty2;
> + u32 flash_status = this->reg_read_buf[3 * i];
> +
> + /*
> + * an erased page flags an error in NAND_FLASH_STATUS, check if
> + * the page is erased by looking for 0x54s at offsets 3 and 175
> + * from the beginning of each codeword
> + */
> + if (flash_status & FS_OP_ERR) {
> + empty1 = &this->data_buffer[3 + i * this->cw_data];
> + empty2 = &this->data_buffer[175 + i * this->cw_data];
> +
> + /*
> + * the error wasn't because of an erased page, bail out
> + * and let someone else do the error checking
> + */
> + if (!((*empty1 == 0x54 && *empty2 == 0xff) ||
> + (*empty1 == 0xff && *empty2 == 0x54)))
> + return;
> + }
> + }
> +
> + for (i = 0; i < mtd->writesize && (this->data_buffer[i] == 0xff ||
> + (i % this->cw_data == 3 || i % this->cw_data == 175)); i++) {
> + }
> +
> + if (i < mtd->writesize)
> + return;
> +
> + /*
> + * the whole page is 0xffs besides the magic offsets, we replace the
> + * 0x54s with 0xffs
> + */
> + for (i = 0; i < cwperpage; i++) {
> + this->data_buffer[3 + i * this->cw_data] = 0xff;
> + this->data_buffer[175 + i * this->cw_data] = 0xff;
> + }
> +
> + /*
> + * raise the erased page flag so that parse_read_errors() doesn't think
> + * it's an error
> + */
> + this->erased_page = true;
> +}
> +
> +/*
> + * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
> + * privately maintained status byte, this status byte can be read after
> + * NAND_CMD_STATUS is called
> + */
> +static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int num_cw;
> + int i;
> +
> + num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
> +
> + for (i = 0; i < num_cw; i++) {
> + u32 flash_status;
> +
> + flash_status = this->reg_read_buf[i];
> +
> + if (flash_status & FS_MPU_ERR)
> + this->status &= ~NAND_STATUS_WP;
> +
> + if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
> + (flash_status & FS_DEVICE_STS_ERR)))
> + this->status |= NAND_STATUS_FAIL;
> + }
> +}
> +
> +static void post_command(struct qcom_nandc_data *this, int command)
> +{
> + switch (command) {
> + case NAND_CMD_READID:
> + memcpy(this->data_buffer, this->reg_read_buf, this->buf_count);
> + break;
> + case NAND_CMD_READ0:
> + case NAND_CMD_READ1:
> + empty_page_fixup(this);
> + break;
> + case NAND_CMD_PAGEPROG:
> + case NAND_CMD_ERASE1:
> + parse_erase_write_errors(this, command);
> + break;
> + default:
> + break;
> + }
> +}
> +
> +static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
> + int column, int page_addr)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + struct qcom_nandc_data *this = chip->priv;
> + bool wait = true;
> + int r = 0;
> +
> + pre_command(this, command);
> +
> + switch (command) {
> + case NAND_CMD_RESET:
> + r = reset(this);
> + break;
> +
> + case NAND_CMD_READID:
> + this->buf_count = 4;
> + r = read_id(this, column);
> + break;
> +
> + case NAND_CMD_READ0:
> + case NAND_CMD_READOOB:
> + this->buf_start = column;
> + this->use_ecc = true;
> +
> + if (command == NAND_CMD_READOOB)
> + this->buf_start += mtd->writesize;
> +
> + /*
> + * for now, the controller always reads complete page data, we
> + * configure DMA to read data + oob or only oob from the
> + * controller's buffer into data_buffer
> + */
> + set_address(this, 0, page_addr);
> + update_rw_regs(this, ecc->steps, true);
> +
> + r = read_page(this, command == NAND_CMD_READOOB);
> + break;
> +
> + case NAND_CMD_PARAM:
> + r = nandc_param(this);
> + break;
> +
> + case NAND_CMD_SEQIN:
> + this->buf_start = column;
> + this->page = page_addr;
> + set_address(this, 0, page_addr);
> + wait = false;
> + break;
> +
> + case NAND_CMD_PAGEPROG:
> + this->use_ecc = true;
> + update_rw_regs(this, ecc->steps, false);
> + r = write_page(this);
> + break;
> +
> + case NAND_CMD_ERASE1:
> + r = erase_block(this, page_addr);
> + break;
> +
> + case NAND_CMD_STATUS:
> + wait = false;
> + break;
> +
> + case NAND_CMD_NONE:
> + default:
> + wait = false;
> + break;
> + }
> +
> + if (r) {
> + dev_err(this->dev, "failure executing command %d\n",
> + command);
> + free_descs(this);
> + return;
> + }
> +
> + if (wait) {
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev,
> + "failure submitting descs for command %d\n",
> + command);
> + }
> +
> + free_descs(this);
> +
> + post_command(this, command);
> +}
> +
> +/*
> + * the bad block marker is readable only when we read the page with ECC
> + * disabled. all the read/write commands like NAND_CMD_READOOB, NAND_CMD_READ0
> + * and NAND_CMD_PAGEPROG are executed in the driver with ECC enabled. therefore,
> + * the default nand helper functions to detect a bad block or mark a bad block
> + * can't be used.
> + */
> +static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
> +{
> + int page, r, mark, bad = 0;
> + struct nand_chip *chip = mtd->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + struct qcom_nandc_data *this = chip->priv;
> + u32 flash_status;
> +
> + pre_command(this, NAND_CMD_NONE);
> +
> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
> +
> + /*
> + * configure registers for a raw page read, the address is set to the
> + * beginning of the last codeword
> + */
> + this->use_ecc = false;
> + set_address(this, this->cw_size * (cwperpage - 1), page);
> +
> + /* we just read one codeword that contains the bad block marker */
> + update_rw_regs(this, 1, true);
> +
> + read_cw(this, this->cw_size, 0);
> +
> + r = submit_descs(this);
> + if (r) {
> + dev_err(this->dev, "error submitting descs\n");
> + goto err;
> + }
> +
> + flash_status = this->reg_read_buf[0];
> +
> + /*
> + * unable to read the marker successfully, is that sufficient to report
> + * the block as bad?
> + */
> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
> + dev_warn(this->dev, "error while reading bad block mark\n");
> + goto err;
> + }
> +
> + mark = mtd->writesize - (this->cw_size * (cwperpage - 1));
> +
> + if (chip->options & NAND_BUSWIDTH_16)
> + bad = this->data_buffer[mark] != 0xff ||
> + this->data_buffer[mark + 1] != 0xff;
> +
> + bad = this->data_buffer[mark] != 0xff;
> +err:
> + free_descs(this);
> +
> + return bad;
> +}
> +
> +static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
> +{
> + int page, r;
> + struct nand_chip *chip = mtd->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + struct qcom_nandc_data *this = chip->priv;
> + u32 flash_status;
> +
> + pre_command(this, NAND_CMD_NONE);
> +
> + /* fill our internal buffer's oob area with 0's */
> + memset(this->data_buffer, 0x00, mtd->writesize + mtd->oobsize);
> +
> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
> +
> + this->use_ecc = false;
> + set_address(this, this->cw_size * (cwperpage - 1), page);
> +
> + /* we just write to one codeword that contains the bad block marker*/
> + update_rw_regs(this, 1, false);
> +
> + /*
> + * overwrite the last codeword with 0s, this will result in setting
> + * the bad block marker to 0 too
> + */
> + write_cw(this, this->cw_size, 0);
> +
> + r = submit_descs(this);
> + if (r) {
> + dev_err(this->dev, "error submitting descs\n");
> + r = -EIO;
> + goto err;
> + }
> +
> + flash_status = this->reg_read_buf[0];
> +
> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR))
> + r = -EIO;
> +
> +err:
> + free_descs(this);
> +
> + return r;
> +}
> +
> +static int parse_read_errors(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + unsigned int max_bitflips = 0;
> + int i;
> +
> + for (i = 0; i < cwperpage; i++) {
> + int stat;
> + u32 flash_status = this->reg_read_buf[3 * i];
> + u32 buffer_status = this->reg_read_buf[3 * i + 1];
> + u32 erased_cw_status = this->reg_read_buf[3 * i + 2];
> +
> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
> +
> + /* ignore erased codeword errors */
> + if (this->bch_enabled) {
> + if ((erased_cw_status & ERASED_CW) == ERASED_CW)
> + continue;
> + } else if (this->erased_page == true) {
> + continue;
> + }
> +
> + if (buffer_status & BS_UNCORRECTABLE_BIT) {
> + mtd->ecc_stats.failed++;
> + continue;
> + }
> + }
> +
> + stat = buffer_status & BS_CORRECTABLE_ERR_MSK;
> + mtd->ecc_stats.corrected += stat;
> +
> + max_bitflips = max_t(unsigned int, max_bitflips, stat);
> + }
> +
> + return max_bitflips;
> +}
> +
> +static int qcom_nandc_read_page_hwecc(struct mtd_info *mtd,
> + struct nand_chip *chip, uint8_t *buf, int oob_required,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> +
> + chip->read_buf(mtd, buf, mtd->writesize);
> + if (oob_required)
> + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
> +
> + return parse_read_errors(this);
> +}
> +
> +/*
> + * the NAND controller cannot write only data or only oob within a codeword.
> + * this is because the controller can't be configured on the fly between
> + * codewords to change the amount of data that needs to be written to the
> + * nand chip. this results in a write performance drop. this can be
> + * optimized if we perform the extra read-copy-write operation only on the
> + * codeword that has spare data
> + */
> +static int qcom_nandc_write_page_hwecc(struct mtd_info *mtd,
> + struct nand_chip *chip, const uint8_t *buf,
> + int oob_required)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> +
> + /* it's all okay when we intend to write both data and oob */
> + if (oob_required) {
> + chip->write_buf(mtd, buf, mtd->writesize);
> + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
> + return 0;
> + }
> +
> + /*
> + * the controller will write oob even when we don't want to write to it.
> + * we read the original OOB, copy it to our buffer and do a full page
> + * write so that the OOB doesn't change
> + */
> + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, this->page);
> +
> + this->buf_start = 0;
> +
> + chip->write_buf(mtd, buf, mtd->writesize);
> +
> + return 0;
> +}
> +
> +static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + int status = 0;
> +
> + /* read complete data + oob */
> + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
> +
> + /*
> + * override the read oob with the new oob content in oob_poi, perform
> + * a full page write
> + */
> + memcpy(this->data_buffer + mtd->writesize, chip->oob_poi,
> + mtd->oobsize);
> +
> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +
> + status = chip->waitfunc(mtd, chip);
> +
> + return status & NAND_STATUS_FAIL ? -EIO : 0;
> +}
> +
> +static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> + uint8_t *buf = (uint8_t *) this->data_buffer;
> + uint8_t ret = 0x0;
> +
> + if (this->last_command == NAND_CMD_STATUS) {
> + ret = this->status;
> +
> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> +
> + return ret;
> + }
> +
> + if (this->buf_start < this->buf_count)
> + ret = buf[this->buf_start++];
> +
> + return ret;
> +}
> +
> +/*
> + * TODO: We always copy DMA to our internal buffer. Try to use the buffer passed
> + * mtd first. Fallback to data_buffer only if the upper layer buffer can't be
> + * used
> + */
> +static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
> +
> + memcpy(buf, this->data_buffer + this->buf_start, real_len);
> + this->buf_start += real_len;
> +}
> +
> +static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
> + int len)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
> +
> + memcpy(this->data_buffer + this->buf_start, buf, real_len);
> +
> + this->buf_start += real_len;
> +}
> +
> +/* we support only one external chip for now */
> +static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> +
> + if (chipnr <= 0)
> + return;
> +
> + dev_warn(this->dev, "invalid chip select\n");
> +}
> +
> +/*
> + * NAND controller page layout info
> + *
> + * |-----------------------| |---------------------------------|
> + * | xx.......xx| | *********xx.......xx|
> + * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
> + * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
> + * | xx.......xx| | *********xx.......xx|
> + * |-----------------------| |---------------------------------|
> + * codeword 1,2..n-1 codeword n
> + * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
> + *
> + * n = number of codewords in the page
> + * . = ECC bytes
> + * * = spare bytes
> + * x = unused/reserved bytes
> + *
> + * 2K page: n = 4, spare = 16 bytes
> + * 4K page: n = 8, spare = 32 bytes
> + * 8K page: n = 16, spare = 64 bytes
> + *
> + * the qcom nand controller operates at a sub page/codeword level. each
> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
> + * the number of ECC bytes vary based on the ECC strength and the bus width.
> + *
> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
> + *
> + * the layout described above is used by the controller when the ECC block is
> + * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
> + * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
> + * layouts defined below doesn't consider the positions occupied by the reserved
> + * bytes
> + *
> + * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
> + * in the last codeword is the position of bad block marker. the bad block
> + * marker cannot be accessed when ECC is enabled.
> + *
> + */
> +
> +/* 2K page, 4 bit ECC */
> +static struct nand_ecclayout layout_oob_64 = {
> + .eccbytes = 40,
> + .eccpos = {
> + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
> + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
> + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
> + 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
> + },
> +
> + .oobfree = {
> + { 30, 16 },
> + },
> +};
> +
> +/* 4K page, 4 bit ECC, 8/16 bit bus width */
> +static struct nand_ecclayout layout_oob_128 = {
> + .eccbytes = 80,
> + .eccpos = {
> + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
> + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
> + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
> + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
> + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
> + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
> + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
> + 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
> + },
> + .oobfree = {
> + { 70, 32 },
> + },
> +};
> +
> +/* 4K page, 8 bit ECC, 8 bit bus width */
> +static struct nand_ecclayout layout_oob_224_x8 = {
> + .eccpos = {
> + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
> + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
> + 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
> + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
> + 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
> + 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
> + 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90,
> + 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
> + },
> + .oobfree = {
> + { 91, 32 },
> + },
> +};
> +
> +/* 4K page, 8 bit ECC, 16 bit bus width */
> +static struct nand_ecclayout layout_oob_224_x16 = {
> + .eccbytes = 112,
> + .eccpos = {
> + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> + 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
> + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
> + 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
> + 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
> + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
> + 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
> + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,
> + },
> + .oobfree = {
> + { 98, 32 },
> + },
> +};
> +
> +/* 8K page, 4 bit ECC, 8/16 bit bus width */
> +static struct nand_ecclayout layout_oob_256 = {
> + .eccbytes = 160,
> + .eccpos = {
> + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
> + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
> + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
> + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
> + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
> + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
> + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
> + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
> + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
> + 90, 91, 92, 93, 94, 96, 97, 98, 99, 100,
> + 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,
> + 111, 112, 113, 114, 115, 116, 117, 118, 119, 120,
> + 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,
> + 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,
> + 141, 142, 143, 144, 145, 146, 147, 148, 149, 150,
> + 215, 216, 217, 218, 219, 220, 221, 222, 223, 224,
> + },
> + .oobfree = {
> + { 151, 64 },
> + },
> +};
> +
> +/*
> + * this is called before scan_ident, we do some minimal configurations so
> + * that reading ID and ONFI params work
> + */
> +static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
> +{
> + /* kill onenand */
> + nandc_write(this, SFLASHC_BURST_CFG, 0);
> +
> + /* enable ADM DMA */
> + nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
> +
> + /* save the original values of these registers */
> + this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
> + this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
> +
> + /* initial status value */
> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> +}
> +
> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage;
> + bool wide_bus;
> +
> + /* the nand controller fetches codewords/chunks of 512 bytes */
> + cwperpage = mtd->writesize >> 9;
> +
> + /* strength is the net strength of the complete page */
> + ecc->strength = this->ecc_strength * cwperpage;
> +
> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> +
> + if (ecc->strength >= 32) {
> + /* 8 bit ECC defaults to BCH ECC on all platforms */
> + ecc->bytes = wide_bus ? 14 : 13;
> + } else {
> + /*
> + * if the controller supports BCH for 4 bit ECC, the controller
> + * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> + * always 10 bytes
> + */
> + if (this->ecc_modes & ECC_BCH_4BIT)
> + ecc->bytes = wide_bus ? 8 : 7;
> + else
> + ecc->bytes = 10;
> + }
> +
> + /* each step consists of 512 bytes of data */
> + ecc->size = NANDC_STEP_SIZE;
> +
> + ecc->read_page = qcom_nandc_read_page_hwecc;
> + ecc->write_page = qcom_nandc_write_page_hwecc;
> + ecc->write_oob = qcom_nandc_write_oob;
> +
> + switch (mtd->oobsize) {
> + case 64:
> + ecc->layout = &layout_oob_64;
> + break;
> + case 128:
> + ecc->layout = &layout_oob_128;
> + break;
> + case 224:
> + if (wide_bus)
> + ecc->layout = &layout_oob_224_x16;
> + else
> + ecc->layout = &layout_oob_224_x8;
> + break;
> + case 256:
> + ecc->layout = &layout_oob_256;
> + break;
> + default:
> + dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
> + mtd->oobsize);
> + return -ENODEV;
> + }
> +
> + ecc->mode = NAND_ECC_HW;
> +
> + /* enable ecc by default */
> + this->use_ecc = true;
> +
> + /* free old buffer, allocate one with page data + oob size */
> + dma_free_coherent(this->dev, this->buf_size, this->data_buffer,
> + this->data_buffer_paddr);
> +
> + this->buf_size = mtd->writesize + mtd->oobsize;
> +
> + this->data_buffer = dma_alloc_coherent(this->dev, this->buf_size,
> + &this->data_buffer_paddr, GFP_KERNEL);
> + if (!this->data_buffer)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +
> +static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + int spare_bytes, bad_block_byte;
> + bool wide_bus;
> + int ecc_mode = 0;
> +
> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> +
> + if (ecc->strength >= 32) {
> + this->cw_size = 532;
> +
> + spare_bytes = wide_bus ? 0 : 2;
> +
> + this->bch_enabled = true;
> + ecc_mode = 1;
> + } else {
> + this->cw_size = 528;
> +
> + if (this->ecc_modes & ECC_BCH_4BIT) {
> + spare_bytes = wide_bus ? 2 : 4;
> +
> + this->bch_enabled = true;
> + ecc_mode = 0;
> + } else {
> + spare_bytes = wide_bus ? 0 : 1;
> + }
> + }
> +
> + /*
> + * DATA_UD_BYTES varies based on whether the read/write command protects
> + * spare data with ECC too. We protect spare data by default, so we set
> + * it to main + spare data, which are 512 and 4 bytes respectively.
> + */
> + this->cw_data = 516;
> +
> + bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
> +
> + this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
> + | this->cw_data << UD_SIZE_BYTES
> + | 0 << DISABLE_STATUS_AFTER_WRITE
> + | 5 << NUM_ADDR_CYCLES
> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
> + | 0 << STATUS_BFR_READ
> + | 1 << SET_RD_MODE_AFTER_STATUS
> + | spare_bytes << SPARE_SIZE_BYTES;
> +
> + this->cfg1 = 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | bad_block_byte << BAD_BLOCK_BYTE_NUM
> + | 0 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | wide_bus << WIDE_FLASH
> + | this->bch_enabled << ENABLE_BCH_ECC;
> +
> + this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
> + | this->cw_size << UD_SIZE_BYTES
> + | 5 << NUM_ADDR_CYCLES
> + | 0 << SPARE_SIZE_BYTES;
> +
> + this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | 17 << BAD_BLOCK_BYTE_NUM
> + | 1 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | wide_bus << WIDE_FLASH
> + | 1 << DEV0_CFG1_ECC_DISABLE;
> +
> + this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
> + | 0 << ECC_SW_RESET
> + | this->cw_data << ECC_NUM_DATA_BYTES
> + | 1 << ECC_FORCE_CLK_OPEN
> + | ecc_mode << ECC_MODE
> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
> +
> + this->ecc_buf_cfg = 0x203 << NUM_STEPS;
> +
> + this->clrflashstatus = FS_READY_BSY_N;
> + this->clrreadstatus = 0xc0;
> +
> + dev_dbg(this->dev, "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x "
> + "cw_size %d cw_data %d strength %d parity_bytes %d "
> + "steps %d\n", this->cfg0, this->cfg1, this->ecc_buf_cfg,
> + this->ecc_bch_cfg, this->cw_size, this->cw_data,
> + ecc->strength, ecc->bytes, cwperpage);
> +}
> +
> +static int qcom_nandc_alloc(struct qcom_nandc_data *this)
> +{
> + int r;
> +
> + r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
> + if (r) {
> + dev_err(this->dev, "failed to set DMA mask\n");
> + return r;
> + }
> +
> + /*
> + * we don't know the page size of the NAND chip yet, set the buffer size
> + * to 512 bytes for now, that's sufficient for reading ID or ONFI params
> + */
> + this->buf_size = SZ_512;
> +
> + this->data_buffer = dma_alloc_coherent(this->dev, this->buf_size,
> + &this->data_buffer_paddr, GFP_KERNEL);
> + if (!this->data_buffer)
> + return -ENOMEM;
> +
> + this->regs = devm_kzalloc(this->dev, sizeof(struct nandc_regs),
> + GFP_KERNEL);
> + if (!this->regs)
> + return -ENOMEM;
> +
> + this->reg_read_buf = devm_kzalloc(this->dev, MAX_REG_RD * sizeof(u32),
> + GFP_KERNEL);
> + if (!this->reg_read_buf)
> + return -ENOMEM;
> +
> + INIT_LIST_HEAD(&this->list);
> +
> + this->chan = dma_request_slave_channel(this->dev, "rxtx");
> + if (!this->chan) {
> + dev_err(this->dev, "failed to request slave channel\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
> +{
> + dma_free_coherent(this->dev, this->buf_size, this->data_buffer,
> + this->data_buffer_paddr);
> +
> + dma_release_channel(this->chan);
> +}
> +
> +static int qcom_nandc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct mtd_part_parser_data ppdata = {};
> + int r;
> +
> + mtd->priv = chip;
> + mtd->name = "qcom-nandc";
> + mtd->owner = THIS_MODULE;
> +
> + chip->priv = this;
> +
> + chip->cmdfunc = qcom_nandc_command;
> + chip->select_chip = qcom_nandc_select_chip;
> + chip->read_byte = qcom_nandc_read_byte;
> + chip->read_buf = qcom_nandc_read_buf;
> + chip->write_buf = qcom_nandc_write_buf;
> + chip->block_bad = qcom_nandc_block_bad;
> + chip->block_markbad = qcom_nandc_block_markbad;
> +
> + /* TODO: both can be supported, need to implement them */
> + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN;
> +
> + if (this->bus_width == 16)
> + chip->options |= NAND_BUSWIDTH_16;
> +
> + qcom_nandc_pre_init(this);
> +
> + r = nand_scan_ident(mtd, 1, NULL);
> + if (r)
> + return r;
> +
> + r = qcom_nandc_ecc_init(this);
> + if (r)
> + return r;
> +
> + r = nand_scan_tail(mtd);
> + if (r)
> + return r;
> +
> + qcom_nandc_hw_post_init(this);
> +
> + ppdata.of_node = this->dev->of_node;
> + r = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
> + if (r)
> + return r;
> +
> + return 0;
> +}
> +
> +static int qcom_nandc_parse_dt(struct platform_device *pdev)
> +{
> + struct device_node *np;
> + struct qcom_nandc_data *this;
> + int r;
> +
> + np = pdev->dev.of_node;
> + if (!np)
> + return -ENODEV;
> +
> + this = platform_get_drvdata(pdev);
> + if (!this)
> + return -ENODEV;
> +
> + this->ecc_strength = of_get_nand_ecc_strength(np);
> + if (this->ecc_strength < 0) {
> + dev_warn(this->dev,
> + "incorrect ecc strength, setting to 4 bits/step\n");
> + this->ecc_strength = 4;
> + }
> +
> + this->bus_width = of_get_nand_bus_width(np);
> + if (this->bus_width < 0) {
> + dev_warn(this->dev, "incorrect bus width, setting to 8\n");
> + this->bus_width = 8;
> + }
> +
> + r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
> + if (r) {
> + dev_err(this->dev, "command CRCI unspecified\n");
> + return r;
> + }
> +
> + r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
> + if (r) {
> + dev_err(this->dev, "data CRCI unspecified\n");
> + return r;
> + }
> +
> + return 0;
> +}
> +
> +#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
> +
> +static const struct of_device_id qcom_nandc_of_match[] = {
> + { .compatible = "qcom,ebi2-nandc",
> + .data = (void *) EBI2_NANDC_ECC_MODES,
> + },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
> +
> +static int qcom_nandc_probe(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this;
> + const struct of_device_id *match;
> + int r;
> +
> + this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
> + if (!this)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, this);
> +
> + this->pdev = pdev;
> + this->dev = &pdev->dev;
> +
> + match = of_match_node(qcom_nandc_of_match, pdev->dev.of_node);
> + if (!match) {
> + dev_err(&pdev->dev, "unsupported NANDc module\n");
> + return -ENODEV;
> + }
> +
> + /* match->data will hold a struct pointer once we support more IPs */
> + this->ecc_modes = (u32) match->data;
> +
> + this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + this->base = devm_ioremap_resource(&pdev->dev, this->res);
> + if (IS_ERR(this->base))
> + return PTR_ERR(this->base);
> +
> + this->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(this->core_clk))
> + return PTR_ERR(this->core_clk);
> +
> + this->aon_clk = devm_clk_get(&pdev->dev, "aon");
> + if (IS_ERR(this->aon_clk))
> + return PTR_ERR(this->aon_clk);
> +
> + r = qcom_nandc_parse_dt(pdev);
> + if (r)
> + return r;
> +
> + r = qcom_nandc_alloc(this);
> + if (r)
> + return r;
> +
> + r = clk_prepare_enable(this->core_clk);
> + if (r)
> + goto err_core_clk;
> +
> + r = clk_prepare_enable(this->aon_clk);
> + if (r)
> + goto err_aon_clk;
> +
> + r = qcom_nandc_init(this);
> + if (r)
> + goto err_init;
> +
> + return 0;
> +
> +err_init:
> + clk_disable_unprepare(this->aon_clk);
> +err_aon_clk:
> + clk_disable_unprepare(this->core_clk);
> +err_core_clk:
> + qcom_nandc_unalloc(this);
> +
> + return r;
> +}
> +
> +static int qcom_nandc_remove(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this;
> +
> + this = platform_get_drvdata(pdev);
> + if (!this)
> + return -ENODEV;
> +
> + qcom_nandc_unalloc(this);
> +
> + clk_disable_unprepare(this->aon_clk);
> + clk_disable_unprepare(this->core_clk);
> +
> + return 0;
> +}
> +
> +static struct platform_driver qcom_nandc_driver = {
> + .driver = {
> + .name = "qcom-nandc",
> + .of_match_table = qcom_nandc_of_match,
> + },
> + .probe = qcom_nandc_probe,
> + .remove = qcom_nandc_remove,
> +};
> +module_platform_driver(qcom_nandc_driver);
> +
> +MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
> +MODULE_LICENSE("GPL");
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/5] mtd: nand: Add qcom nand controller driver
2015-01-21 0:54 ` Daniel Ehrenberg
@ 2015-01-22 6:36 ` Archit Taneja
2015-01-26 21:05 ` Kevin Cernekee
0 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-01-22 6:36 UTC (permalink / raw)
To: Daniel Ehrenberg; +Cc: linux-arm-msm, galak, linux-mtd, linux-kernel, agross
Hi,
On 01/21/2015 06:24 AM, Daniel Ehrenberg wrote:
> On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja <architt@codeaurora.org> wrote:
>> +/*
>> + * the bad block marker is readable only when we read the page with ECC
>> + * disabled. all the read/write commands like NAND_CMD_READOOB, NAND_CMD_READ0
>> + * and NAND_CMD_PAGEPROG are executed in the driver with ECC enabled. therefore,
>> + * the default nand helper functions to detect a bad block or mark a bad block
>> + * can't be used.
>> + */
>> +static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
>> +{
>> + int page, r, mark, bad = 0;
>> + struct nand_chip *chip = mtd->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + struct qcom_nandc_data *this = chip->priv;
>> + u32 flash_status;
>> +
>> + pre_command(this, NAND_CMD_NONE);
>> +
>> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
>> +
>> + /*
>> + * configure registers for a raw page read, the address is set to the
>> + * beginning of the last codeword
>> + */
>> + this->use_ecc = false;
>> + set_address(this, this->cw_size * (cwperpage - 1), page);
>> +
>> + /* we just read one codeword that contains the bad block marker */
>> + update_rw_regs(this, 1, true);
>> +
>> + read_cw(this, this->cw_size, 0);
>> +
>> + r = submit_descs(this);
>> + if (r) {
>> + dev_err(this->dev, "error submitting descs\n");
>> + goto err;
>> + }
>> +
>> + flash_status = this->reg_read_buf[0];
>> +
>> + /*
>> + * unable to read the marker successfully, is that sufficient to report
>> + * the block as bad?
>> + */
>> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
>> + dev_warn(this->dev, "error while reading bad block mark\n");
>> + goto err;
>> + }
>> +
>> + mark = mtd->writesize - (this->cw_size * (cwperpage - 1));
>> +
>> + if (chip->options & NAND_BUSWIDTH_16)
>> + bad = this->data_buffer[mark] != 0xff ||
>> + this->data_buffer[mark + 1] != 0xff;
>> +
>> + bad = this->data_buffer[mark] != 0xff;
>> +err:
>> + free_descs(this);
>> +
>> + return bad;
>> +}
>> +
>> +static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>> +{
>> + int page, r;
>> + struct nand_chip *chip = mtd->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + struct qcom_nandc_data *this = chip->priv;
>> + u32 flash_status;
>> +
>> + pre_command(this, NAND_CMD_NONE);
>> +
>> + /* fill our internal buffer's oob area with 0's */
>> + memset(this->data_buffer, 0x00, mtd->writesize + mtd->oobsize);
>> +
>> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
>> +
>> + this->use_ecc = false;
>> + set_address(this, this->cw_size * (cwperpage - 1), page);
>> +
>> + /* we just write to one codeword that contains the bad block marker*/
>> + update_rw_regs(this, 1, false);
>> +
>> + /*
>> + * overwrite the last codeword with 0s, this will result in setting
>> + * the bad block marker to 0 too
>> + */
>> + write_cw(this, this->cw_size, 0);
>> +
>> + r = submit_descs(this);
>> + if (r) {
>> + dev_err(this->dev, "error submitting descs\n");
>> + r = -EIO;
>> + goto err;
>> + }
>> +
>> + flash_status = this->reg_read_buf[0];
>> +
>> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR))
>> + r = -EIO;
>> +
>> +err:
>> + free_descs(this);
>> +
>> + return r;
>> +}
>
> Looks like this code marks block bad and reads bad block information
> based on information in the OOB area. And in qcom_nandc_init,
> NAND_SKIP_BBTSCAN is set, meaning that this is the code used in
> practice on the chip in the mtd_block_isbad path. Can this driver be
> used with an on-flash OOB table by editing the init function's chip
> flags, or would it need more significant changes to allow that?
The code doesn't exactly read the OOB area. When the ECC HW block is
enabled, the bad block isn't in either oob or data area! We can access
it only when ECC is disabled. With ECC disabled, the bad block marker
lies in the last codeword somewhere in the middle of the user data. For
the mtd_read_oob()/write_oob() functions, we have the ECC always
enabled, hence, we never access the bad block marker through them at all.
Creating an on-flash bad block table won't work right now. The reason is
that the nand_bbt library assumes that it can find the bad block marker
by reading oob. While creating a bbt in memory, it scans the device for
bad blocks using the function scan_block_fast(). This would currently
result in not reading the bad block marker, and therefore break things.
I'm trying to find out if there is a way by which the controller can
access the bad block marker with ECC HW enabled. If that works, we can
use the nand_bbt helper as is. For now, I wanted to get the driver
upstream without the BBT functionality.
Archit
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/5] mtd: nand: Add qcom nand controller driver
2015-01-22 6:36 ` Archit Taneja
@ 2015-01-26 21:05 ` Kevin Cernekee
2015-01-27 3:56 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Kevin Cernekee @ 2015-01-26 21:05 UTC (permalink / raw)
To: Archit Taneja, Brian Norris
Cc: Daniel Ehrenberg, linux-arm-msm, agross, linux-mtd, linux-kernel, galak
On Wed, Jan 21, 2015 at 10:36 PM, Archit Taneja <architt@codeaurora.org> wrote:
> On 01/21/2015 06:24 AM, Daniel Ehrenberg wrote:
>> On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja <architt@codeaurora.org>
>> wrote:
>>>
>>> +/*
>>> + * the bad block marker is readable only when we read the page with ECC
>>> + * disabled. all the read/write commands like NAND_CMD_READOOB,
>>> NAND_CMD_READ0
>>> + * and NAND_CMD_PAGEPROG are executed in the driver with ECC enabled.
>>> therefore,
>>> + * the default nand helper functions to detect a bad block or mark a bad
>>> block
>>> + * can't be used.
>>> + */
>>> +static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs, int
>>> getchip)
>>> +{
>>> + int page, r, mark, bad = 0;
>>> + struct nand_chip *chip = mtd->priv;
>>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>>> + int cwperpage = ecc->steps;
>>> + struct qcom_nandc_data *this = chip->priv;
>>> + u32 flash_status;
>>> +
>>> + pre_command(this, NAND_CMD_NONE);
>>> +
>>> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
>>> +
>>> + /*
>>> + * configure registers for a raw page read, the address is set to
>>> the
>>> + * beginning of the last codeword
>>> + */
>>> + this->use_ecc = false;
>>> + set_address(this, this->cw_size * (cwperpage - 1), page);
>>> +
>>> + /* we just read one codeword that contains the bad block marker
>>> */
>>> + update_rw_regs(this, 1, true);
>>> +
>>> + read_cw(this, this->cw_size, 0);
>>> +
>>> + r = submit_descs(this);
>>> + if (r) {
>>> + dev_err(this->dev, "error submitting descs\n");
>>> + goto err;
>>> + }
>>> +
>>> + flash_status = this->reg_read_buf[0];
>>> +
>>> + /*
>>> + * unable to read the marker successfully, is that sufficient to
>>> report
>>> + * the block as bad?
>>> + */
>>> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
>>> + dev_warn(this->dev, "error while reading bad block
>>> mark\n");
>>> + goto err;
>>> + }
>>> +
>>> + mark = mtd->writesize - (this->cw_size * (cwperpage - 1));
>>> +
>>> + if (chip->options & NAND_BUSWIDTH_16)
>>> + bad = this->data_buffer[mark] != 0xff ||
>>> + this->data_buffer[mark + 1] != 0xff;
>>> +
>>> + bad = this->data_buffer[mark] != 0xff;
>>> +err:
>>> + free_descs(this);
>>> +
>>> + return bad;
>>> +}
>>> +
>>> +static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>>> +{
>>> + int page, r;
>>> + struct nand_chip *chip = mtd->priv;
>>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>>> + int cwperpage = ecc->steps;
>>> + struct qcom_nandc_data *this = chip->priv;
>>> + u32 flash_status;
>>> +
>>> + pre_command(this, NAND_CMD_NONE);
>>> +
>>> + /* fill our internal buffer's oob area with 0's */
>>> + memset(this->data_buffer, 0x00, mtd->writesize + mtd->oobsize);
>>> +
>>> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
>>> +
>>> + this->use_ecc = false;
>>> + set_address(this, this->cw_size * (cwperpage - 1), page);
>>> +
>>> + /* we just write to one codeword that contains the bad block
>>> marker*/
>>> + update_rw_regs(this, 1, false);
>>> +
>>> + /*
>>> + * overwrite the last codeword with 0s, this will result in
>>> setting
>>> + * the bad block marker to 0 too
>>> + */
>>> + write_cw(this, this->cw_size, 0);
>>> +
>>> + r = submit_descs(this);
>>> + if (r) {
>>> + dev_err(this->dev, "error submitting descs\n");
>>> + r = -EIO;
>>> + goto err;
>>> + }
>>> +
>>> + flash_status = this->reg_read_buf[0];
>>> +
>>> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR))
>>> + r = -EIO;
>>> +
>>> +err:
>>> + free_descs(this);
>>> +
>>> + return r;
>>> +}
Would it be possible to refactor this code so that it implements
generic read_oob_raw() and write_oob_raw() callbacks, which can
read/write arbitrary uncorrected OOB bytes instead of just the BBI?
Or is the controller limited in which OOB bytes can be directly
accessed?
One advantage of implementing the generic raw read/write callbacks is
that the MTD subsystem already has logic to handle old NAND chips with
different BBI positions, bitflips in the BBI, and other corner cases.
>> Looks like this code marks block bad and reads bad block information
>> based on information in the OOB area. And in qcom_nandc_init,
>> NAND_SKIP_BBTSCAN is set, meaning that this is the code used in
>> practice on the chip in the mtd_block_isbad path. Can this driver be
>> used with an on-flash OOB table by editing the init function's chip
>> flags, or would it need more significant changes to allow that?
>
>
> The code doesn't exactly read the OOB area. When the ECC HW block is
> enabled, the bad block isn't in either oob or data area! We can access it
> only when ECC is disabled. With ECC disabled, the bad block marker lies in
> the last codeword somewhere in the middle of the user data. For the
> mtd_read_oob()/write_oob() functions, we have the ECC always enabled, hence,
> we never access the bad block marker through them at all.
>
> Creating an on-flash bad block table won't work right now. The reason is
> that the nand_bbt library assumes that it can find the bad block marker by
> reading oob. While creating a bbt in memory, it scans the device for bad
> blocks using the function scan_block_fast(). This would currently result in
> not reading the bad block marker, and therefore break things.
>
> I'm trying to find out if there is a way by which the controller can access
> the bad block marker with ECC HW enabled. If that works, we can use the
> nand_bbt helper as is. For now, I wanted to get the driver upstream without
> the BBT functionality.
So, back in commit a7e68834fc2739 ("mtd: nand: use ECC, if present,
when scanning OOB"), the BBT code was changed to use MTD_OPS_PLACE_OOB
instead of MTD_OPS_RAW, because some controllers offer the ability to
provide corrected OOB data and we wanted to use it if possible. The
changelog notes that many existing drivers still disabled ECC when
reading OOB in MTD_OPS_PLACE_OOB mode.
Now it sounds like the qcom_nandc controller can either provide access
to some corrected OOB bytes (not including the BBI) when
MTD_OPS_PLACE_OOB is used, or all (?) uncorrected OOB bytes (including
the BBI) when MTD_OPS_RAW is used.
Two possible options are:
1) qcom_nandc should just disable ECC when performing OOB reads/writes
in MTD_OPS_PLACE_OOB mode
2) MTD should be made aware of whether the controller can access the
BBI in MTD_OPS_PLACE_OOB mode, and fall back to MTD_OPS_RAW mode if
the hardware cannot do so
Any thoughts?
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/5] mtd: nand: Add qcom nand controller driver
2015-01-26 21:05 ` Kevin Cernekee
@ 2015-01-27 3:56 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-01-27 3:56 UTC (permalink / raw)
To: Kevin Cernekee, Brian Norris
Cc: Daniel Ehrenberg, linux-arm-msm, agross, linux-kernel, linux-mtd, galak
On 01/27/2015 02:35 AM, Kevin Cernekee wrote:
> On Wed, Jan 21, 2015 at 10:36 PM, Archit Taneja <architt@codeaurora.org> wrote:
>> On 01/21/2015 06:24 AM, Daniel Ehrenberg wrote:
>>> On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja <architt@codeaurora.org>
>>> wrote:
>>>>
>>>> +/*
>>>> + * the bad block marker is readable only when we read the page with ECC
>>>> + * disabled. all the read/write commands like NAND_CMD_READOOB,
>>>> NAND_CMD_READ0
>>>> + * and NAND_CMD_PAGEPROG are executed in the driver with ECC enabled.
>>>> therefore,
>>>> + * the default nand helper functions to detect a bad block or mark a bad
>>>> block
>>>> + * can't be used.
>>>> + */
>>>> +static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs, int
>>>> getchip)
>>>> +{
>>>> + int page, r, mark, bad = 0;
>>>> + struct nand_chip *chip = mtd->priv;
>>>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>>>> + int cwperpage = ecc->steps;
>>>> + struct qcom_nandc_data *this = chip->priv;
>>>> + u32 flash_status;
>>>> +
>>>> + pre_command(this, NAND_CMD_NONE);
>>>> +
>>>> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
>>>> +
>>>> + /*
>>>> + * configure registers for a raw page read, the address is set to
>>>> the
>>>> + * beginning of the last codeword
>>>> + */
>>>> + this->use_ecc = false;
>>>> + set_address(this, this->cw_size * (cwperpage - 1), page);
>>>> +
>>>> + /* we just read one codeword that contains the bad block marker
>>>> */
>>>> + update_rw_regs(this, 1, true);
>>>> +
>>>> + read_cw(this, this->cw_size, 0);
>>>> +
>>>> + r = submit_descs(this);
>>>> + if (r) {
>>>> + dev_err(this->dev, "error submitting descs\n");
>>>> + goto err;
>>>> + }
>>>> +
>>>> + flash_status = this->reg_read_buf[0];
>>>> +
>>>> + /*
>>>> + * unable to read the marker successfully, is that sufficient to
>>>> report
>>>> + * the block as bad?
>>>> + */
>>>> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
>>>> + dev_warn(this->dev, "error while reading bad block
>>>> mark\n");
>>>> + goto err;
>>>> + }
>>>> +
>>>> + mark = mtd->writesize - (this->cw_size * (cwperpage - 1));
>>>> +
>>>> + if (chip->options & NAND_BUSWIDTH_16)
>>>> + bad = this->data_buffer[mark] != 0xff ||
>>>> + this->data_buffer[mark + 1] != 0xff;
>>>> +
>>>> + bad = this->data_buffer[mark] != 0xff;
>>>> +err:
>>>> + free_descs(this);
>>>> +
>>>> + return bad;
>>>> +}
>>>> +
>>>> +static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>>>> +{
>>>> + int page, r;
>>>> + struct nand_chip *chip = mtd->priv;
>>>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>>>> + int cwperpage = ecc->steps;
>>>> + struct qcom_nandc_data *this = chip->priv;
>>>> + u32 flash_status;
>>>> +
>>>> + pre_command(this, NAND_CMD_NONE);
>>>> +
>>>> + /* fill our internal buffer's oob area with 0's */
>>>> + memset(this->data_buffer, 0x00, mtd->writesize + mtd->oobsize);
>>>> +
>>>> + page = (int)(ofs >> chip->page_shift) & chip->pagemask;
>>>> +
>>>> + this->use_ecc = false;
>>>> + set_address(this, this->cw_size * (cwperpage - 1), page);
>>>> +
>>>> + /* we just write to one codeword that contains the bad block
>>>> marker*/
>>>> + update_rw_regs(this, 1, false);
>>>> +
>>>> + /*
>>>> + * overwrite the last codeword with 0s, this will result in
>>>> setting
>>>> + * the bad block marker to 0 too
>>>> + */
>>>> + write_cw(this, this->cw_size, 0);
>>>> +
>>>> + r = submit_descs(this);
>>>> + if (r) {
>>>> + dev_err(this->dev, "error submitting descs\n");
>>>> + r = -EIO;
>>>> + goto err;
>>>> + }
>>>> +
>>>> + flash_status = this->reg_read_buf[0];
>>>> +
>>>> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR))
>>>> + r = -EIO;
>>>> +
>>>> +err:
>>>> + free_descs(this);
>>>> +
>>>> + return r;
>>>> +}
>
> Would it be possible to refactor this code so that it implements
> generic read_oob_raw() and write_oob_raw() callbacks, which can
> read/write arbitrary uncorrected OOB bytes instead of just the BBI?
> Or is the controller limited in which OOB bytes can be directly
> accessed?
When accessing the page with ECC disabled, there doesn't seem to be any
limitation.
We have 528/32 bytes per codeword, and we can access all of it in raw mode.
>
> One advantage of implementing the generic raw read/write callbacks is
> that the MTD subsystem already has logic to handle old NAND chips with
> different BBI positions, bitflips in the BBI, and other corner cases.
>
>>> Looks like this code marks block bad and reads bad block information
>>> based on information in the OOB area. And in qcom_nandc_init,
>>> NAND_SKIP_BBTSCAN is set, meaning that this is the code used in
>>> practice on the chip in the mtd_block_isbad path. Can this driver be
>>> used with an on-flash OOB table by editing the init function's chip
>>> flags, or would it need more significant changes to allow that?
>>
>>
>> The code doesn't exactly read the OOB area. When the ECC HW block is
>> enabled, the bad block isn't in either oob or data area! We can access it
>> only when ECC is disabled. With ECC disabled, the bad block marker lies in
>> the last codeword somewhere in the middle of the user data. For the
>> mtd_read_oob()/write_oob() functions, we have the ECC always enabled, hence,
>> we never access the bad block marker through them at all.
>>
>> Creating an on-flash bad block table won't work right now. The reason is
>> that the nand_bbt library assumes that it can find the bad block marker by
>> reading oob. While creating a bbt in memory, it scans the device for bad
>> blocks using the function scan_block_fast(). This would currently result in
>> not reading the bad block marker, and therefore break things.
>>
>> I'm trying to find out if there is a way by which the controller can access
>> the bad block marker with ECC HW enabled. If that works, we can use the
>> nand_bbt helper as is. For now, I wanted to get the driver upstream without
>> the BBT functionality.
>
> So, back in commit a7e68834fc2739 ("mtd: nand: use ECC, if present,
> when scanning OOB"), the BBT code was changed to use MTD_OPS_PLACE_OOB
> instead of MTD_OPS_RAW, because some controllers offer the ability to
> provide corrected OOB data and we wanted to use it if possible. The
> changelog notes that many existing drivers still disabled ECC when
> reading OOB in MTD_OPS_PLACE_OOB mode.
>
> Now it sounds like the qcom_nandc controller can either provide access
> to some corrected OOB bytes (not including the BBI) when
> MTD_OPS_PLACE_OOB is used, or all (?) uncorrected OOB bytes (including
> the BBI) when MTD_OPS_RAW is used.
That's right.
>
> Two possible options are:
>
> 1) qcom_nandc should just disable ECC when performing OOB reads/writes
> in MTD_OPS_PLACE_OOB mode
What prevented me from doing this was how the
chip->ecc.read_page/write_page funcs are defined. They take
the param called oob_required.
If oob_required is set, we would need to read/write page contents with
ECC disabled too. Or, perform 2 rounds of acceses. One for the page
contents with ECC enabled, and other for oob with ECC disabled.
I don't know how often oob_required is set by the mtd subsystem, if it's
a path that is never exercised, we could try this option.
>
> 2) MTD should be made aware of whether the controller can access the
> BBI in MTD_OPS_PLACE_OOB mode, and fall back to MTD_OPS_RAW mode if
> the hardware cannot do so
That sounds like a good option. A NAND chip option mentioning this
capability could be helpful here.
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x
2015-01-16 14:48 ` [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x Archit Taneja
2015-01-16 21:56 ` Stephen Boyd
@ 2015-01-29 22:21 ` Stephen Boyd
1 sibling, 0 replies; 71+ messages in thread
From: Stephen Boyd @ 2015-01-29 22:21 UTC (permalink / raw)
To: Archit Taneja, linux-mtd, linux-arm-msm; +Cc: linux-kernel, agross, galak
On 01/16/15 06:48, Archit Taneja wrote:
> +
> +static struct clk_branch ebi2_aon_clk = {
> + .hwcg_reg = 0x3b00,
> + .hwcg_bit = 6,
It looks like these bits only apply to ebi2_clk, and not ebi2_aon_clk,
so these two lines should be dropped.
> + .halt_reg = 0x2fcc,
> + .halt_bit = 0,
> + .clkr = {
> + .enable_reg = 0x3b00,
> + .enable_mask = BIT(8),
> + .hw.init = &(struct clk_init_data){
> + .name = "ebi2_always_on_clk",
> + .ops = &clk_branch_ops,
> + .flags = CLK_IS_ROOT,
> + },
> + },
> +};
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 0/5] mtd: Qualcomm NAND controller driver
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (4 preceding siblings ...)
2015-01-16 14:48 ` [PATCH 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 pplatform Archit Taneja
@ 2015-02-18 6:03 ` Archit Taneja
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
7 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-02-18 6:03 UTC (permalink / raw)
To: linux-mtd, linux-arm-msm; +Cc: linux-kernel, agross, galak
Hi,
On 01/16/2015 08:18 PM, Archit Taneja wrote:
> Add support for the NAND controller driver for SoC's that contain EBI2. For now,
> the only SoC upstream that has EBI2 is IPQ806x.
>
> The patchset requires the ADM dmaengine patches posted by Andy:
>
> http://thread.gmane.org/gmane.linux.ports.arm.msm/11136
I'd really appreciate if I could get some reviews on this driver from
the mtd community.
Please let me know if I need to do anything to make it easier to review.
Thanks,
Archit
>
> Archit Taneja (5):
> clk: qcom: Add EBI2 clocks for IPQ806x
> mtd: nand: Add qcom nand controller driver
> Documentaion: dt: add DT bindings for Qualcomm NAND controller
> arm: qcom: dts: Add NAND controller node for ipq806x
> arm: qcom: dts: Enale NAND node on IPQ8064 AP148 pplatform
>
> .../devicetree/bindings/mtd/qcom_nandc.txt | 48 +
> arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 32 +
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +-
> drivers/clk/qcom/gcc-ipq806x.c | 34 +
> drivers/mtd/nand/Kconfig | 7 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qcom_nandc.c | 1995 ++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 +
> 8 files changed, 2136 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> create mode 100644 drivers/mtd/nand/qcom_nandc.c
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v2 0/5] mtd: Qualcomm NAND controller driver
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (5 preceding siblings ...)
2015-02-18 6:03 ` [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
@ 2015-07-21 10:34 ` Archit Taneja
2015-07-21 10:34 ` [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
` (4 more replies)
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
7 siblings, 5 replies; 71+ messages in thread
From: Archit Taneja @ 2015-07-21 10:34 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja
Add support for the NAND controller driver for SoC's that contain EBI2.
For now, the only SoC upstream that has EBI2 is IPQ806x.
The original version was posted a while back. The main comments were
about the driver not being able to use nand_bbt. This was because the
controller could read factory bad block markers only in RAW mode. This
forced us to implement our own versions of chip->block_bad and
chip->blobk_markbad, and also we had to skip creating a BBT.
Discussions with Kevin Cernekee concluded that having a new BBT flag
that incorporates this controller's special requirement is a possible
option.
The new version makes use of this flag and now uses nand_bbt, at the
cost of implement read_oob_raw and write_oob_raw ops.
The patchset requires the v6 ADM dmaengine patches posted by Andy:
https://lkml.org/lkml/2015/3/17/19
v1:
- original series:
https://lkml.org/lkml/2015/1/16/317
v2:
- Added a new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
Archit Taneja (5):
mtd: nand: Create a BBT flag to access bad block markers in raw mode
mtd: nand: Qualcomm NAND controller driver
dt/bindings: qcom_nandc: Add DT bindings
arm: qcom: dts: Add NAND controller node for ipq806x
arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform
.../devicetree/bindings/mtd/qcom_nandc.txt | 48 +
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 +
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/nand_base.c | 6 +-
drivers/mtd/nand/nand_bbt.c | 6 +-
drivers/mtd/nand/qcom_nandc.c | 2019 ++++++++++++++++++++
include/linux/mtd/bbm.h | 7 +
9 files changed, 2143 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
create mode 100644 drivers/mtd/nand/qcom_nandc.c
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
@ 2015-07-21 10:34 ` Archit Taneja
2015-07-24 19:01 ` Andy Gross
2015-07-21 10:34 ` [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
` (3 subsequent siblings)
4 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-07-21 10:34 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja
Some controllers can access the factory bad block marker from OOB only
when they read it in raw mode. When ECC is enabled, these controllers
discard reading/writing bad block markers, preventing access to them
altogether.
The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
This results in the nand driver's ecc->read_oob() op to be called, which
works with ECC enabled.
Create a new BBT option flag that tells nand_bbt to force the mode to
MTD_OPS_RAW. This would result in the correct op being called for the
underlying nand controller driver.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/nand_base.c | 6 +++++-
drivers/mtd/nand/nand_bbt.c | 6 +++++-
include/linux/mtd/bbm.h | 7 +++++++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ceb68ca..0a0c524 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -394,7 +394,11 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
} else {
ops.len = ops.ooblen = 1;
}
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
/* Write to first/last page(s) if necessary */
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 63a1a36..f2d89c9 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -420,7 +420,11 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
ops.oobbuf = buf;
ops.ooboffs = 0;
ops.datbuf = NULL;
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
for (j = 0; j < numpages; j++) {
/*
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index 36bb6a5..f67f84a 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -116,6 +116,13 @@ struct nand_bbt_descr {
#define NAND_BBT_NO_OOB_BBM 0x00080000
/*
+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
+ * when in RAW access mode
+ */
+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
+
+/*
* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
* in nand_chip.bbt_options.
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
2015-07-21 10:34 ` [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
@ 2015-07-21 10:34 ` Archit Taneja
2015-07-24 19:39 ` Andy Gross
2015-07-25 0:51 ` Stephen Boyd
2015-07-21 10:34 ` [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
` (2 subsequent siblings)
4 siblings, 2 replies; 71+ messages in thread
From: Archit Taneja @ 2015-07-21 10:34 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
broader interface for external slow peripheral devices such as LCD and
NAND/NOR flash memory or SRAM like interfaces.
We add support for the NAND controller found within EBI2. For the SoCs
of our interest, we only use the NAND controller within EBI2. Therefore,
it's safe for us to assume that the NAND controller is a standalone block
within the SoC.
The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
and spare data. The controller contains an internal 512 byte page buffer
to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
for register read/write and data transfers. The controller performs page
reads and writes at a codeword/step level of 512 bytes. It can support up
to 2 external chips of different configurations.
The driver prepares register read and write configuration descriptors for
each codeword, followed by data descriptors to read or write data from the
controller's internal buffer. It uses a single ADM DMA channel that we get
via dmaengine API. The controller requires 2 ADM CRCIs for command and
data flow control. These are passed via DT.
The ecc layout used by the controller is syndrome like, but we can't use
the standard syndrome ecc ops because of several reasons. First, the amount
of data bytes covered by ecc isn't same in each step. Second, writing to
free oob space requires us writing to the entire step in which the oob
lies. This forces us to create our own ecc ops.
One more difference is how the controller accesses the bad block marker.
The controller ignores reading the marker when ECC is enabled. ECC needs
to be explicity disabled to read or write to the bad block marker. For
this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
read the factory provided bad block markers.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qcom_nandc.c | 2019 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 2027 insertions(+)
create mode 100644 drivers/mtd/nand/qcom_nandc.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5b2806a..31951fc 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -538,4 +538,11 @@ config MTD_NAND_HISI504
help
Enables support for NAND controller on Hisilicon SoC Hip04.
+config MTD_NAND_QCOM
+ tristate "Support for NAND on QCOM SoCs"
+ depends on ARCH_QCOM && QCOM_ADM
+ help
+ Enables support for NAND flash chips on SoCs containing the EBI2 NAND
+ controller. This controller is found on IPQ806x SoC.
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f897ec..87b6a1d 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
+obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
new file mode 100644
index 0000000..51c284c
--- /dev/null
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -0,0 +1,2019 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_mtd.h>
+#include <linux/delay.h>
+
+/* NANDc reg offsets */
+#define NAND_FLASH_CMD 0x00
+#define NAND_ADDR0 0x04
+#define NAND_ADDR1 0x08
+#define NAND_FLASH_CHIP_SELECT 0x0c
+#define NAND_EXEC_CMD 0x10
+#define NAND_FLASH_STATUS 0x14
+#define NAND_BUFFER_STATUS 0x18
+#define NAND_DEV0_CFG0 0x20
+#define NAND_DEV0_CFG1 0x24
+#define NAND_DEV0_ECC_CFG 0x28
+#define NAND_DEV1_ECC_CFG 0x2c
+#define NAND_DEV1_CFG0 0x30
+#define NAND_DEV1_CFG1 0x34
+#define NAND_READ_ID 0x40
+#define NAND_READ_STATUS 0x44
+#define NAND_DEV_CMD0 0xa0
+#define NAND_DEV_CMD1 0xa4
+#define NAND_DEV_CMD2 0xa8
+#define NAND_DEV_CMD_VLD 0xac
+#define SFLASHC_BURST_CFG 0xe0
+#define NAND_ERASED_CW_DETECT_CFG 0xe8
+#define NAND_ERASED_CW_DETECT_STATUS 0xec
+#define NAND_EBI2_ECC_BUF_CFG 0xf0
+#define FLASH_BUF_ACC 0x100
+
+#define NAND_CTRL 0xf00
+#define NAND_VERSION 0xf08
+#define NAND_READ_LOCATION_0 0xf20
+#define NAND_READ_LOCATION_1 0xf24
+
+/* NAND_FLASH_CMD bits */
+#define PAGE_ACC BIT(4)
+#define LAST_PAGE BIT(5)
+
+/* NAND_FLASH_CHIP_SELECT bits */
+#define NAND_DEV_SEL 0
+#define DM_EN BIT(2)
+
+/* NAND_FLASH_STATUS bits */
+#define FS_OP_ERR BIT(4)
+#define FS_READY_BSY_N BIT(5)
+#define FS_MPU_ERR BIT(8)
+#define FS_DEVICE_STS_ERR BIT(16)
+#define FS_DEVICE_WP BIT(23)
+
+/* NAND_BUFFER_STATUS bits */
+#define BS_UNCORRECTABLE_BIT BIT(8)
+#define BS_CORRECTABLE_ERR_MSK 0x1f
+
+/* NAND_DEVn_CFG0 bits */
+#define DISABLE_STATUS_AFTER_WRITE 4
+#define CW_PER_PAGE 6
+#define UD_SIZE_BYTES 9
+#define ECC_PARITY_SIZE_BYTES_RS 19
+#define SPARE_SIZE_BYTES 23
+#define NUM_ADDR_CYCLES 27
+#define STATUS_BFR_READ 30
+#define SET_RD_MODE_AFTER_STATUS 31
+
+/* NAND_DEVn_CFG0 bits */
+#define DEV0_CFG1_ECC_DISABLE 0
+#define WIDE_FLASH 1
+#define NAND_RECOVERY_CYCLES 2
+#define CS_ACTIVE_BSY 5
+#define BAD_BLOCK_BYTE_NUM 6
+#define BAD_BLOCK_IN_SPARE_AREA 16
+#define WR_RD_BSY_GAP 17
+#define ENABLE_BCH_ECC 27
+
+/* NAND_DEV0_ECC_CFG bits */
+#define ECC_CFG_ECC_DISABLE 0
+#define ECC_SW_RESET 1
+#define ECC_MODE 4
+#define ECC_PARITY_SIZE_BYTES_BCH 8
+#define ECC_NUM_DATA_BYTES 16
+#define ECC_FORCE_CLK_OPEN 30
+
+/* NAND_DEV_CMD1 bits */
+#define READ_ADDR 0
+
+/* NAND_DEV_CMD_VLD bits */
+#define READ_START_VLD 0
+
+/* NAND_EBI2_ECC_BUF_CFG bits */
+#define NUM_STEPS 0
+
+/* NAND_ERASED_CW_DETECT_CFG bits */
+#define ERASED_CW_ECC_MASK 1
+#define AUTO_DETECT_RES 0
+#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
+#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
+#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
+#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
+#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
+
+/* NAND_ERASED_CW_DETECT_STATUS bits */
+#define PAGE_ALL_ERASED BIT(7)
+#define CODEWORD_ALL_ERASED BIT(6)
+#define PAGE_ERASED BIT(5)
+#define CODEWORD_ERASED BIT(4)
+#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
+#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
+
+/* Version Mask */
+#define NAND_VERSION_MAJOR_MASK 0xf0000000
+#define NAND_VERSION_MAJOR_SHIFT 28
+#define NAND_VERSION_MINOR_MASK 0x0fff0000
+#define NAND_VERSION_MINOR_SHIFT 16
+
+/* NAND OP_CMDs */
+#define PAGE_READ 0x2
+#define PAGE_READ_WITH_ECC 0x3
+#define PAGE_READ_WITH_ECC_SPARE 0x4
+#define PROGRAM_PAGE 0x6
+#define PAGE_PROGRAM_WITH_ECC 0x7
+#define PROGRAM_PAGE_SPARE 0x9
+#define BLOCK_ERASE 0xa
+#define FETCH_ID 0xb
+#define RESET_DEVICE 0xd
+
+/*
+ * the NAND controller performs reads/writes with ECC in 516 byte chunks.
+ * the driver calls the chunks 'step' or 'codeword' interchangeably
+ */
+#define NANDC_STEP_SIZE 512
+
+/*
+ * the largest page size we support is 8K, this will have 16 steps/codewords
+ * of 512 bytes each
+ */
+#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
+
+/* we read at most 3 registers per codeword scan */
+#define MAX_REG_RD (3 * MAX_NUM_STEPS)
+
+/* ECC modes */
+#define ECC_NONE BIT(0)
+#define ECC_RS_4BIT BIT(1)
+#define ECC_BCH_4BIT BIT(2)
+#define ECC_BCH_8BIT BIT(3)
+
+struct desc_info {
+ struct list_head list;
+
+ enum dma_transfer_direction dir;
+ struct scatterlist sgl;
+ struct dma_async_tx_descriptor *dma_desc;
+};
+
+/*
+ * holds the current register values that we want to write. acts as a contiguous
+ * chunk of memory which we use to write the controller registers through DMA.
+ */
+struct nandc_regs {
+ u32 cmd;
+ u32 addr0;
+ u32 addr1;
+ u32 chip_sel;
+ u32 exec;
+
+ u32 cfg0;
+ u32 cfg1;
+ u32 ecc_bch_cfg;
+
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+
+ u32 cmd1;
+ u32 vld;
+
+ u32 orig_cmd1;
+ u32 orig_vld;
+
+ u32 ecc_buf_cfg;
+};
+
+/*
+ * @cmd_crci: ADM DMA CRCI for command flow control
+ * @data_crci: ADM DMA CRCI for data flow control
+ * @list: DMA descriptor list (list of desc_infos)
+ * @dma_done: completion param to denote end of last
+ * descriptor in the list
+ * @data_buffer: our local DMA buffer for page read/writes,
+ * used when we can't use the buffer provided
+ * by upper layers directly
+ * @buf_size/count/start: markers for chip->read_buf/write_buf functions
+ * @reg_read_buf: buffer for reading register data via DMA
+ * @reg_read_pos: marker for data read in reg_read_buf
+ * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
+ * ecc/non-ecc mode for the current nand flash
+ * device
+ * @regs: a contiguous chunk of memory for DMA register
+ * writes
+ * @ecc_strength: 4 bit or 8 bit ecc, received via DT
+ * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
+ * @ecc_modes: supported ECC modes by the current controller,
+ * initialized via DT match data
+ * @cw_size: the number of bytes in a single step/codeword
+ * of a page, consisting of all data, ecc, spare
+ * and reserved bytes
+ * @cw_data: the number of bytes within a codeword protected
+ * by ECC
+ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
+ * @status: value to be returned if NAND_CMD_STATUS command
+ * is executed
+ */
+struct qcom_nandc_data {
+ struct platform_device *pdev;
+ struct device *dev;
+
+ void __iomem *base;
+ struct resource *res;
+
+ struct clk *core_clk;
+ struct clk *aon_clk;
+
+ /* DMA stuff */
+ struct dma_chan *chan;
+ struct dma_slave_config slave_conf;
+ unsigned int cmd_crci;
+ unsigned int data_crci;
+ struct list_head list;
+ struct completion dma_done;
+
+ /* MTD stuff */
+ struct nand_chip chip;
+ struct mtd_info mtd;
+
+ /* local data buffer and markers */
+ u8 *data_buffer;
+ int buf_size;
+ int buf_count;
+ int buf_start;
+
+ /* local buffer to read back registers */
+ u32 *reg_read_buf;
+ dma_addr_t reg_read_paddr;
+ int reg_read_pos;
+
+ /* required configs */
+ u32 cfg0, cfg1;
+ u32 cfg0_raw, cfg1_raw;
+ u32 ecc_buf_cfg;
+ u32 ecc_bch_cfg;
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+ u32 sflashc_burst_cfg;
+ u32 cmd1, vld;
+
+ /* register state */
+ struct nandc_regs *regs;
+
+ /* things we get from DT */
+ int ecc_strength;
+ int bus_width;
+
+ u32 ecc_modes;
+
+ /* misc params */
+ int cw_size;
+ int cw_data;
+ bool use_ecc;
+ bool bch_enabled;
+ u8 status;
+ int last_command;
+};
+
+static inline unsigned int nandc_read(struct qcom_nandc_data *this, int offset)
+{
+ return ioread32(this->base + offset);
+}
+
+static inline void nandc_write(struct qcom_nandc_data *this, int offset,
+ unsigned int val)
+{
+ iowrite32(val, this->base + offset);
+}
+
+/* helper to configure address register values */
+static void set_address(struct qcom_nandc_data *this, u16 column, int page)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nandc_regs *regs = this->regs;
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ column >>= 1;
+
+ regs->addr0 = page << 16 | column;
+ regs->addr1 = page >> 16 & 0xff;
+}
+
+/*
+ * update_rw_regs: set up read/write register values, these will be
+ * written to the NAND controller registers via DMA
+ *
+ * @num_cw: number of steps for the read/write operation
+ * @read: read or write operation
+ */
+static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
+{
+ struct nandc_regs *regs = this->regs;
+
+ if (this->use_ecc) {
+ if (read)
+ regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
+ else
+ regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
+
+ regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ regs->cfg1 = this->cfg1;
+ regs->ecc_bch_cfg = this->ecc_bch_cfg;
+ } else {
+ if (read)
+ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ else
+ regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
+
+ regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ regs->cfg1 = this->cfg1_raw;
+ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ }
+
+ regs->ecc_buf_cfg = this->ecc_buf_cfg;
+ regs->clrflashstatus = this->clrflashstatus;
+ regs->clrreadstatus = this->clrreadstatus;
+ regs->exec = 1;
+}
+
+/*
+ * write_reg_dma: prepares a descriptor to write a given number of
+ * contiguous registers
+ *
+ * @first: offset of the first register in the contiguous block
+ * @reg: starting address containing the reg values to write
+ * @num_regs: number of registers to write
+ * @flow_control: flow control enabled/disabled
+ */
+static int write_reg_dma(struct qcom_nandc_data *this, int first, u32 *reg,
+ int num_regs, bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ int size;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ size = num_regs * sizeof(u32);
+
+ sg_init_one(sgl, reg, size);
+
+ desc->dir = DMA_MEM_TO_DEV;
+
+ dma_map_sg(this->dev, sgl, 1, desc->dir);
+
+ this->slave_conf.device_fc = flow_control ? 1 : 0;
+ this->slave_conf.dst_addr = this->res->start + first;
+ this->slave_conf.dst_maxburst = 16;
+ this->slave_conf.slave_id = this->cmd_crci;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare register write desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * read_reg_dma: prepares a descriptor to read a given number of
+ * contiguous registers to the reg_read_buf pointer
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to read
+ * @flow_control: flow control enabled/disabled
+ */
+static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs,
+ bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ int size;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ size = num_regs * sizeof(u32);
+
+ sg_init_one(sgl, this->reg_read_buf + this->reg_read_pos, size);
+
+ desc->dir = DMA_DEV_TO_MEM;
+
+ dma_map_sg(this->dev, sgl, 1, desc->dir);
+
+ this->slave_conf.device_fc = flow_control ? 1 : 0;
+ this->slave_conf.src_addr = this->res->start + first;
+ this->slave_conf.src_maxburst = 16;
+ this->slave_conf.slave_id = this->data_crci;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare register read desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ this->reg_read_pos += num_regs;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * read_data_dma: prepares a DMA descriptor to transfer data from the
+ * controller's internal buffer to the buffer 'vaddr'
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to write to
+ * @size: DMA transaction size in bytes
+ */
+static int read_data_dma(struct qcom_nandc_data *this, int reg_off, u8 *vaddr,
+ int size)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ sg_init_one(sgl, vaddr, size);
+
+ desc->dir = DMA_DEV_TO_MEM;
+
+ r = dma_map_sg(this->dev, sgl, 1, desc->dir);
+ if (r == 0)
+ goto err;
+
+ this->slave_conf.device_fc = 0;
+ this->slave_conf.src_addr = this->res->start + reg_off;
+ this->slave_conf.src_maxburst = 16;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare data read desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * write_data_dma: prepares a DMA descriptor to transfer data from
+ * 'vaddr' to the controller's internal buffer
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to read from
+ * @size: DMA transaction size in bytes
+ */
+static int write_data_dma(struct qcom_nandc_data *this, int reg_off, u8 *vaddr,
+ int size)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ sg_init_one(sgl, vaddr, size);
+
+ desc->dir = DMA_MEM_TO_DEV;
+
+ r = dma_map_sg(this->dev, sgl, 1, desc->dir);
+ if (r == 0)
+ goto err;
+
+ this->slave_conf.device_fc = 0;
+ this->slave_conf.dst_addr = this->res->start + reg_off;
+ this->slave_conf.dst_maxburst = 16;
+
+ r = dmaengine_slave_config(this->chan, &this->slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare data write desc\n");
+ r = PTR_ERR(dma_desc);
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * helper to prepare dma descriptors to configure registers needed for reading a
+ * codeword/step in a page
+ */
+static void config_cw_read(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
+ write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
+ 1, false);
+
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 2, true);
+ read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1, false);
+}
+
+/*
+ * helpers to prepare dma descriptors used to configure registers needed for
+ * writing a codeword/step in a page
+ */
+static void config_cw_write_pre(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
+ write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
+ 1, false);
+}
+
+static void config_cw_write_post(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, ®s->clrflashstatus, 1, false);
+ write_reg_dma(this, NAND_READ_STATUS, ®s->clrreadstatus, 1, false);
+}
+
+/*
+ * the following functions are used within chip->cmdfunc() to perform different
+ * NAND_CMD_* commands
+ */
+
+/* sets up descriptors for NAND_CMD_PARAM */
+static int nandc_param(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ /*
+ * NAND_CMD_PARAM is called before we know much about the FLASH chip
+ * in use. we configure the controller to perform a raw read of 512
+ * bytes to read onfi params
+ */
+ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ regs->addr0 = 0;
+ regs->addr1 = 0;
+ regs->cfg0 = 0 << CW_PER_PAGE
+ | 512 << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ regs->cfg1 = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | 0 << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+
+ /* configure CMD1 and VLD for ONFI param probing */
+ regs->vld = (this->vld & ~(1 << READ_START_VLD))
+ | 0 << READ_START_VLD;
+
+ regs->cmd1 = (this->cmd1 & ~(0xFF << READ_ADDR))
+ | NAND_CMD_PARAM << READ_ADDR;
+
+ regs->exec = 1;
+
+ regs->orig_cmd1 = this->cmd1;
+ regs->orig_vld = this->vld;
+
+ write_reg_dma(this, NAND_DEV_CMD_VLD, ®s->vld, 1, false);
+ write_reg_dma(this, NAND_DEV_CMD1, ®s->cmd1, 1, false);
+
+ this->buf_count = 512;
+ memset(this->data_buffer, 0xff, this->buf_count);
+
+ config_cw_read(this);
+
+ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->buf_count);
+
+ /* restore CMD1 and VLD regs */
+ write_reg_dma(this, NAND_DEV_CMD1, ®s->orig_cmd1, 1, false);
+ write_reg_dma(this, NAND_DEV_CMD_VLD, ®s->orig_vld, 1, false);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_ERASE1 */
+static int erase_block(struct qcom_nandc_data *this, int page_addr)
+{
+ struct nandc_regs *regs = this->regs;
+
+ regs->cmd = BLOCK_ERASE | PAGE_ACC | LAST_PAGE;
+ regs->addr0 = page_addr;
+ regs->addr1 = 0;
+ regs->cfg0 = this->cfg0_raw & ~(7 << CW_PER_PAGE);
+ regs->cfg1 = this->cfg1_raw;
+ regs->exec = 1;
+ regs->clrflashstatus = this->clrflashstatus;
+ regs->clrreadstatus = this->clrreadstatus;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
+ write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 2, false);
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, ®s->clrflashstatus, 1, false);
+ write_reg_dma(this, NAND_READ_STATUS, ®s->clrreadstatus, 1, false);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_READID */
+static int read_id(struct qcom_nandc_data *this, int column)
+{
+ struct nandc_regs *regs = this->regs;
+
+ if (column == -1)
+ return 0;
+
+ regs->cmd = FETCH_ID;
+ regs->addr0 = column;
+ regs->addr1 = 0;
+ regs->chip_sel = DM_EN;
+ regs->exec = 1;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 4, true);
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_READ_ID, 1, true);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_RESET */
+static int reset(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ regs->cmd = RESET_DEVICE;
+ regs->exec = 1;
+
+ write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 1, true);
+ write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
+
+ return 0;
+}
+
+/* helpers to submit/free our list of dma descriptors */
+static void dma_callback(void *param)
+{
+ struct qcom_nandc_data *this = (struct qcom_nandc_data *) param;
+ struct completion *c = &this->dma_done;
+
+ complete(c);
+}
+
+static int submit_descs(struct qcom_nandc_data *this)
+{
+ struct completion *c = &this->dma_done;
+ struct desc_info *desc;
+ int r;
+
+ init_completion(c);
+
+ list_for_each_entry(desc, &this->list, list) {
+ /*
+ * we add a callback the last descriptor in our list to notify
+ * completion of command
+ */
+ if (list_is_last(&desc->list, &this->list)) {
+ desc->dma_desc->callback = dma_callback;
+ desc->dma_desc->callback_param = this;
+ }
+
+ dmaengine_submit(desc->dma_desc);
+ }
+
+ dma_async_issue_pending(this->chan);
+
+ r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
+ if (!r)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void free_descs(struct qcom_nandc_data *this)
+{
+ struct desc_info *desc, *n;
+
+ list_for_each_entry_safe(desc, n, &this->list, list) {
+ list_del(&desc->list);
+ dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir);
+ kfree(desc);
+ }
+}
+
+/* reset the register read buffer for next NAND operation */
+static void clear_read_regs(struct qcom_nandc_data *this)
+{
+ this->reg_read_pos = 0;
+ memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(u32));
+}
+
+static void pre_command(struct qcom_nandc_data *this, int command)
+{
+ this->buf_count = 0;
+ this->buf_start = 0;
+ this->use_ecc = false;
+ this->last_command = command;
+
+ clear_read_regs(this);
+}
+
+/*
+ * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
+ * privately maintained status byte, this status byte can be read after
+ * NAND_CMD_STATUS is called
+ */
+static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int num_cw;
+ int i;
+
+ num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
+
+ for (i = 0; i < num_cw; i++) {
+ u32 flash_status;
+
+ flash_status = this->reg_read_buf[i];
+
+ if (flash_status & FS_MPU_ERR)
+ this->status &= ~NAND_STATUS_WP;
+
+ if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
+ (flash_status & FS_DEVICE_STS_ERR)))
+ this->status |= NAND_STATUS_FAIL;
+ }
+}
+
+static void post_command(struct qcom_nandc_data *this, int command)
+{
+ switch (command) {
+ case NAND_CMD_READID:
+ memcpy(this->data_buffer, this->reg_read_buf, this->buf_count);
+ break;
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_ERASE1:
+ parse_erase_write_errors(this, command);
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Implements chip->cmdfunc. It's only used for a limited set of commands.
+ * The rest of the commands wouldn't be called by upper layers. For example,
+ * NAND_CMD_READOOB would never be called because we have our own versions
+ * of read_oob ops for nand_ecc_ctrl.
+ */
+static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct qcom_nandc_data *this = chip->priv;
+ bool wait = false;
+ int r = 0;
+
+ pre_command(this, command);
+
+ switch (command) {
+ case NAND_CMD_RESET:
+ r = reset(this);
+ wait = true;
+ break;
+
+ case NAND_CMD_READID:
+ this->buf_count = 4;
+ r = read_id(this, column);
+ wait = true;
+ break;
+
+ case NAND_CMD_PARAM:
+ r = nandc_param(this);
+ wait = true;
+ break;
+
+ case NAND_CMD_ERASE1:
+ r = erase_block(this, page_addr);
+ wait = true;
+ break;
+
+ case NAND_CMD_READ0:
+ /* we read the entire page for now */
+ WARN_ON(column != 0);
+
+ this->use_ecc = true;
+ set_address(this, 0, page_addr);
+ update_rw_regs(this, ecc->steps, true);
+ break;
+
+ case NAND_CMD_SEQIN:
+ WARN_ON(column != 0);
+ set_address(this, 0, page_addr);
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_STATUS:
+ case NAND_CMD_NONE:
+ default:
+ break;
+ }
+
+ if (r) {
+ dev_err(this->dev, "failure executing command %d\n",
+ command);
+ free_descs(this);
+ return;
+ }
+
+ if (wait) {
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev,
+ "failure submitting descs for command %d\n",
+ command);
+ }
+
+ free_descs(this);
+
+ post_command(this, command);
+}
+
+/*
+ * when using RS ECC, the NAND controller flags an error when reading an
+ * erased page. however, there are special characters at certain offsets when
+ * we read the erased page. we check here if the page is really empty. if so,
+ * we replace the magic characters with 0xffs
+ */
+static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ int i;
+
+ /* if BCH is enabled, HW will take care of detecting erased pages */
+ if (this->bch_enabled || !this->use_ecc)
+ return false;
+
+ for (i = 0; i < cwperpage; i++) {
+ u8 *empty1, *empty2;
+ u32 flash_status = this->reg_read_buf[3 * i];
+
+ /*
+ * an erased page flags an error in NAND_FLASH_STATUS, check if
+ * the page is erased by looking for 0x54s at offsets 3 and 175
+ * from the beginning of each codeword
+ */
+ if (flash_status & FS_OP_ERR) {
+ empty1 = &data_buf[3 + i * this->cw_data];
+ empty2 = &data_buf[175 + i * this->cw_data];
+
+ /*
+ * the error wasn't because of an erased page, bail out
+ * and let someone else do the error checking
+ */
+ if (!((*empty1 == 0x54 && *empty2 == 0xff) ||
+ (*empty1 == 0xff && *empty2 == 0x54)))
+ return false;
+ }
+ }
+
+ for (i = 0; i < mtd->writesize && (data_buf[i] == 0xff ||
+ (i % this->cw_data == 3 || i % this->cw_data == 175)); i++) {
+ }
+
+ if (i < mtd->writesize)
+ return false;
+
+ /*
+ * the whole page is 0xffs besides the magic offsets, we replace the
+ * 0x54s with 0xffs
+ */
+ for (i = 0; i < cwperpage; i++) {
+ data_buf[3 + i * this->cw_data] = 0xff;
+ data_buf[175 + i * this->cw_data] = 0xff;
+ }
+
+ /*
+ * tell the caller that the page was empty and is fixed up, so that
+ * parse_read_errors() doesn't think it's and error
+ */
+ return true;
+}
+
+/*
+ * reads back status registers set by the controller to notify page read
+ * errors. this is equivalent to what 'ecc->correct()' would do.
+ */
+static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ unsigned int max_bitflips = 0;
+ int i;
+
+ for (i = 0; i < cwperpage; i++) {
+ int stat;
+ u32 flash_status = this->reg_read_buf[3 * i];
+ u32 buffer_status = this->reg_read_buf[3 * i + 1];
+ u32 erased_cw_status = this->reg_read_buf[3 * i + 2];
+
+ if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
+
+ /* ignore erased codeword errors */
+ if (this->bch_enabled) {
+ if ((erased_cw_status & ERASED_CW) == ERASED_CW)
+ continue;
+ } else if (erased_page) {
+ continue;
+ }
+
+ if (buffer_status & BS_UNCORRECTABLE_BIT) {
+ mtd->ecc_stats.failed++;
+ continue;
+ }
+ }
+
+ stat = buffer_status & BS_CORRECTABLE_ERR_MSK;
+ mtd->ecc_stats.corrected += stat;
+
+ max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ }
+
+ return max_bitflips;
+}
+
+/*
+ * helper to perform the actual page read operation, used by ecc->read_page()
+ * and ecc->read_oob()
+ */
+static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf,
+ u8 *oob_buf)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int i, r;
+
+ /* queue cmd descs for each codeword */
+ for (i = 0; i < ecc->steps; i++) {
+ int data_size, oob_size;
+
+ if (i == (ecc->steps - 1)) {
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+ }
+
+ config_cw_read(this);
+
+ if (data_buf)
+ read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
+
+ if (oob_buf)
+ read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf,
+ oob_size);
+
+ if (data_buf)
+ data_buf += data_size;
+ if (oob_buf)
+ oob_buf += oob_size;
+ }
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to read page/oob\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/*
+ * a helper that copies the last step/codeword of a page (containing free oob)
+ * into our local buffer
+ */
+static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int size;
+ int r;
+
+ clear_read_regs(this);
+
+ size = use_ecc ? this->cw_data : this->cw_size;
+
+ /* prepare a clean read buffer */
+ memset(this->data_buffer, 0xff, size);
+
+ this->use_ecc = use_ecc;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, true);
+
+ config_cw_read(this);
+
+ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size);
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failed to copy last codeword\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/* implements ecc->read_page() */
+static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ u8 *data_buf, *oob_buf = NULL;
+ bool direct_dma, erased_page;
+ int r;
+
+ /*
+ * first try to map the upper buffer directly, else, use our own buf
+ * and memcpy to upper buf
+ */
+ if (virt_addr_valid(buf) && !object_is_on_stack(buf)) {
+ direct_dma = true;
+ data_buf = buf;
+ } else {
+ direct_dma = false;
+ data_buf = this->data_buffer;
+ memset(data_buf, 0xff, mtd->writesize + mtd->oobsize);
+ }
+
+ oob_buf = oob_required ? chip->oob_poi : NULL;
+
+ r = read_page_low(this, data_buf, oob_buf);
+ if (r) {
+ dev_err(this->dev, "failure to read page\n");
+ goto err;
+ }
+
+ erased_page = empty_page_fixup(this, data_buf);
+
+ if (!direct_dma)
+ memcpy(buf, this->data_buffer, mtd->writesize);
+
+ r = parse_read_errors(this, erased_page);
+err:
+ return r;
+}
+
+/* implements ecc->read_oob() */
+static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int r;
+
+ clear_read_regs(this);
+
+ this->use_ecc = true;
+ set_address(this, 0, page);
+ update_rw_regs(this, ecc->steps, true);
+
+ r = read_page_low(this, NULL, chip->oob_poi);
+ if (r)
+ dev_err(this->dev, "failure to read oob\n");
+
+ return r;
+}
+
+/* implements ecc->read_oob_raw(), used to read the bad block marker flag */
+static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int start, length;
+ int r;
+
+ /*
+ * configure registers for a raw page read, the address is set to the
+ * beginning of the last codeword, we don't care about reading ecc
+ * portion of oob, just the free stuff
+ */
+ r = copy_last_cw(this, false, page);
+ if (r)
+ return r;
+
+ /*
+ * reading raw oob has 2 parts, first the bad block byte, then the
+ * actual free oob region. perform a memcpy in two steps
+ */
+ start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
+ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
+
+ memcpy(oob, this->data_buffer + start, length);
+
+ oob += length;
+
+ start = this->cw_data - (ecc->steps << 2) + 1;
+ length = ecc->steps << 2;
+
+ memcpy(oob, this->data_buffer + start, length);
+
+ return 0;
+}
+
+/* implements ecc->write_page() */
+static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ u8 *data_buf, *oob_buf;
+ bool direct_dma;
+ int i, r = 0;
+
+ clear_read_regs(this);
+
+ /*
+ * first try to map the upper buffer directly, else, memcpy upper
+ * buffer to our local buffer
+ */
+ direct_dma = virt_addr_valid(buf) && !object_is_on_stack((void *) buf);
+
+ if (!direct_dma) {
+ memcpy(this->data_buffer, buf, mtd->writesize);
+ data_buf = this->data_buffer;
+ } else {
+ data_buf = (u8 *) buf;
+ }
+
+ oob_buf = chip->oob_poi;
+
+ this->use_ecc = true;
+ update_rw_regs(this, ecc->steps, false);
+
+ for (i = 0; i < ecc->steps; i++) {
+ int data_size, oob_size;
+
+ if (i == (ecc->steps - 1)) {
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+ }
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
+
+ /*
+ * we don't really need to write anything to oob for the
+ * first n - 1 codewords since these oob regions just
+ * contain ecc that's written by the controller itself
+ */
+ if (i == (ecc->steps - 1))
+ write_data_dma(this, FLASH_BUF_ACC + data_size,
+ oob_buf, oob_size);
+ config_cw_write_post(this);
+
+ data_buf += data_size;
+ oob_buf += oob_size;
+ }
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to write page\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/*
+ * implements ecc->write_oob()
+ *
+ * the NAND controller cannot write only data or only oob within a codeword,
+ * since ecc is calculated for the combined codeword. we first copy the
+ * entire contents for the last codeword(data + oob), replace the old oob
+ * with the new one in chip->oob_poi, and then write the entire codeword.
+ * this read-copy-write operation results in a slight perormance loss.
+ */
+static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int free_boff;
+ int data_size, oob_size;
+ int r, status = 0;
+
+ r = copy_last_cw(this, true, page);
+ if (r)
+ return r;
+
+ clear_read_regs(this);
+
+ /* calculate the data and oob size for the last codeword/step */
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+
+ /*
+ * the location of spare data in the oob buffer, we could also use
+ * ecc->layout.oobfree here
+ */
+ free_boff = ecc->bytes * (ecc->steps - 1);
+
+ /* override new oob content to last codeword */
+ memcpy(this->data_buffer + data_size, oob + free_boff, oob_size);
+
+ this->use_ecc = true;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, false);
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer,
+ data_size + oob_size);
+ config_cw_write_post(this);
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to write oob\n");
+
+ free_descs(this);
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/* implements ecc->write_oob_raw(), used to write bad block marker flag */
+static int qcom_nandc_write_oob_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int start, length;
+ int r, status = 0;
+
+ r = copy_last_cw(this, false, page);
+ if (r)
+ return r;
+
+ clear_read_regs(this);
+
+ /*
+ * writing raw oob has 2 parts, first the bad block region, then the
+ * actual free region
+ */
+ start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
+ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
+
+ memcpy(this->data_buffer + start, oob, length);
+
+ oob += length;
+
+ start = this->cw_data - (ecc->steps << 2) + 1;
+ length = ecc->steps << 2;
+
+ memcpy(this->data_buffer + start, oob, length);
+
+ /* prepare write */
+ this->use_ecc = false;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, false);
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size);
+ config_cw_write_post(this);
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to write updated oob\n");
+
+ free_descs(this);
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/*
+ * the three functions below implement chip->read_byte(), chip->read_buf()
+ * and chip->write_buf() respectively. these aren't used for
+ * reading/writing page data, they are used for smaller data like reading
+ * id, status etc
+ */
+static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ uint8_t *buf = (uint8_t *) this->data_buffer;
+ uint8_t ret = 0x0;
+
+ if (this->last_command == NAND_CMD_STATUS) {
+ ret = this->status;
+
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+
+ return ret;
+ }
+
+ if (this->buf_start < this->buf_count)
+ ret = buf[this->buf_start++];
+
+ return ret;
+}
+
+static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(buf, this->data_buffer + this->buf_start, real_len);
+ this->buf_start += real_len;
+}
+
+static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(this->data_buffer + this->buf_start, buf, real_len);
+
+ this->buf_start += real_len;
+}
+
+/* we support only one external chip for now */
+static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+
+ if (chipnr <= 0)
+ return;
+
+ dev_warn(this->dev, "invalid chip select\n");
+}
+
+/*
+ * NAND controller page layout info
+ *
+ * |-----------------------| |---------------------------------|
+ * | xx.......xx| | *********xx.......xx|
+ * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
+ * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
+ * | xx.......xx| | *********xx.......xx|
+ * |-----------------------| |---------------------------------|
+ * codeword 1,2..n-1 codeword n
+ * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
+ *
+ * n = number of codewords in the page
+ * . = ECC bytes
+ * * = spare bytes
+ * x = unused/reserved bytes
+ *
+ * 2K page: n = 4, spare = 16 bytes
+ * 4K page: n = 8, spare = 32 bytes
+ * 8K page: n = 16, spare = 64 bytes
+ *
+ * the qcom nand controller operates at a sub page/codeword level. each
+ * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
+ * the number of ECC bytes vary based on the ECC strength and the bus width.
+ *
+ * the first n - 1 codewords contains 516 bytes of user data, the remaining
+ * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
+ * both user data and spare(oobavail) bytes that sum up to 516 bytes.
+ *
+ * the layout described above is used by the controller when the ECC block is
+ * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
+ * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
+ * layouts defined below doesn't consider the positions occupied by the reserved
+ * bytes
+ *
+ * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
+ * in the last codeword is the position of bad block marker. the bad block
+ * marker cannot be accessed when ECC is enabled.
+ *
+ */
+
+/*
+ * Layouts for different page sizes and ecc modes. We skip the eccpos field
+ * since it isn't needed for this driver
+ */
+
+/* 2K page, 4 bit ECC */
+static struct nand_ecclayout layout_oob_64 = {
+ .eccbytes = 40,
+ .oobfree = {
+ { 30, 16 },
+ },
+};
+
+/* 4K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_128 = {
+ .eccbytes = 80,
+ .oobfree = {
+ { 70, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 8 bit bus width */
+static struct nand_ecclayout layout_oob_224_x8 = {
+ .eccbytes = 104,
+ .oobfree = {
+ { 91, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 16 bit bus width */
+static struct nand_ecclayout layout_oob_224_x16 = {
+ .eccbytes = 112,
+ .oobfree = {
+ { 98, 32 },
+ },
+};
+
+/* 8K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_256 = {
+ .eccbytes = 160,
+ .oobfree = {
+ { 151, 64 },
+ },
+};
+
+/*
+ * this is called before scan_ident, we do some minimal configurations so
+ * that reading ID and ONFI params work
+ */
+static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
+{
+ /* kill onenand */
+ nandc_write(this, SFLASHC_BURST_CFG, 0);
+
+ /* enable ADM DMA */
+ nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
+
+ /* save the original values of these registers */
+ this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
+ this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
+
+ /* initial status value */
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+}
+
+static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage;
+ bool wide_bus;
+
+ /* the nand controller fetches codewords/chunks of 512 bytes */
+ cwperpage = mtd->writesize >> 9;
+
+ /* strength is the net strength of the complete page */
+ ecc->strength = this->ecc_strength * cwperpage;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 32) {
+ /* 8 bit ECC defaults to BCH ECC on all platforms */
+ ecc->bytes = wide_bus ? 14 : 13;
+ } else {
+ /*
+ * if the controller supports BCH for 4 bit ECC, the controller
+ * uses lesser bytes for ECC. If RS is used, the ECC bytes is
+ * always 10 bytes
+ */
+ if (this->ecc_modes & ECC_BCH_4BIT)
+ ecc->bytes = wide_bus ? 8 : 7;
+ else
+ ecc->bytes = 10;
+ }
+
+ /* each step consists of 512 bytes of data */
+ ecc->size = NANDC_STEP_SIZE;
+
+ ecc->read_page = qcom_nandc_read_page;
+ ecc->read_oob = qcom_nandc_read_oob;
+ ecc->write_page = qcom_nandc_write_page;
+ ecc->write_oob = qcom_nandc_write_oob;
+
+ /*
+ * the bad block marker is readable only when we read the page with ECC
+ * disabled. all the ops above run with ECC enabled. We need raw read
+ * and write function for oob in order to access bad block marker.
+ */
+ ecc->read_oob_raw = qcom_nandc_read_oob_raw;
+ ecc->write_oob_raw = qcom_nandc_write_oob_raw;
+
+ switch (mtd->oobsize) {
+ case 64:
+ ecc->layout = &layout_oob_64;
+ break;
+ case 128:
+ ecc->layout = &layout_oob_128;
+ break;
+ case 224:
+ if (wide_bus)
+ ecc->layout = &layout_oob_224_x16;
+ else
+ ecc->layout = &layout_oob_224_x8;
+ break;
+ case 256:
+ ecc->layout = &layout_oob_256;
+ break;
+ default:
+ dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
+ mtd->oobsize);
+ return -ENODEV;
+ }
+
+ ecc->mode = NAND_ECC_HW;
+
+ /* enable ecc by default */
+ this->use_ecc = true;
+
+ /* free old buffer, allocate one with page data + oob size */
+ devm_kfree(this->dev, this->data_buffer);
+
+ this->buf_size = mtd->writesize + mtd->oobsize;
+
+ this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
+ if (!this->data_buffer)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = mtd->writesize / ecc->size;
+ int spare_bytes, bad_block_byte;
+ bool wide_bus;
+ int ecc_mode = 0;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 32) {
+ this->cw_size = 532;
+
+ spare_bytes = wide_bus ? 0 : 2;
+
+ this->bch_enabled = true;
+ ecc_mode = 1;
+ } else {
+ this->cw_size = 528;
+
+ if (this->ecc_modes & ECC_BCH_4BIT) {
+ spare_bytes = wide_bus ? 2 : 4;
+
+ this->bch_enabled = true;
+ ecc_mode = 0;
+ } else {
+ spare_bytes = wide_bus ? 0 : 1;
+ }
+ }
+
+ /*
+ * DATA_UD_BYTES varies based on whether the read/write command protects
+ * spare data with ECC too. We protect spare data by default, so we set
+ * it to main + spare data, which are 512 and 4 bytes respectively.
+ */
+ this->cw_data = 516;
+
+ bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
+
+ this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_data << UD_SIZE_BYTES
+ | 0 << DISABLE_STATUS_AFTER_WRITE
+ | 5 << NUM_ADDR_CYCLES
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
+ | 0 << STATUS_BFR_READ
+ | 1 << SET_RD_MODE_AFTER_STATUS
+ | spare_bytes << SPARE_SIZE_BYTES;
+
+ this->cfg1 = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | bad_block_byte << BAD_BLOCK_BYTE_NUM
+ | 0 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | this->bch_enabled << ENABLE_BCH_ECC;
+
+ this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_size << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
+ | 0 << ECC_SW_RESET
+ | this->cw_data << ECC_NUM_DATA_BYTES
+ | 1 << ECC_FORCE_CLK_OPEN
+ | ecc_mode << ECC_MODE
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
+
+ this->ecc_buf_cfg = 0x203 << NUM_STEPS;
+
+ this->clrflashstatus = FS_READY_BSY_N;
+ this->clrreadstatus = 0xc0;
+
+ dev_dbg(this->dev,
+ "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
+ this->cfg0, this->cfg1, this->ecc_buf_cfg,
+ this->ecc_bch_cfg, this->cw_size, this->cw_data,
+ ecc->strength, ecc->bytes, cwperpage);
+}
+
+static int qcom_nandc_alloc(struct qcom_nandc_data *this)
+{
+ int r;
+
+ r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
+ if (r) {
+ dev_err(this->dev, "failed to set DMA mask\n");
+ return r;
+ }
+
+ /*
+ * we don't know the page size of the NAND chip yet, set the buffer size
+ * to 512 bytes for now, that's sufficient for reading ID or ONFI params
+ */
+ this->buf_size = SZ_512;
+
+ this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
+ if (!this->data_buffer)
+ return -ENOMEM;
+
+ this->regs = devm_kzalloc(this->dev, sizeof(struct nandc_regs),
+ GFP_KERNEL);
+ if (!this->regs)
+ return -ENOMEM;
+
+ this->reg_read_buf = devm_kzalloc(this->dev, MAX_REG_RD * sizeof(u32),
+ GFP_KERNEL);
+ if (!this->reg_read_buf)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&this->list);
+
+ this->chan = dma_request_slave_channel(this->dev, "rxtx");
+ if (!this->chan) {
+ dev_err(this->dev, "failed to request slave channel\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
+{
+ dma_release_channel(this->chan);
+}
+
+static int qcom_nandc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct mtd_part_parser_data ppdata = {};
+ int r;
+
+ mtd->priv = chip;
+ mtd->name = "qcom-nandc";
+ mtd->owner = THIS_MODULE;
+
+ chip->priv = this;
+
+ chip->cmdfunc = qcom_nandc_command;
+ chip->select_chip = qcom_nandc_select_chip;
+ chip->read_byte = qcom_nandc_read_byte;
+ chip->read_buf = qcom_nandc_read_buf;
+ chip->write_buf = qcom_nandc_write_buf;
+
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+ chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW | NAND_BBT_USE_FLASH;
+
+ if (this->bus_width == 16)
+ chip->options |= NAND_BUSWIDTH_16;
+
+ qcom_nandc_pre_init(this);
+
+ r = nand_scan_ident(mtd, 1, NULL);
+ if (r)
+ return r;
+
+ r = qcom_nandc_ecc_init(this);
+ if (r)
+ return r;
+
+ qcom_nandc_hw_post_init(this);
+
+ r = nand_scan_tail(mtd);
+ if (r)
+ return r;
+
+
+ ppdata.of_node = this->dev->of_node;
+ r = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+ if (r)
+ return r;
+
+ return 0;
+}
+
+static int qcom_nandc_parse_dt(struct platform_device *pdev)
+{
+ struct device_node *np;
+ struct qcom_nandc_data *this;
+ int r;
+
+ np = pdev->dev.of_node;
+ if (!np)
+ return -ENODEV;
+
+ this = platform_get_drvdata(pdev);
+ if (!this)
+ return -ENODEV;
+
+ this->ecc_strength = of_get_nand_ecc_strength(np);
+ if (this->ecc_strength < 0) {
+ dev_warn(this->dev,
+ "incorrect ecc strength, setting to 4 bits/step\n");
+ this->ecc_strength = 4;
+ }
+
+ this->bus_width = of_get_nand_bus_width(np);
+ if (this->bus_width < 0) {
+ dev_warn(this->dev, "incorrect bus width, setting to 8\n");
+ this->bus_width = 8;
+ }
+
+ r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
+ if (r) {
+ dev_err(this->dev, "command CRCI unspecified\n");
+ return r;
+ }
+
+ r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
+ if (r) {
+ dev_err(this->dev, "data CRCI unspecified\n");
+ return r;
+ }
+
+ return 0;
+}
+
+#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
+
+static const struct of_device_id qcom_nandc_of_match[] = {
+ { .compatible = "qcom,ebi2-nandc",
+ .data = (void *) EBI2_NANDC_ECC_MODES,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
+
+static int qcom_nandc_probe(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this;
+ const struct of_device_id *match;
+ int r;
+
+ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
+ if (!this)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, this);
+
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+
+ match = of_match_node(qcom_nandc_of_match, pdev->dev.of_node);
+ if (!match) {
+ dev_err(&pdev->dev, "unsupported NANDc module\n");
+ return -ENODEV;
+ }
+
+ /* match->data will hold a struct pointer once we support more IPs */
+ this->ecc_modes = (u32) match->data;
+
+ this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ this->base = devm_ioremap_resource(&pdev->dev, this->res);
+ if (IS_ERR(this->base))
+ return PTR_ERR(this->base);
+
+ this->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(this->core_clk))
+ return PTR_ERR(this->core_clk);
+
+ this->aon_clk = devm_clk_get(&pdev->dev, "aon");
+ if (IS_ERR(this->aon_clk))
+ return PTR_ERR(this->aon_clk);
+
+ r = qcom_nandc_parse_dt(pdev);
+ if (r)
+ return r;
+
+ r = qcom_nandc_alloc(this);
+ if (r)
+ return r;
+
+ r = clk_prepare_enable(this->core_clk);
+ if (r)
+ goto err_core_clk;
+
+ r = clk_prepare_enable(this->aon_clk);
+ if (r)
+ goto err_aon_clk;
+
+ r = qcom_nandc_init(this);
+ if (r)
+ goto err_init;
+
+ return 0;
+
+err_init:
+ clk_disable_unprepare(this->aon_clk);
+err_aon_clk:
+ clk_disable_unprepare(this->core_clk);
+err_core_clk:
+ qcom_nandc_unalloc(this);
+
+ return r;
+}
+
+static int qcom_nandc_remove(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this;
+
+ this = platform_get_drvdata(pdev);
+ if (!this)
+ return -ENODEV;
+
+ qcom_nandc_unalloc(this);
+
+ clk_disable_unprepare(this->aon_clk);
+ clk_disable_unprepare(this->core_clk);
+
+ return 0;
+}
+
+static struct platform_driver qcom_nandc_driver = {
+ .driver = {
+ .name = "qcom-nandc",
+ .of_match_table = qcom_nandc_of_match,
+ },
+ .probe = qcom_nandc_probe,
+ .remove = qcom_nandc_remove,
+};
+module_platform_driver(qcom_nandc_driver);
+
+MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
+MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
+MODULE_LICENSE("GPL");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
2015-07-21 10:34 ` [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-07-21 10:34 ` [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
@ 2015-07-21 10:34 ` Archit Taneja
2015-07-24 18:57 ` Andy Gross
2015-07-24 19:37 ` Stephen Boyd
2015-07-21 10:34 ` [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-07-21 10:34 ` [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform Archit Taneja
4 siblings, 2 replies; 71+ messages in thread
From: Archit Taneja @ 2015-07-21 10:34 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja, devicetree
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
new file mode 100644
index 0000000..e24c77a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -0,0 +1,48 @@
+* Qualcomm NAND controller
+
+Required properties:
+- compatible: should be "qcom,ebi2-nand" for IPQ806x
+- reg: MMIO address range
+- clocks: must contain core clock and always on clock
+- clock-names: must contain "core" for the core clock and "aon" for the
+ always on clock
+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
+ controller node and the channel number to be used for
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
+- dma-names: must be "rxtx"
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+- qcom,data-crci: must contain the ADM data type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+
+Optional properties:
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
+ as default
+
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
+ bits. If not present, 4 is chosen as default
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand@0x1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ partition@0 {
+ ...
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
` (2 preceding siblings ...)
2015-07-21 10:34 ` [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
@ 2015-07-21 10:34 ` Archit Taneja
2015-07-24 19:01 ` Andy Gross
2015-07-21 10:34 ` [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform Archit Taneja
4 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-07-21 10:34 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja, devicetree
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 1e1b3f0..08dc2ef 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -350,5 +350,20 @@
status = "disabled";
};
+ nand@0x1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ status = "disabled";
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
` (3 preceding siblings ...)
2015-07-21 10:34 ` [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
@ 2015-07-21 10:34 ` Archit Taneja
2015-07-24 18:58 ` Andy Gross
2015-07-24 18:59 ` Andy Gross
4 siblings, 2 replies; 71+ messages in thread
From: Archit Taneja @ 2015-07-21 10:34 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja, devicetree
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..03fd6b7 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,28 @@
bias-none;
};
};
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
gsbi@16300000 {
@@ -93,5 +115,19 @@
sata@29000000 {
status = "ok";
};
+
+ nand@0x1ac00000 {
+ status = "ok";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ };
};
};
+
+&adm_dma {
+ status = "ok";
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings
2015-07-21 10:34 ` [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
@ 2015-07-24 18:57 ` Andy Gross
2015-07-24 19:37 ` Stephen Boyd
1 sibling, 0 replies; 71+ messages in thread
From: Andy Gross @ 2015-07-24 18:57 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, linux-kernel, devicetree
On Tue, Jul 21, 2015 at 04:04:44PM +0530, Archit Taneja wrote:
> Add DT bindings document for the Qualcomm NAND controller driver.
>
> Cc: devicetree@vger.kernel.org
>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
Acked-by: Andy Gross <agross@codeaurora.org>
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform
2015-07-21 10:34 ` [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform Archit Taneja
@ 2015-07-24 18:58 ` Andy Gross
2015-07-24 18:59 ` Andy Gross
1 sibling, 0 replies; 71+ messages in thread
From: Andy Gross @ 2015-07-24 18:58 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, linux-kernel, devicetree
On Tue, Jul 21, 2015 at 04:04:46PM +0530, Archit Taneja wrote:
> Enable the NAND controller node on the AP148 platform. Provide pinmux
> information.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
Looks fine.
Reviewed-by: Andy Gross <agross@codeaurora.org>
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform
2015-07-21 10:34 ` [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform Archit Taneja
2015-07-24 18:58 ` Andy Gross
@ 2015-07-24 18:59 ` Andy Gross
1 sibling, 0 replies; 71+ messages in thread
From: Andy Gross @ 2015-07-24 18:59 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, linux-kernel, devicetree
On Tue, Jul 21, 2015 at 04:04:46PM +0530, Archit Taneja wrote:
> Enable the NAND controller node on the AP148 platform. Provide pinmux
> information.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
One nit though. The subject mispells Enable.
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-07-21 10:34 ` [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
@ 2015-07-24 19:01 ` Andy Gross
0 siblings, 0 replies; 71+ messages in thread
From: Andy Gross @ 2015-07-24 19:01 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, linux-kernel
On Tue, Jul 21, 2015 at 04:04:42PM +0530, Archit Taneja wrote:
> Some controllers can access the factory bad block marker from OOB only
> when they read it in raw mode. When ECC is enabled, these controllers
> discard reading/writing bad block markers, preventing access to them
> altogether.
>
> The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
> This results in the nand driver's ecc->read_oob() op to be called, which
> works with ECC enabled.
>
> Create a new BBT option flag that tells nand_bbt to force the mode to
> MTD_OPS_RAW. This would result in the correct op being called for the
> underlying nand controller driver.
>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
Reviewed-by: Andy Gross <agross@codeaurora.org>
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x
2015-07-21 10:34 ` [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
@ 2015-07-24 19:01 ` Andy Gross
0 siblings, 0 replies; 71+ messages in thread
From: Andy Gross @ 2015-07-24 19:01 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, linux-kernel, devicetree
On Tue, Jul 21, 2015 at 04:04:45PM +0530, Archit Taneja wrote:
> The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
> compatible string.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
Reviewed-by: Andy Gross <agross@codeaurora.org>
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings
2015-07-21 10:34 ` [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2015-07-24 18:57 ` Andy Gross
@ 2015-07-24 19:37 ` Stephen Boyd
1 sibling, 0 replies; 71+ messages in thread
From: Stephen Boyd @ 2015-07-24 19:37 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, agross, linux-kernel, devicetree
On 07/21/2015 03:34 AM, Archit Taneja wrote:
> +
> +nand@0x1ac00000 {
s/0x//
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-21 10:34 ` [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
@ 2015-07-24 19:39 ` Andy Gross
2015-07-25 0:51 ` Stephen Boyd
1 sibling, 0 replies; 71+ messages in thread
From: Andy Gross @ 2015-07-24 19:39 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, linux-kernel
On Tue, Jul 21, 2015 at 04:04:43PM +0530, Archit Taneja wrote:
<snip>
>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
Reviewed-by: Andy Gross <agross@codeaurora.org>
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-21 10:34 ` [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-07-24 19:39 ` Andy Gross
@ 2015-07-25 0:51 ` Stephen Boyd
2015-07-28 4:34 ` Archit Taneja
1 sibling, 1 reply; 71+ messages in thread
From: Stephen Boyd @ 2015-07-25 0:51 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, agross, linux-kernel
On 07/21/2015 03:34 AM, Archit Taneja wrote:
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 5b2806a..31951fc 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -538,4 +538,11 @@ config MTD_NAND_HISI504
> help
> Enables support for NAND controller on Hisilicon SoC Hip04.
>
> +config MTD_NAND_QCOM
> + tristate "Support for NAND on QCOM SoCs"
> + depends on ARCH_QCOM && QCOM_ADM
This is sort of annoying that the menu won't show up unless the ADM
driver is also enabled (which would be in a completely different area of
the configurator). Perhaps drop that requirement because it isn't
required to build?
> + help
> + Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> + controller. This controller is found on IPQ806x SoC.
> +
> endif # MTD_NAND
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> new file mode 100644
> index 0000000..51c284c
> --- /dev/null
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -0,0 +1,2019 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/interrupt.h>
Where is this used?
> +#include <linux/bitops.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> +#include <linux/module.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_mtd.h>
> +#include <linux/delay.h>
> +
[..]
> +/*
> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> + * the driver calls the chunks 'step' or 'codeword' interchangeably
> + */
> +#define NANDC_STEP_SIZE 512
> +
> +/*
> + * the largest page size we support is 8K, this will have 16 steps/codewords
> + * of 512 bytes each
> + */
> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
> +
> +/* we read at most 3 registers per codeword scan */
> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
> +
> +/* ECC modes */
> +#define ECC_NONE BIT(0)
> +#define ECC_RS_4BIT BIT(1)
> +#define ECC_BCH_4BIT BIT(2)
> +#define ECC_BCH_8BIT BIT(3)
> +
> +struct desc_info {
> + struct list_head list;
> +
> + enum dma_transfer_direction dir;
> + struct scatterlist sgl;
> + struct dma_async_tx_descriptor *dma_desc;
> +};
> +
> +/*
> + * holds the current register values that we want to write. acts as a contiguous
> + * chunk of memory which we use to write the controller registers through DMA.
> + */
> +struct nandc_regs {
> + u32 cmd;
> + u32 addr0;
> + u32 addr1;
> + u32 chip_sel;
> + u32 exec;
> +
> + u32 cfg0;
> + u32 cfg1;
> + u32 ecc_bch_cfg;
> +
> + u32 clrflashstatus;
> + u32 clrreadstatus;
> +
> + u32 cmd1;
> + u32 vld;
> +
> + u32 orig_cmd1;
> + u32 orig_vld;
> +
> + u32 ecc_buf_cfg;
> +};
> +
> +/*
> + * @cmd_crci: ADM DMA CRCI for command flow control
> + * @data_crci: ADM DMA CRCI for data flow control
> + * @list: DMA descriptor list (list of desc_infos)
> + * @dma_done: completion param to denote end of last
> + * descriptor in the list
> + * @data_buffer: our local DMA buffer for page read/writes,
> + * used when we can't use the buffer provided
> + * by upper layers directly
> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
> + * @reg_read_buf: buffer for reading register data via DMA
> + * @reg_read_pos: marker for data read in reg_read_buf
> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
> + * ecc/non-ecc mode for the current nand flash
> + * device
> + * @regs: a contiguous chunk of memory for DMA register
> + * writes
> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
> + * @ecc_modes: supported ECC modes by the current controller,
> + * initialized via DT match data
> + * @cw_size: the number of bytes in a single step/codeword
> + * of a page, consisting of all data, ecc, spare
> + * and reserved bytes
> + * @cw_data: the number of bytes within a codeword protected
> + * by ECC
> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
> + * @status: value to be returned if NAND_CMD_STATUS command
> + * is executed
> + */
> +struct qcom_nandc_data {
> + struct platform_device *pdev;
> + struct device *dev;
> +
> + void __iomem *base;
> + struct resource *res;
> +
> + struct clk *core_clk;
> + struct clk *aon_clk;
> +
> + /* DMA stuff */
> + struct dma_chan *chan;
> + struct dma_slave_config slave_conf;
> + unsigned int cmd_crci;
> + unsigned int data_crci;
> + struct list_head list;
> + struct completion dma_done;
> +
> + /* MTD stuff */
> + struct nand_chip chip;
> + struct mtd_info mtd;
> +
> + /* local data buffer and markers */
> + u8 *data_buffer;
> + int buf_size;
> + int buf_count;
> + int buf_start;
> +
> + /* local buffer to read back registers */
> + u32 *reg_read_buf;
> + dma_addr_t reg_read_paddr;
Is this used?
> + int reg_read_pos;
> +
> + /* required configs */
> + u32 cfg0, cfg1;
> + u32 cfg0_raw, cfg1_raw;
> + u32 ecc_buf_cfg;
> + u32 ecc_bch_cfg;
> + u32 clrflashstatus;
> + u32 clrreadstatus;
> + u32 sflashc_burst_cfg;
> + u32 cmd1, vld;
> +
> + /* register state */
> + struct nandc_regs *regs;
> +
> + /* things we get from DT */
> + int ecc_strength;
> + int bus_width;
> +
> + u32 ecc_modes;
> +
> + /* misc params */
> + int cw_size;
> + int cw_data;
> + bool use_ecc;
> + bool bch_enabled;
> + u8 status;
> + int last_command;
> +};
> +
> +static inline unsigned int nandc_read(struct qcom_nandc_data *this, int offset)
> +{
> + return ioread32(this->base + offset);
> +}
> +
> +static inline void nandc_write(struct qcom_nandc_data *this, int offset,
> + unsigned int val)
> +{
> + iowrite32(val, this->base + offset);
> +}
Perhaps these should take and return u32s to match the signature of
ioread32/iowrite32
> +
> +/* helper to configure address register values */
> +static void set_address(struct qcom_nandc_data *this, u16 column, int page)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nandc_regs *regs = this->regs;
> +
> + if (chip->options & NAND_BUSWIDTH_16)
> + column >>= 1;
> +
> + regs->addr0 = page << 16 | column;
> + regs->addr1 = page >> 16 & 0xff;
> +}
> +
> +/*
> + * update_rw_regs: set up read/write register values, these will be
> + * written to the NAND controller registers via DMA
> + *
> + * @num_cw: number of steps for the read/write operation
> + * @read: read or write operation
> + */
> +static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + if (this->use_ecc) {
> + if (read)
> + regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
> + else
> + regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
> +
> + regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
> + (num_cw - 1) << CW_PER_PAGE;
> +
> + regs->cfg1 = this->cfg1;
> + regs->ecc_bch_cfg = this->ecc_bch_cfg;
> + } else {
> + if (read)
> + regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
> + else
> + regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
> +
> + regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
> + (num_cw - 1) << CW_PER_PAGE;
> +
> + regs->cfg1 = this->cfg1_raw;
> + regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
> + }
These two arms are almost exactly the same, except regs->cmd has
PAGE_READ_WITH_ECC vs PAGE_READ and regs->ecc_bch_cfg is different. It
should be possible to push the use_ecc case down into the two places
that need it and reduce lines.
> +
> + regs->ecc_buf_cfg = this->ecc_buf_cfg;
> + regs->clrflashstatus = this->clrflashstatus;
> + regs->clrreadstatus = this->clrreadstatus;
> + regs->exec = 1;
> +}
> +
> +/*
> + * write_reg_dma: prepares a descriptor to write a given number of
> + * contiguous registers
> + *
> + * @first: offset of the first register in the contiguous block
> + * @reg: starting address containing the reg values to write
> + * @num_regs: number of registers to write
> + * @flow_control: flow control enabled/disabled
> + */
> +static int write_reg_dma(struct qcom_nandc_data *this, int first, u32 *reg,
> + int num_regs, bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + int size;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + sgl = &desc->sgl;
> +
> + size = num_regs * sizeof(u32);
> +
> + sg_init_one(sgl, reg, size);
> +
> + desc->dir = DMA_MEM_TO_DEV;
> +
> + dma_map_sg(this->dev, sgl, 1, desc->dir);
> +
> + this->slave_conf.device_fc = flow_control ? 1 : 0;
> + this->slave_conf.dst_addr = this->res->start + first;
> + this->slave_conf.dst_maxburst = 16;
> + this->slave_conf.slave_id = this->cmd_crci;
> +
> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare register write desc\n");
> + r = PTR_ERR(dma_desc);
PTR_ERR(NULL) doesn't make sense. It would be nice if the DMA engine
APIs were documented so we knew if it returned NULL or an error pointer
on failure.
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
> +/*
BTW, this isn't kernel doc. That would need two asterisks.
> + * read_reg_dma: prepares a descriptor to read a given number of
> + * contiguous registers to the reg_read_buf pointer
> + *
> + * @first: offset of the first register in the contiguous block
> + * @num_regs: number of registers to read
> + * @flow_control: flow control enabled/disabled
> + */
> +static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs,
> + bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + int size;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + sgl = &desc->sgl;
> +
> + size = num_regs * sizeof(u32);
> +
> + sg_init_one(sgl, this->reg_read_buf + this->reg_read_pos, size);
> +
> + desc->dir = DMA_DEV_TO_MEM;
> +
> + dma_map_sg(this->dev, sgl, 1, desc->dir);
> +
> + this->slave_conf.device_fc = flow_control ? 1 : 0;
device_fc is a bool, so why the 1 : 0 trick? flow_control is already bool.
> + this->slave_conf.src_addr = this->res->start + first;
> + this->slave_conf.src_maxburst = 16;
> + this->slave_conf.slave_id = this->data_crci;
> +
> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare register read desc\n");
> + r = PTR_ERR(dma_desc);
Same problem here for PTR_ERR. Would be nice to figure out a way to
consolidate these DMA functions. They're only subtly different.
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + this->reg_read_pos += num_regs;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
[..]
> +
> +/*
> + * write_data_dma: prepares a DMA descriptor to transfer data from
> + * 'vaddr' to the controller's internal buffer
> + *
> + * @reg_off: offset within the controller's data buffer
> + * @vaddr: virtual address of the buffer we want to read from
> + * @size: DMA transaction size in bytes
> + */
> +static int write_data_dma(struct qcom_nandc_data *this, int reg_off, u8 *vaddr,
const u8 *vaddr?
> + int size)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + sgl = &desc->sgl;
> +
> + sg_init_one(sgl, vaddr, size);
> +
> + desc->dir = DMA_MEM_TO_DEV;
> +
> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
> + if (r == 0)
> + goto err;
Should we return an error in this case? Looks like return 0.
> +
> + this->slave_conf.device_fc = 0;
> + this->slave_conf.dst_addr = this->res->start + reg_off;
> + this->slave_conf.dst_maxburst = 16;
Is there any reason why slave_conf can't be on the stack? Otherwise it's
odd that it's overwritten a few times before we submit the descriptors,
so it must be copied by the dmaengine provider, but that isn't clear at
all from the code. If it isn't copied, perhaps it should be part of the
desc_info structure. If it is copied I wonder why it isn't const in the
function signature.
> +
> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare data write desc\n");
> + r = PTR_ERR(dma_desc);
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
> +/*
> + * helper to prepare dma descriptors to configure registers needed for reading a
> + * codeword/step in a page
> + */
> +static void config_cw_read(struct qcom_nandc_data *this)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
Maybe it would be better to have a case statement inside
{write,read}_reg_dma() that looked at the second argument and matched it
up with an offset in regs. Then this could be
write_reg_dma(this, NAND_FLASH_CMD, 3, true);
and we wouldn't have to worry about having the wrong argument for
parameter 2 and parameter 3. It may even be that we always read the same
number of registers too? In which case we could move parameter 4 into
the case statement too?
> + write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
> + 1, false);
> +
> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 2, true);
> + read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1, false);
> +}
> +
[...]
> +/* sets up descriptors for NAND_CMD_RESET */
> +static int reset(struct qcom_nandc_data *this)
> +{
> + struct nandc_regs *regs = this->regs;
> +
> + regs->cmd = RESET_DEVICE;
> + regs->exec = 1;
> +
> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 1, true);
> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
> +
> + return 0;
> +}
> +
> +/* helpers to submit/free our list of dma descriptors */
> +static void dma_callback(void *param)
> +{
> + struct qcom_nandc_data *this = (struct qcom_nandc_data *) param;
Useless cast.
> + struct completion *c = &this->dma_done;
> +
> + complete(c);
> +}
> +
> +static int submit_descs(struct qcom_nandc_data *this)
> +{
> + struct completion *c = &this->dma_done;
> + struct desc_info *desc;
> + int r;
> +
> + init_completion(c);
> +
> + list_for_each_entry(desc, &this->list, list) {
> + /*
> + * we add a callback the last descriptor in our list to notify
to the last?
> + * completion of command
> + */
> + if (list_is_last(&desc->list, &this->list)) {
> + desc->dma_desc->callback = dma_callback;
> + desc->dma_desc->callback_param = this;
> + }
> +
> + dmaengine_submit(desc->dma_desc);
> + }
> +
> + dma_async_issue_pending(this->chan);
> +
> + r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
> + if (!r)
> + return -EINVAL;
Why not -ETIMEDOUT?
> +
> + return 0;
> +}
> +
[...]
> +
> +/*
> + * when using RS ECC, the NAND controller flags an error when reading an
> + * erased page. however, there are special characters at certain offsets when
> + * we read the erased page. we check here if the page is really empty. if so,
> + * we replace the magic characters with 0xffs
> + */
> +static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + int i;
> +
> + /* if BCH is enabled, HW will take care of detecting erased pages */
> + if (this->bch_enabled || !this->use_ecc)
> + return false;
> +
> + for (i = 0; i < cwperpage; i++) {
> + u8 *empty1, *empty2;
> + u32 flash_status = this->reg_read_buf[3 * i];
> +
> + /*
> + * an erased page flags an error in NAND_FLASH_STATUS, check if
> + * the page is erased by looking for 0x54s at offsets 3 and 175
> + * from the beginning of each codeword
> + */
> + if (flash_status & FS_OP_ERR) {
> + empty1 = &data_buf[3 + i * this->cw_data];
> + empty2 = &data_buf[175 + i * this->cw_data];
> +
> + /*
> + * the error wasn't because of an erased page, bail out
> + * and let someone else do the error checking
> + */
> + if (!((*empty1 == 0x54 && *empty2 == 0xff) ||
> + (*empty1 == 0xff && *empty2 == 0x54)))
Why are we using pointers? Just use u8 empty1, empty2 = data_buf[...] ?
> + return false;
> + }
> + }
> +
> + for (i = 0; i < mtd->writesize && (data_buf[i] == 0xff ||
> + (i % this->cw_data == 3 || i % this->cw_data == 175)); i++) {
> + }
This might be clearer like so:
for (i = 0; i < mtd->writesize; i++) {
if (i % this->cw_data == 3 || i % this->cw_data == 175);
continue;
if (data_buf[i] != 0xff)
return false;
}
and then drop the if after the loop. Actually since we're checking the
whole page it may be better to do this:
+
+ /*
+ * the whole page is 0xffs besides the magic offsets, we replace the
+ * 0x54s with 0xffs
+ */
+ for (i = 0; i < cwperpage; i++) {
+ data_buf[3 + i * this->cw_data] = 0xff;
+ data_buf[175 + i * this->cw_data] = 0xff;
+ }
+
and then
return memchr_inv(data_buf, 0xff, mtd->writesize) ? false : true ;
the memchr_inv() is optimized to find the bad characters 8 bytes at a time.
> +
> + if (i < mtd->writesize)
> + return false;
> +
> + /*
> + * the whole page is 0xffs besides the magic offsets, we replace the
> + * 0x54s with 0xffs
> + */
> + for (i = 0; i < cwperpage; i++) {
> + data_buf[3 + i * this->cw_data] = 0xff;
> + data_buf[175 + i * this->cw_data] = 0xff;
> + }
> +
> + /*
> + * tell the caller that the page was empty and is fixed up, so that
> + * parse_read_errors() doesn't think it's and error
> + */
> + return true;
> +}
> +
> +/*
> + * reads back status registers set by the controller to notify page read
> + * errors. this is equivalent to what 'ecc->correct()' would do.
> + */
> +static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + unsigned int max_bitflips = 0;
> + int i;
> +
> + for (i = 0; i < cwperpage; i++) {
> + int stat;
> + u32 flash_status = this->reg_read_buf[3 * i];
> + u32 buffer_status = this->reg_read_buf[3 * i + 1];
> + u32 erased_cw_status = this->reg_read_buf[3 * i + 2];
struct stats {
u32 flash;
u32 buffer;
u32 erased_cw;
};
struct stats *buf = (struct stat *)this->reg_read_buf;
for (i = 0; i < cwperpage; i++, buf++) {
int stat;
if (buf->flash & (FS_OP_ERR | FS_MPU_ERR))
?
Also, is the buffer little endian? If so, that should be a __le32 flash,
__le32 buffer, etc. up there and then le32_to_cpu().
> +
> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
> +
> + /* ignore erased codeword errors */
> + if (this->bch_enabled) {
> + if ((erased_cw_status & ERASED_CW) == ERASED_CW)
> + continue;
> + } else if (erased_page) {
> + continue;
> + }
> +
> + if (buffer_status & BS_UNCORRECTABLE_BIT) {
> + mtd->ecc_stats.failed++;
> + continue;
> + }
> + }
> +
> + stat = buffer_status & BS_CORRECTABLE_ERR_MSK;
> + mtd->ecc_stats.corrected += stat;
> +
> + max_bitflips = max_t(unsigned int, max_bitflips, stat);
> + }
> +
> + return max_bitflips;
> +}
> +
> +/*
> + * helper to perform the actual page read operation, used by ecc->read_page()
> + * and ecc->read_oob()
> + */
> +static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf,
> + u8 *oob_buf)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int i, r;
> +
> + /* queue cmd descs for each codeword */
> + for (i = 0; i < ecc->steps; i++) {
> + int data_size, oob_size;
> +
> + if (i == (ecc->steps - 1)) {
> + data_size = ecc->size - ((ecc->steps - 1) << 2);
> + oob_size = (ecc->steps << 2) + ecc->bytes;
> + } else {
> + data_size = this->cw_data;
> + oob_size = ecc->bytes;
> + }
> +
> + config_cw_read(this);
> +
> + if (data_buf)
> + read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
> +
> + if (oob_buf)
> + read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf,
> + oob_size);
> +
> + if (data_buf)
> + data_buf += data_size;
> + if (oob_buf)
> + oob_buf += oob_size;
> + }
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failure to read page/oob\n");
> +
> + free_descs(this);
> +
> + return r;
> +}
> +
> +/*
> + * a helper that copies the last step/codeword of a page (containing free oob)
> + * into our local buffer
> + */
> +static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int size;
> + int r;
> +
> + clear_read_regs(this);
> +
> + size = use_ecc ? this->cw_data : this->cw_size;
> +
> + /* prepare a clean read buffer */
> + memset(this->data_buffer, 0xff, size);
> +
> + this->use_ecc = use_ecc;
> + set_address(this, this->cw_size * (ecc->steps - 1), page);
> + update_rw_regs(this, 1, true);
> +
> + config_cw_read(this);
> +
> + read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size);
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failed to copy last codeword\n");
> +
> + free_descs(this);
> +
> + return r;
> +}
> +
> +/* implements ecc->read_page() */
> +static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
> + uint8_t *buf, int oob_required, int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + u8 *data_buf, *oob_buf = NULL;
> + bool direct_dma, erased_page;
> + int r;
> +
> + /*
> + * first try to map the upper buffer directly, else, use our own buf
> + * and memcpy to upper buf
> + */
> + if (virt_addr_valid(buf) && !object_is_on_stack(buf)) {
> + direct_dma = true;
> + data_buf = buf;
> + } else {
> + direct_dma = false;
> + data_buf = this->data_buffer;
> + memset(data_buf, 0xff, mtd->writesize + mtd->oobsize);
> + }
> +
> + oob_buf = oob_required ? chip->oob_poi : NULL;
> +
> + r = read_page_low(this, data_buf, oob_buf);
> + if (r) {
> + dev_err(this->dev, "failure to read page\n");
> + goto err;
return r?
> + }
> +
> + erased_page = empty_page_fixup(this, data_buf);
> +
> + if (!direct_dma)
> + memcpy(buf, this->data_buffer, mtd->writesize);
> +
> + r = parse_read_errors(this, erased_page);
> +err:
> + return r;
and then return parse_read_errors()?
> +}
> +
> +/* implements ecc->read_oob() */
> +static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int r;
> +
> + clear_read_regs(this);
> +
> + this->use_ecc = true;
> + set_address(this, 0, page);
> + update_rw_regs(this, ecc->steps, true);
> +
> + r = read_page_low(this, NULL, chip->oob_poi);
> + if (r)
> + dev_err(this->dev, "failure to read oob\n");
> +
> + return r;
> +}
> +
> +/* implements ecc->read_oob_raw(), used to read the bad block marker flag */
> +static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + uint8_t *oob = chip->oob_poi;
> + int start, length;
> + int r;
> +
> + /*
> + * configure registers for a raw page read, the address is set to the
> + * beginning of the last codeword, we don't care about reading ecc
> + * portion of oob, just the free stuff
> + */
> + r = copy_last_cw(this, false, page);
> + if (r)
> + return r;
> +
> + /*
> + * reading raw oob has 2 parts, first the bad block byte, then the
> + * actual free oob region. perform a memcpy in two steps
> + */
> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
> +
> + memcpy(oob, this->data_buffer + start, length);
> +
> + oob += length;
> +
> + start = this->cw_data - (ecc->steps << 2) + 1;
> + length = ecc->steps << 2;
> +
> + memcpy(oob, this->data_buffer + start, length);
> +
> + return 0;
> +}
> +
> +/* implements ecc->write_page() */
> +static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> + const uint8_t *buf, int oob_required)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + u8 *data_buf, *oob_buf;
> + bool direct_dma;
> + int i, r = 0;
> +
> + clear_read_regs(this);
> +
> + /*
> + * first try to map the upper buffer directly, else, memcpy upper
> + * buffer to our local buffer
> + */
> + direct_dma = virt_addr_valid(buf) && !object_is_on_stack((void *) buf);
We should change object_is_on_stack() to take a const pointer.
Are we guaranteed that this is called within the same context as where
the buffer is passed to this function? Otherwise this stack check isn't
going to work because object_is_on_stack() will silently fail.
> +
> + if (!direct_dma) {
> + memcpy(this->data_buffer, buf, mtd->writesize
> );
> + data_buf = this->data_buffer;
> + } else {
> + data_buf = (u8 *) buf;
Shouldn't need to cast away const...
> + }
> +
> + oob_buf = chip->oob_poi;
> +
> + this->use_ecc = true;
> + update_rw_regs(this, ecc->steps, false);
> +
> + for (i = 0; i < ecc->steps; i++) {
> + int data_size, oob_size;
> +
> + if (i == (ecc->steps - 1)) {
> + data_size = ecc->size - ((ecc->steps - 1) << 2);
> + oob_size = (ecc->steps << 2) + ecc->bytes;
> + } else {
> + data_size = this->cw_data;
> + oob_size = ecc->bytes;
> + }
> +
> + config_cw_write_pre(this);
> + write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
> +
> + /*
> + * we don't really need to write anything to oob for the
> + * first n - 1 codewords since these oob regions just
> + * contain ecc that's written by the controller itself
> + */
> + if (i == (ecc->steps - 1))
> + write_data_dma(this, FLASH_BUF_ACC + data_size,
> + oob_buf, oob_size);
> + config_cw_write_post(this);
> +
> + data_buf += data_size;
> + oob_buf += oob_size;
> + }
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failure to write page\n");
> +
> + free_descs(this);
> +
> + return r;
> +}
> +
> +/*
> + * implements ecc->write_oob()
> + *
> + * the NAND controller cannot write only data or only oob within a codeword,
> + * since ecc is calculated for the combined codeword. we first copy the
> + * entire contents for the last codeword(data + oob), replace the old oob
> + * with the new one in chip->oob_poi, and then write the entire codeword.
> + * this read-copy-write operation results in a slight perormance loss.
> + */
> +static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + uint8_t *oob = chip->oob_poi;
> + int free_boff;
> + int data_size, oob_size;
> + int r, status = 0;
> +
> + r = copy_last_cw(this, true, page);
> + if (r)
> + return r;
> +
> + clear_read_regs(this);
> +
> + /* calculate the data and oob size for the last codeword/step */
> + data_size = ecc->size - ((ecc->steps - 1) << 2);
> + oob_size = (ecc->steps << 2) + ecc->bytes;
> +
> + /*
> + * the location of spare data in the oob buffer, we could also use
> + * ecc->layout.oobfree here
> + */
> + free_boff = ecc->bytes * (ecc->steps - 1);
> +
> + /* override new oob content to last codeword */
> + memcpy(this->data_buffer + data_size, oob + free_boff, oob_size);
> +
> + this->use_ecc = true;
> + set_address(this, this->cw_size * (ecc->steps - 1), page);
> + update_rw_regs(this, 1, false);
> +
> + config_cw_write_pre(this);
> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer,
> + data_size + oob_size);
> + config_cw_write_post(this);
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failure to write oob\n");
> +
> + free_descs(this);
> +
> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +
> + status = chip->waitfunc(mtd, chip);
Should we wait if the submission failed?
> +
> + return status & NAND_STATUS_FAIL ? -EIO : 0;
> +}
> +
> +/* implements ecc->write_oob_raw(), used to write bad block marker flag */
> +static int qcom_nandc_write_oob_raw(struct mtd_info *mtd,
> + struct nand_chip *chip, int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + uint8_t *oob = chip->oob_poi;
> + int start, length;
> + int r, status = 0;
> +
> + r = copy_last_cw(this, false, page);
> + if (r)
> + return r;
> +
> + clear_read_regs(this);
> +
> + /*
> + * writing raw oob has 2 parts, first the bad block region, then the
> + * actual free region
> + */
> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
> +
> + memcpy(this->data_buffer + start, oob, length);
> +
> + oob += length;
> +
> + start = this->cw_data - (ecc->steps << 2) + 1;
> + length = ecc->steps << 2;
> +
> + memcpy(this->data_buffer + start, oob, length);
> +
> + /* prepare write */
> + this->use_ecc = false;
> + set_address(this, this->cw_size * (ecc->steps - 1), page);
> + update_rw_regs(this, 1, false);
> +
> + config_cw_write_pre(this);
> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size);
> + config_cw_write_post(this);
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failure to write updated oob\n");
> +
> + free_descs(this);
> +
> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +
> + status = chip->waitfunc(mtd, chip);
Ditto.
> +
> + return status & NAND_STATUS_FAIL ? -EIO : 0;
> +}
> +
> +/*
> + * the three functions below implement chip->read_byte(), chip->read_buf()
> + * and chip->write_buf() respectively. these aren't used for
> + * reading/writing page data, they are used for smaller data like reading
> + * id, status etc
> + */
> +static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> + uint8_t *buf = (uint8_t *) this->data_buffer;
isn't it already uint8_t?
> + uint8_t ret = 0x0;
> +
> + if (this->last_command == NAND_CMD_STATUS) {
> + ret = this->status;
> +
> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> +
> + return ret;
> + }
> +
> + if (this->buf_start < this->buf_count)
> + ret = buf[this->buf_start++];
> +
> + return ret;
> +}
> +
[...]
> +
> +static int qcom_nandc_alloc(struct qcom_nandc_data *this)
> +{
> + int r;
> +
> + r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
> + if (r) {
> + dev_err(this->dev, "failed to set DMA mask\n");
> + return r;
> + }
> +
> + /*
> + * we don't know the page size of the NAND chip yet, set the buffer size
> + * to 512 bytes for now, that's sufficient for reading ID or ONFI params
> + */
> + this->buf_size = SZ_512;
> +
> + this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
> + if (!this->data_buffer)
> + return -ENOMEM;
> +
> + this->regs = devm_kzalloc(this->dev, sizeof(struct nandc_regs),
sizeof(*this->regs)?
> + GFP_KERNEL);
> + if (!this->regs)
> + return -ENOMEM;
> +
> + this->reg_read_buf = devm_kzalloc(this->dev, MAX_REG_RD * sizeof(u32),
> + GFP_KERNEL);
devm_kcalloc() and sizeof(*this->reg_read_buf) ?
> + if (!this->reg_read_buf)
> + return -ENOMEM;
> +
> + INIT_LIST_HEAD(&this->list);
> +
> + this->chan = dma_request_slave_channel(this->dev, "rxtx");
> + if (!this->chan) {
> + dev_err(this->dev, "failed to request slave channel\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
> +{
> + dma_release_channel(this->chan);
> +}
> +
> +static int qcom_nandc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct mtd_part_parser_data ppdata = {};
> + int r;
> +
> + mtd->priv = chip;
> + mtd->name = "qcom-nandc";
> + mtd->owner = THIS_MODULE;
> +
> + chip->priv = this;
> +
> + chip->cmdfunc = qcom_nandc_command;
> + chip->select_chip = qcom_nandc_select_chip;
> + chip->read_byte = qcom_nandc_read_byte;
> + chip->read_buf = qcom_nandc_read_buf;
> + chip->write_buf = qcom_nandc_write_buf;
> +
> + chip->options |= NAND_NO_SUBPAGE_WRITE;
> + chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW | NAND_BBT_USE_FLASH;
> +
> + if (this->bus_width == 16)
> + chip->options |= NAND_BUSWIDTH_16;
> +
> + qcom_nandc_pre_init(this);
> +
> + r = nand_scan_ident(mtd, 1, NULL);
> + if (r)
> + return r;
> +
> + r = qcom_nandc_ecc_init(this);
> + if (r)
> + return r;
> +
> + qcom_nandc_hw_post_init(this);
> +
> + r = nand_scan_tail(mtd);
> + if (r)
> + return r;
> +
> +
Weird double newline here.
> + ppdata.of_node = this->dev->of_node;
> + r = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
> + if (r)
> + return r;
> +
> + return 0;
Could be simplified to return mtd_device_parse_register(...).
> +}
> +
[..]
> +
> +static int qcom_nandc_remove(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this;
> +
> + this = platform_get_drvdata(pdev);
> + if (!this)
> + return -ENODEV;
This seems impossible, so why check for it?
> +
> + qcom_nandc_unalloc(this);
> +
> + clk_disable_unprepare(this->aon_clk);
> + clk_disable_unprepare(this->core_clk);
> +
> + return 0;
> +}
> +
> +static struct platform_driver qcom_nandc_driver = {
> + .driver = {
> + .name = "qcom-nandc",
> + .of_match_table = qcom_nandc_of_match,
> + },
> + .probe = qcom_nandc_probe,
> + .remove = qcom_nandc_remove,
> +};
> +module_platform_driver(qcom_nandc_driver);
> +
> +MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
> +MODULE_LICENSE("GPL");
This should say GPL v2 explicitly.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-25 0:51 ` Stephen Boyd
@ 2015-07-28 4:34 ` Archit Taneja
2015-07-29 1:48 ` Stephen Boyd
0 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-07-28 4:34 UTC (permalink / raw)
To: Stephen Boyd
Cc: dehrenberg, linux-arm-msm, cernekee, linux-kernel, linux-mtd,
agross, computersforpeace
Hi,
On 07/25/2015 06:21 AM, Stephen Boyd wrote:
> On 07/21/2015 03:34 AM, Archit Taneja wrote:
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 5b2806a..31951fc 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -538,4 +538,11 @@ config MTD_NAND_HISI504
>> help
>> Enables support for NAND controller on Hisilicon SoC Hip04.
>>
>> +config MTD_NAND_QCOM
>> + tristate "Support for NAND on QCOM SoCs"
>> + depends on ARCH_QCOM && QCOM_ADM
>
> This is sort of annoying that the menu won't show up unless the ADM
> driver is also enabled (which would be in a completely different area of
> the configurator). Perhaps drop that requirement because it isn't
> required to build?
That makes sense. I'll drop the QCOM_ADM requirement.
>
>> + help
>> + Enables support for NAND flash chips on SoCs containing the EBI2 NAND
>> + controller. This controller is found on IPQ806x SoC.
>> +
>> endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
>> new file mode 100644
>> index 0000000..51c284c
>> --- /dev/null
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -0,0 +1,2019 @@
>> +/*
>> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/slab.h>
>> +#include <linux/interrupt.h>
>
> Where is this used?
It isn't. I'll remove it.
>
>> +#include <linux/bitops.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/dmaengine.h>
>> +#include <linux/module.h>
>> +#include <linux/mtd/nand.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/of_mtd.h>
>> +#include <linux/delay.h>
>> +
> [..]
>> +/*
>> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>> + * the driver calls the chunks 'step' or 'codeword' interchangeably
>> + */
>> +#define NANDC_STEP_SIZE 512
>> +
>> +/*
>> + * the largest page size we support is 8K, this will have 16 steps/codewords
>> + * of 512 bytes each
>> + */
>> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
>> +
>> +/* we read at most 3 registers per codeword scan */
>> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
>> +
>> +/* ECC modes */
>> +#define ECC_NONE BIT(0)
>> +#define ECC_RS_4BIT BIT(1)
>> +#define ECC_BCH_4BIT BIT(2)
>> +#define ECC_BCH_8BIT BIT(3)
>> +
>> +struct desc_info {
>> + struct list_head list;
>> +
>> + enum dma_transfer_direction dir;
>> + struct scatterlist sgl;
>> + struct dma_async_tx_descriptor *dma_desc;
>> +};
>> +
>> +/*
>> + * holds the current register values that we want to write. acts as a contiguous
>> + * chunk of memory which we use to write the controller registers through DMA.
>> + */
>> +struct nandc_regs {
>> + u32 cmd;
>> + u32 addr0;
>> + u32 addr1;
>> + u32 chip_sel;
>> + u32 exec;
>> +
>> + u32 cfg0;
>> + u32 cfg1;
>> + u32 ecc_bch_cfg;
>> +
>> + u32 clrflashstatus;
>> + u32 clrreadstatus;
>> +
>> + u32 cmd1;
>> + u32 vld;
>> +
>> + u32 orig_cmd1;
>> + u32 orig_vld;
>> +
>> + u32 ecc_buf_cfg;
>> +};
>> +
>> +/*
>> + * @cmd_crci: ADM DMA CRCI for command flow control
>> + * @data_crci: ADM DMA CRCI for data flow control
>> + * @list: DMA descriptor list (list of desc_infos)
>> + * @dma_done: completion param to denote end of last
>> + * descriptor in the list
>> + * @data_buffer: our local DMA buffer for page read/writes,
>> + * used when we can't use the buffer provided
>> + * by upper layers directly
>> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
>> + * @reg_read_buf: buffer for reading register data via DMA
>> + * @reg_read_pos: marker for data read in reg_read_buf
>> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
>> + * ecc/non-ecc mode for the current nand flash
>> + * device
>> + * @regs: a contiguous chunk of memory for DMA register
>> + * writes
>> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
>> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
>> + * @ecc_modes: supported ECC modes by the current controller,
>> + * initialized via DT match data
>> + * @cw_size: the number of bytes in a single step/codeword
>> + * of a page, consisting of all data, ecc, spare
>> + * and reserved bytes
>> + * @cw_data: the number of bytes within a codeword protected
>> + * by ECC
>> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
>> + * @status: value to be returned if NAND_CMD_STATUS command
>> + * is executed
>> + */
>> +struct qcom_nandc_data {
>> + struct platform_device *pdev;
>> + struct device *dev;
>> +
>> + void __iomem *base;
>> + struct resource *res;
>> +
>> + struct clk *core_clk;
>> + struct clk *aon_clk;
>> +
>> + /* DMA stuff */
>> + struct dma_chan *chan;
>> + struct dma_slave_config slave_conf;
>> + unsigned int cmd_crci;
>> + unsigned int data_crci;
>> + struct list_head list;
>> + struct completion dma_done;
>> +
>> + /* MTD stuff */
>> + struct nand_chip chip;
>> + struct mtd_info mtd;
>> +
>> + /* local data buffer and markers */
>> + u8 *data_buffer;
>> + int buf_size;
>> + int buf_count;
>> + int buf_start;
>> +
>> + /* local buffer to read back registers */
>> + u32 *reg_read_buf;
>> + dma_addr_t reg_read_paddr;
>
> Is this used?
No, it isn't. It's a leftover from when I used dma_alloc_coherent for
this buffer. Will remove it.
>
>> + int reg_read_pos;
>> +
>> + /* required configs */
>> + u32 cfg0, cfg1;
>> + u32 cfg0_raw, cfg1_raw;
>> + u32 ecc_buf_cfg;
>> + u32 ecc_bch_cfg;
>> + u32 clrflashstatus;
>> + u32 clrreadstatus;
>> + u32 sflashc_burst_cfg;
>> + u32 cmd1, vld;
>> +
>> + /* register state */
>> + struct nandc_regs *regs;
>> +
>> + /* things we get from DT */
>> + int ecc_strength;
>> + int bus_width;
>> +
>> + u32 ecc_modes;
>> +
>> + /* misc params */
>> + int cw_size;
>> + int cw_data;
>> + bool use_ecc;
>> + bool bch_enabled;
>> + u8 status;
>> + int last_command;
>> +};
>> +
>> +static inline unsigned int nandc_read(struct qcom_nandc_data *this, int offset)
>> +{
>> + return ioread32(this->base + offset);
>> +}
>> +
>> +static inline void nandc_write(struct qcom_nandc_data *this, int offset,
>> + unsigned int val)
>> +{
>> + iowrite32(val, this->base + offset);
>> +}
>
> Perhaps these should take and return u32s to match the signature of
> ioread32/iowrite32
I'll fix this.
>
>> +
>> +/* helper to configure address register values */
>> +static void set_address(struct qcom_nandc_data *this, u16 column, int page)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> + struct nandc_regs *regs = this->regs;
>> +
>> + if (chip->options & NAND_BUSWIDTH_16)
>> + column >>= 1;
>> +
>> + regs->addr0 = page << 16 | column;
>> + regs->addr1 = page >> 16 & 0xff;
>> +}
>> +
>> +/*
>> + * update_rw_regs: set up read/write register values, these will be
>> + * written to the NAND controller registers via DMA
>> + *
>> + * @num_cw: number of steps for the read/write operation
>> + * @read: read or write operation
>> + */
>> +static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
>> +{
>> + struct nandc_regs *regs = this->regs;
>> +
>> + if (this->use_ecc) {
>> + if (read)
>> + regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
>> + else
>> + regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
>> +
>> + regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
>> + (num_cw - 1) << CW_PER_PAGE;
>> +
>> + regs->cfg1 = this->cfg1;
>> + regs->ecc_bch_cfg = this->ecc_bch_cfg;
>> + } else {
>> + if (read)
>> + regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
>> + else
>> + regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
>> +
>> + regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
>> + (num_cw - 1) << CW_PER_PAGE;
>> +
>> + regs->cfg1 = this->cfg1_raw;
>> + regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
>> + }
>
> These two arms are almost exactly the same, except regs->cmd has
> PAGE_READ_WITH_ECC vs PAGE_READ and regs->ecc_bch_cfg is different. It
> should be possible to push the use_ecc case down into the two places
> that need it and reduce lines.
cfg0 and cfg1 are set differently too, they need to be set to cfg0_raw
and cfg1_raw when use_ecc isn't set.
The only one line that I can save is the extra common PROGRAM_PAGE
assignment that's same irrespective of use_ecc. I'll do that.
>
>> +
>> + regs->ecc_buf_cfg = this->ecc_buf_cfg;
>> + regs->clrflashstatus = this->clrflashstatus;
>> + regs->clrreadstatus = this->clrreadstatus;
>> + regs->exec = 1;
>> +}
>> +
>> +/*
>> + * write_reg_dma: prepares a descriptor to write a given number of
>> + * contiguous registers
>> + *
>> + * @first: offset of the first register in the contiguous block
>> + * @reg: starting address containing the reg values to write
>> + * @num_regs: number of registers to write
>> + * @flow_control: flow control enabled/disabled
>> + */
>> +static int write_reg_dma(struct qcom_nandc_data *this, int first, u32 *reg,
>> + int num_regs, bool flow_control)
>> +{
>> + struct desc_info *desc;
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct scatterlist *sgl;
>> + int size;
>> + int r;
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + list_add_tail(&desc->list, &this->list);
>> +
>> + sgl = &desc->sgl;
>> +
>> + size = num_regs * sizeof(u32);
>> +
>> + sg_init_one(sgl, reg, size);
>> +
>> + desc->dir = DMA_MEM_TO_DEV;
>> +
>> + dma_map_sg(this->dev, sgl, 1, desc->dir);
>> +
>> + this->slave_conf.device_fc = flow_control ? 1 : 0;
>> + this->slave_conf.dst_addr = this->res->start + first;
>> + this->slave_conf.dst_maxburst = 16;
>> + this->slave_conf.slave_id = this->cmd_crci;
>> +
>> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
>> + if (r) {
>> + dev_err(this->dev, "failed to configure dma channel\n");
>> + goto err;
>> + }
>> +
>> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
>> + if (!dma_desc) {
>> + dev_err(this->dev, "failed to prepare register write desc\n");
>> + r = PTR_ERR(dma_desc);
>
> PTR_ERR(NULL) doesn't make sense. It would be nice if the DMA engine
> APIs were documented so we knew if it returned NULL or an error pointer
> on failure.
Yes, this is wrong. I have to fix this habit of mixing error pointer and
NULL return values. Will fix it.
>
>> + goto err;
>> + }
>> +
>> + desc->dma_desc = dma_desc;
>> +
>> + return 0;
>> +err:
>> + kfree(desc);
>> +
>> + return r;
>> +}
>> +
>> +/*
>
> BTW, this isn't kernel doc. That would need two asterisks.
I didn't intend them to be a part of the kernel doc. I kept a kernel
doc like format at a few places since it was legible.
>
>> + * read_reg_dma: prepares a descriptor to read a given number of
>> + * contiguous registers to the reg_read_buf pointer
>> + *
>> + * @first: offset of the first register in the contiguous block
>> + * @num_regs: number of registers to read
>> + * @flow_control: flow control enabled/disabled
>> + */
>> +static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs,
>> + bool flow_control)
>> +{
>> + struct desc_info *desc;
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct scatterlist *sgl;
>> + int size;
>> + int r;
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + list_add_tail(&desc->list, &this->list);
>> +
>> + sgl = &desc->sgl;
>> +
>> + size = num_regs * sizeof(u32);
>> +
>> + sg_init_one(sgl, this->reg_read_buf + this->reg_read_pos, size);
>> +
>> + desc->dir = DMA_DEV_TO_MEM;
>> +
>> + dma_map_sg(this->dev, sgl, 1, desc->dir);
>> +
>> + this->slave_conf.device_fc = flow_control ? 1 : 0;
>
> device_fc is a bool, so why the 1 : 0 trick? flow_control is already bool.
I'll fix this.
>
>> + this->slave_conf.src_addr = this->res->start + first;
>> + this->slave_conf.src_maxburst = 16;
>> + this->slave_conf.slave_id = this->data_crci;
>> +
>> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
>> + if (r) {
>> + dev_err(this->dev, "failed to configure dma channel\n");
>> + goto err;
>> + }
>> +
>> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
>> + if (!dma_desc) {
>> + dev_err(this->dev, "failed to prepare register read desc\n");
>> + r = PTR_ERR(dma_desc);
>
> Same problem here for PTR_ERR. Would be nice to figure out a way to
> consolidate these DMA functions. They're only subtly different.
I'll try this out.
>
>> + goto err;
>> + }
>> +
>> + desc->dma_desc = dma_desc;
>> +
>> + this->reg_read_pos += num_regs;
>> +
>> + return 0;
>> +err:
>> + kfree(desc);
>> +
>> + return r;
>> +}
>> +
> [..]
>> +
>> +/*
>> + * write_data_dma: prepares a DMA descriptor to transfer data from
>> + * 'vaddr' to the controller's internal buffer
>> + *
>> + * @reg_off: offset within the controller's data buffer
>> + * @vaddr: virtual address of the buffer we want to read from
>> + * @size: DMA transaction size in bytes
>> + */
>> +static int write_data_dma(struct qcom_nandc_data *this, int reg_off, u8 *vaddr,
>
> const u8 *vaddr?
>
>> + int size)
>> +{
>> + struct desc_info *desc;
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct scatterlist *sgl;
>> + int r;
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + list_add_tail(&desc->list, &this->list);
>> +
>> + sgl = &desc->sgl;
>> +
>> + sg_init_one(sgl, vaddr, size);
>> +
>> + desc->dir = DMA_MEM_TO_DEV;
>> +
>> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
>> + if (r == 0)
>> + goto err;
>
> Should we return an error in this case? Looks like return 0.
dma_map_sg returns the number of sg entries successfully mapped. In
this case, it should be 1.
>
>> +
>> + this->slave_conf.device_fc = 0;
>> + this->slave_conf.dst_addr = this->res->start + reg_off;
>> + this->slave_conf.dst_maxburst = 16;
>
> Is there any reason why slave_conf can't be on the stack? Otherwise it's
> odd that it's overwritten a few times before we submit the descriptors,
> so it must be copied by the dmaengine provider, but that isn't clear at
> all from the code. If it isn't copied, perhaps it should be part of the
> desc_info structure. If it is copied I wonder why it isn't const in the
> function signature.
The dmaengine drivers either memcpy slave_config in their
device_config() dmaengine op, or populate their local members reading
params in the passed slave_config.
I'll move slave_conf to stack. As you said, the config argument
in dmaengine_slave_config should ideally use const.
>
>> +
>> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
>> + if (r) {
>> + dev_err(this->dev, "failed to configure dma channel\n");
>> + goto err;
>> + }
>> +
>> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
>> + if (!dma_desc) {
>> + dev_err(this->dev, "failed to prepare data write desc\n");
>> + r = PTR_ERR(dma_desc);
>> + goto err;
>> + }
>> +
>> + desc->dma_desc = dma_desc;
>> +
>> + return 0;
>> +err:
>> + kfree(desc);
>> +
>> + return r;
>> +}
>> +
>> +/*
>> + * helper to prepare dma descriptors to configure registers needed for reading a
>> + * codeword/step in a page
>> + */
>> +static void config_cw_read(struct qcom_nandc_data *this)
>> +{
>> + struct nandc_regs *regs = this->regs;
>> +
>> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
>
> Maybe it would be better to have a case statement inside
> {write,read}_reg_dma() that looked at the second argument and matched it
> up with an offset in regs. Then this could be
>
> write_reg_dma(this, NAND_FLASH_CMD, 3, true);
That's a good idea. However, we have at least one programming seqeunce
(in nandc_param) where we need to write two different values to the same
register. In such a case, we need two different locations to store the
two values.
I can split up the programming sequence into two parts such that we
won't write to the same register twice. But doing this for the sake of
reducing an argument to write_reg_dma seems a bit unnecessary.
>
> and we wouldn't have to worry about having the wrong argument for
> parameter 2 and parameter 3. It may even be that we always read the same
> number of registers too? In which case we could move parameter 4 into
> the case statement too?
Parameter 4 can vary for the same starting register. It won't be
possible to move that.
The last parameter (flow_control) is actually limited to a few
registers, I will move that into the function.
>
>> + write_reg_dma(this, NAND_DEV0_CFG0, ®s->cfg0, 3, false);
>> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, ®s->ecc_buf_cfg,
>> + 1, false);
>> +
>> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
>> +
>> + read_reg_dma(this, NAND_FLASH_STATUS, 2, true);
>> + read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1, false);
>> +}
>> +
> [...]
>> +/* sets up descriptors for NAND_CMD_RESET */
>> +static int reset(struct qcom_nandc_data *this)
>> +{
>> + struct nandc_regs *regs = this->regs;
>> +
>> + regs->cmd = RESET_DEVICE;
>> + regs->exec = 1;
>> +
>> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 1, true);
>> + write_reg_dma(this, NAND_EXEC_CMD, ®s->exec, 1, false);
>> +
>> + read_reg_dma(this, NAND_FLASH_STATUS, 1, true);
>> +
>> + return 0;
>> +}
>> +
>> +/* helpers to submit/free our list of dma descriptors */
>> +static void dma_callback(void *param)
>> +{
>> + struct qcom_nandc_data *this = (struct qcom_nandc_data *) param;
>
> Useless cast.
Will fix it.
>
>> + struct completion *c = &this->dma_done;
>> +
>> + complete(c);
>> +}
>> +
>> +static int submit_descs(struct qcom_nandc_data *this)
>> +{
>> + struct completion *c = &this->dma_done;
>> + struct desc_info *desc;
>> + int r;
>> +
>> + init_completion(c);
>> +
>> + list_for_each_entry(desc, &this->list, list) {
>> + /*
>> + * we add a callback the last descriptor in our list to notify
>
> to the last?
Yes. I'll fix this.
>
>> + * completion of command
>> + */
>> + if (list_is_last(&desc->list, &this->list)) {
>> + desc->dma_desc->callback = dma_callback;
>> + desc->dma_desc->callback_param = this;
>> + }
>> +
>> + dmaengine_submit(desc->dma_desc);
>> + }
>> +
>> + dma_async_issue_pending(this->chan);
>> +
>> + r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
>> + if (!r)
>> + return -EINVAL;
>
> Why not -ETIMEDOUT?
I'll replace this with -ETIMEDOUT
>
>> +
>> + return 0;
>> +}
>> +
> [...]
>> +
>> +/*
>> + * when using RS ECC, the NAND controller flags an error when reading an
>> + * erased page. however, there are special characters at certain offsets when
>> + * we read the erased page. we check here if the page is really empty. if so,
>> + * we replace the magic characters with 0xffs
>> + */
>> +static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + int i;
>> +
>> + /* if BCH is enabled, HW will take care of detecting erased pages */
>> + if (this->bch_enabled || !this->use_ecc)
>> + return false;
>> +
>> + for (i = 0; i < cwperpage; i++) {
>> + u8 *empty1, *empty2;
>> + u32 flash_status = this->reg_read_buf[3 * i];
>> +
>> + /*
>> + * an erased page flags an error in NAND_FLASH_STATUS, check if
>> + * the page is erased by looking for 0x54s at offsets 3 and 175
>> + * from the beginning of each codeword
>> + */
>> + if (flash_status & FS_OP_ERR) {
>> + empty1 = &data_buf[3 + i * this->cw_data];
>> + empty2 = &data_buf[175 + i * this->cw_data];
>> +
>> + /*
>> + * the error wasn't because of an erased page, bail out
>> + * and let someone else do the error checking
>> + */
>> + if (!((*empty1 == 0x54 && *empty2 == 0xff) ||
>> + (*empty1 == 0xff && *empty2 == 0x54)))
>
> Why are we using pointers? Just use u8 empty1, empty2 = data_buf[...] ?
Yes. Not sure why I did this.
>
>> + return false;
>> + }
>> + }
>> +
>> + for (i = 0; i < mtd->writesize && (data_buf[i] == 0xff ||
>> + (i % this->cw_data == 3 || i % this->cw_data == 175)); i++) {
>> + }
>
> This might be clearer like so:
>
> for (i = 0; i < mtd->writesize; i++) {
> if (i % this->cw_data == 3 || i % this->cw_data == 175);
> continue;
> if (data_buf[i] != 0xff)
> return false;
> }
>
> and then drop the if after the loop. Actually since we're checking the
> whole page it may be better to do this:
>
> +
> + /*
> + * the whole page is 0xffs besides the magic offsets, we replace the
> + * 0x54s with 0xffs
> + */
> + for (i = 0; i < cwperpage; i++) {
> + data_buf[3 + i * this->cw_data] = 0xff;
> + data_buf[175 + i * this->cw_data] = 0xff;
> + }
> +
>
>
> and then
>
> return memchr_inv(data_buf, 0xff, mtd->writesize) ? false : true ;
>
> the memchr_inv() is optimized to find the bad characters 8 bytes at a time.
That's a good idea. Although, if memchr_inv doesn't report that the
buffer comprises entirely of 0xffs, we will need to revert the magic
offsets back to their original values, since in that case, 0x54 could
have been valid data.
I guess it'll still be faster than the linear check. I'll try to change it.
>
>> +
>> + if (i < mtd->writesize)
>> + return false;
>> +
>> + /*
>> + * the whole page is 0xffs besides the magic offsets, we replace the
>> + * 0x54s with 0xffs
>> + */
>> + for (i = 0; i < cwperpage; i++) {
>> + data_buf[3 + i * this->cw_data] = 0xff;
>> + data_buf[175 + i * this->cw_data] = 0xff;
>> + }
>> +
>> + /*
>> + * tell the caller that the page was empty and is fixed up, so that
>> + * parse_read_errors() doesn't think it's and error
>> + */
>> + return true;
>> +}
>> +
>> +/*
>> + * reads back status registers set by the controller to notify page read
>> + * errors. this is equivalent to what 'ecc->correct()' would do.
>> + */
>> +static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + unsigned int max_bitflips = 0;
>> + int i;
>> +
>> + for (i = 0; i < cwperpage; i++) {
>> + int stat;
>> + u32 flash_status = this->reg_read_buf[3 * i];
>> + u32 buffer_status = this->reg_read_buf[3 * i + 1];
>> + u32 erased_cw_status = this->reg_read_buf[3 * i + 2];
>
> struct stats {
> u32 flash;
> u32 buffer;
> u32 erased_cw;
> };
>
> struct stats *buf = (struct stat *)this->reg_read_buf;
>
> for (i = 0; i < cwperpage; i++, buf++) {
> int stat;
> if (buf->flash & (FS_OP_ERR | FS_MPU_ERR))
>
> ?
This does look neat. I'll switch to this.
>
> Also, is the buffer little endian? If so, that should be a __le32 flash,
> __le32 buffer, etc. up there and then le32_to_cpu().
It is. I'll update.
>
>> +
>> + if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
>> +
>> + /* ignore erased codeword errors */
>> + if (this->bch_enabled) {
>> + if ((erased_cw_status & ERASED_CW) == ERASED_CW)
>> + continue;
>> + } else if (erased_page) {
>> + continue;
>> + }
>> +
>> + if (buffer_status & BS_UNCORRECTABLE_BIT) {
>> + mtd->ecc_stats.failed++;
>> + continue;
>> + }
>> + }
>> +
>> + stat = buffer_status & BS_CORRECTABLE_ERR_MSK;
>> + mtd->ecc_stats.corrected += stat;
>> +
>> + max_bitflips = max_t(unsigned int, max_bitflips, stat);
>> + }
>> +
>> + return max_bitflips;
>> +}
>> +
>> +/*
>> + * helper to perform the actual page read operation, used by ecc->read_page()
>> + * and ecc->read_oob()
>> + */
>> +static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf,
>> + u8 *oob_buf)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int i, r;
>> +
>> + /* queue cmd descs for each codeword */
>> + for (i = 0; i < ecc->steps; i++) {
>> + int data_size, oob_size;
>> +
>> + if (i == (ecc->steps - 1)) {
>> + data_size = ecc->size - ((ecc->steps - 1) << 2);
>> + oob_size = (ecc->steps << 2) + ecc->bytes;
>> + } else {
>> + data_size = this->cw_data;
>> + oob_size = ecc->bytes;
>> + }
>> +
>> + config_cw_read(this);
>> +
>> + if (data_buf)
>> + read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
>> +
>> + if (oob_buf)
>> + read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf,
>> + oob_size);
>> +
>> + if (data_buf)
>> + data_buf += data_size;
>> + if (oob_buf)
>> + oob_buf += oob_size;
>> + }
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failure to read page/oob\n");
>> +
>> + free_descs(this);
>> +
>> + return r;
>> +}
>> +
>> +/*
>> + * a helper that copies the last step/codeword of a page (containing free oob)
>> + * into our local buffer
>> + */
>> +static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int size;
>> + int r;
>> +
>> + clear_read_regs(this);
>> +
>> + size = use_ecc ? this->cw_data : this->cw_size;
>> +
>> + /* prepare a clean read buffer */
>> + memset(this->data_buffer, 0xff, size);
>> +
>> + this->use_ecc = use_ecc;
>> + set_address(this, this->cw_size * (ecc->steps - 1), page);
>> + update_rw_regs(this, 1, true);
>> +
>> + config_cw_read(this);
>> +
>> + read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size);
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failed to copy last codeword\n");
>> +
>> + free_descs(this);
>> +
>> + return r;
>> +}
>> +
>> +/* implements ecc->read_page() */
>> +static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + uint8_t *buf, int oob_required, int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + u8 *data_buf, *oob_buf = NULL;
>> + bool direct_dma, erased_page;
>> + int r;
>> +
>> + /*
>> + * first try to map the upper buffer directly, else, use our own buf
>> + * and memcpy to upper buf
>> + */
>> + if (virt_addr_valid(buf) && !object_is_on_stack(buf)) {
>> + direct_dma = true;
>> + data_buf = buf;
>> + } else {
>> + direct_dma = false;
>> + data_buf = this->data_buffer;
>> + memset(data_buf, 0xff, mtd->writesize + mtd->oobsize);
>> + }
>> +
>> + oob_buf = oob_required ? chip->oob_poi : NULL;
>> +
>> + r = read_page_low(this, data_buf, oob_buf);
>> + if (r) {
>> + dev_err(this->dev, "failure to read page\n");
>> + goto err;
>
> return r?
>
>> + }
>> +
>> + erased_page = empty_page_fixup(this, data_buf);
>> +
>> + if (!direct_dma)
>> + memcpy(buf, this->data_buffer, mtd->writesize);
>> +
>> + r = parse_read_errors(this, erased_page);
>> +err:
>> + return r;
>
> and then return parse_read_errors()?
Will do this.
>
>> +}
>> +
>> +/* implements ecc->read_oob() */
>> +static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
>> + int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int r;
>> +
>> + clear_read_regs(this);
>> +
>> + this->use_ecc = true;
>> + set_address(this, 0, page);
>> + update_rw_regs(this, ecc->steps, true);
>> +
>> + r = read_page_low(this, NULL, chip->oob_poi);
>> + if (r)
>> + dev_err(this->dev, "failure to read oob\n");
>> +
>> + return r;
>> +}
>> +
>> +/* implements ecc->read_oob_raw(), used to read the bad block marker flag */
>> +static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
>> + int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + uint8_t *oob = chip->oob_poi;
>> + int start, length;
>> + int r;
>> +
>> + /*
>> + * configure registers for a raw page read, the address is set to the
>> + * beginning of the last codeword, we don't care about reading ecc
>> + * portion of oob, just the free stuff
>> + */
>> + r = copy_last_cw(this, false, page);
>> + if (r)
>> + return r;
>> +
>> + /*
>> + * reading raw oob has 2 parts, first the bad block byte, then the
>> + * actual free oob region. perform a memcpy in two steps
>> + */
>> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
>> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
>> +
>> + memcpy(oob, this->data_buffer + start, length);
>> +
>> + oob += length;
>> +
>> + start = this->cw_data - (ecc->steps << 2) + 1;
>> + length = ecc->steps << 2;
>> +
>> + memcpy(oob, this->data_buffer + start, length);
>> +
>> + return 0;
>> +}
>> +
>> +/* implements ecc->write_page() */
>> +static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + const uint8_t *buf, int oob_required)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + u8 *data_buf, *oob_buf;
>> + bool direct_dma;
>> + int i, r = 0;
>> +
>> + clear_read_regs(this);
>> +
>> + /*
>> + * first try to map the upper buffer directly, else, memcpy upper
>> + * buffer to our local buffer
>> + */
>> + direct_dma = virt_addr_valid(buf) && !object_is_on_stack((void *) buf);
>
> We should change object_is_on_stack() to take a const pointer.
Yeah. That makes it two funcs. This and dmaengine_slave_config.
>
> Are we guaranteed that this is called within the same context as where
> the buffer is passed to this function? Otherwise this stack check isn't
> going to work because object_is_on_stack() will silently fail.
These are funcs are finally tied to mtd ops. I think in normal operation
it'll be the same context. I'll still cross check. The aim of the check
is to prevent a memcpy of the buffer to/from the layer above. A false
negative will result in a slower read/write operation.
>
>> +
>> + if (!direct_dma) {
>> + memcpy(this->data_buffer, buf, mtd->writesize
>> );
>> + data_buf = this->data_buffer;
>> + } else {
>> + data_buf = (u8 *) buf;
>
> Shouldn't need to cast away const...
Right. I'll remove this.
>
>> + }
>> +
>> + oob_buf = chip->oob_poi;
>> +
>> + this->use_ecc = true;
>> + update_rw_regs(this, ecc->steps, false);
>> +
>> + for (i = 0; i < ecc->steps; i++) {
>> + int data_size, oob_size;
>> +
>> + if (i == (ecc->steps - 1)) {
>> + data_size = ecc->size - ((ecc->steps - 1) << 2);
>> + oob_size = (ecc->steps << 2) + ecc->bytes;
>> + } else {
>> + data_size = this->cw_data;
>> + oob_size = ecc->bytes;
>> + }
>> +
>> + config_cw_write_pre(this);
>> + write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
>> +
>> + /*
>> + * we don't really need to write anything to oob for the
>> + * first n - 1 codewords since these oob regions just
>> + * contain ecc that's written by the controller itself
>> + */
>> + if (i == (ecc->steps - 1))
>> + write_data_dma(this, FLASH_BUF_ACC + data_size,
>> + oob_buf, oob_size);
>> + config_cw_write_post(this);
>> +
>> + data_buf += data_size;
>> + oob_buf += oob_size;
>> + }
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failure to write page\n");
>> +
>> + free_descs(this);
>> +
>> + return r;
>> +}
>> +
>> +/*
>> + * implements ecc->write_oob()
>> + *
>> + * the NAND controller cannot write only data or only oob within a codeword,
>> + * since ecc is calculated for the combined codeword. we first copy the
>> + * entire contents for the last codeword(data + oob), replace the old oob
>> + * with the new one in chip->oob_poi, and then write the entire codeword.
>> + * this read-copy-write operation results in a slight perormance loss.
>> + */
>> +static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>> + int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + uint8_t *oob = chip->oob_poi;
>> + int free_boff;
>> + int data_size, oob_size;
>> + int r, status = 0;
>> +
>> + r = copy_last_cw(this, true, page);
>> + if (r)
>> + return r;
>> +
>> + clear_read_regs(this);
>> +
>> + /* calculate the data and oob size for the last codeword/step */
>> + data_size = ecc->size - ((ecc->steps - 1) << 2);
>> + oob_size = (ecc->steps << 2) + ecc->bytes;
>> +
>> + /*
>> + * the location of spare data in the oob buffer, we could also use
>> + * ecc->layout.oobfree here
>> + */
>> + free_boff = ecc->bytes * (ecc->steps - 1);
>> +
>> + /* override new oob content to last codeword */
>> + memcpy(this->data_buffer + data_size, oob + free_boff, oob_size);
>> +
>> + this->use_ecc = true;
>> + set_address(this, this->cw_size * (ecc->steps - 1), page);
>> + update_rw_regs(this, 1, false);
>> +
>> + config_cw_write_pre(this);
>> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer,
>> + data_size + oob_size);
>> + config_cw_write_post(this);
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failure to write oob\n");
>> +
>> + free_descs(this);
>> +
>> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
>> +
>> + status = chip->waitfunc(mtd, chip);
>
> Should we wait if the submission failed?
That's a good point. We don't need to call waitfunc if dma
itself failed. Will fix it.
>
>> +
>> + return status & NAND_STATUS_FAIL ? -EIO : 0;
>> +}
>> +
>> +/* implements ecc->write_oob_raw(), used to write bad block marker flag */
>> +static int qcom_nandc_write_oob_raw(struct mtd_info *mtd,
>> + struct nand_chip *chip, int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + uint8_t *oob = chip->oob_poi;
>> + int start, length;
>> + int r, status = 0;
>> +
>> + r = copy_last_cw(this, false, page);
>> + if (r)
>> + return r;
>> +
>> + clear_read_regs(this);
>> +
>> + /*
>> + * writing raw oob has 2 parts, first the bad block region, then the
>> + * actual free region
>> + */
>> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
>> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
>> +
>> + memcpy(this->data_buffer + start, oob, length);
>> +
>> + oob += length;
>> +
>> + start = this->cw_data - (ecc->steps << 2) + 1;
>> + length = ecc->steps << 2;
>> +
>> + memcpy(this->data_buffer + start, oob, length);
>> +
>> + /* prepare write */
>> + this->use_ecc = false;
>> + set_address(this, this->cw_size * (ecc->steps - 1), page);
>> + update_rw_regs(this, 1, false);
>> +
>> + config_cw_write_pre(this);
>> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size);
>> + config_cw_write_post(this);
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failure to write updated oob\n");
>> +
>> + free_descs(this);
>> +
>> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
>> +
>> + status = chip->waitfunc(mtd, chip);
>
> Ditto.
>
>> +
>> + return status & NAND_STATUS_FAIL ? -EIO : 0;
>> +}
>> +
>> +/*
>> + * the three functions below implement chip->read_byte(), chip->read_buf()
>> + * and chip->write_buf() respectively. these aren't used for
>> + * reading/writing page data, they are used for smaller data like reading
>> + * id, status etc
>> + */
>> +static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>> + struct qcom_nandc_data *this = chip->priv;
>> + uint8_t *buf = (uint8_t *) this->data_buffer;
>
> isn't it already uint8_t?
Yes.
>
>> + uint8_t ret = 0x0;
>> +
>> + if (this->last_command == NAND_CMD_STATUS) {
>> + ret = this->status;
>> +
>> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
>> +
>> + return ret;
>> + }
>> +
>> + if (this->buf_start < this->buf_count)
>> + ret = buf[this->buf_start++];
>> +
>> + return ret;
>> +}
>> +
> [...]
>> +
>> +static int qcom_nandc_alloc(struct qcom_nandc_data *this)
>> +{
>> + int r;
>> +
>> + r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
>> + if (r) {
>> + dev_err(this->dev, "failed to set DMA mask\n");
>> + return r;
>> + }
>> +
>> + /*
>> + * we don't know the page size of the NAND chip yet, set the buffer size
>> + * to 512 bytes for now, that's sufficient for reading ID or ONFI params
>> + */
>> + this->buf_size = SZ_512;
>> +
>> + this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
>> + if (!this->data_buffer)
>> + return -ENOMEM;
>> +
>> + this->regs = devm_kzalloc(this->dev, sizeof(struct nandc_regs),
>
> sizeof(*this->regs)?
>
>> + GFP_KERNEL);
>> + if (!this->regs)
>> + return -ENOMEM;
>> +
>> + this->reg_read_buf = devm_kzalloc(this->dev, MAX_REG_RD * sizeof(u32),
>> + GFP_KERNEL);
>
> devm_kcalloc() and sizeof(*this->reg_read_buf) ?
Sure.
>
>> + if (!this->reg_read_buf)
>> + return -ENOMEM;
>> +
>> + INIT_LIST_HEAD(&this->list);
>> +
>> + this->chan = dma_request_slave_channel(this->dev, "rxtx");
>> + if (!this->chan) {
>> + dev_err(this->dev, "failed to request slave channel\n");
>> + return -ENODEV;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
>> +{
>> + dma_release_channel(this->chan);
>> +}
>> +
>> +static int qcom_nandc_init(struct qcom_nandc_data *this)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct mtd_part_parser_data ppdata = {};
>> + int r;
>> +
>> + mtd->priv = chip;
>> + mtd->name = "qcom-nandc";
>> + mtd->owner = THIS_MODULE;
>> +
>> + chip->priv = this;
>> +
>> + chip->cmdfunc = qcom_nandc_command;
>> + chip->select_chip = qcom_nandc_select_chip;
>> + chip->read_byte = qcom_nandc_read_byte;
>> + chip->read_buf = qcom_nandc_read_buf;
>> + chip->write_buf = qcom_nandc_write_buf;
>> +
>> + chip->options |= NAND_NO_SUBPAGE_WRITE;
>> + chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW | NAND_BBT_USE_FLASH;
>> +
>> + if (this->bus_width == 16)
>> + chip->options |= NAND_BUSWIDTH_16;
>> +
>> + qcom_nandc_pre_init(this);
>> +
>> + r = nand_scan_ident(mtd, 1, NULL);
>> + if (r)
>> + return r;
>> +
>> + r = qcom_nandc_ecc_init(this);
>> + if (r)
>> + return r;
>> +
>> + qcom_nandc_hw_post_init(this);
>> +
>> + r = nand_scan_tail(mtd);
>> + if (r)
>> + return r;
>> +
>> +
>
> Weird double newline here.
>
>> + ppdata.of_node = this->dev->of_node;
>> + r = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
>> + if (r)
>> + return r;
>> +
>> + return 0;
>
> Could be simplified to return mtd_device_parse_register(...).
>
>> +}
>> +
> [..]
>> +
>> +static int qcom_nandc_remove(struct platform_device *pdev)
>> +{
>> + struct qcom_nandc_data *this;
>> +
>> + this = platform_get_drvdata(pdev);
>> + if (!this)
>> + return -ENODEV;
>
> This seems impossible, so why check for it?
Will fix this.
>
>> +
>> + qcom_nandc_unalloc(this);
>> +
>> + clk_disable_unprepare(this->aon_clk);
>> + clk_disable_unprepare(this->core_clk);
>> +
>> + return 0;
>> +}
>> +
>> +static struct platform_driver qcom_nandc_driver = {
>> + .driver = {
>> + .name = "qcom-nandc",
>> + .of_match_table = qcom_nandc_of_match,
>> + },
>> + .probe = qcom_nandc_probe,
>> + .remove = qcom_nandc_remove,
>> +};
>> +module_platform_driver(qcom_nandc_driver);
>> +
>> +MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
>> +MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
>> +MODULE_LICENSE("GPL");
>
> This should say GPL v2 explicitly.
I'll update this.
Thanks for the thorough review!
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-28 4:34 ` Archit Taneja
@ 2015-07-29 1:48 ` Stephen Boyd
2015-07-29 5:14 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Stephen Boyd @ 2015-07-29 1:48 UTC (permalink / raw)
To: Archit Taneja
Cc: dehrenberg, linux-arm-msm, cernekee, linux-kernel, linux-mtd,
agross, computersforpeace
On 07/27/2015 09:34 PM, Archit Taneja wrote:
> Hi,
>
> On 07/25/2015 06:21 AM, Stephen Boyd wrote:
>> On 07/21/2015 03:34 AM, Archit Taneja wrote:
>>
>>> + int size)
>>> +{
>>> + struct desc_info *desc;
>>> + struct dma_async_tx_descriptor *dma_desc;
>>> + struct scatterlist *sgl;
>>> + int r;
>>> +
>>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>>> + if (!desc)
>>> + return -ENOMEM;
>>> +
>>> + list_add_tail(&desc->list, &this->list);
>>> +
>>> + sgl = &desc->sgl;
>>> +
>>> + sg_init_one(sgl, vaddr, size);
>>> +
>>> + desc->dir = DMA_MEM_TO_DEV;
>>> +
>>> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
>>> + if (r == 0)
>>> + goto err;
>>
>> Should we return an error in this case? Looks like return 0.
>
> dma_map_sg returns the number of sg entries successfully mapped. In
> this case, it should be 1.
Right, but this function returns 0 (success?) if we failed to map anything.
>
>>
>>> +
>>> + this->slave_conf.device_fc = 0;
>>> + this->slave_conf.dst_addr = this->res->start + reg_off;
>>> + this->slave_conf.dst_maxburst = 16;
>>
>> Is there any reason why slave_conf can't be on the stack? Otherwise it's
>> odd that it's overwritten a few times before we submit the descriptors,
>> so it must be copied by the dmaengine provider, but that isn't clear at
>> all from the code. If it isn't copied, perhaps it should be part of the
>> desc_info structure. If it is copied I wonder why it isn't const in the
>> function signature.
>
> The dmaengine drivers either memcpy slave_config in their
> device_config() dmaengine op, or populate their local members reading
> params in the passed slave_config.
>
> I'll move slave_conf to stack. As you said, the config argument
> in dmaengine_slave_config should ideally use const.
Cool, someone should send a patch.
>
>>
>>> +
>>> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
>>> + if (r) {
>>> + dev_err(this->dev, "failed to configure dma channel\n");
>>> + goto err;
>>> + }
>>> +
>>> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1,
>>> desc->dir, 0);
>>> + if (!dma_desc) {
>>> + dev_err(this->dev, "failed to prepare data write desc\n");
>>> + r = PTR_ERR(dma_desc);
>>> + goto err;
>>> + }
>>> +
>>> + desc->dma_desc = dma_desc;
>>> +
>>> + return 0;
>>> +err:
>>> + kfree(desc);
>>> +
>>> + return r;
>>> +}
>>> +
>>> +/*
>>> + * helper to prepare dma descriptors to configure registers needed
>>> for reading a
>>> + * codeword/step in a page
>>> + */
>>> +static void config_cw_read(struct qcom_nandc_data *this)
>>> +{
>>> + struct nandc_regs *regs = this->regs;
>>> +
>>> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
>>
>> Maybe it would be better to have a case statement inside
>> {write,read}_reg_dma() that looked at the second argument and matched it
>> up with an offset in regs. Then this could be
>>
>> write_reg_dma(this, NAND_FLASH_CMD, 3, true);
>
> That's a good idea. However, we have at least one programming seqeunce
> (in nandc_param) where we need to write two different values to the
> same register. In such a case, we need two different locations to
> store the two values.
>
> I can split up the programming sequence into two parts such that we
> won't write to the same register twice. But doing this for the sake of
> reducing an argument to write_reg_dma seems a bit unnecessary.
>
Or you could have two #defines that indicate the different usage? Like
NAND_CMD_FOO and NAND_CMD_BAR that both map to the same register but
uses different locations as storage.
>>
>> Are we guaranteed that this is called within the same context as where
>> the buffer is passed to this function? Otherwise this stack check isn't
>> going to work because object_is_on_stack() will silently fail.
>
> These are funcs are finally tied to mtd ops. I think in normal operation
> it'll be the same context. I'll still cross check. The aim of the check
> is to prevent a memcpy of the buffer to/from the layer above. A false
> negative will result in a slower read/write operation.
Right. It would be nice if the mtd layer was DMA aware and could
indicate to drivers that DMA on the buffer is allowable or not. Trying
to figure it out if the buffer is in lowmem after the buffer is mapped
is error prone, which is why not a lot of usage of object_is_on_stack()
exists. Honestly I'm confused, I thought the DMA APIs would "do the
right thing" when highmem was passed into the mapping APIs, but maybe
I'm wrong. I'll have to look.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-29 1:48 ` Stephen Boyd
@ 2015-07-29 5:14 ` Archit Taneja
2015-07-29 18:33 ` Stephen Boyd
0 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-07-29 5:14 UTC (permalink / raw)
To: Stephen Boyd
Cc: dehrenberg, linux-arm-msm, cernekee, linux-kernel, linux-mtd,
agross, computersforpeace
On 07/29/2015 07:18 AM, Stephen Boyd wrote:
> On 07/27/2015 09:34 PM, Archit Taneja wrote:
>> Hi,
>>
>> On 07/25/2015 06:21 AM, Stephen Boyd wrote:
>>> On 07/21/2015 03:34 AM, Archit Taneja wrote:
>>>
>>>> + int size)
>>>> +{Looks like a
>>>> + struct desc_info *desc;
>>>> + struct dma_async_tx_descriptor *dma_desc;
>>>> + struct scatterlist *sgl;
>>>> + int r;
>>>> +
>>>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>>>> + if (!desc)
>>>> + return -ENOMEM;
>>>> +
>>>> + list_add_tail(&desc->list, &this->list);
>>>> +
>>>> + sgl = &desc->sgl;
>>>> +
>>>> + sg_init_one(sgl, vaddr, size);
>>>> +
>>>> + desc->dir = DMA_MEM_TO_DEV;
>>>> +
>>>> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
>>>> + if (r == 0)
>>>> + goto err;
>>>
>>> Should we return an error in this case? Looks like return 0.
>>
>> dma_map_sg returns the number of sg entries successfully mapped. In
>> this case, it should be 1.
>
> Right, but this function returns 0 (success?) if we failed to map anything.
Yes. The return value is number of entries successfully mapped.
dma_map_sg is a macro that is replaced by dma_map_sg_attrs. Its comment
says:
"dma_maps_sg_attrs returns 0 on error and > 0 on success. It should
never return a value < 0."
>
>>
>>>
>>>> +
>>>> + this->slave_conf.device_fc = 0;
>>>> + this->slave_conf.dst_addr = this->res->start + reg_off;
>>>> + this->slave_conf.dst_maxburst = 16;
>>>
>>> Is there any reason why slave_conf can't be on the stack? Otherwise it's
>>> odd that it's overwritten a few times before we submit the descriptors,
>>> so it must be copied by the dmaengine provider, but that isn't clear at
>>> all from the code. If it isn't copied, perhaps it should be part of the
>>> desc_info structure. If it is copied I wonder why it isn't const in the
>>> function signature.
>>
>> The dmaengine drivers either memcpy slave_config in their
>> device_config() dmaengine op, or populate their local members reading
>> params in the passed slave_config.
>>
>> I'll move slave_conf to stack. As you said, the config argument
>> in dmaengine_slave_config should ideally use const.
>
> Cool, someone should send a patch.
>
>>
>>>
>>>> +
>>>> + r = dmaengine_slave_config(this->chan, &this->slave_conf);
>>>> + if (r) {
>>>> + dev_err(this->dev, "failed to configure dma channel\n");
>>>> + goto err;
>>>> + }
>>>> +
>>>> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1,
>>>> desc->dir, 0);
>>>> + if (!dma_desc) {
>>>> + dev_err(this->dev, "failed to prepare data write desc\n");
>>>> + r = PTR_ERR(dma_desc);
>>>> + goto err;
>>>> + }
>>>> +
>>>> + desc->dma_desc = dma_desc;
>>>> +
>>>> + return 0;
>>>> +err:
>>>> + kfree(desc);
>>>> +
>>>> + return r;
>>>> +}
>>>> +
>>>> +/*
>>>> + * helper to prepare dma descriptors to configure registers needed
>>>> for reading a
>>>> + * codeword/step in a page
>>>> + */
>>>> +static void config_cw_read(struct qcom_nandc_data *this)
>>>> +{
>>>> + struct nandc_regs *regs = this->regs;
>>>> +
>>>> + write_reg_dma(this, NAND_FLASH_CMD, ®s->cmd, 3, true);
>>>
>>> Maybe it would be better to have a case statement inside
>>> {write,read}_reg_dma() that looked at the second argument and matched it
>>> up with an offset in regs. Then this could be
>>>
>>> write_reg_dma(this, NAND_FLASH_CMD, 3, true);
>>
>> That's a good idea. However, we have at least one programming seqeunce
>> (in nandc_param) where we need to write two different values to the
>> same register. In such a case, we need two different locations to
>> store the two values.
>>
>> I can split up the programming sequence into two parts such that we
>> won't write to the same register twice. But doing this for the sake of
>> reducing an argument to write_reg_dma seems a bit unnecessary.
>>
>
> Or you could have two #defines that indicate the different usage? Like
> NAND_CMD_FOO and NAND_CMD_BAR that both map to the same register but
> uses different locations as storage.
Yeah, that seems like a good option. I'll try this out.
>
>>>
>>> Are we guaranteed that this is called within the same context as where
>>> the buffer is passed to this function? Otherwise this stack check isn't
>>> going to work because object_is_on_stack() will silently fail.
>>
>> These are funcs are finally tied to mtd ops. I think in normal operation
>> it'll be the same context. I'll still cross check. The aim of the check
>> is to prevent a memcpy of the buffer to/from the layer above. A false
>> negative will result in a slower read/write operation.
>
> Right. It would be nice if the mtd layer was DMA aware and could
> indicate to drivers that DMA on the buffer is allowable or not. Trying
> to figure it out if the buffer is in lowmem after the buffer is mapped
> is error prone, which is why not a lot of usage of object_is_on_stack()
> exists. Honestly I'm confused, I thought the DMA APIs would "do the
> right thing" when highmem was passed into the mapping APIs, but maybe
> I'm wrong. I'll have to look.
It looks like NAND_USE_BOUNCE_BUFFER does just that. If we set this
flag, the nand_base layer provides a DMA-able buffer even if the
filesystem didn't.
No one was using this flag when I last checked. A new driver
brcmnand now uses it. I'll give this a try.
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-29 5:14 ` Archit Taneja
@ 2015-07-29 18:33 ` Stephen Boyd
2015-07-30 6:53 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Stephen Boyd @ 2015-07-29 18:33 UTC (permalink / raw)
To: Archit Taneja
Cc: dehrenberg, linux-arm-msm, cernekee, linux-kernel, linux-mtd,
agross, computersforpeace
On 07/29, Archit Taneja wrote:
> On 07/29/2015 07:18 AM, Stephen Boyd wrote:
> >On 07/27/2015 09:34 PM, Archit Taneja wrote:
> >>Hi,
> >>
> >>On 07/25/2015 06:21 AM, Stephen Boyd wrote:
> >>>On 07/21/2015 03:34 AM, Archit Taneja wrote:
> >>>
> >>>>+ int size)
> >>>>+{Looks like a
> >>>>+ struct desc_info *desc;
> >>>>+ struct dma_async_tx_descriptor *dma_desc;
> >>>>+ struct scatterlist *sgl;
> >>>>+ int r;
> >>>>+
> >>>>+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> >>>>+ if (!desc)
> >>>>+ return -ENOMEM;
> >>>>+
> >>>>+ list_add_tail(&desc->list, &this->list);
> >>>>+
> >>>>+ sgl = &desc->sgl;
> >>>>+
> >>>>+ sg_init_one(sgl, vaddr, size);
> >>>>+
> >>>>+ desc->dir = DMA_MEM_TO_DEV;
> >>>>+
> >>>>+ r = dma_map_sg(this->dev, sgl, 1, desc->dir);
> >>>>+ if (r == 0)
> >>>>+ goto err;
> >>>
> >>>Should we return an error in this case? Looks like return 0.
> >>
> >>dma_map_sg returns the number of sg entries successfully mapped. In
> >>this case, it should be 1.
> >
> >Right, but this function returns 0 (success?) if we failed to map anything.
>
> Yes. The return value is number of entries successfully mapped.
> dma_map_sg is a macro that is replaced by dma_map_sg_attrs. Its
> comment
> says:
>
> "dma_maps_sg_attrs returns 0 on error and > 0 on success. It should
> never return a value < 0."
Yes, and so this function that calls dma_map_sg() is going to
return 0 to the caller when it didn't do what it was asked to do?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver
2015-07-29 18:33 ` Stephen Boyd
@ 2015-07-30 6:53 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-07-30 6:53 UTC (permalink / raw)
To: Stephen Boyd
Cc: dehrenberg, linux-arm-msm, cernekee, linux-kernel, linux-mtd,
agross, computersforpeace
On 7/30/2015 12:03 AM, Stephen Boyd wrote:
> On 07/29, Archit Taneja wrote:
>> On 07/29/2015 07:18 AM, Stephen Boyd wrote:
>>> On 07/27/2015 09:34 PM, Archit Taneja wrote:
>>>> Hi,
>>>>
>>>> On 07/25/2015 06:21 AM, Stephen Boyd wrote:
>>>>> On 07/21/2015 03:34 AM, Archit Taneja wrote:
>>>>>
>>>>>> + int size)
>>>>>> +{Looks like a
>>>>>> + struct desc_info *desc;
>>>>>> + struct dma_async_tx_descriptor *dma_desc;
>>>>>> + struct scatterlist *sgl;
>>>>>> + int r;
>>>>>> +
>>>>>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>>>>>> + if (!desc)
>>>>>> + return -ENOMEM;
>>>>>> +
>>>>>> + list_add_tail(&desc->list, &this->list);
>>>>>> +
>>>>>> + sgl = &desc->sgl;
>>>>>> +
>>>>>> + sg_init_one(sgl, vaddr, size);
>>>>>> +
>>>>>> + desc->dir = DMA_MEM_TO_DEV;
>>>>>> +
>>>>>> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
>>>>>> + if (r == 0)
>>>>>> + goto err;
>>>>>
>>>>> Should we return an error in this case? Looks like return 0.
>>>>
>>>> dma_map_sg returns the number of sg entries successfully mapped. In
>>>> this case, it should be 1.
>>>
>>> Right, but this function returns 0 (success?) if we failed to map anything.
>>
>> Yes. The return value is number of entries successfully mapped.
>> dma_map_sg is a macro that is replaced by dma_map_sg_attrs. Its
>> comment
>> says:
>>
>> "dma_maps_sg_attrs returns 0 on error and > 0 on success. It should
>> never return a value < 0."
>
> Yes, and so this function that calls dma_map_sg() is going to
> return 0 to the caller when it didn't do what it was asked to do?
Ah, I get your point now :p. I thought you were referring to the
return value of dma_map_sg, and not write_data_dma. Will fix this.
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 0/5] mtd: Qualcomm NAND controller driver
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (6 preceding siblings ...)
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
@ 2015-08-03 5:08 ` Archit Taneja
2015-08-03 5:08 ` [PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
` (5 more replies)
7 siblings, 6 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-03 5:08 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, sboyd, linux-kernel, Archit Taneja
Add support for the NAND controller driver for SoC's that contain EBI2.
For now, the only SoC upstream that has EBI2 is IPQ806x.
The original version was posted a while back. The main comments were
about the driver not being able to use nand_bbt. This was because the
controller could read factory bad block markers only in RAW mode. This
forced us to implement our own versions of chip->block_bad and
chip->blobk_markbad, and also we had to skip creating a BBT.
Discussions with Kevin Cernekee concluded that having a new BBT flag
that incorporates this controller's special requirement is a possible
option.
The new version makes use of this flag and now uses nand_bbt, at the
cost of implement read_oob_raw and write_oob_raw ops.
The patchset requires the v6 ADM dmaengine patches posted by Andy:
https://lkml.org/lkml/2015/3/17/19
v3:
- Various fixes and clean ups suggested by Stephen Boyd.
v2:
- Added a new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
v1:
- original series:
https://lkml.org/lkml/2015/1/16/317
Archit Taneja (5):
mtd: nand: Create a BBT flag to access bad block markers in raw mode
mtd: nand: Qualcomm NAND controller driver
dt/bindings: qcom_nandc: Add DT bindings
arm: qcom: dts: Add NAND controller node for ipq806x
arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 +
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 +
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/nand_base.c | 6 +-
drivers/mtd/nand/nand_bbt.c | 6 +-
drivers/mtd/nand/qcom_nandc.c | 1913 ++++++++++++++++++++
include/linux/mtd/bbm.h | 7 +
9 files changed, 2038 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
create mode 100644 drivers/mtd/nand/qcom_nandc.c
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
@ 2015-08-03 5:08 ` Archit Taneja
2015-08-03 5:08 ` [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
` (4 subsequent siblings)
5 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-03 5:08 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, sboyd, linux-kernel, Archit Taneja
Some controllers can access the factory bad block marker from OOB only
when they read it in raw mode. When ECC is enabled, these controllers
discard reading/writing bad block markers, preventing access to them
altogether.
The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
This results in the nand driver's ecc->read_oob() op to be called, which
works with ECC enabled.
Create a new BBT option flag that tells nand_bbt to force the mode to
MTD_OPS_RAW. This would result in the correct op being called for the
underlying nand controller driver.
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/nand_base.c | 6 +++++-
drivers/mtd/nand/nand_bbt.c | 6 +++++-
include/linux/mtd/bbm.h | 7 +++++++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ceb68ca..0a0c524 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -394,7 +394,11 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
} else {
ops.len = ops.ooblen = 1;
}
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
/* Write to first/last page(s) if necessary */
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 63a1a36..f2d89c9 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -420,7 +420,11 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
ops.oobbuf = buf;
ops.ooboffs = 0;
ops.datbuf = NULL;
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
for (j = 0; j < numpages; j++) {
/*
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index 36bb6a5..f67f84a 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -116,6 +116,13 @@ struct nand_bbt_descr {
#define NAND_BBT_NO_OOB_BBM 0x00080000
/*
+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
+ * when in RAW access mode
+ */
+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
+
+/*
* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
* in nand_chip.bbt_options.
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-03 5:08 ` [PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
@ 2015-08-03 5:08 ` Archit Taneja
2015-08-03 23:38 ` Stephen Boyd
2015-08-03 5:08 ` [PATCH v3 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
` (3 subsequent siblings)
5 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-08-03 5:08 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, sboyd, linux-kernel, Archit Taneja
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
broader interface for external slow peripheral devices such as LCD and
NAND/NOR flash memory or SRAM like interfaces.
We add support for the NAND controller found within EBI2. For the SoCs
of our interest, we only use the NAND controller within EBI2. Therefore,
it's safe for us to assume that the NAND controller is a standalone block
within the SoC.
The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
and spare data. The controller contains an internal 512 byte page buffer
to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
for register read/write and data transfers. The controller performs page
reads and writes at a codeword/step level of 512 bytes. It can support up
to 2 external chips of different configurations.
The driver prepares register read and write configuration descriptors for
each codeword, followed by data descriptors to read or write data from the
controller's internal buffer. It uses a single ADM DMA channel that we get
via dmaengine API. The controller requires 2 ADM CRCIs for command and
data flow control. These are passed via DT.
The ecc layout used by the controller is syndrome like, but we can't use
the standard syndrome ecc ops because of several reasons. First, the amount
of data bytes covered by ecc isn't same in each step. Second, writing to
free oob space requires us writing to the entire step in which the oob
lies. This forces us to create our own ecc ops.
One more difference is how the controller accesses the bad block marker.
The controller ignores reading the marker when ECC is enabled. ECC needs
to be explicity disabled to read or write to the bad block marker. For
this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
read the factory provided bad block markers.
v3:
- Refactor dma functions for maximum reuse
- Use dma_slave_confing on stack
- optimize and clean upempty_page_fixup using memchr_inv
- ensure portability with dma register reads using le32_* funcs
- use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
- fix handling of return values of dmaengine funcs
- constify wherever possible
- Remove dependency on ADM DMA in Kconfig
- Misc fixes and clean ups
v2:
- Use new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qcom_nandc.c | 1913 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 1921 insertions(+)
create mode 100644 drivers/mtd/nand/qcom_nandc.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5b2806a..6085b8a 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -538,4 +538,11 @@ config MTD_NAND_HISI504
help
Enables support for NAND controller on Hisilicon SoC Hip04.
+config MTD_NAND_QCOM
+ tristate "Support for NAND on QCOM SoCs"
+ depends on ARCH_QCOM
+ help
+ Enables support for NAND flash chips on SoCs containing the EBI2 NAND
+ controller. This controller is found on IPQ806x SoC.
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f897ec..87b6a1d 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
+obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
new file mode 100644
index 0000000..e1f1576
--- /dev/null
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -0,0 +1,1913 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_mtd.h>
+#include <linux/delay.h>
+
+/* NANDc reg offsets */
+#define NAND_FLASH_CMD 0x00
+#define NAND_ADDR0 0x04
+#define NAND_ADDR1 0x08
+#define NAND_FLASH_CHIP_SELECT 0x0c
+#define NAND_EXEC_CMD 0x10
+#define NAND_FLASH_STATUS 0x14
+#define NAND_BUFFER_STATUS 0x18
+#define NAND_DEV0_CFG0 0x20
+#define NAND_DEV0_CFG1 0x24
+#define NAND_DEV0_ECC_CFG 0x28
+#define NAND_DEV1_ECC_CFG 0x2c
+#define NAND_DEV1_CFG0 0x30
+#define NAND_DEV1_CFG1 0x34
+#define NAND_READ_ID 0x40
+#define NAND_READ_STATUS 0x44
+#define NAND_DEV_CMD0 0xa0
+#define NAND_DEV_CMD1 0xa4
+#define NAND_DEV_CMD2 0xa8
+#define NAND_DEV_CMD_VLD 0xac
+#define SFLASHC_BURST_CFG 0xe0
+#define NAND_ERASED_CW_DETECT_CFG 0xe8
+#define NAND_ERASED_CW_DETECT_STATUS 0xec
+#define NAND_EBI2_ECC_BUF_CFG 0xf0
+#define FLASH_BUF_ACC 0x100
+
+#define NAND_CTRL 0xf00
+#define NAND_VERSION 0xf08
+#define NAND_READ_LOCATION_0 0xf20
+#define NAND_READ_LOCATION_1 0xf24
+
+/* dummy register offsets, used by write_reg_dma */
+#define NAND_DEV_CMD1_RESTORE 0xdead
+#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
+
+/* NAND_FLASH_CMD bits */
+#define PAGE_ACC BIT(4)
+#define LAST_PAGE BIT(5)
+
+/* NAND_FLASH_CHIP_SELECT bits */
+#define NAND_DEV_SEL 0
+#define DM_EN BIT(2)
+
+/* NAND_FLASH_STATUS bits */
+#define FS_OP_ERR BIT(4)
+#define FS_READY_BSY_N BIT(5)
+#define FS_MPU_ERR BIT(8)
+#define FS_DEVICE_STS_ERR BIT(16)
+#define FS_DEVICE_WP BIT(23)
+
+/* NAND_BUFFER_STATUS bits */
+#define BS_UNCORRECTABLE_BIT BIT(8)
+#define BS_CORRECTABLE_ERR_MSK 0x1f
+
+/* NAND_DEVn_CFG0 bits */
+#define DISABLE_STATUS_AFTER_WRITE 4
+#define CW_PER_PAGE 6
+#define UD_SIZE_BYTES 9
+#define ECC_PARITY_SIZE_BYTES_RS 19
+#define SPARE_SIZE_BYTES 23
+#define NUM_ADDR_CYCLES 27
+#define STATUS_BFR_READ 30
+#define SET_RD_MODE_AFTER_STATUS 31
+
+/* NAND_DEVn_CFG0 bits */
+#define DEV0_CFG1_ECC_DISABLE 0
+#define WIDE_FLASH 1
+#define NAND_RECOVERY_CYCLES 2
+#define CS_ACTIVE_BSY 5
+#define BAD_BLOCK_BYTE_NUM 6
+#define BAD_BLOCK_IN_SPARE_AREA 16
+#define WR_RD_BSY_GAP 17
+#define ENABLE_BCH_ECC 27
+
+/* NAND_DEV0_ECC_CFG bits */
+#define ECC_CFG_ECC_DISABLE 0
+#define ECC_SW_RESET 1
+#define ECC_MODE 4
+#define ECC_PARITY_SIZE_BYTES_BCH 8
+#define ECC_NUM_DATA_BYTES 16
+#define ECC_FORCE_CLK_OPEN 30
+
+/* NAND_DEV_CMD1 bits */
+#define READ_ADDR 0
+
+/* NAND_DEV_CMD_VLD bits */
+#define READ_START_VLD 0
+
+/* NAND_EBI2_ECC_BUF_CFG bits */
+#define NUM_STEPS 0
+
+/* NAND_ERASED_CW_DETECT_CFG bits */
+#define ERASED_CW_ECC_MASK 1
+#define AUTO_DETECT_RES 0
+#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
+#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
+#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
+#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
+#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
+
+/* NAND_ERASED_CW_DETECT_STATUS bits */
+#define PAGE_ALL_ERASED BIT(7)
+#define CODEWORD_ALL_ERASED BIT(6)
+#define PAGE_ERASED BIT(5)
+#define CODEWORD_ERASED BIT(4)
+#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
+#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
+
+/* Version Mask */
+#define NAND_VERSION_MAJOR_MASK 0xf0000000
+#define NAND_VERSION_MAJOR_SHIFT 28
+#define NAND_VERSION_MINOR_MASK 0x0fff0000
+#define NAND_VERSION_MINOR_SHIFT 16
+
+/* NAND OP_CMDs */
+#define PAGE_READ 0x2
+#define PAGE_READ_WITH_ECC 0x3
+#define PAGE_READ_WITH_ECC_SPARE 0x4
+#define PROGRAM_PAGE 0x6
+#define PAGE_PROGRAM_WITH_ECC 0x7
+#define PROGRAM_PAGE_SPARE 0x9
+#define BLOCK_ERASE 0xa
+#define FETCH_ID 0xb
+#define RESET_DEVICE 0xd
+
+/*
+ * the NAND controller performs reads/writes with ECC in 516 byte chunks.
+ * the driver calls the chunks 'step' or 'codeword' interchangeably
+ */
+#define NANDC_STEP_SIZE 512
+
+/*
+ * the largest page size we support is 8K, this will have 16 steps/codewords
+ * of 512 bytes each
+ */
+#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
+
+/* we read at most 3 registers per codeword scan */
+#define MAX_REG_RD (3 * MAX_NUM_STEPS)
+
+/* ECC modes */
+#define ECC_NONE BIT(0)
+#define ECC_RS_4BIT BIT(1)
+#define ECC_BCH_4BIT BIT(2)
+#define ECC_BCH_8BIT BIT(3)
+
+struct desc_info {
+ struct list_head list;
+
+ enum dma_transfer_direction dir;
+ struct scatterlist sgl;
+ struct dma_async_tx_descriptor *dma_desc;
+};
+
+/*
+ * holds the current register values that we want to write. acts as a contiguous
+ * chunk of memory which we use to write the controller registers through DMA.
+ */
+struct nandc_regs {
+ u32 cmd;
+ u32 addr0;
+ u32 addr1;
+ u32 chip_sel;
+ u32 exec;
+
+ u32 cfg0;
+ u32 cfg1;
+ u32 ecc_bch_cfg;
+
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+
+ u32 cmd1;
+ u32 vld;
+
+ u32 orig_cmd1;
+ u32 orig_vld;
+
+ u32 ecc_buf_cfg;
+};
+
+/*
+ * @cmd_crci: ADM DMA CRCI for command flow control
+ * @data_crci: ADM DMA CRCI for data flow control
+ * @list: DMA descriptor list (list of desc_infos)
+ * @dma_done: completion param to denote end of last
+ * descriptor in the list
+ * @data_buffer: our local DMA buffer for page read/writes,
+ * used when we can't use the buffer provided
+ * by upper layers directly
+ * @buf_size/count/start: markers for chip->read_buf/write_buf functions
+ * @reg_read_buf: buffer for reading register data via DMA
+ * @reg_read_pos: marker for data read in reg_read_buf
+ * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
+ * ecc/non-ecc mode for the current nand flash
+ * device
+ * @regs: a contiguous chunk of memory for DMA register
+ * writes
+ * @ecc_strength: 4 bit or 8 bit ecc, received via DT
+ * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
+ * @ecc_modes: supported ECC modes by the current controller,
+ * initialized via DT match data
+ * @cw_size: the number of bytes in a single step/codeword
+ * of a page, consisting of all data, ecc, spare
+ * and reserved bytes
+ * @cw_data: the number of bytes within a codeword protected
+ * by ECC
+ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
+ * @status: value to be returned if NAND_CMD_STATUS command
+ * is executed
+ */
+struct qcom_nandc_data {
+ struct platform_device *pdev;
+ struct device *dev;
+
+ void __iomem *base;
+ struct resource *res;
+
+ struct clk *core_clk;
+ struct clk *aon_clk;
+
+ /* DMA stuff */
+ struct dma_chan *chan;
+ struct dma_slave_config slave_conf;
+ unsigned int cmd_crci;
+ unsigned int data_crci;
+ struct list_head list;
+ struct completion dma_done;
+
+ /* MTD stuff */
+ struct nand_chip chip;
+ struct mtd_info mtd;
+
+ /* local data buffer and markers */
+ u8 *data_buffer;
+ int buf_size;
+ int buf_count;
+ int buf_start;
+
+ /* local buffer to read back registers */
+ u32 *reg_read_buf;
+ int reg_read_pos;
+
+ /* required configs */
+ u32 cfg0, cfg1;
+ u32 cfg0_raw, cfg1_raw;
+ u32 ecc_buf_cfg;
+ u32 ecc_bch_cfg;
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+ u32 sflashc_burst_cfg;
+ u32 cmd1, vld;
+
+ /* register state */
+ struct nandc_regs *regs;
+
+ /* things we get from DT */
+ int ecc_strength;
+ int bus_width;
+
+ u32 ecc_modes;
+
+ /* misc params */
+ int cw_size;
+ int cw_data;
+ bool use_ecc;
+ bool bch_enabled;
+ u8 status;
+ int last_command;
+};
+
+static inline u32 nandc_read(struct qcom_nandc_data *this, int offset)
+{
+ return ioread32(this->base + offset);
+}
+
+static inline void nandc_write(struct qcom_nandc_data *this, int offset,
+ u32 val)
+{
+ iowrite32(val, this->base + offset);
+}
+
+/* helper to configure address register values */
+static void set_address(struct qcom_nandc_data *this, u16 column, int page)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nandc_regs *regs = this->regs;
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ column >>= 1;
+
+ regs->addr0 = page << 16 | column;
+ regs->addr1 = page >> 16 & 0xff;
+}
+
+/*
+ * update_rw_regs: set up read/write register values, these will be
+ * written to the NAND controller registers via DMA
+ *
+ * @num_cw: number of steps for the read/write operation
+ * @read: read or write operation
+ */
+static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
+{
+ struct nandc_regs *regs = this->regs;
+
+ if (read) {
+ if (this->use_ecc)
+ regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
+ else
+ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ } else {
+ regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
+ }
+
+ if (this->use_ecc) {
+ regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ regs->cfg1 = this->cfg1;
+ regs->ecc_bch_cfg = this->ecc_bch_cfg;
+ } else {
+ regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ regs->cfg1 = this->cfg1_raw;
+ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ }
+
+ regs->ecc_buf_cfg = this->ecc_buf_cfg;
+ regs->clrflashstatus = this->clrflashstatus;
+ regs->clrreadstatus = this->clrreadstatus;
+ regs->exec = 1;
+}
+
+static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
+ const void *vaddr, int size, bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ struct dma_slave_config slave_conf;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ list_add_tail(&desc->list, &this->list);
+
+ sgl = &desc->sgl;
+
+ sg_init_one(sgl, vaddr, size);
+
+ desc->dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
+
+ r = dma_map_sg(this->dev, sgl, 1, desc->dir);
+ if (r == 0) {
+ r = -ENOMEM;
+ goto err;
+ }
+
+ memset(&slave_conf, 0x00, sizeof(slave_conf));
+
+ slave_conf.device_fc = flow_control;
+ if (read) {
+ slave_conf.src_maxburst = 16;
+ slave_conf.src_addr = this->res->start + reg_off;
+ slave_conf.slave_id = this->data_crci;
+ } else {
+ slave_conf.dst_maxburst = 16;
+ slave_conf.dst_addr = this->res->start + reg_off;
+ slave_conf.slave_id = this->cmd_crci;
+ }
+
+ r = dmaengine_slave_config(this->chan, &slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare desc\n");
+ r = -EINVAL;
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * read_reg_dma: prepares a descriptor to read a given number of
+ * contiguous registers to the reg_read_buf pointer
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to read
+ */
+static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
+{
+ bool flow_control = false;
+ void *vaddr;
+ int size;
+
+ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
+ flow_control = true;
+
+ size = num_regs * sizeof(u32);
+ vaddr = this->reg_read_buf + this->reg_read_pos;
+ this->reg_read_pos += num_regs;
+
+ return prep_dma_desc(this, true, first, vaddr, size, flow_control);
+}
+
+/*
+ * write_reg_dma: prepares a descriptor to write a given number of
+ * contiguous registers
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to write
+ */
+static int write_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
+{
+ bool flow_control = false;
+ struct nandc_regs *regs = this->regs;
+ void *vaddr;
+ int size;
+
+ switch (first) {
+ case NAND_FLASH_CMD:
+ vaddr = ®s->cmd;
+ flow_control = true;
+ break;
+ case NAND_EXEC_CMD:
+ vaddr = ®s->exec;
+ break;
+ case NAND_FLASH_STATUS:
+ vaddr = ®s->clrflashstatus;
+ break;
+ case NAND_DEV0_CFG0:
+ vaddr = ®s->cfg0;
+ break;
+ case NAND_READ_STATUS:
+ vaddr = ®s->clrreadstatus;
+ break;
+ case NAND_DEV_CMD1:
+ vaddr = ®s->cmd1;
+ break;
+ case NAND_DEV_CMD1_RESTORE:
+ first = NAND_DEV_CMD1;
+ vaddr = ®s->orig_cmd1;
+ break;
+ case NAND_DEV_CMD_VLD:
+ vaddr = ®s->vld;
+ break;
+ case NAND_DEV_CMD_VLD_RESTORE:
+ first = NAND_DEV_CMD_VLD;
+ vaddr = ®s->orig_vld;
+ break;
+ case NAND_EBI2_ECC_BUF_CFG:
+ vaddr = ®s->ecc_buf_cfg;
+ break;
+ default:
+ dev_err(this->dev, "invalid starting register\n");
+ return -EINVAL;
+ }
+
+ size = num_regs * sizeof(u32);
+
+ return prep_dma_desc(this, false, first, vaddr, size, flow_control);
+}
+
+/*
+ * read_data_dma: prepares a DMA descriptor to transfer data from the
+ * controller's internal buffer to the buffer 'vaddr'
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to write to
+ * @size: DMA transaction size in bytes
+ */
+static int read_data_dma(struct qcom_nandc_data *this, int reg_off,
+ const u8 *vaddr, int size)
+{
+ return prep_dma_desc(this, true, reg_off, vaddr, size, false);
+}
+
+/*
+ * write_data_dma: prepares a DMA descriptor to transfer data from
+ * 'vaddr' to the controller's internal buffer
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to read from
+ * @size: DMA transaction size in bytes
+ */
+static int write_data_dma(struct qcom_nandc_data *this, int reg_off,
+ const u8 *vaddr, int size)
+{
+ return prep_dma_desc(this, false, reg_off, vaddr, size, false);
+}
+
+/*
+ * helper to prepare dma descriptors to configure registers needed for reading a
+ * codeword/step in a page
+ */
+static void config_cw_read(struct qcom_nandc_data *this)
+{
+ write_reg_dma(this, NAND_FLASH_CMD, 3);
+ write_reg_dma(this, NAND_DEV0_CFG0, 3);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
+
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 2);
+ read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1);
+}
+
+/*
+ * helpers to prepare dma descriptors used to configure registers needed for
+ * writing a codeword/step in a page
+ */
+static void config_cw_write_pre(struct qcom_nandc_data *this)
+{
+ write_reg_dma(this, NAND_FLASH_CMD, 3);
+ write_reg_dma(this, NAND_DEV0_CFG0, 3);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
+}
+
+static void config_cw_write_post(struct qcom_nandc_data *this)
+{
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, 1);
+ write_reg_dma(this, NAND_READ_STATUS, 1);
+}
+
+/*
+ * the following functions are used within chip->cmdfunc() to perform different
+ * NAND_CMD_* commands
+ */
+
+/* sets up descriptors for NAND_CMD_PARAM */
+static int nandc_param(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ /*
+ * NAND_CMD_PARAM is called before we know much about the FLASH chip
+ * in use. we configure the controller to perform a raw read of 512
+ * bytes to read onfi params
+ */
+ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ regs->addr0 = 0;
+ regs->addr1 = 0;
+ regs->cfg0 = 0 << CW_PER_PAGE
+ | 512 << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ regs->cfg1 = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | 0 << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+
+ /* configure CMD1 and VLD for ONFI param probing */
+ regs->vld = (this->vld & ~(1 << READ_START_VLD))
+ | 0 << READ_START_VLD;
+
+ regs->cmd1 = (this->cmd1 & ~(0xFF << READ_ADDR))
+ | NAND_CMD_PARAM << READ_ADDR;
+
+ regs->exec = 1;
+
+ regs->orig_cmd1 = this->cmd1;
+ regs->orig_vld = this->vld;
+
+ write_reg_dma(this, NAND_DEV_CMD_VLD, 1);
+ write_reg_dma(this, NAND_DEV_CMD1, 1);
+
+ this->buf_count = 512;
+ memset(this->data_buffer, 0xff, this->buf_count);
+
+ config_cw_read(this);
+
+ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->buf_count);
+
+ /* restore CMD1 and VLD regs */
+ write_reg_dma(this, NAND_DEV_CMD1_RESTORE, 1);
+ write_reg_dma(this, NAND_DEV_CMD_VLD_RESTORE, 1);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_ERASE1 */
+static int erase_block(struct qcom_nandc_data *this, int page_addr)
+{
+ struct nandc_regs *regs = this->regs;
+
+ regs->cmd = BLOCK_ERASE | PAGE_ACC | LAST_PAGE;
+ regs->addr0 = page_addr;
+ regs->addr1 = 0;
+ regs->cfg0 = this->cfg0_raw & ~(7 << CW_PER_PAGE);
+ regs->cfg1 = this->cfg1_raw;
+ regs->exec = 1;
+ regs->clrflashstatus = this->clrflashstatus;
+ regs->clrreadstatus = this->clrreadstatus;
+
+ write_reg_dma(this, NAND_FLASH_CMD, 3);
+ write_reg_dma(this, NAND_DEV0_CFG0, 2);
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, 1);
+ write_reg_dma(this, NAND_READ_STATUS, 1);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_READID */
+static int read_id(struct qcom_nandc_data *this, int column)
+{
+ struct nandc_regs *regs = this->regs;
+
+ if (column == -1)
+ return 0;
+
+ regs->cmd = FETCH_ID;
+ regs->addr0 = column;
+ regs->addr1 = 0;
+ regs->chip_sel = DM_EN;
+ regs->exec = 1;
+
+ write_reg_dma(this, NAND_FLASH_CMD, 4);
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_READ_ID, 1);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_RESET */
+static int reset(struct qcom_nandc_data *this)
+{
+ struct nandc_regs *regs = this->regs;
+
+ regs->cmd = RESET_DEVICE;
+ regs->exec = 1;
+
+ write_reg_dma(this, NAND_FLASH_CMD, 1);
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1);
+
+ return 0;
+}
+
+/* helpers to submit/free our list of dma descriptors */
+static void dma_callback(void *param)
+{
+ struct qcom_nandc_data *this = param;
+ struct completion *c = &this->dma_done;
+
+ complete(c);
+}
+
+static int submit_descs(struct qcom_nandc_data *this)
+{
+ struct completion *c = &this->dma_done;
+ struct desc_info *desc;
+ int r;
+
+ init_completion(c);
+
+ list_for_each_entry(desc, &this->list, list) {
+ /*
+ * we add a callback to the last descriptor in our list to
+ * notify completion of command
+ */
+ if (list_is_last(&desc->list, &this->list)) {
+ desc->dma_desc->callback = dma_callback;
+ desc->dma_desc->callback_param = this;
+ }
+
+ dmaengine_submit(desc->dma_desc);
+ }
+
+ dma_async_issue_pending(this->chan);
+
+ r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
+ if (!r)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static void free_descs(struct qcom_nandc_data *this)
+{
+ struct desc_info *desc, *n;
+
+ list_for_each_entry_safe(desc, n, &this->list, list) {
+ list_del(&desc->list);
+ dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir);
+ kfree(desc);
+ }
+}
+
+/* reset the register read buffer for next NAND operation */
+static void clear_read_regs(struct qcom_nandc_data *this)
+{
+ this->reg_read_pos = 0;
+ memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(*this->reg_read_buf));
+}
+
+static void pre_command(struct qcom_nandc_data *this, int command)
+{
+ this->buf_count = 0;
+ this->buf_start = 0;
+ this->use_ecc = false;
+ this->last_command = command;
+
+ clear_read_regs(this);
+}
+
+/*
+ * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
+ * privately maintained status byte, this status byte can be read after
+ * NAND_CMD_STATUS is called
+ */
+static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int num_cw;
+ int i;
+
+ num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
+
+ for (i = 0; i < num_cw; i++) {
+ __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
+
+ if (flash_status & FS_MPU_ERR)
+ this->status &= ~NAND_STATUS_WP;
+
+ if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
+ (flash_status & FS_DEVICE_STS_ERR)))
+ this->status |= NAND_STATUS_FAIL;
+ }
+}
+
+static void post_command(struct qcom_nandc_data *this, int command)
+{
+ switch (command) {
+ case NAND_CMD_READID:
+ memcpy(this->data_buffer, this->reg_read_buf, this->buf_count);
+ break;
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_ERASE1:
+ parse_erase_write_errors(this, command);
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Implements chip->cmdfunc. It's only used for a limited set of commands.
+ * The rest of the commands wouldn't be called by upper layers. For example,
+ * NAND_CMD_READOOB would never be called because we have our own versions
+ * of read_oob ops for nand_ecc_ctrl.
+ */
+static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct qcom_nandc_data *this = chip->priv;
+ bool wait = false;
+ int r = 0;
+
+ pre_command(this, command);
+
+ switch (command) {
+ case NAND_CMD_RESET:
+ r = reset(this);
+ wait = true;
+ break;
+
+ case NAND_CMD_READID:
+ this->buf_count = 4;
+ r = read_id(this, column);
+ wait = true;
+ break;
+
+ case NAND_CMD_PARAM:
+ r = nandc_param(this);
+ wait = true;
+ break;
+
+ case NAND_CMD_ERASE1:
+ r = erase_block(this, page_addr);
+ wait = true;
+ break;
+
+ case NAND_CMD_READ0:
+ /* we read the entire page for now */
+ WARN_ON(column != 0);
+
+ this->use_ecc = true;
+ set_address(this, 0, page_addr);
+ update_rw_regs(this, ecc->steps, true);
+ break;
+
+ case NAND_CMD_SEQIN:
+ WARN_ON(column != 0);
+ set_address(this, 0, page_addr);
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_STATUS:
+ case NAND_CMD_NONE:
+ default:
+ break;
+ }
+
+ if (r) {
+ dev_err(this->dev, "failure executing command %d\n",
+ command);
+ free_descs(this);
+ return;
+ }
+
+ if (wait) {
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev,
+ "failure submitting descs for command %d\n",
+ command);
+ }
+
+ free_descs(this);
+
+ post_command(this, command);
+}
+
+/*
+ * when using RS ECC, the NAND controller flags an error when reading an
+ * erased page. however, there are special characters at certain offsets when
+ * we read the erased page. we check here if the page is really empty. if so,
+ * we replace the magic characters with 0xffs
+ */
+static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS];
+ int i, j;
+
+ /* if BCH is enabled, HW will take care of detecting erased pages */
+ if (this->bch_enabled || !this->use_ecc)
+ return false;
+
+ for (i = 0; i < cwperpage; i++) {
+ u8 *empty1, *empty2;
+ __le32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
+
+ /*
+ * an erased page flags an error in NAND_FLASH_STATUS, check if
+ * the page is erased by looking for 0x54s at offsets 3 and 175
+ * from the beginning of each codeword
+ */
+ if (!(flash_status & FS_OP_ERR))
+ break;
+
+ empty1 = &data_buf[3 + i * this->cw_data];
+ empty2 = &data_buf[175 + i * this->cw_data];
+
+ /*
+ * if the error wasn't because of an erased page, bail out and
+ * and let someone else do the error checking
+ */
+ if ((*empty1 == 0x54 && *empty2 == 0xff) ||
+ (*empty1 == 0xff && *empty2 == 0x54)) {
+ orig1[i] = *empty1;
+ orig2[i] = *empty2;
+
+ *empty1 = 0xff;
+ *empty2 = 0xff;
+ } else {
+ break;
+ }
+ }
+
+ if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize))
+ goto not_empty;
+
+ /*
+ * tell the caller that the page was empty and is fixed up, so that
+ * parse_read_errors() doesn't think it's an error
+ */
+ return true;
+
+not_empty:
+ /* restore original values if not empty*/
+ for (j = 0; j < i; j++) {
+ data_buf[3 + j * this->cw_data] = orig1[j];
+ data_buf[175 + j * this->cw_data] = orig2[j];
+ }
+
+ return false;
+}
+
+struct read_stats {
+ __le32 flash;
+ __le32 buffer;
+ __le32 erased_cw;
+};
+
+/*
+ * reads back status registers set by the controller to notify page read
+ * errors. this is equivalent to what 'ecc->correct()' would do.
+ */
+static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ unsigned int max_bitflips = 0;
+ int i;
+
+ for (i = 0; i < cwperpage; i++) {
+ int stat;
+ struct read_stats *buf;
+
+ buf = (struct read_stats *) (this->reg_read_buf + 3 * i);
+
+ buf->flash = le32_to_cpu(buf->flash);
+ buf->buffer = le32_to_cpu(buf->buffer);
+ buf->erased_cw = le32_to_cpu(buf->erased_cw);
+
+ if (buf->flash & (FS_OP_ERR | FS_MPU_ERR)) {
+
+ /* ignore erased codeword errors */
+ if (this->bch_enabled) {
+ if ((buf->erased_cw & ERASED_CW) == ERASED_CW)
+ continue;
+ } else if (erased_page) {
+ continue;
+ }
+
+ if (buf->buffer & BS_UNCORRECTABLE_BIT) {
+ mtd->ecc_stats.failed++;
+ continue;
+ }
+ }
+
+ stat = buf->buffer & BS_CORRECTABLE_ERR_MSK;
+ mtd->ecc_stats.corrected += stat;
+
+ max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ }
+
+ return max_bitflips;
+}
+
+/*
+ * helper to perform the actual page read operation, used by ecc->read_page()
+ * and ecc->read_oob()
+ */
+static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf,
+ u8 *oob_buf)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int i, r;
+
+ /* queue cmd descs for each codeword */
+ for (i = 0; i < ecc->steps; i++) {
+ int data_size, oob_size;
+
+ if (i == (ecc->steps - 1)) {
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+ }
+
+ config_cw_read(this);
+
+ if (data_buf)
+ read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
+
+ if (oob_buf)
+ read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf,
+ oob_size);
+
+ if (data_buf)
+ data_buf += data_size;
+ if (oob_buf)
+ oob_buf += oob_size;
+ }
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to read page/oob\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/*
+ * a helper that copies the last step/codeword of a page (containing free oob)
+ * into our local buffer
+ */
+static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int size;
+ int r;
+
+ clear_read_regs(this);
+
+ size = use_ecc ? this->cw_data : this->cw_size;
+
+ /* prepare a clean read buffer */
+ memset(this->data_buffer, 0xff, size);
+
+ this->use_ecc = use_ecc;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, true);
+
+ config_cw_read(this);
+
+ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size);
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failed to copy last codeword\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/* implements ecc->read_page() */
+static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ u8 *data_buf, *oob_buf = NULL;
+ bool erased_page;
+ int r;
+
+ data_buf = buf;
+ oob_buf = oob_required ? chip->oob_poi : NULL;
+
+ r = read_page_low(this, data_buf, oob_buf);
+ if (r) {
+ dev_err(this->dev, "failure to read page\n");
+ return r;
+ }
+
+ erased_page = empty_page_fixup(this, data_buf);
+
+ return parse_read_errors(this, erased_page);
+}
+
+/* implements ecc->read_oob() */
+static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int r;
+
+ clear_read_regs(this);
+
+ this->use_ecc = true;
+ set_address(this, 0, page);
+ update_rw_regs(this, ecc->steps, true);
+
+ r = read_page_low(this, NULL, chip->oob_poi);
+ if (r)
+ dev_err(this->dev, "failure to read oob\n");
+
+ return r;
+}
+
+/* implements ecc->read_oob_raw(), used to read the bad block marker flag */
+static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int start, length;
+ int r;
+
+ /*
+ * configure registers for a raw page read, the address is set to the
+ * beginning of the last codeword, we don't care about reading ecc
+ * portion of oob, just the free stuff
+ */
+ r = copy_last_cw(this, false, page);
+ if (r)
+ return r;
+
+ /*
+ * reading raw oob has 2 parts, first the bad block byte, then the
+ * actual free oob region. perform a memcpy in two steps
+ */
+ start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
+ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
+
+ memcpy(oob, this->data_buffer + start, length);
+
+ oob += length;
+
+ start = this->cw_data - (ecc->steps << 2) + 1;
+ length = ecc->steps << 2;
+
+ memcpy(oob, this->data_buffer + start, length);
+
+ return 0;
+}
+
+/* implements ecc->write_page() */
+static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ u8 *data_buf, *oob_buf;
+ int i, r = 0;
+
+ clear_read_regs(this);
+
+ data_buf = (u8 *) buf;
+ oob_buf = chip->oob_poi;
+
+ this->use_ecc = true;
+ update_rw_regs(this, ecc->steps, false);
+
+ for (i = 0; i < ecc->steps; i++) {
+ int data_size, oob_size;
+
+ if (i == (ecc->steps - 1)) {
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+ }
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
+
+ /*
+ * we don't really need to write anything to oob for the
+ * first n - 1 codewords since these oob regions just
+ * contain ecc that's written by the controller itself
+ */
+ if (i == (ecc->steps - 1))
+ write_data_dma(this, FLASH_BUF_ACC + data_size,
+ oob_buf, oob_size);
+ config_cw_write_post(this);
+
+ data_buf += data_size;
+ oob_buf += oob_size;
+ }
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to write page\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/*
+ * implements ecc->write_oob()
+ *
+ * the NAND controller cannot write only data or only oob within a codeword,
+ * since ecc is calculated for the combined codeword. we first copy the
+ * entire contents for the last codeword(data + oob), replace the old oob
+ * with the new one in chip->oob_poi, and then write the entire codeword.
+ * this read-copy-write operation results in a slight perormance loss.
+ */
+static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int free_boff;
+ int data_size, oob_size;
+ int r, status = 0;
+
+ r = copy_last_cw(this, true, page);
+ if (r)
+ return r;
+
+ clear_read_regs(this);
+
+ /* calculate the data and oob size for the last codeword/step */
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+
+ /*
+ * the location of spare data in the oob buffer, we could also use
+ * ecc->layout.oobfree here
+ */
+ free_boff = ecc->bytes * (ecc->steps - 1);
+
+ /* override new oob content to last codeword */
+ memcpy(this->data_buffer + data_size, oob + free_boff, oob_size);
+
+ this->use_ecc = true;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, false);
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer,
+ data_size + oob_size);
+ config_cw_write_post(this);
+
+ r = submit_descs(this);
+
+ free_descs(this);
+
+ if (r) {
+ dev_err(this->dev, "failure to write oob\n");
+ return -EIO;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/* implements ecc->write_oob_raw(), used to write bad block marker flag */
+static int qcom_nandc_write_oob_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int start, length;
+ int r, status = 0;
+
+ r = copy_last_cw(this, false, page);
+ if (r)
+ return r;
+
+ clear_read_regs(this);
+
+ /*
+ * writing raw oob has 2 parts, first the bad block region, then the
+ * actual free region
+ */
+ start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
+ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
+
+ memcpy(this->data_buffer + start, oob, length);
+
+ oob += length;
+
+ start = this->cw_data - (ecc->steps << 2) + 1;
+ length = ecc->steps << 2;
+
+ memcpy(this->data_buffer + start, oob, length);
+
+ /* prepare write */
+ this->use_ecc = false;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, false);
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size);
+ config_cw_write_post(this);
+
+ r = submit_descs(this);
+
+ free_descs(this);
+
+ if (r) {
+ dev_err(this->dev, "failure to write updated oob\n");
+ return -EIO;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/*
+ * the three functions below implement chip->read_byte(), chip->read_buf()
+ * and chip->write_buf() respectively. these aren't used for
+ * reading/writing page data, they are used for smaller data like reading
+ * id, status etc
+ */
+static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ uint8_t *buf = this->data_buffer;
+ uint8_t ret = 0x0;
+
+ if (this->last_command == NAND_CMD_STATUS) {
+ ret = this->status;
+
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+
+ return ret;
+ }
+
+ if (this->buf_start < this->buf_count)
+ ret = buf[this->buf_start++];
+
+ return ret;
+}
+
+static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(buf, this->data_buffer + this->buf_start, real_len);
+ this->buf_start += real_len;
+}
+
+static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(this->data_buffer + this->buf_start, buf, real_len);
+
+ this->buf_start += real_len;
+}
+
+/* we support only one external chip for now */
+static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+
+ if (chipnr <= 0)
+ return;
+
+ dev_warn(this->dev, "invalid chip select\n");
+}
+
+/*
+ * NAND controller page layout info
+ *
+ * |-----------------------| |---------------------------------|
+ * | xx.......xx| | *********xx.......xx|
+ * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
+ * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
+ * | xx.......xx| | *********xx.......xx|
+ * |-----------------------| |---------------------------------|
+ * codeword 1,2..n-1 codeword n
+ * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
+ *
+ * n = number of codewords in the page
+ * . = ECC bytes
+ * * = spare bytes
+ * x = unused/reserved bytes
+ *
+ * 2K page: n = 4, spare = 16 bytes
+ * 4K page: n = 8, spare = 32 bytes
+ * 8K page: n = 16, spare = 64 bytes
+ *
+ * the qcom nand controller operates at a sub page/codeword level. each
+ * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
+ * the number of ECC bytes vary based on the ECC strength and the bus width.
+ *
+ * the first n - 1 codewords contains 516 bytes of user data, the remaining
+ * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
+ * both user data and spare(oobavail) bytes that sum up to 516 bytes.
+ *
+ * the layout described above is used by the controller when the ECC block is
+ * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
+ * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
+ * layouts defined below doesn't consider the positions occupied by the reserved
+ * bytes
+ *
+ * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
+ * in the last codeword is the position of bad block marker. the bad block
+ * marker cannot be accessed when ECC is enabled.
+ *
+ */
+
+/*
+ * Layouts for different page sizes and ecc modes. We skip the eccpos field
+ * since it isn't needed for this driver
+ */
+
+/* 2K page, 4 bit ECC */
+static struct nand_ecclayout layout_oob_64 = {
+ .eccbytes = 40,
+ .oobfree = {
+ { 30, 16 },
+ },
+};
+
+/* 4K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_128 = {
+ .eccbytes = 80,
+ .oobfree = {
+ { 70, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 8 bit bus width */
+static struct nand_ecclayout layout_oob_224_x8 = {
+ .eccbytes = 104,
+ .oobfree = {
+ { 91, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 16 bit bus width */
+static struct nand_ecclayout layout_oob_224_x16 = {
+ .eccbytes = 112,
+ .oobfree = {
+ { 98, 32 },
+ },
+};
+
+/* 8K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_256 = {
+ .eccbytes = 160,
+ .oobfree = {
+ { 151, 64 },
+ },
+};
+
+/*
+ * this is called before scan_ident, we do some minimal configurations so
+ * that reading ID and ONFI params work
+ */
+static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
+{
+ /* kill onenand */
+ nandc_write(this, SFLASHC_BURST_CFG, 0);
+
+ /* enable ADM DMA */
+ nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
+
+ /* save the original values of these registers */
+ this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
+ this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
+
+ /* initial status value */
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+}
+
+static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage;
+ bool wide_bus;
+
+ /* the nand controller fetches codewords/chunks of 512 bytes */
+ cwperpage = mtd->writesize >> 9;
+
+ ecc->strength = this->ecc_strength;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 8) {
+ /* 8 bit ECC defaults to BCH ECC on all platforms */
+ ecc->bytes = wide_bus ? 14 : 13;
+ } else {
+ /*
+ * if the controller supports BCH for 4 bit ECC, the controller
+ * uses lesser bytes for ECC. If RS is used, the ECC bytes is
+ * always 10 bytes
+ */
+ if (this->ecc_modes & ECC_BCH_4BIT)
+ ecc->bytes = wide_bus ? 8 : 7;
+ else
+ ecc->bytes = 10;
+ }
+
+ /* each step consists of 512 bytes of data */
+ ecc->size = NANDC_STEP_SIZE;
+
+ ecc->read_page = qcom_nandc_read_page;
+ ecc->read_oob = qcom_nandc_read_oob;
+ ecc->write_page = qcom_nandc_write_page;
+ ecc->write_oob = qcom_nandc_write_oob;
+
+ /*
+ * the bad block marker is readable only when we read the page with ECC
+ * disabled. all the ops above run with ECC enabled. We need raw read
+ * and write function for oob in order to access bad block marker.
+ */
+ ecc->read_oob_raw = qcom_nandc_read_oob_raw;
+ ecc->write_oob_raw = qcom_nandc_write_oob_raw;
+
+ switch (mtd->oobsize) {
+ case 64:
+ ecc->layout = &layout_oob_64;
+ break;
+ case 128:
+ ecc->layout = &layout_oob_128;
+ break;
+ case 224:
+ if (wide_bus)
+ ecc->layout = &layout_oob_224_x16;
+ else
+ ecc->layout = &layout_oob_224_x8;
+ break;
+ case 256:
+ ecc->layout = &layout_oob_256;
+ break;
+ default:
+ dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
+ mtd->oobsize);
+ return -ENODEV;
+ }
+
+ ecc->mode = NAND_ECC_HW;
+
+ /* enable ecc by default */
+ this->use_ecc = true;
+
+ return 0;
+}
+
+static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = mtd->writesize / ecc->size;
+ int spare_bytes, bad_block_byte;
+ bool wide_bus;
+ int ecc_mode = 0;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 8) {
+ this->cw_size = 532;
+
+ spare_bytes = wide_bus ? 0 : 2;
+
+ this->bch_enabled = true;
+ ecc_mode = 1;
+ } else {
+ this->cw_size = 528;
+
+ if (this->ecc_modes & ECC_BCH_4BIT) {
+ spare_bytes = wide_bus ? 2 : 4;
+
+ this->bch_enabled = true;
+ ecc_mode = 0;
+ } else {
+ spare_bytes = wide_bus ? 0 : 1;
+ }
+ }
+
+ /*
+ * DATA_UD_BYTES varies based on whether the read/write command protects
+ * spare data with ECC too. We protect spare data by default, so we set
+ * it to main + spare data, which are 512 and 4 bytes respectively.
+ */
+ this->cw_data = 516;
+
+ bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
+
+ this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_data << UD_SIZE_BYTES
+ | 0 << DISABLE_STATUS_AFTER_WRITE
+ | 5 << NUM_ADDR_CYCLES
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
+ | 0 << STATUS_BFR_READ
+ | 1 << SET_RD_MODE_AFTER_STATUS
+ | spare_bytes << SPARE_SIZE_BYTES;
+
+ this->cfg1 = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | bad_block_byte << BAD_BLOCK_BYTE_NUM
+ | 0 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | this->bch_enabled << ENABLE_BCH_ECC;
+
+ this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_size << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
+ | 0 << ECC_SW_RESET
+ | this->cw_data << ECC_NUM_DATA_BYTES
+ | 1 << ECC_FORCE_CLK_OPEN
+ | ecc_mode << ECC_MODE
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
+
+ this->ecc_buf_cfg = 0x203 << NUM_STEPS;
+
+ this->clrflashstatus = FS_READY_BSY_N;
+ this->clrreadstatus = 0xc0;
+
+ dev_dbg(this->dev,
+ "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
+ this->cfg0, this->cfg1, this->ecc_buf_cfg,
+ this->ecc_bch_cfg, this->cw_size, this->cw_data,
+ ecc->strength, ecc->bytes, cwperpage);
+}
+
+static int qcom_nandc_alloc(struct qcom_nandc_data *this)
+{
+ int r;
+
+ r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
+ if (r) {
+ dev_err(this->dev, "failed to set DMA mask\n");
+ return r;
+ }
+
+ /*
+ * we use the internal buffer for reading ONFI params, reading small
+ * data like ID and status, and preforming read-copy-write operations
+ * when writing to a codeword partially. 532 is the maximum possible
+ * size of a codeword for our nand controller
+ */
+ this->buf_size = 532;
+
+ this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
+ if (!this->data_buffer)
+ return -ENOMEM;
+
+ this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL);
+ if (!this->regs)
+ return -ENOMEM;
+
+ this->reg_read_buf = devm_kzalloc(this->dev,
+ MAX_REG_RD * sizeof(*this->reg_read_buf),
+ GFP_KERNEL);
+ if (!this->reg_read_buf)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&this->list);
+
+ this->chan = dma_request_slave_channel(this->dev, "rxtx");
+ if (!this->chan) {
+ dev_err(this->dev, "failed to request slave channel\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
+{
+ dma_release_channel(this->chan);
+}
+
+static int qcom_nandc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct device_node *np = this->dev->of_node;
+ struct mtd_part_parser_data ppdata = { .of_node = np };
+ int r;
+
+ mtd->priv = chip;
+ mtd->name = "qcom-nandc";
+ mtd->owner = THIS_MODULE;
+
+ chip->priv = this;
+
+ chip->cmdfunc = qcom_nandc_command;
+ chip->select_chip = qcom_nandc_select_chip;
+ chip->read_byte = qcom_nandc_read_byte;
+ chip->read_buf = qcom_nandc_read_buf;
+ chip->write_buf = qcom_nandc_write_buf;
+
+ chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
+ if (this->bus_width == 16)
+ chip->options |= NAND_BUSWIDTH_16;
+
+ chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
+ if (of_get_nand_on_flash_bbt(np))
+ chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+
+ qcom_nandc_pre_init(this);
+
+ r = nand_scan_ident(mtd, 1, NULL);
+ if (r)
+ return r;
+
+ r = qcom_nandc_ecc_init(this);
+ if (r)
+ return r;
+
+ qcom_nandc_hw_post_init(this);
+
+ r = nand_scan_tail(mtd);
+ if (r)
+ return r;
+
+ return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+}
+
+static int qcom_nandc_parse_dt(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this = platform_get_drvdata(pdev);
+ struct device_node *np = this->dev->of_node;
+ int r;
+
+ this->ecc_strength = of_get_nand_ecc_strength(np);
+ if (this->ecc_strength < 0) {
+ dev_warn(this->dev,
+ "incorrect ecc strength, setting to 4 bits/step\n");
+ this->ecc_strength = 4;
+ }
+
+ this->bus_width = of_get_nand_bus_width(np);
+ if (this->bus_width < 0) {
+ dev_warn(this->dev, "incorrect bus width, setting to 8\n");
+ this->bus_width = 8;
+ }
+
+ r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
+ if (r) {
+ dev_err(this->dev, "command CRCI unspecified\n");
+ return r;
+ }
+
+ r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
+ if (r) {
+ dev_err(this->dev, "data CRCI unspecified\n");
+ return r;
+ }
+
+ return 0;
+}
+
+static int qcom_nandc_probe(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this;
+ const void *dev_data;
+ int r;
+
+ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
+ if (!this)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, this);
+
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+
+ dev_data = of_device_get_match_data(&pdev->dev);
+ if (!dev_data) {
+ dev_err(&pdev->dev, "failed to get device data\n");
+ return -ENODEV;
+ }
+
+ this->ecc_modes = (u32) dev_data;
+
+ this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ this->base = devm_ioremap_resource(&pdev->dev, this->res);
+ if (IS_ERR(this->base))
+ return PTR_ERR(this->base);
+
+ this->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(this->core_clk))
+ return PTR_ERR(this->core_clk);
+
+ this->aon_clk = devm_clk_get(&pdev->dev, "aon");
+ if (IS_ERR(this->aon_clk))
+ return PTR_ERR(this->aon_clk);
+
+ r = qcom_nandc_parse_dt(pdev);
+ if (r)
+ return r;
+
+ r = qcom_nandc_alloc(this);
+ if (r)
+ return r;
+
+ r = clk_prepare_enable(this->core_clk);
+ if (r)
+ goto err_core_clk;
+
+ r = clk_prepare_enable(this->aon_clk);
+ if (r)
+ goto err_aon_clk;
+
+ r = qcom_nandc_init(this);
+ if (r)
+ goto err_init;
+
+ return 0;
+
+err_init:
+ clk_disable_unprepare(this->aon_clk);
+err_aon_clk:
+ clk_disable_unprepare(this->core_clk);
+err_core_clk:
+ qcom_nandc_unalloc(this);
+
+ return r;
+}
+
+static int qcom_nandc_remove(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this = platform_get_drvdata(pdev);
+
+ qcom_nandc_unalloc(this);
+
+ clk_disable_unprepare(this->aon_clk);
+ clk_disable_unprepare(this->core_clk);
+
+ return 0;
+}
+
+#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
+
+/*
+ * data will hold a struct pointer containing more differences once we support
+ * more IPs
+ */
+static const struct of_device_id qcom_nandc_of_match[] = {
+ { .compatible = "qcom,ebi2-nandc",
+ .data = (void *) EBI2_NANDC_ECC_MODES,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
+
+static struct platform_driver qcom_nandc_driver = {
+ .driver = {
+ .name = "qcom-nandc",
+ .of_match_table = qcom_nandc_of_match,
+ },
+ .probe = qcom_nandc_probe,
+ .remove = qcom_nandc_remove,
+};
+module_platform_driver(qcom_nandc_driver);
+
+MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
+MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 3/5] dt/bindings: qcom_nandc: Add DT bindings
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-03 5:08 ` [PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-08-03 5:08 ` [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
@ 2015-08-03 5:08 ` Archit Taneja
2015-08-03 5:08 ` [PATCH v3 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
` (2 subsequent siblings)
5 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-03 5:08 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, sboyd, linux-kernel, Archit Taneja, devicetree
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicetree@vger.kernel.org
v3:
- Don't use '0x' when specifying nand controller address space
- Add optional property for on-flash bbt usage
Acked-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
new file mode 100644
index 0000000..1de4643
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -0,0 +1,49 @@
+* Qualcomm NAND controller
+
+Required properties:
+- compatible: should be "qcom,ebi2-nand" for IPQ806x
+- reg: MMIO address range
+- clocks: must contain core clock and always on clock
+- clock-names: must contain "core" for the core clock and "aon" for the
+ always on clock
+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
+ controller node and the channel number to be used for
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
+- dma-names: must be "rxtx"
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+- qcom,data-crci: must contain the ADM data type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+
+Optional properties:
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
+ as default
+
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
+ bits. If not present, 4 is chosen as default
+- nand-on-flash-bbt: Create/use on-flash bad block table
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ partition@0 {
+ ...
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 4/5] arm: qcom: dts: Add NAND controller node for ipq806x
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (2 preceding siblings ...)
2015-08-03 5:08 ` [PATCH v3 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
@ 2015-08-03 5:08 ` Archit Taneja
2015-08-03 5:08 ` [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
5 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-03 5:08 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, sboyd, linux-kernel, Archit Taneja, devicetree
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicetree@vger.kernel.org
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 1e1b3f0..a7f0ee5 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -350,5 +350,20 @@
status = "disabled";
};
+ nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ status = "disabled";
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (3 preceding siblings ...)
2015-08-03 5:08 ` [PATCH v3 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
@ 2015-08-03 5:08 ` Archit Taneja
2015-08-03 19:35 ` Andy Gross
2015-08-03 20:58 ` Stephen Boyd
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
5 siblings, 2 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-03 5:08 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace
Cc: linux-arm-msm, agross, sboyd, linux-kernel, Archit Taneja, devicetree
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..2e88eff 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,28 @@
bias-none;
};
};
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
gsbi@16300000 {
@@ -93,5 +115,19 @@
sata@29000000 {
status = "ok";
};
+
+ nand@1ac00000 {
+ status = "ok";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ };
};
};
+
+&adm_dma {
+ status = "ok";
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
2015-08-03 5:08 ` [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
@ 2015-08-03 19:35 ` Andy Gross
2015-08-04 15:05 ` Archit Taneja
2015-08-03 20:58 ` Stephen Boyd
1 sibling, 1 reply; 71+ messages in thread
From: Andy Gross @ 2015-08-03 19:35 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, sboyd, linux-kernel, devicetree
On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote:
> Enable the NAND controller node on the AP148 platform. Provide pinmux
> information.
>
> Cc: devicetree@vger.kernel.org
>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
> arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> index 7f9ea50..2e88eff 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> @@ -30,6 +30,28 @@
> bias-none;
> };
> };
> + nand_pins: nand_pins {
> + mux {
> + pins = "gpio34", "gpio35", "gpio36",
> + "gpio37", "gpio38", "gpio39",
> + "gpio40", "gpio41", "gpio42",
> + "gpio43", "gpio44", "gpio45",
> + "gpio46", "gpio47";
> + function = "nand";
> + drive-strength = <10>;
> + bias-disable;
> + };
> + pullups {
> + pins = "gpio39";
> + bias-pull-up;
> + };
> + hold {
> + pins = "gpio40", "gpio41", "gpio42",
> + "gpio43", "gpio44", "gpio45",
> + "gpio46", "gpio47";
> + bias-bus-hold;
Maybe split out the bias-disable into a separate set and remove that property
from the mux.
> + };
> + };
> };
>
> gsbi@16300000 {
> @@ -93,5 +115,19 @@
> sata@29000000 {
> status = "ok";
> };
> +
> + nand@1ac00000 {
> + status = "ok";
> +
> + pinctrl-0 = <&nand_pins>;
> + pinctrl-names = "default";
> +
> + nand-ecc-strength = <4>;
> + nand-bus-width = <8>;
> + };
> };
> };
> +
> +&adm_dma {
> + status = "ok";
> +};
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
>
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
2015-08-03 5:08 ` [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
2015-08-03 19:35 ` Andy Gross
@ 2015-08-03 20:58 ` Stephen Boyd
2015-08-04 15:06 ` Archit Taneja
1 sibling, 1 reply; 71+ messages in thread
From: Stephen Boyd @ 2015-08-03 20:58 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, agross, linux-kernel, devicetree
On 08/03, Archit Taneja wrote:
> @@ -93,5 +115,19 @@
> sata@29000000 {
> status = "ok";
> };
> +
> + nand@1ac00000 {
> + status = "ok";
> +
> + pinctrl-0 = <&nand_pins>;
> + pinctrl-names = "default";
> +
> + nand-ecc-strength = <4>;
> + nand-bus-width = <8>;
> + };
> };
> };
> +
> +&adm_dma {
> + status = "ok";
> +};
I think the preference is to put the full path to the device in
the dts file and then have status = "ok". So please move this
into the soc node and give the correct offset, etc. like we've
done for other nodes.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-03 5:08 ` [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
@ 2015-08-03 23:38 ` Stephen Boyd
2015-08-04 15:04 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Stephen Boyd @ 2015-08-03 23:38 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, agross, linux-kernel
On 08/03, Archit Taneja wrote:
> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
> MDM9x15 series.
There are some checker errors and le32 usage is not correct:
drivers/mtd/nand/qcom_nandc.c:383:13: warning: mixing different enum types
drivers/mtd/nand/qcom_nandc.c:383:13: int enum dma_transfer_direction versus
drivers/mtd/nand/qcom_nandc.c:383:13: int enum dma_data_direction
drivers/mtd/nand/qcom_nandc.c:741:17: warning: mixing different enum types
drivers/mtd/nand/qcom_nandc.c:741:17: int enum dma_transfer_direction versus
drivers/mtd/nand/qcom_nandc.c:741:17: int enum dma_data_direction
/
drivers/mtd/nand/qcom_nandc.c:1828:20: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
You can find the le32 problems with
make C=2 CF="-D__CHECK_ENDIAN__" drivers/mtd/nand/qcom_nandc.o
Feel free to squash the following in:
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---8<----
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index e1f15766e63d..6cc1df1a6df0 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -173,7 +173,7 @@
struct desc_info {
struct list_head list;
- enum dma_transfer_direction dir;
+ enum dma_data_direction dir;
struct scatterlist sgl;
struct dma_async_tx_descriptor *dma_desc;
};
@@ -264,7 +264,7 @@ struct qcom_nandc_data {
int buf_start;
/* local buffer to read back registers */
- u32 *reg_read_buf;
+ __le32 *reg_read_buf;
int reg_read_pos;
/* required configs */
@@ -366,6 +366,7 @@ static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
struct dma_async_tx_descriptor *dma_desc;
struct scatterlist *sgl;
struct dma_slave_config slave_conf;
+ enum dma_transfer_direction dir_eng;
int r;
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
@@ -378,7 +379,13 @@ static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
sg_init_one(sgl, vaddr, size);
- desc->dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
+ if (read) {
+ dir_eng = DMA_DEV_TO_MEM;
+ desc->dir = DMA_FROM_DEVICE;
+ } else {
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ }
r = dma_map_sg(this->dev, sgl, 1, desc->dir);
if (r == 0) {
@@ -405,7 +412,7 @@ static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
goto err;
}
- dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, dir_eng, 0);
if (!dma_desc) {
dev_err(this->dev, "failed to prepare desc\n");
r = -EINVAL;
@@ -775,7 +782,7 @@ static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
for (i = 0; i < num_cw; i++) {
- __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
+ u32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
if (flash_status & FS_MPU_ERR)
this->status &= ~NAND_STATUS_WP;
@@ -902,7 +909,7 @@ static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
for (i = 0; i < cwperpage; i++) {
u8 *empty1, *empty2;
- __le32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
+ u32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
/*
* an erased page flags an error in NAND_FLASH_STATUS, check if
@@ -968,37 +975,37 @@ static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
int cwperpage = ecc->steps;
unsigned int max_bitflips = 0;
int i;
+ struct read_stats *buf;
- for (i = 0; i < cwperpage; i++) {
- int stat;
- struct read_stats *buf;
-
- buf = (struct read_stats *) (this->reg_read_buf + 3 * i);
+ buf = (struct read_stats *)this->reg_read_buf;
+ for (i = 0; i < cwperpage; i++, buf++) {
+ unsigned int stat;
+ u32 flash, buffer, erased_cw;
- buf->flash = le32_to_cpu(buf->flash);
- buf->buffer = le32_to_cpu(buf->buffer);
- buf->erased_cw = le32_to_cpu(buf->erased_cw);
+ flash = le32_to_cpu(buf->flash);
+ buffer = le32_to_cpu(buf->buffer);
+ erased_cw = le32_to_cpu(buf->erased_cw);
- if (buf->flash & (FS_OP_ERR | FS_MPU_ERR)) {
+ if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
/* ignore erased codeword errors */
if (this->bch_enabled) {
- if ((buf->erased_cw & ERASED_CW) == ERASED_CW)
+ if ((erased_cw & ERASED_CW) == ERASED_CW)
continue;
} else if (erased_page) {
continue;
}
- if (buf->buffer & BS_UNCORRECTABLE_BIT) {
+ if (buffer & BS_UNCORRECTABLE_BIT) {
mtd->ecc_stats.failed++;
continue;
}
}
- stat = buf->buffer & BS_CORRECTABLE_ERR_MSK;
+ stat = buffer & BS_CORRECTABLE_ERR_MSK;
mtd->ecc_stats.corrected += stat;
- max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ max_bitflips = max(max_bitflips, stat);
}
return max_bitflips;
@@ -1825,7 +1832,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
return -ENODEV;
}
- this->ecc_modes = (u32) dev_data;
+ this->ecc_modes = (unsigned long)dev_data;
this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
this->base = devm_ioremap_resource(&pdev->dev, this->res);
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> new file mode 100644
> index 0000000..e1f1576
> --- /dev/null
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -0,0 +1,1913 @@
> +struct qcom_nandc_data {
> + struct platform_device *pdev;
> + struct device *dev;
> +
> + void __iomem *base;
> + struct resource *res;
> +
> + struct clk *core_clk;
> + struct clk *aon_clk;
> +
> + /* DMA stuff */
> + struct dma_chan *chan;
> + struct dma_slave_config slave_conf;
> + unsigned int cmd_crci;
> + unsigned int data_crci;
> + struct list_head list;
> + struct completion dma_done;
> +
> + /* MTD stuff */
> + struct nand_chip chip;
> + struct mtd_info mtd;
> +
> + /* local data buffer and markers */
> + u8 *data_buffer;
> + int buf_size;
> + int buf_count;
> + int buf_start;
> +
> + /* local buffer to read back registers */
> + u32 *reg_read_buf;
> + int reg_read_pos;
> +
> + /* required configs */
> + u32 cfg0, cfg1;
> + u32 cfg0_raw, cfg1_raw;
> + u32 ecc_buf_cfg;
> + u32 ecc_bch_cfg;
> + u32 clrflashstatus;
> + u32 clrreadstatus;
> + u32 sflashc_burst_cfg;
> + u32 cmd1, vld;
> +
> + /* register state */
> + struct nandc_regs *regs;
I also wonder if this is little endian? It looks like some sort
of in memory register map that we point DMA to so that it can
write the values to the actual hardware registers?
> +
> + /* things we get from DT */
> + int ecc_strength;
> + int bus_width;
> +
> + u32 ecc_modes;
> +
> + /* misc params */
> + int cw_size;
> + int cw_data;
> + bool use_ecc;
> + bool bch_enabled;
> + u8 status;
> + int last_command;
> +};
[...]
> +
> +static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
> + const void *vaddr, int size, bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + struct dma_slave_config slave_conf;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + list_add_tail(&desc->list, &this->list);
Should we move this list add to at least after the dma_map_sg()?
It looks like on the error path (which is only checked sometimes)
we always call dma_unmap_sg() and so this may have not been
mapped in the first place.
> +
> + sgl = &desc->sgl;
> +
> + sg_init_one(sgl, vaddr, size);
> +
> + desc->dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
> +
> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
> + if (r == 0) {
> + r = -ENOMEM;
> + goto err;
> + }
> +
> + memset(&slave_conf, 0x00, sizeof(slave_conf));
> +
> + slave_conf.device_fc = flow_control;
> + if (read) {
> + slave_conf.src_maxburst = 16;
> + slave_conf.src_addr = this->res->start + reg_off;
> + slave_conf.slave_id = this->data_crci;
> + } else {
> + slave_conf.dst_maxburst = 16;
> + slave_conf.dst_addr = this->res->start + reg_off;
> + slave_conf.slave_id = this->cmd_crci;
> + }
> +
> + r = dmaengine_slave_config(this->chan, &slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare desc\n");
> + r = -EINVAL;
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
[...]
> +
> +static int submit_descs(struct qcom_nandc_data *this)
> +{
> + struct completion *c = &this->dma_done;
> + struct desc_info *desc;
> + int r;
> +
> + init_completion(c);
> +
> + list_for_each_entry(desc, &this->list, list) {
> + /*
> + * we add a callback to the last descriptor in our list to
> + * notify completion of command
> + */
> + if (list_is_last(&desc->list, &this->list)) {
> + desc->dma_desc->callback = dma_callback;
> + desc->dma_desc->callback_param = this;
> + }
> +
> + dmaengine_submit(desc->dma_desc);
> + }
> +
> + dma_async_issue_pending(this->chan);
> +
> + r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
> + if (!r)
> + return -ETIMEDOUT;
Any reason this can't all be done with dma_sync_wait()? The
timeout is a little different (5 seconds instead of .5 seconds)
but otherwise it looks like we could keep track of the last
cookie we got from dmaengine_submit() and then call
dma_sync_wait() with that:
list_for_each_entry(desc, &this->list, list)
cookie = dmaengine_submit(desc->dma_desc);
if (dma_sync_wait(this->chan, cookie) != DMA_COMPLETE)
return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
[...]
> +
> +/*
> + * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
> + * privately maintained status byte, this status byte can be read after
> + * NAND_CMD_STATUS is called
> + */
> +static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int num_cw;
> + int i;
> +
> + num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
> +
> + for (i = 0; i < num_cw; i++) {
> + __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
So this doesn't need the i * 3 thing? If it does, perhaps
reg_read_buf needs to be of type struct read_stats instead.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-03 23:38 ` Stephen Boyd
@ 2015-08-04 15:04 ` Archit Taneja
2015-08-04 17:53 ` Stephen Boyd
0 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-08-04 15:04 UTC (permalink / raw)
To: Stephen Boyd
Cc: dehrenberg, linux-arm-msm, cernekee, linux-kernel, linux-mtd,
agross, computersforpeace
On 8/4/2015 5:08 AM, Stephen Boyd wrote:
> On 08/03, Archit Taneja wrote:
>> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
>> MDM9x15 series.
>
> There are some checker errors and le32 usage is not correct:
>
> drivers/mtd/nand/qcom_nandc.c:383:13: warning: mixing different enum types
> drivers/mtd/nand/qcom_nandc.c:383:13: int enum dma_transfer_direction versus
> drivers/mtd/nand/qcom_nandc.c:383:13: int enum dma_data_direction
> drivers/mtd/nand/qcom_nandc.c:741:17: warning: mixing different enum types
> drivers/mtd/nand/qcom_nandc.c:741:17: int enum dma_transfer_direction versus
> drivers/mtd/nand/qcom_nandc.c:741:17: int enum dma_data_direction
> /
> drivers/mtd/nand/qcom_nandc.c:1828:20: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
>
> You can find the le32 problems with
>
> make C=2 CF="-D__CHECK_ENDIAN__" drivers/mtd/nand/qcom_nandc.o
>
> Feel free to squash the following in:
Thanks for fixing these issues. I'll squash them in.
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---8<----
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index e1f15766e63d..6cc1df1a6df0 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -173,7 +173,7 @@
> struct desc_info {
> struct list_head list;
>
> - enum dma_transfer_direction dir;
> + enum dma_data_direction dir;
> struct scatterlist sgl;
> struct dma_async_tx_descriptor *dma_desc;
> };
> @@ -264,7 +264,7 @@ struct qcom_nandc_data {
> int buf_start;
>
> /* local buffer to read back registers */
> - u32 *reg_read_buf;
> + __le32 *reg_read_buf;
> int reg_read_pos;
>
> /* required configs */
> @@ -366,6 +366,7 @@ static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
> struct dma_async_tx_descriptor *dma_desc;
> struct scatterlist *sgl;
> struct dma_slave_config slave_conf;
> + enum dma_transfer_direction dir_eng;
> int r;
>
> desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> @@ -378,7 +379,13 @@ static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
>
> sg_init_one(sgl, vaddr, size);
>
> - desc->dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
> + if (read) {
> + dir_eng = DMA_DEV_TO_MEM;
> + desc->dir = DMA_FROM_DEVICE;
> + } else {
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + }
>
> r = dma_map_sg(this->dev, sgl, 1, desc->dir);
> if (r == 0) {
> @@ -405,7 +412,7 @@ static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
> goto err;
> }
>
> - dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, dir_eng, 0);
> if (!dma_desc) {
> dev_err(this->dev, "failed to prepare desc\n");
> r = -EINVAL;
> @@ -775,7 +782,7 @@ static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
> num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
>
> for (i = 0; i < num_cw; i++) {
> - __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
> + u32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
>
> if (flash_status & FS_MPU_ERR)
> this->status &= ~NAND_STATUS_WP;
> @@ -902,7 +909,7 @@ static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
>
> for (i = 0; i < cwperpage; i++) {
> u8 *empty1, *empty2;
> - __le32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
> + u32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
>
> /*
> * an erased page flags an error in NAND_FLASH_STATUS, check if
> @@ -968,37 +975,37 @@ static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
> int cwperpage = ecc->steps;
> unsigned int max_bitflips = 0;
> int i;
> + struct read_stats *buf;
>
> - for (i = 0; i < cwperpage; i++) {
> - int stat;
> - struct read_stats *buf;
> -
> - buf = (struct read_stats *) (this->reg_read_buf + 3 * i);
> + buf = (struct read_stats *)this->reg_read_buf;
> + for (i = 0; i < cwperpage; i++, buf++) {
> + unsigned int stat;
> + u32 flash, buffer, erased_cw;
>
> - buf->flash = le32_to_cpu(buf->flash);
> - buf->buffer = le32_to_cpu(buf->buffer);
> - buf->erased_cw = le32_to_cpu(buf->erased_cw);
> + flash = le32_to_cpu(buf->flash);
> + buffer = le32_to_cpu(buf->buffer);
> + erased_cw = le32_to_cpu(buf->erased_cw);
>
> - if (buf->flash & (FS_OP_ERR | FS_MPU_ERR)) {
> + if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
>
> /* ignore erased codeword errors */
> if (this->bch_enabled) {
> - if ((buf->erased_cw & ERASED_CW) == ERASED_CW)
> + if ((erased_cw & ERASED_CW) == ERASED_CW)
> continue;
> } else if (erased_page) {
> continue;
> }
>
> - if (buf->buffer & BS_UNCORRECTABLE_BIT) {
> + if (buffer & BS_UNCORRECTABLE_BIT) {
> mtd->ecc_stats.failed++;
> continue;
> }
> }
>
> - stat = buf->buffer & BS_CORRECTABLE_ERR_MSK;
> + stat = buffer & BS_CORRECTABLE_ERR_MSK;
> mtd->ecc_stats.corrected += stat;
>
> - max_bitflips = max_t(unsigned int, max_bitflips, stat);
> + max_bitflips = max(max_bitflips, stat);
> }
>
> return max_bitflips;
> @@ -1825,7 +1832,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> return -ENODEV;
> }
>
> - this->ecc_modes = (u32) dev_data;
> + this->ecc_modes = (unsigned long)dev_data;
>
> this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> this->base = devm_ioremap_resource(&pdev->dev, this->res);
>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
>> new file mode 100644
>> index 0000000..e1f1576
>> --- /dev/null
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -0,0 +1,1913 @@
>> +struct qcom_nandc_data {
>> + struct platform_device *pdev;
>> + struct device *dev;
>> +
>> + void __iomem *base;
>> + struct resource *res;
>> +
>> + struct clk *core_clk;
>> + struct clk *aon_clk;
>> +
>> + /* DMA stuff */
>> + struct dma_chan *chan;
>> + struct dma_slave_config slave_conf;
>> + unsigned int cmd_crci;
>> + unsigned int data_crci;
>> + struct list_head list;
>> + struct completion dma_done;
>> +
>> + /* MTD stuff */
>> + struct nand_chip chip;
>> + struct mtd_info mtd;
>> +
>> + /* local data buffer and markers */
>> + u8 *data_buffer;
>> + int buf_size;
>> + int buf_count;
>> + int buf_start;
>> +
>> + /* local buffer to read back registers */
>> + u32 *reg_read_buf;
>> + int reg_read_pos;
>> +
>> + /* required configs */
>> + u32 cfg0, cfg1;
>> + u32 cfg0_raw, cfg1_raw;
>> + u32 ecc_buf_cfg;
>> + u32 ecc_bch_cfg;
>> + u32 clrflashstatus;
>> + u32 clrreadstatus;
>> + u32 sflashc_burst_cfg;
>> + u32 cmd1, vld;
>> +
>> + /* register state */
>> + struct nandc_regs *regs;
>
> I also wonder if this is little endian? It looks like some sort
> of in memory register map that we point DMA to so that it can
> write the values to the actual hardware registers?
Yes, that's what it's supposed to do. I kept it in the form above
so that updating the register map is as easy as assigning a new
value to the member.
I've tried to fix it for endianness in the diff below. I created
some funcs to not flood the driver with cpu_to_le32() calls. Does
it look okay?
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -183,26 +183,26 @@ struct desc_info {
* chunk of memory which we use to write the controller registers
through DMA.
*/
struct nandc_regs {
- u32 cmd;
- u32 addr0;
- u32 addr1;
- u32 chip_sel;
- u32 exec;
-
- u32 cfg0;
- u32 cfg1;
- u32 ecc_bch_cfg;
+ __le32 cmd;
+ __le32 addr0;
+ __le32 addr1;
+ __le32 chip_sel;
+ __le32 exec;
- u32 clrflashstatus;
- u32 clrreadstatus;
+ __le32 cfg0;
+ __le32 cfg1;
+ __le32 ecc_bch_cfg;
- u32 cmd1;
- u32 vld;
+ __le32 clrflashstatus;
+ __le32 clrreadstatus;
- u32 orig_cmd1;
- u32 orig_vld;
+ __le32 cmd1;
+ __le32 vld;
- u32 ecc_buf_cfg;
+ __le32 orig_cmd1;
+ __le32 orig_vld;
+
+ __le32 ecc_buf_cfg;
};
/*
@@ -306,17 +306,65 @@ static inline void nandc_write(struct
qcom_nandc_data *this, int offset,
iowrite32(val, this->base + offset);
}
+static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
+{
+ switch (offset) {
+ case NAND_FLASH_CMD:
+ return ®s->cmd;
+ case NAND_ADDR0:
+ return ®s->addr0;
+ case NAND_ADDR1:
+ return ®s->addr1;
+ case NAND_FLASH_CHIP_SELECT:
+ return ®s->chip_sel;
+ case NAND_EXEC_CMD:
+ return ®s->exec;
+ case NAND_FLASH_STATUS:
+ return ®s->clrflashstatus;
+ case NAND_DEV0_CFG0:
+ return ®s->cfg0;
+ case NAND_DEV0_CFG1:
+ return ®s->cfg1;
+ case NAND_DEV0_ECC_CFG:
+ return ®s->ecc_bch_cfg;
+ case NAND_READ_STATUS:
+ return ®s->clrreadstatus;
+ case NAND_DEV_CMD1:
+ return ®s->cmd1;
+ case NAND_DEV_CMD1_RESTORE:
+ return ®s->orig_cmd1;
+ case NAND_DEV_CMD_VLD:
+ return ®s->vld;
+ case NAND_DEV_CMD_VLD_RESTORE:
+ return ®s->orig_vld;
+ case NAND_EBI2_ECC_BUF_CFG:
+ return ®s->ecc_buf_cfg;
+ default:
+ return NULL;
+ }
+}
+
+static void set_nandc_reg(struct qcom_nandc_data *this, int offset, u32
val)
+{
+ struct nandc_regs *regs = this->regs;
+ __le32 *reg;
+
+ reg = offset_to_nandc_reg(regs, offset);
+
+ if (reg)
+ *reg = cpu_to_le32(val);
+}
+
/* helper to configure address register values */
static void set_address(struct qcom_nandc_data *this, u16 column, int
page)
{
struct nand_chip *chip = &this->chip;
- struct nandc_regs *regs = this->regs;
if (chip->options & NAND_BUSWIDTH_16)
column >>= 1;
- regs->addr0 = page << 16 | column;
- regs->addr1 = page >> 16 & 0xff;
+ set_nandc_reg(this, NAND_ADDR0, page << 16 | column);
+ set_nandc_reg(this, NAND_ADDR1, page >> 16 & 0xff);
}
/*
@@ -328,35 +376,39 @@ static void set_address(struct qcom_nandc_data
*this, u16 column, int page)
*/
static void update_rw_regs(struct qcom_nandc_data *this, int num_cw,
bool read)
{
- struct nandc_regs *regs = this->regs;
+ u32 cmd, cfg0, cfg1, ecc_bch_cfg;
if (read) {
if (this->use_ecc)
- regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
+ cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
else
- regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
} else {
- regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
+ cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
}
if (this->use_ecc) {
- regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
+ cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
(num_cw - 1) << CW_PER_PAGE;
- regs->cfg1 = this->cfg1;
- regs->ecc_bch_cfg = this->ecc_bch_cfg;
+ cfg1 = this->cfg1;
+ ecc_bch_cfg = this->ecc_bch_cfg;
} else {
- regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
+ cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
(num_cw - 1) << CW_PER_PAGE;
- regs->cfg1 = this->cfg1_raw;
- regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ cfg1 = this->cfg1_raw;
+ ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
}
- regs->ecc_buf_cfg = this->ecc_buf_cfg;
- regs->clrflashstatus = this->clrflashstatus;
- regs->clrreadstatus = this->clrreadstatus;
- regs->exec = 1;
+ set_nandc_reg(this, NAND_FLASH_CMD, cmd);
+ set_nandc_reg(this, NAND_DEV0_CFG0, cfg0);
+ set_nandc_reg(this, NAND_DEV0_CFG1, cfg1);
+ set_nandc_reg(this, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
+ set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, this->ecc_buf_cfg);
+ set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
+ set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
}
static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int
reg_off,
@@ -465,44 +517,16 @@ static int write_reg_dma(struct qcom_nandc_data
*this, int first, int num_regs)
void *vaddr;
int size;
- switch (first) {
- case NAND_FLASH_CMD:
- vaddr = ®s->cmd;
+ vaddr = offset_to_nandc_reg(regs, first);
+
+ if (first == NAND_FLASH_CMD)
flow_control = true;
- break;
- case NAND_EXEC_CMD:
- vaddr = ®s->exec;
- break;
- case NAND_FLASH_STATUS:
- vaddr = ®s->clrflashstatus;
- break;
- case NAND_DEV0_CFG0:
- vaddr = ®s->cfg0;
- break;
- case NAND_READ_STATUS:
- vaddr = ®s->clrreadstatus;
- break;
- case NAND_DEV_CMD1:
- vaddr = ®s->cmd1;
- break;
- case NAND_DEV_CMD1_RESTORE:
+
+ if (first == NAND_DEV_CMD1_RESTORE)
first = NAND_DEV_CMD1;
- vaddr = ®s->orig_cmd1;
- break;
- case NAND_DEV_CMD_VLD:
- vaddr = ®s->vld;
- break;
- case NAND_DEV_CMD_VLD_RESTORE:
+
+ if (first == NAND_DEV_CMD_VLD_RESTORE)
first = NAND_DEV_CMD_VLD;
- vaddr = ®s->orig_vld;
- break;
- case NAND_EBI2_ECC_BUF_CFG:
- vaddr = ®s->ecc_buf_cfg;
- break;
- default:
- dev_err(this->dev, "invalid starting register\n");
- return -EINVAL;
- }
size = num_regs * sizeof(u32);
@@ -582,42 +606,40 @@ static void config_cw_write_post(struct
qcom_nandc_data *this)
/* sets up descriptors for NAND_CMD_PARAM */
static int nandc_param(struct qcom_nandc_data *this)
{
- struct nandc_regs *regs = this->regs;
-
/*
* NAND_CMD_PARAM is called before we know much about the FLASH chip
* in use. we configure the controller to perform a raw read of 512
* bytes to read onfi params
*/
- regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
- regs->addr0 = 0;
- regs->addr1 = 0;
- regs->cfg0 = 0 << CW_PER_PAGE
- | 512 << UD_SIZE_BYTES
- | 5 << NUM_ADDR_CYCLES
- | 0 << SPARE_SIZE_BYTES;
-
- regs->cfg1 = 7 << NAND_RECOVERY_CYCLES
- | 0 << CS_ACTIVE_BSY
- | 17 << BAD_BLOCK_BYTE_NUM
- | 1 << BAD_BLOCK_IN_SPARE_AREA
- | 2 << WR_RD_BSY_GAP
- | 0 << WIDE_FLASH
- | 1 << DEV0_CFG1_ECC_DISABLE;
-
- regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ set_nandc_reg(this, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
+ set_nandc_reg(this, NAND_ADDR0, 0);
+ set_nandc_reg(this, NAND_ADDR1, 0);
+ set_nandc_reg(this, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
+ | 512 << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES);
+ set_nandc_reg(this, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | 0 << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE);
+ set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
- /* configure CMD1 and VLD for ONFI param probing */
- regs->vld = (this->vld & ~(1 << READ_START_VLD))
- | 0 << READ_START_VLD;
- regs->cmd1 = (this->cmd1 & ~(0xFF << READ_ADDR))
- | NAND_CMD_PARAM << READ_ADDR;
+ /* configure CMD1 and VLD for ONFI param probing */
+ set_nandc_reg(this, NAND_DEV_CMD_VLD,
+ (this->vld & ~(1 << READ_START_VLD))
+ | 0 << READ_START_VLD);
+ set_nandc_reg(this, NAND_DEV_CMD1,
+ (this->cmd1 & ~(0xFF << READ_ADDR))
+ | NAND_CMD_PARAM << READ_ADDR);
- regs->exec = 1;
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
- regs->orig_cmd1 = this->cmd1;
- regs->orig_vld = this->vld;
+ set_nandc_reg(this, NAND_DEV_CMD1_RESTORE, this->cmd1);
+ set_nandc_reg(this, NAND_DEV_CMD_VLD_RESTORE, this->vld);
write_reg_dma(this, NAND_DEV_CMD_VLD, 1);
write_reg_dma(this, NAND_DEV_CMD1, 1);
@@ -639,16 +661,15 @@ static int nandc_param(struct qcom_nandc_data *this)
/* sets up descriptors for NAND_CMD_ERASE1 */
static int erase_block(struct qcom_nandc_data *this, int page_addr)
{
- struct nandc_regs *regs = this->regs;
-
- regs->cmd = BLOCK_ERASE | PAGE_ACC | LAST_PAGE;
- regs->addr0 = page_addr;
- regs->addr1 = 0;
- regs->cfg0 = this->cfg0_raw & ~(7 << CW_PER_PAGE);
- regs->cfg1 = this->cfg1_raw;
- regs->exec = 1;
- regs->clrflashstatus = this->clrflashstatus;
- regs->clrreadstatus = this->clrreadstatus;
+ set_nandc_reg(this, NAND_FLASH_CMD, BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
+ set_nandc_reg(this, NAND_ADDR0, page_addr);
+ set_nandc_reg(this, NAND_ADDR1, 0);
+ set_nandc_reg(this, NAND_DEV0_CFG0,
+ this->cfg0_raw & ~(7 << CW_PER_PAGE));
+ set_nandc_reg(this, NAND_DEV0_CFG1, this->cfg1_raw);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
+ set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
+ set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
write_reg_dma(this, NAND_FLASH_CMD, 3);
write_reg_dma(this, NAND_DEV0_CFG0, 2);
@@ -665,16 +686,14 @@ static int erase_block(struct qcom_nandc_data
*this, int page_addr)
/* sets up descriptors for NAND_CMD_READID */
static int read_id(struct qcom_nandc_data *this, int column)
{
- struct nandc_regs *regs = this->regs;
-
if (column == -1)
return 0;
- regs->cmd = FETCH_ID;
- regs->addr0 = column;
- regs->addr1 = 0;
- regs->chip_sel = DM_EN;
- regs->exec = 1;
+ set_nandc_reg(this, NAND_FLASH_CMD, FETCH_ID);
+ set_nandc_reg(this, NAND_ADDR0, column);
+ set_nandc_reg(this, NAND_ADDR1, 0);
+ set_nandc_reg(this, NAND_FLASH_CHIP_SELECT, DM_EN);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
write_reg_dma(this, NAND_FLASH_CMD, 4);
write_reg_dma(this, NAND_EXEC_CMD, 1);
@@ -687,10 +706,8 @@ static int read_id(struct qcom_nandc_data *this,
int column)
/* sets up descriptors for NAND_CMD_RESET */
static int reset(struct qcom_nandc_data *this)
{
- struct nandc_regs *regs = this->regs;
-
- regs->cmd = RESET_DEVICE;
- regs->exec = 1;
+ set_nandc_reg(this, NAND_FLASH_CMD, RESET_DEVICE);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
write_reg_dma(this, NAND_FLASH_CMD, 1);
write_reg_dma(this, NAND_EXEC_CMD, 1);
>
>> +
>> + /* things we get from DT */
>> + int ecc_strength;
>> + int bus_width;
>> +
>> + u32 ecc_modes;
>> +
>> + /* misc params */
>> + int cw_size;
>> + int cw_data;
>> + bool use_ecc;
>> + bool bch_enabled;
>> + u8 status;
>> + int last_command;
>> +};
> [...]
>> +
>> +static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
>> + const void *vaddr, int size, bool flow_control)
>> +{
>> + struct desc_info *desc;
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct scatterlist *sgl;
>> + struct dma_slave_config slave_conf;
>> + int r;
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + list_add_tail(&desc->list, &this->list);
>
> Should we move this list add to at least after the dma_map_sg()?
> It looks like on the error path (which is only checked sometimes)
> we always call dma_unmap_sg() and so this may have not been
> mapped in the first place.
The error path isn't checked by the callers of this func, so, it's
best to keep it later as you suggested.
>
>> +
>> + sgl = &desc->sgl;
>> +
>> + sg_init_one(sgl, vaddr, size);
>> +
>> + desc->dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
>> +
>> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
>> + if (r == 0) {
>> + r = -ENOMEM;
>> + goto err;
>> + }
>> +
>> + memset(&slave_conf, 0x00, sizeof(slave_conf));
>> +
>> + slave_conf.device_fc = flow_control;
>> + if (read) {
>> + slave_conf.src_maxburst = 16;
>> + slave_conf.src_addr = this->res->start + reg_off;
>> + slave_conf.slave_id = this->data_crci;
>> + } else {
>> + slave_conf.dst_maxburst = 16;
>> + slave_conf.dst_addr = this->res->start + reg_off;
>> + slave_conf.slave_id = this->cmd_crci;
>> + }
>> +
>> + r = dmaengine_slave_config(this->chan, &slave_conf);
>> + if (r) {
>> + dev_err(this->dev, "failed to configure dma channel\n");
>> + goto err;
>> + }
>> +
>> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0);
>> + if (!dma_desc) {
>> + dev_err(this->dev, "failed to prepare desc\n");
>> + r = -EINVAL;
>> + goto err;
>> + }
>> +
>> + desc->dma_desc = dma_desc;
>> +
>> + return 0;
>> +err:
>> + kfree(desc);
>> +
>> + return r;
>> +}
> [...]
>> +
>> +static int submit_descs(struct qcom_nandc_data *this)
>> +{
>> + struct completion *c = &this->dma_done;
>> + struct desc_info *desc;
>> + int r;
>> +
>> + init_completion(c);
>> +
>> + list_for_each_entry(desc, &this->list, list) {
>> + /*
>> + * we add a callback to the last descriptor in our list to
>> + * notify completion of command
>> + */
>> + if (list_is_last(&desc->list, &this->list)) {
>> + desc->dma_desc->callback = dma_callback;
>> + desc->dma_desc->callback_param = this;
>> + }
>> +
>> + dmaengine_submit(desc->dma_desc);
>> + }
>> +
>> + dma_async_issue_pending(this->chan);
>> +
>> + r = wait_for_completion_timeout(c, msecs_to_jiffies(500));
>> + if (!r)
>> + return -ETIMEDOUT;
>
> Any reason this can't all be done with dma_sync_wait()? The
> timeout is a little different (5 seconds instead of .5 seconds)
> but otherwise it looks like we could keep track of the last
> cookie we got from dmaengine_submit() and then call
> dma_sync_wait() with that:
>
> list_for_each_entry(desc, &this->list, list)
> cookie = dmaengine_submit(desc->dma_desc);
>
> if (dma_sync_wait(this->chan, cookie) != DMA_COMPLETE)
> return -ETIMEDOUT;
I didn't know about this function, will give it a try.
>
>> +
>> + return 0;
>> +}
>> +
> [...]
>> +
>> +/*
>> + * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
>> + * privately maintained status byte, this status byte can be read after
>> + * NAND_CMD_STATUS is called
>> + */
>> +static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int num_cw;
>> + int i;
>> +
>> + num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
>> +
>> + for (i = 0; i < num_cw; i++) {
>> + __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
>
> So this doesn't need the i * 3 thing? If it does, perhaps
> reg_read_buf needs to be of type struct read_stats instead.
We just read back one register per codeword here, so we can't do
the read_stats thing as before. I could read back the extra registers
and discrading them, but I'd I'll leave that for later.
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
2015-08-03 19:35 ` Andy Gross
@ 2015-08-04 15:05 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-04 15:05 UTC (permalink / raw)
To: Andy Gross
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, sboyd, linux-kernel, devicetree
On 8/4/2015 1:05 AM, Andy Gross wrote:
> On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote:
>> Enable the NAND controller node on the AP148 platform. Provide pinmux
>> information.
>>
>> Cc: devicetree@vger.kernel.org
>>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>> ---
>> arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
>> 1 file changed, 36 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
>> index 7f9ea50..2e88eff 100644
>> --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
>> +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
>> @@ -30,6 +30,28 @@
>> bias-none;
>> };
>> };
>> + nand_pins: nand_pins {
>> + mux {
>> + pins = "gpio34", "gpio35", "gpio36",
>> + "gpio37", "gpio38", "gpio39",
>> + "gpio40", "gpio41", "gpio42",
>> + "gpio43", "gpio44", "gpio45",
>> + "gpio46", "gpio47";
>> + function = "nand";
>> + drive-strength = <10>;
>> + bias-disable;
>> + };
>> + pullups {
>> + pins = "gpio39";
>> + bias-pull-up;
>> + };
>> + hold {
>> + pins = "gpio40", "gpio41", "gpio42",
>> + "gpio43", "gpio44", "gpio45",
>> + "gpio46", "gpio47";
>> + bias-bus-hold;
>
> Maybe split out the bias-disable into a separate set and remove that property
> from the mux.
I'll fix this.
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
2015-08-03 20:58 ` Stephen Boyd
@ 2015-08-04 15:06 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-04 15:06 UTC (permalink / raw)
To: Stephen Boyd
Cc: devicetree, dehrenberg, linux-arm-msm, cernekee, linux-kernel,
linux-mtd, agross, computersforpeace
On 8/4/2015 2:28 AM, Stephen Boyd wrote:
> On 08/03, Archit Taneja wrote:
>> @@ -93,5 +115,19 @@
>> sata@29000000 {
>> status = "ok";
>> };
>> +
>> + nand@1ac00000 {
>> + status = "ok";
>> +
>> + pinctrl-0 = <&nand_pins>;
>> + pinctrl-names = "default";
>> +
>> + nand-ecc-strength = <4>;
>> + nand-bus-width = <8>;
>> + };
>> };
>> };
>> +
>> +&adm_dma {
>> + status = "ok";
>> +};
>
> I think the preference is to put the full path to the device in
> the dts file and then have status = "ok". So please move this
> into the soc node and give the correct offset, etc. like we've
> done for other nodes.
I'll do that.
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-04 15:04 ` Archit Taneja
@ 2015-08-04 17:53 ` Stephen Boyd
0 siblings, 0 replies; 71+ messages in thread
From: Stephen Boyd @ 2015-08-04 17:53 UTC (permalink / raw)
To: Archit Taneja
Cc: dehrenberg, linux-arm-msm, cernekee, linux-kernel, linux-mtd,
agross, computersforpeace
On 08/04/2015 08:04 AM, Archit Taneja wrote:
>
> On 8/4/2015 5:08 AM, Stephen Boyd wrote:
>> I also wonder if this is little endian? It looks like some sort
>> of in memory register map that we point DMA to so that it can
>> write the values to the actual hardware registers?
>
> Yes, that's what it's supposed to do. I kept it in the form above
> so that updating the register map is as easy as assigning a new
> value to the member.
>
> I've tried to fix it for endianness in the diff below. I created
> some funcs to not flood the driver with cpu_to_le32() calls. Does
> it look okay?
>
Looks good.
>>
>>> +
>>> + return 0;
>>> +}
>>> +
>> [...]
>>> +
>>> +/*
>>> + * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to
>>> set our
>>> + * privately maintained status byte, this status byte can be read
>>> after
>>> + * NAND_CMD_STATUS is called
>>> + */
>>> +static void parse_erase_write_errors(struct qcom_nandc_data *this,
>>> int command)
>>> +{
>>> + struct nand_chip *chip = &this->chip;
>>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>>> + int num_cw;
>>> + int i;
>>> +
>>> + num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
>>> +
>>> + for (i = 0; i < num_cw; i++) {
>>> + __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
>>
>> So this doesn't need the i * 3 thing? If it does, perhaps
>> reg_read_buf needs to be of type struct read_stats instead.
>
> We just read back one register per codeword here, so we can't do
> the read_stats thing as before. I could read back the extra registers
> and discrading them, but I'd I'll leave that for later.
Ah right. Sounds like nothing to change then.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v4 0/5] mtd: Qualcomm NAND controller driver
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (4 preceding siblings ...)
2015-08-03 5:08 ` [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
@ 2015-08-19 4:49 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
` (4 more replies)
5 siblings, 5 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-19 4:49 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja
Add support for the NAND controller driver for SoC's that contain EBI2.
For now, the only SoC upstream that has EBI2 is IPQ806x.
The original version was posted a while back. The main comments were
about the driver not being able to use nand_bbt. This was because the
controller could read factory bad block markers only in RAW mode. This
forced us to implement our own versions of chip->block_bad and
chip->blobk_markbad, and also we had to skip creating a BBT.
Discussions with Kevin Cernekee concluded that having a new BBT flag
that incorporates this controller's special requirement is a possible
option.
The new version makes use of this flag and now uses nand_bbt, at the
cost of implement read_oob_raw and write_oob_raw ops.
The patchset requires the v6 ADM dmaengine patches posted by Andy:
https://lkml.org/lkml/2015/3/17/19
v4:
- Some more fixes. Mentioned in patch's changelog.
v3:
- Various fixes and clean ups suggested by Stephen Boyd.
v2:
- Added a new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
v1:
- original series:
https://lkml.org/lkml/2015/1/16/317
Archit Taneja (5):
mtd: nand: Create a BBT flag to access bad block markers in raw mode
mtd: nand: Qualcomm NAND controller driver
dt/bindings: qcom_nandc: Add DT bindings
arm: qcom: dts: Add NAND controller node for ipq806x
arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 +
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40 +
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/nand_base.c | 6 +-
drivers/mtd/nand/nand_bbt.c | 6 +-
drivers/mtd/nand/qcom_nandc.c | 1910 ++++++++++++++++++++
include/linux/mtd/bbm.h | 7 +
9 files changed, 2039 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
create mode 100644 drivers/mtd/nand/qcom_nandc.c
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
@ 2015-08-19 4:49 ` Archit Taneja
2015-10-02 2:44 ` Brian Norris
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
` (3 subsequent siblings)
4 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-08-19 4:49 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja
Some controllers can access the factory bad block marker from OOB only
when they read it in raw mode. When ECC is enabled, these controllers
discard reading/writing bad block markers, preventing access to them
altogether.
The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
This results in the nand driver's ecc->read_oob() op to be called, which
works with ECC enabled.
Create a new BBT option flag that tells nand_bbt to force the mode to
MTD_OPS_RAW. This would result in the correct op being called for the
underlying nand controller driver.
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/nand_base.c | 6 +++++-
drivers/mtd/nand/nand_bbt.c | 6 +++++-
include/linux/mtd/bbm.h | 7 +++++++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ceb68ca..0a0c524 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -394,7 +394,11 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
} else {
ops.len = ops.ooblen = 1;
}
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
/* Write to first/last page(s) if necessary */
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 63a1a36..f2d89c9 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -420,7 +420,11 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
ops.oobbuf = buf;
ops.ooboffs = 0;
ops.datbuf = NULL;
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
for (j = 0; j < numpages; j++) {
/*
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index 36bb6a5..f67f84a 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -116,6 +116,13 @@ struct nand_bbt_descr {
#define NAND_BBT_NO_OOB_BBM 0x00080000
/*
+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
+ * when in RAW access mode
+ */
+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
+
+/*
* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
* in nand_chip.bbt_options.
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-19 4:49 ` [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
@ 2015-08-19 4:49 ` Archit Taneja
2015-08-26 23:37 ` Stephen Boyd
` (3 more replies)
2015-08-19 4:49 ` [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
` (2 subsequent siblings)
4 siblings, 4 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-19 4:49 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
broader interface for external slow peripheral devices such as LCD and
NAND/NOR flash memory or SRAM like interfaces.
We add support for the NAND controller found within EBI2. For the SoCs
of our interest, we only use the NAND controller within EBI2. Therefore,
it's safe for us to assume that the NAND controller is a standalone block
within the SoC.
The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
and spare data. The controller contains an internal 512 byte page buffer
to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
for register read/write and data transfers. The controller performs page
reads and writes at a codeword/step level of 512 bytes. It can support up
to 2 external chips of different configurations.
The driver prepares register read and write configuration descriptors for
each codeword, followed by data descriptors to read or write data from the
controller's internal buffer. It uses a single ADM DMA channel that we get
via dmaengine API. The controller requires 2 ADM CRCIs for command and
data flow control. These are passed via DT.
The ecc layout used by the controller is syndrome like, but we can't use
the standard syndrome ecc ops because of several reasons. First, the amount
of data bytes covered by ecc isn't same in each step. Second, writing to
free oob space requires us writing to the entire step in which the oob
lies. This forces us to create our own ecc ops.
One more difference is how the controller accesses the bad block marker.
The controller ignores reading the marker when ECC is enabled. ECC needs
to be explicity disabled to read or write to the bad block marker. For
this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
read the factory provided bad block markers.
v4:
- Shrink submit_descs
- add desc list node at the end of dma_prep_desc
- Endianness and warning fixes
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
v3:
- Refactor dma functions for maximum reuse
- Use dma_slave_confing on stack
- optimize and clean upempty_page_fixup using memchr_inv
- ensure portability with dma register reads using le32_* funcs
- use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
- fix handling of return values of dmaengine funcs
- constify wherever possible
- Remove dependency on ADM DMA in Kconfig
- Misc fixes and clean ups
v2:
- Use new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qcom_nandc.c | 1910 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 1918 insertions(+)
create mode 100644 drivers/mtd/nand/qcom_nandc.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5b2806a..6085b8a 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -538,4 +538,11 @@ config MTD_NAND_HISI504
help
Enables support for NAND controller on Hisilicon SoC Hip04.
+config MTD_NAND_QCOM
+ tristate "Support for NAND on QCOM SoCs"
+ depends on ARCH_QCOM
+ help
+ Enables support for NAND flash chips on SoCs containing the EBI2 NAND
+ controller. This controller is found on IPQ806x SoC.
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f897ec..87b6a1d 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
+obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
new file mode 100644
index 0000000..2337731
--- /dev/null
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -0,0 +1,1910 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_mtd.h>
+#include <linux/delay.h>
+
+/* NANDc reg offsets */
+#define NAND_FLASH_CMD 0x00
+#define NAND_ADDR0 0x04
+#define NAND_ADDR1 0x08
+#define NAND_FLASH_CHIP_SELECT 0x0c
+#define NAND_EXEC_CMD 0x10
+#define NAND_FLASH_STATUS 0x14
+#define NAND_BUFFER_STATUS 0x18
+#define NAND_DEV0_CFG0 0x20
+#define NAND_DEV0_CFG1 0x24
+#define NAND_DEV0_ECC_CFG 0x28
+#define NAND_DEV1_ECC_CFG 0x2c
+#define NAND_DEV1_CFG0 0x30
+#define NAND_DEV1_CFG1 0x34
+#define NAND_READ_ID 0x40
+#define NAND_READ_STATUS 0x44
+#define NAND_DEV_CMD0 0xa0
+#define NAND_DEV_CMD1 0xa4
+#define NAND_DEV_CMD2 0xa8
+#define NAND_DEV_CMD_VLD 0xac
+#define SFLASHC_BURST_CFG 0xe0
+#define NAND_ERASED_CW_DETECT_CFG 0xe8
+#define NAND_ERASED_CW_DETECT_STATUS 0xec
+#define NAND_EBI2_ECC_BUF_CFG 0xf0
+#define FLASH_BUF_ACC 0x100
+
+#define NAND_CTRL 0xf00
+#define NAND_VERSION 0xf08
+#define NAND_READ_LOCATION_0 0xf20
+#define NAND_READ_LOCATION_1 0xf24
+
+/* dummy register offsets, used by write_reg_dma */
+#define NAND_DEV_CMD1_RESTORE 0xdead
+#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
+
+/* NAND_FLASH_CMD bits */
+#define PAGE_ACC BIT(4)
+#define LAST_PAGE BIT(5)
+
+/* NAND_FLASH_CHIP_SELECT bits */
+#define NAND_DEV_SEL 0
+#define DM_EN BIT(2)
+
+/* NAND_FLASH_STATUS bits */
+#define FS_OP_ERR BIT(4)
+#define FS_READY_BSY_N BIT(5)
+#define FS_MPU_ERR BIT(8)
+#define FS_DEVICE_STS_ERR BIT(16)
+#define FS_DEVICE_WP BIT(23)
+
+/* NAND_BUFFER_STATUS bits */
+#define BS_UNCORRECTABLE_BIT BIT(8)
+#define BS_CORRECTABLE_ERR_MSK 0x1f
+
+/* NAND_DEVn_CFG0 bits */
+#define DISABLE_STATUS_AFTER_WRITE 4
+#define CW_PER_PAGE 6
+#define UD_SIZE_BYTES 9
+#define ECC_PARITY_SIZE_BYTES_RS 19
+#define SPARE_SIZE_BYTES 23
+#define NUM_ADDR_CYCLES 27
+#define STATUS_BFR_READ 30
+#define SET_RD_MODE_AFTER_STATUS 31
+
+/* NAND_DEVn_CFG0 bits */
+#define DEV0_CFG1_ECC_DISABLE 0
+#define WIDE_FLASH 1
+#define NAND_RECOVERY_CYCLES 2
+#define CS_ACTIVE_BSY 5
+#define BAD_BLOCK_BYTE_NUM 6
+#define BAD_BLOCK_IN_SPARE_AREA 16
+#define WR_RD_BSY_GAP 17
+#define ENABLE_BCH_ECC 27
+
+/* NAND_DEV0_ECC_CFG bits */
+#define ECC_CFG_ECC_DISABLE 0
+#define ECC_SW_RESET 1
+#define ECC_MODE 4
+#define ECC_PARITY_SIZE_BYTES_BCH 8
+#define ECC_NUM_DATA_BYTES 16
+#define ECC_FORCE_CLK_OPEN 30
+
+/* NAND_DEV_CMD1 bits */
+#define READ_ADDR 0
+
+/* NAND_DEV_CMD_VLD bits */
+#define READ_START_VLD 0
+
+/* NAND_EBI2_ECC_BUF_CFG bits */
+#define NUM_STEPS 0
+
+/* NAND_ERASED_CW_DETECT_CFG bits */
+#define ERASED_CW_ECC_MASK 1
+#define AUTO_DETECT_RES 0
+#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
+#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
+#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
+#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
+#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
+
+/* NAND_ERASED_CW_DETECT_STATUS bits */
+#define PAGE_ALL_ERASED BIT(7)
+#define CODEWORD_ALL_ERASED BIT(6)
+#define PAGE_ERASED BIT(5)
+#define CODEWORD_ERASED BIT(4)
+#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
+#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
+
+/* Version Mask */
+#define NAND_VERSION_MAJOR_MASK 0xf0000000
+#define NAND_VERSION_MAJOR_SHIFT 28
+#define NAND_VERSION_MINOR_MASK 0x0fff0000
+#define NAND_VERSION_MINOR_SHIFT 16
+
+/* NAND OP_CMDs */
+#define PAGE_READ 0x2
+#define PAGE_READ_WITH_ECC 0x3
+#define PAGE_READ_WITH_ECC_SPARE 0x4
+#define PROGRAM_PAGE 0x6
+#define PAGE_PROGRAM_WITH_ECC 0x7
+#define PROGRAM_PAGE_SPARE 0x9
+#define BLOCK_ERASE 0xa
+#define FETCH_ID 0xb
+#define RESET_DEVICE 0xd
+
+/*
+ * the NAND controller performs reads/writes with ECC in 516 byte chunks.
+ * the driver calls the chunks 'step' or 'codeword' interchangeably
+ */
+#define NANDC_STEP_SIZE 512
+
+/*
+ * the largest page size we support is 8K, this will have 16 steps/codewords
+ * of 512 bytes each
+ */
+#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
+
+/* we read at most 3 registers per codeword scan */
+#define MAX_REG_RD (3 * MAX_NUM_STEPS)
+
+/* ECC modes */
+#define ECC_NONE BIT(0)
+#define ECC_RS_4BIT BIT(1)
+#define ECC_BCH_4BIT BIT(2)
+#define ECC_BCH_8BIT BIT(3)
+
+struct desc_info {
+ struct list_head list;
+
+ enum dma_data_direction dir;
+ struct scatterlist sgl;
+ struct dma_async_tx_descriptor *dma_desc;
+};
+
+/*
+ * holds the current register values that we want to write. acts as a contiguous
+ * chunk of memory which we use to write the controller registers through DMA.
+ */
+struct nandc_regs {
+ __le32 cmd;
+ __le32 addr0;
+ __le32 addr1;
+ __le32 chip_sel;
+ __le32 exec;
+
+ __le32 cfg0;
+ __le32 cfg1;
+ __le32 ecc_bch_cfg;
+
+ __le32 clrflashstatus;
+ __le32 clrreadstatus;
+
+ __le32 cmd1;
+ __le32 vld;
+
+ __le32 orig_cmd1;
+ __le32 orig_vld;
+
+ __le32 ecc_buf_cfg;
+};
+
+/*
+ * @cmd_crci: ADM DMA CRCI for command flow control
+ * @data_crci: ADM DMA CRCI for data flow control
+ * @list: DMA descriptor list (list of desc_infos)
+ * @data_buffer: our local DMA buffer for page read/writes,
+ * used when we can't use the buffer provided
+ * by upper layers directly
+ * @buf_size/count/start: markers for chip->read_buf/write_buf functions
+ * @reg_read_buf: buffer for reading register data via DMA
+ * @reg_read_pos: marker for data read in reg_read_buf
+ * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
+ * ecc/non-ecc mode for the current nand flash
+ * device
+ * @regs: a contiguous chunk of memory for DMA register
+ * writes
+ * @ecc_strength: 4 bit or 8 bit ecc, received via DT
+ * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
+ * @ecc_modes: supported ECC modes by the current controller,
+ * initialized via DT match data
+ * @cw_size: the number of bytes in a single step/codeword
+ * of a page, consisting of all data, ecc, spare
+ * and reserved bytes
+ * @cw_data: the number of bytes within a codeword protected
+ * by ECC
+ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
+ * @status: value to be returned if NAND_CMD_STATUS command
+ * is executed
+ */
+struct qcom_nandc_data {
+ struct platform_device *pdev;
+ struct device *dev;
+
+ void __iomem *base;
+ struct resource *res;
+
+ struct clk *core_clk;
+ struct clk *aon_clk;
+
+ /* DMA stuff */
+ struct dma_chan *chan;
+ struct dma_slave_config slave_conf;
+ unsigned int cmd_crci;
+ unsigned int data_crci;
+ struct list_head list;
+
+ /* MTD stuff */
+ struct nand_chip chip;
+ struct mtd_info mtd;
+
+ /* local data buffer and markers */
+ u8 *data_buffer;
+ int buf_size;
+ int buf_count;
+ int buf_start;
+
+ /* local buffer to read back registers */
+ __le32 *reg_read_buf;
+ int reg_read_pos;
+
+ /* required configs */
+ u32 cfg0, cfg1;
+ u32 cfg0_raw, cfg1_raw;
+ u32 ecc_buf_cfg;
+ u32 ecc_bch_cfg;
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+ u32 sflashc_burst_cfg;
+ u32 cmd1, vld;
+
+ /* register state */
+ struct nandc_regs *regs;
+
+ /* things we get from DT */
+ int ecc_strength;
+ int bus_width;
+
+ u32 ecc_modes;
+
+ /* misc params */
+ int cw_size;
+ int cw_data;
+ bool use_ecc;
+ bool bch_enabled;
+ u8 status;
+ int last_command;
+};
+
+static inline u32 nandc_read(struct qcom_nandc_data *this, int offset)
+{
+ return ioread32(this->base + offset);
+}
+
+static inline void nandc_write(struct qcom_nandc_data *this, int offset,
+ u32 val)
+{
+ iowrite32(val, this->base + offset);
+}
+
+static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
+{
+ switch (offset) {
+ case NAND_FLASH_CMD:
+ return ®s->cmd;
+ case NAND_ADDR0:
+ return ®s->addr0;
+ case NAND_ADDR1:
+ return ®s->addr1;
+ case NAND_FLASH_CHIP_SELECT:
+ return ®s->chip_sel;
+ case NAND_EXEC_CMD:
+ return ®s->exec;
+ case NAND_FLASH_STATUS:
+ return ®s->clrflashstatus;
+ case NAND_DEV0_CFG0:
+ return ®s->cfg0;
+ case NAND_DEV0_CFG1:
+ return ®s->cfg1;
+ case NAND_DEV0_ECC_CFG:
+ return ®s->ecc_bch_cfg;
+ case NAND_READ_STATUS:
+ return ®s->clrreadstatus;
+ case NAND_DEV_CMD1:
+ return ®s->cmd1;
+ case NAND_DEV_CMD1_RESTORE:
+ return ®s->orig_cmd1;
+ case NAND_DEV_CMD_VLD:
+ return ®s->vld;
+ case NAND_DEV_CMD_VLD_RESTORE:
+ return ®s->orig_vld;
+ case NAND_EBI2_ECC_BUF_CFG:
+ return ®s->ecc_buf_cfg;
+ default:
+ return NULL;
+ }
+}
+
+static void set_nandc_reg(struct qcom_nandc_data *this, int offset, u32 val)
+{
+ struct nandc_regs *regs = this->regs;
+ __le32 *reg;
+
+ reg = offset_to_nandc_reg(regs, offset);
+
+ if (reg)
+ *reg = cpu_to_le32(val);
+}
+
+/* helper to configure address register values */
+static void set_address(struct qcom_nandc_data *this, u16 column, int page)
+{
+ struct nand_chip *chip = &this->chip;
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ column >>= 1;
+
+ set_nandc_reg(this, NAND_ADDR0, page << 16 | column);
+ set_nandc_reg(this, NAND_ADDR1, page >> 16 & 0xff);
+}
+
+/*
+ * update_rw_regs: set up read/write register values, these will be
+ * written to the NAND controller registers via DMA
+ *
+ * @num_cw: number of steps for the read/write operation
+ * @read: read or write operation
+ */
+static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
+{
+ u32 cmd, cfg0, cfg1, ecc_bch_cfg;
+
+ if (read) {
+ if (this->use_ecc)
+ cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
+ else
+ cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
+ } else {
+ cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
+ }
+
+ if (this->use_ecc) {
+ cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ cfg1 = this->cfg1;
+ ecc_bch_cfg = this->ecc_bch_cfg;
+ } else {
+ cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+
+ cfg1 = this->cfg1_raw;
+ ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ }
+
+ set_nandc_reg(this, NAND_FLASH_CMD, cmd);
+ set_nandc_reg(this, NAND_DEV0_CFG0, cfg0);
+ set_nandc_reg(this, NAND_DEV0_CFG1, cfg1);
+ set_nandc_reg(this, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
+ set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, this->ecc_buf_cfg);
+ set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
+ set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
+}
+
+static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
+ const void *vaddr, int size, bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ struct dma_slave_config slave_conf;
+ enum dma_transfer_direction dir_eng;
+ int r;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ sgl = &desc->sgl;
+
+ sg_init_one(sgl, vaddr, size);
+
+ if (read) {
+ dir_eng = DMA_DEV_TO_MEM;
+ desc->dir = DMA_FROM_DEVICE;
+ } else {
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ }
+
+ r = dma_map_sg(this->dev, sgl, 1, desc->dir);
+ if (r == 0) {
+ r = -ENOMEM;
+ goto err;
+ }
+
+ memset(&slave_conf, 0x00, sizeof(slave_conf));
+
+ slave_conf.device_fc = flow_control;
+ if (read) {
+ slave_conf.src_maxburst = 16;
+ slave_conf.src_addr = this->res->start + reg_off;
+ slave_conf.slave_id = this->data_crci;
+ } else {
+ slave_conf.dst_maxburst = 16;
+ slave_conf.dst_addr = this->res->start + reg_off;
+ slave_conf.slave_id = this->cmd_crci;
+ }
+
+ r = dmaengine_slave_config(this->chan, &slave_conf);
+ if (r) {
+ dev_err(this->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, dir_eng, 0);
+ if (!dma_desc) {
+ dev_err(this->dev, "failed to prepare desc\n");
+ r = -EINVAL;
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ list_add_tail(&desc->list, &this->list);
+
+ return 0;
+err:
+ kfree(desc);
+
+ return r;
+}
+
+/*
+ * read_reg_dma: prepares a descriptor to read a given number of
+ * contiguous registers to the reg_read_buf pointer
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to read
+ */
+static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
+{
+ bool flow_control = false;
+ void *vaddr;
+ int size;
+
+ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
+ flow_control = true;
+
+ size = num_regs * sizeof(u32);
+ vaddr = this->reg_read_buf + this->reg_read_pos;
+ this->reg_read_pos += num_regs;
+
+ return prep_dma_desc(this, true, first, vaddr, size, flow_control);
+}
+
+/*
+ * write_reg_dma: prepares a descriptor to write a given number of
+ * contiguous registers
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to write
+ */
+static int write_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
+{
+ bool flow_control = false;
+ struct nandc_regs *regs = this->regs;
+ void *vaddr;
+ int size;
+
+ vaddr = offset_to_nandc_reg(regs, first);
+
+ if (first == NAND_FLASH_CMD)
+ flow_control = true;
+
+ if (first == NAND_DEV_CMD1_RESTORE)
+ first = NAND_DEV_CMD1;
+
+ if (first == NAND_DEV_CMD_VLD_RESTORE)
+ first = NAND_DEV_CMD_VLD;
+
+ size = num_regs * sizeof(u32);
+
+ return prep_dma_desc(this, false, first, vaddr, size, flow_control);
+}
+
+/*
+ * read_data_dma: prepares a DMA descriptor to transfer data from the
+ * controller's internal buffer to the buffer 'vaddr'
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to write to
+ * @size: DMA transaction size in bytes
+ */
+static int read_data_dma(struct qcom_nandc_data *this, int reg_off,
+ const u8 *vaddr, int size)
+{
+ return prep_dma_desc(this, true, reg_off, vaddr, size, false);
+}
+
+/*
+ * write_data_dma: prepares a DMA descriptor to transfer data from
+ * 'vaddr' to the controller's internal buffer
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to read from
+ * @size: DMA transaction size in bytes
+ */
+static int write_data_dma(struct qcom_nandc_data *this, int reg_off,
+ const u8 *vaddr, int size)
+{
+ return prep_dma_desc(this, false, reg_off, vaddr, size, false);
+}
+
+/*
+ * helper to prepare dma descriptors to configure registers needed for reading a
+ * codeword/step in a page
+ */
+static void config_cw_read(struct qcom_nandc_data *this)
+{
+ write_reg_dma(this, NAND_FLASH_CMD, 3);
+ write_reg_dma(this, NAND_DEV0_CFG0, 3);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
+
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 2);
+ read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1);
+}
+
+/*
+ * helpers to prepare dma descriptors used to configure registers needed for
+ * writing a codeword/step in a page
+ */
+static void config_cw_write_pre(struct qcom_nandc_data *this)
+{
+ write_reg_dma(this, NAND_FLASH_CMD, 3);
+ write_reg_dma(this, NAND_DEV0_CFG0, 3);
+ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
+}
+
+static void config_cw_write_post(struct qcom_nandc_data *this)
+{
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, 1);
+ write_reg_dma(this, NAND_READ_STATUS, 1);
+}
+
+/*
+ * the following functions are used within chip->cmdfunc() to perform different
+ * NAND_CMD_* commands
+ */
+
+/* sets up descriptors for NAND_CMD_PARAM */
+static int nandc_param(struct qcom_nandc_data *this)
+{
+ /*
+ * NAND_CMD_PARAM is called before we know much about the FLASH chip
+ * in use. we configure the controller to perform a raw read of 512
+ * bytes to read onfi params
+ */
+ set_nandc_reg(this, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
+ set_nandc_reg(this, NAND_ADDR0, 0);
+ set_nandc_reg(this, NAND_ADDR1, 0);
+ set_nandc_reg(this, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
+ | 512 << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES);
+ set_nandc_reg(this, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | 0 << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE);
+ set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
+
+
+ /* configure CMD1 and VLD for ONFI param probing */
+ set_nandc_reg(this, NAND_DEV_CMD_VLD,
+ (this->vld & ~(1 << READ_START_VLD))
+ | 0 << READ_START_VLD);
+ set_nandc_reg(this, NAND_DEV_CMD1,
+ (this->cmd1 & ~(0xFF << READ_ADDR))
+ | NAND_CMD_PARAM << READ_ADDR);
+
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
+
+ set_nandc_reg(this, NAND_DEV_CMD1_RESTORE, this->cmd1);
+ set_nandc_reg(this, NAND_DEV_CMD_VLD_RESTORE, this->vld);
+
+ write_reg_dma(this, NAND_DEV_CMD_VLD, 1);
+ write_reg_dma(this, NAND_DEV_CMD1, 1);
+
+ this->buf_count = 512;
+ memset(this->data_buffer, 0xff, this->buf_count);
+
+ config_cw_read(this);
+
+ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->buf_count);
+
+ /* restore CMD1 and VLD regs */
+ write_reg_dma(this, NAND_DEV_CMD1_RESTORE, 1);
+ write_reg_dma(this, NAND_DEV_CMD_VLD_RESTORE, 1);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_ERASE1 */
+static int erase_block(struct qcom_nandc_data *this, int page_addr)
+{
+ set_nandc_reg(this, NAND_FLASH_CMD, BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
+ set_nandc_reg(this, NAND_ADDR0, page_addr);
+ set_nandc_reg(this, NAND_ADDR1, 0);
+ set_nandc_reg(this, NAND_DEV0_CFG0,
+ this->cfg0_raw & ~(7 << CW_PER_PAGE));
+ set_nandc_reg(this, NAND_DEV0_CFG1, this->cfg1_raw);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
+ set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
+ set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
+
+ write_reg_dma(this, NAND_FLASH_CMD, 3);
+ write_reg_dma(this, NAND_DEV0_CFG0, 2);
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1);
+
+ write_reg_dma(this, NAND_FLASH_STATUS, 1);
+ write_reg_dma(this, NAND_READ_STATUS, 1);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_READID */
+static int read_id(struct qcom_nandc_data *this, int column)
+{
+ if (column == -1)
+ return 0;
+
+ set_nandc_reg(this, NAND_FLASH_CMD, FETCH_ID);
+ set_nandc_reg(this, NAND_ADDR0, column);
+ set_nandc_reg(this, NAND_ADDR1, 0);
+ set_nandc_reg(this, NAND_FLASH_CHIP_SELECT, DM_EN);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
+
+ write_reg_dma(this, NAND_FLASH_CMD, 4);
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_READ_ID, 1);
+
+ return 0;
+}
+
+/* sets up descriptors for NAND_CMD_RESET */
+static int reset(struct qcom_nandc_data *this)
+{
+ set_nandc_reg(this, NAND_FLASH_CMD, RESET_DEVICE);
+ set_nandc_reg(this, NAND_EXEC_CMD, 1);
+
+ write_reg_dma(this, NAND_FLASH_CMD, 1);
+ write_reg_dma(this, NAND_EXEC_CMD, 1);
+
+ read_reg_dma(this, NAND_FLASH_STATUS, 1);
+
+ return 0;
+}
+
+/* helpers to submit/free our list of dma descriptors */
+static int submit_descs(struct qcom_nandc_data *this)
+{
+ struct desc_info *desc;
+ dma_cookie_t cookie = 0;
+
+ list_for_each_entry(desc, &this->list, list)
+ cookie = dmaengine_submit(desc->dma_desc);
+
+ if (dma_sync_wait(this->chan, cookie) != DMA_COMPLETE)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static void free_descs(struct qcom_nandc_data *this)
+{
+ struct desc_info *desc, *n;
+
+ list_for_each_entry_safe(desc, n, &this->list, list) {
+ list_del(&desc->list);
+ dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir);
+ kfree(desc);
+ }
+}
+
+/* reset the register read buffer for next NAND operation */
+static void clear_read_regs(struct qcom_nandc_data *this)
+{
+ this->reg_read_pos = 0;
+ memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(*this->reg_read_buf));
+}
+
+static void pre_command(struct qcom_nandc_data *this, int command)
+{
+ this->buf_count = 0;
+ this->buf_start = 0;
+ this->use_ecc = false;
+ this->last_command = command;
+
+ clear_read_regs(this);
+}
+
+/*
+ * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
+ * privately maintained status byte, this status byte can be read after
+ * NAND_CMD_STATUS is called
+ */
+static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int num_cw;
+ int i;
+
+ num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
+
+ for (i = 0; i < num_cw; i++) {
+ u32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
+
+ if (flash_status & FS_MPU_ERR)
+ this->status &= ~NAND_STATUS_WP;
+
+ if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
+ (flash_status & FS_DEVICE_STS_ERR)))
+ this->status |= NAND_STATUS_FAIL;
+ }
+}
+
+static void post_command(struct qcom_nandc_data *this, int command)
+{
+ switch (command) {
+ case NAND_CMD_READID:
+ memcpy(this->data_buffer, this->reg_read_buf, this->buf_count);
+ break;
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_ERASE1:
+ parse_erase_write_errors(this, command);
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Implements chip->cmdfunc. It's only used for a limited set of commands.
+ * The rest of the commands wouldn't be called by upper layers. For example,
+ * NAND_CMD_READOOB would never be called because we have our own versions
+ * of read_oob ops for nand_ecc_ctrl.
+ */
+static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct qcom_nandc_data *this = chip->priv;
+ bool wait = false;
+ int r = 0;
+
+ pre_command(this, command);
+
+ switch (command) {
+ case NAND_CMD_RESET:
+ r = reset(this);
+ wait = true;
+ break;
+
+ case NAND_CMD_READID:
+ this->buf_count = 4;
+ r = read_id(this, column);
+ wait = true;
+ break;
+
+ case NAND_CMD_PARAM:
+ r = nandc_param(this);
+ wait = true;
+ break;
+
+ case NAND_CMD_ERASE1:
+ r = erase_block(this, page_addr);
+ wait = true;
+ break;
+
+ case NAND_CMD_READ0:
+ /* we read the entire page for now */
+ WARN_ON(column != 0);
+
+ this->use_ecc = true;
+ set_address(this, 0, page_addr);
+ update_rw_regs(this, ecc->steps, true);
+ break;
+
+ case NAND_CMD_SEQIN:
+ WARN_ON(column != 0);
+ set_address(this, 0, page_addr);
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_STATUS:
+ case NAND_CMD_NONE:
+ default:
+ break;
+ }
+
+ if (r) {
+ dev_err(this->dev, "failure executing command %d\n",
+ command);
+ free_descs(this);
+ return;
+ }
+
+ if (wait) {
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev,
+ "failure submitting descs for command %d\n",
+ command);
+ }
+
+ free_descs(this);
+
+ post_command(this, command);
+}
+
+/*
+ * when using RS ECC, the NAND controller flags an error when reading an
+ * erased page. however, there are special characters at certain offsets when
+ * we read the erased page. we check here if the page is really empty. if so,
+ * we replace the magic characters with 0xffs
+ */
+static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS];
+ int i, j;
+
+ /* if BCH is enabled, HW will take care of detecting erased pages */
+ if (this->bch_enabled || !this->use_ecc)
+ return false;
+
+ for (i = 0; i < cwperpage; i++) {
+ u8 *empty1, *empty2;
+ u32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
+
+ /*
+ * an erased page flags an error in NAND_FLASH_STATUS, check if
+ * the page is erased by looking for 0x54s at offsets 3 and 175
+ * from the beginning of each codeword
+ */
+ if (!(flash_status & FS_OP_ERR))
+ break;
+
+ empty1 = &data_buf[3 + i * this->cw_data];
+ empty2 = &data_buf[175 + i * this->cw_data];
+
+ /*
+ * if the error wasn't because of an erased page, bail out and
+ * and let someone else do the error checking
+ */
+ if ((*empty1 == 0x54 && *empty2 == 0xff) ||
+ (*empty1 == 0xff && *empty2 == 0x54)) {
+ orig1[i] = *empty1;
+ orig2[i] = *empty2;
+
+ *empty1 = 0xff;
+ *empty2 = 0xff;
+ } else {
+ break;
+ }
+ }
+
+ if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize))
+ goto not_empty;
+
+ /*
+ * tell the caller that the page was empty and is fixed up, so that
+ * parse_read_errors() doesn't think it's an error
+ */
+ return true;
+
+not_empty:
+ /* restore original values if not empty*/
+ for (j = 0; j < i; j++) {
+ data_buf[3 + j * this->cw_data] = orig1[j];
+ data_buf[175 + j * this->cw_data] = orig2[j];
+ }
+
+ return false;
+}
+
+struct read_stats {
+ __le32 flash;
+ __le32 buffer;
+ __le32 erased_cw;
+};
+
+/*
+ * reads back status registers set by the controller to notify page read
+ * errors. this is equivalent to what 'ecc->correct()' would do.
+ */
+static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = ecc->steps;
+ unsigned int max_bitflips = 0;
+ int i;
+ struct read_stats *buf;
+
+ buf = (struct read_stats *)this->reg_read_buf;
+ for (i = 0; i < cwperpage; i++, buf++) {
+ unsigned int stat;
+ u32 flash, buffer, erased_cw;
+
+ flash = le32_to_cpu(buf->flash);
+ buffer = le32_to_cpu(buf->buffer);
+ erased_cw = le32_to_cpu(buf->erased_cw);
+
+ if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
+
+ /* ignore erased codeword errors */
+ if (this->bch_enabled) {
+ if ((erased_cw & ERASED_CW) == ERASED_CW)
+ continue;
+ } else if (erased_page) {
+ continue;
+ }
+
+ if (buffer & BS_UNCORRECTABLE_BIT) {
+ mtd->ecc_stats.failed++;
+ continue;
+ }
+ }
+
+ stat = buffer & BS_CORRECTABLE_ERR_MSK;
+ mtd->ecc_stats.corrected += stat;
+
+ max_bitflips = max(max_bitflips, stat);
+ }
+
+ return max_bitflips;
+}
+
+/*
+ * helper to perform the actual page read operation, used by ecc->read_page()
+ * and ecc->read_oob()
+ */
+static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf,
+ u8 *oob_buf)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int i, r;
+
+ /* queue cmd descs for each codeword */
+ for (i = 0; i < ecc->steps; i++) {
+ int data_size, oob_size;
+
+ if (i == (ecc->steps - 1)) {
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+ }
+
+ config_cw_read(this);
+
+ if (data_buf)
+ read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
+
+ if (oob_buf)
+ read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf,
+ oob_size);
+
+ if (data_buf)
+ data_buf += data_size;
+ if (oob_buf)
+ oob_buf += oob_size;
+ }
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to read page/oob\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/*
+ * a helper that copies the last step/codeword of a page (containing free oob)
+ * into our local buffer
+ */
+static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page)
+{
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int size;
+ int r;
+
+ clear_read_regs(this);
+
+ size = use_ecc ? this->cw_data : this->cw_size;
+
+ /* prepare a clean read buffer */
+ memset(this->data_buffer, 0xff, size);
+
+ this->use_ecc = use_ecc;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, true);
+
+ config_cw_read(this);
+
+ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size);
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failed to copy last codeword\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/* implements ecc->read_page() */
+static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ u8 *data_buf, *oob_buf = NULL;
+ bool erased_page;
+ int r;
+
+ data_buf = buf;
+ oob_buf = oob_required ? chip->oob_poi : NULL;
+
+ r = read_page_low(this, data_buf, oob_buf);
+ if (r) {
+ dev_err(this->dev, "failure to read page\n");
+ return r;
+ }
+
+ erased_page = empty_page_fixup(this, data_buf);
+
+ return parse_read_errors(this, erased_page);
+}
+
+/* implements ecc->read_oob() */
+static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int r;
+
+ clear_read_regs(this);
+
+ this->use_ecc = true;
+ set_address(this, 0, page);
+ update_rw_regs(this, ecc->steps, true);
+
+ r = read_page_low(this, NULL, chip->oob_poi);
+ if (r)
+ dev_err(this->dev, "failure to read oob\n");
+
+ return r;
+}
+
+/* implements ecc->read_oob_raw(), used to read the bad block marker flag */
+static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int start, length;
+ int r;
+
+ /*
+ * configure registers for a raw page read, the address is set to the
+ * beginning of the last codeword, we don't care about reading ecc
+ * portion of oob, just the free stuff
+ */
+ r = copy_last_cw(this, false, page);
+ if (r)
+ return r;
+
+ /*
+ * reading raw oob has 2 parts, first the bad block byte, then the
+ * actual free oob region. perform a memcpy in two steps
+ */
+ start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
+ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
+
+ memcpy(oob, this->data_buffer + start, length);
+
+ oob += length;
+
+ start = this->cw_data - (ecc->steps << 2) + 1;
+ length = ecc->steps << 2;
+
+ memcpy(oob, this->data_buffer + start, length);
+
+ return 0;
+}
+
+/* implements ecc->write_page() */
+static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ u8 *data_buf, *oob_buf;
+ int i, r = 0;
+
+ clear_read_regs(this);
+
+ data_buf = (u8 *) buf;
+ oob_buf = chip->oob_poi;
+
+ this->use_ecc = true;
+ update_rw_regs(this, ecc->steps, false);
+
+ for (i = 0; i < ecc->steps; i++) {
+ int data_size, oob_size;
+
+ if (i == (ecc->steps - 1)) {
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+ } else {
+ data_size = this->cw_data;
+ oob_size = ecc->bytes;
+ }
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
+
+ /*
+ * we don't really need to write anything to oob for the
+ * first n - 1 codewords since these oob regions just
+ * contain ecc that's written by the controller itself
+ */
+ if (i == (ecc->steps - 1))
+ write_data_dma(this, FLASH_BUF_ACC + data_size,
+ oob_buf, oob_size);
+ config_cw_write_post(this);
+
+ data_buf += data_size;
+ oob_buf += oob_size;
+ }
+
+ r = submit_descs(this);
+ if (r)
+ dev_err(this->dev, "failure to write page\n");
+
+ free_descs(this);
+
+ return r;
+}
+
+/*
+ * implements ecc->write_oob()
+ *
+ * the NAND controller cannot write only data or only oob within a codeword,
+ * since ecc is calculated for the combined codeword. we first copy the
+ * entire contents for the last codeword(data + oob), replace the old oob
+ * with the new one in chip->oob_poi, and then write the entire codeword.
+ * this read-copy-write operation results in a slight perormance loss.
+ */
+static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int free_boff;
+ int data_size, oob_size;
+ int r, status = 0;
+
+ r = copy_last_cw(this, true, page);
+ if (r)
+ return r;
+
+ clear_read_regs(this);
+
+ /* calculate the data and oob size for the last codeword/step */
+ data_size = ecc->size - ((ecc->steps - 1) << 2);
+ oob_size = (ecc->steps << 2) + ecc->bytes;
+
+ /*
+ * the location of spare data in the oob buffer, we could also use
+ * ecc->layout.oobfree here
+ */
+ free_boff = ecc->bytes * (ecc->steps - 1);
+
+ /* override new oob content to last codeword */
+ memcpy(this->data_buffer + data_size, oob + free_boff, oob_size);
+
+ this->use_ecc = true;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, false);
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer,
+ data_size + oob_size);
+ config_cw_write_post(this);
+
+ r = submit_descs(this);
+
+ free_descs(this);
+
+ if (r) {
+ dev_err(this->dev, "failure to write oob\n");
+ return -EIO;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/* implements ecc->write_oob_raw(), used to write bad block marker flag */
+static int qcom_nandc_write_oob_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ struct qcom_nandc_data *this = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ uint8_t *oob = chip->oob_poi;
+ int start, length;
+ int r, status = 0;
+
+ r = copy_last_cw(this, false, page);
+ if (r)
+ return r;
+
+ clear_read_regs(this);
+
+ /*
+ * writing raw oob has 2 parts, first the bad block region, then the
+ * actual free region
+ */
+ start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
+ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
+
+ memcpy(this->data_buffer + start, oob, length);
+
+ oob += length;
+
+ start = this->cw_data - (ecc->steps << 2) + 1;
+ length = ecc->steps << 2;
+
+ memcpy(this->data_buffer + start, oob, length);
+
+ /* prepare write */
+ this->use_ecc = false;
+ set_address(this, this->cw_size * (ecc->steps - 1), page);
+ update_rw_regs(this, 1, false);
+
+ config_cw_write_pre(this);
+ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size);
+ config_cw_write_post(this);
+
+ r = submit_descs(this);
+
+ free_descs(this);
+
+ if (r) {
+ dev_err(this->dev, "failure to write updated oob\n");
+ return -EIO;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/*
+ * the three functions below implement chip->read_byte(), chip->read_buf()
+ * and chip->write_buf() respectively. these aren't used for
+ * reading/writing page data, they are used for smaller data like reading
+ * id, status etc
+ */
+static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ uint8_t *buf = this->data_buffer;
+ uint8_t ret = 0x0;
+
+ if (this->last_command == NAND_CMD_STATUS) {
+ ret = this->status;
+
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+
+ return ret;
+ }
+
+ if (this->buf_start < this->buf_count)
+ ret = buf[this->buf_start++];
+
+ return ret;
+}
+
+static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(buf, this->data_buffer + this->buf_start, real_len);
+ this->buf_start += real_len;
+}
+
+static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+ int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
+
+ memcpy(this->data_buffer + this->buf_start, buf, real_len);
+
+ this->buf_start += real_len;
+}
+
+/* we support only one external chip for now */
+static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct qcom_nandc_data *this = chip->priv;
+
+ if (chipnr <= 0)
+ return;
+
+ dev_warn(this->dev, "invalid chip select\n");
+}
+
+/*
+ * NAND controller page layout info
+ *
+ * |-----------------------| |---------------------------------|
+ * | xx.......xx| | *********xx.......xx|
+ * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
+ * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
+ * | xx.......xx| | *********xx.......xx|
+ * |-----------------------| |---------------------------------|
+ * codeword 1,2..n-1 codeword n
+ * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
+ *
+ * n = number of codewords in the page
+ * . = ECC bytes
+ * * = spare bytes
+ * x = unused/reserved bytes
+ *
+ * 2K page: n = 4, spare = 16 bytes
+ * 4K page: n = 8, spare = 32 bytes
+ * 8K page: n = 16, spare = 64 bytes
+ *
+ * the qcom nand controller operates at a sub page/codeword level. each
+ * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
+ * the number of ECC bytes vary based on the ECC strength and the bus width.
+ *
+ * the first n - 1 codewords contains 516 bytes of user data, the remaining
+ * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
+ * both user data and spare(oobavail) bytes that sum up to 516 bytes.
+ *
+ * the layout described above is used by the controller when the ECC block is
+ * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
+ * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
+ * layouts defined below doesn't consider the positions occupied by the reserved
+ * bytes
+ *
+ * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
+ * in the last codeword is the position of bad block marker. the bad block
+ * marker cannot be accessed when ECC is enabled.
+ *
+ */
+
+/*
+ * Layouts for different page sizes and ecc modes. We skip the eccpos field
+ * since it isn't needed for this driver
+ */
+
+/* 2K page, 4 bit ECC */
+static struct nand_ecclayout layout_oob_64 = {
+ .eccbytes = 40,
+ .oobfree = {
+ { 30, 16 },
+ },
+};
+
+/* 4K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_128 = {
+ .eccbytes = 80,
+ .oobfree = {
+ { 70, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 8 bit bus width */
+static struct nand_ecclayout layout_oob_224_x8 = {
+ .eccbytes = 104,
+ .oobfree = {
+ { 91, 32 },
+ },
+};
+
+/* 4K page, 8 bit ECC, 16 bit bus width */
+static struct nand_ecclayout layout_oob_224_x16 = {
+ .eccbytes = 112,
+ .oobfree = {
+ { 98, 32 },
+ },
+};
+
+/* 8K page, 4 bit ECC, 8/16 bit bus width */
+static struct nand_ecclayout layout_oob_256 = {
+ .eccbytes = 160,
+ .oobfree = {
+ { 151, 64 },
+ },
+};
+
+/*
+ * this is called before scan_ident, we do some minimal configurations so
+ * that reading ID and ONFI params work
+ */
+static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
+{
+ /* kill onenand */
+ nandc_write(this, SFLASHC_BURST_CFG, 0);
+
+ /* enable ADM DMA */
+ nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
+
+ /* save the original values of these registers */
+ this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
+ this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
+
+ /* initial status value */
+ this->status = NAND_STATUS_READY | NAND_STATUS_WP;
+}
+
+static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage;
+ bool wide_bus;
+
+ /* the nand controller fetches codewords/chunks of 512 bytes */
+ cwperpage = mtd->writesize >> 9;
+
+ ecc->strength = this->ecc_strength;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 8) {
+ /* 8 bit ECC defaults to BCH ECC on all platforms */
+ ecc->bytes = wide_bus ? 14 : 13;
+ } else {
+ /*
+ * if the controller supports BCH for 4 bit ECC, the controller
+ * uses lesser bytes for ECC. If RS is used, the ECC bytes is
+ * always 10 bytes
+ */
+ if (this->ecc_modes & ECC_BCH_4BIT)
+ ecc->bytes = wide_bus ? 8 : 7;
+ else
+ ecc->bytes = 10;
+ }
+
+ /* each step consists of 512 bytes of data */
+ ecc->size = NANDC_STEP_SIZE;
+
+ ecc->read_page = qcom_nandc_read_page;
+ ecc->read_oob = qcom_nandc_read_oob;
+ ecc->write_page = qcom_nandc_write_page;
+ ecc->write_oob = qcom_nandc_write_oob;
+
+ /*
+ * the bad block marker is readable only when we read the page with ECC
+ * disabled. all the ops above run with ECC enabled. We need raw read
+ * and write function for oob in order to access bad block marker.
+ */
+ ecc->read_oob_raw = qcom_nandc_read_oob_raw;
+ ecc->write_oob_raw = qcom_nandc_write_oob_raw;
+
+ switch (mtd->oobsize) {
+ case 64:
+ ecc->layout = &layout_oob_64;
+ break;
+ case 128:
+ ecc->layout = &layout_oob_128;
+ break;
+ case 224:
+ if (wide_bus)
+ ecc->layout = &layout_oob_224_x16;
+ else
+ ecc->layout = &layout_oob_224_x8;
+ break;
+ case 256:
+ ecc->layout = &layout_oob_256;
+ break;
+ default:
+ dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
+ mtd->oobsize);
+ return -ENODEV;
+ }
+
+ ecc->mode = NAND_ECC_HW;
+
+ /* enable ecc by default */
+ this->use_ecc = true;
+
+ return 0;
+}
+
+static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int cwperpage = mtd->writesize / ecc->size;
+ int spare_bytes, bad_block_byte;
+ bool wide_bus;
+ int ecc_mode = 0;
+
+ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+
+ if (ecc->strength >= 8) {
+ this->cw_size = 532;
+
+ spare_bytes = wide_bus ? 0 : 2;
+
+ this->bch_enabled = true;
+ ecc_mode = 1;
+ } else {
+ this->cw_size = 528;
+
+ if (this->ecc_modes & ECC_BCH_4BIT) {
+ spare_bytes = wide_bus ? 2 : 4;
+
+ this->bch_enabled = true;
+ ecc_mode = 0;
+ } else {
+ spare_bytes = wide_bus ? 0 : 1;
+ }
+ }
+
+ /*
+ * DATA_UD_BYTES varies based on whether the read/write command protects
+ * spare data with ECC too. We protect spare data by default, so we set
+ * it to main + spare data, which are 512 and 4 bytes respectively.
+ */
+ this->cw_data = 516;
+
+ bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
+
+ this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_data << UD_SIZE_BYTES
+ | 0 << DISABLE_STATUS_AFTER_WRITE
+ | 5 << NUM_ADDR_CYCLES
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
+ | 0 << STATUS_BFR_READ
+ | 1 << SET_RD_MODE_AFTER_STATUS
+ | spare_bytes << SPARE_SIZE_BYTES;
+
+ this->cfg1 = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | bad_block_byte << BAD_BLOCK_BYTE_NUM
+ | 0 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | this->bch_enabled << ENABLE_BCH_ECC;
+
+ this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
+ | this->cw_size << UD_SIZE_BYTES
+ | 5 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 2 << WR_RD_BSY_GAP
+ | wide_bus << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
+ | 0 << ECC_SW_RESET
+ | this->cw_data << ECC_NUM_DATA_BYTES
+ | 1 << ECC_FORCE_CLK_OPEN
+ | ecc_mode << ECC_MODE
+ | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
+
+ this->ecc_buf_cfg = 0x203 << NUM_STEPS;
+
+ this->clrflashstatus = FS_READY_BSY_N;
+ this->clrreadstatus = 0xc0;
+
+ dev_dbg(this->dev,
+ "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
+ this->cfg0, this->cfg1, this->ecc_buf_cfg,
+ this->ecc_bch_cfg, this->cw_size, this->cw_data,
+ ecc->strength, ecc->bytes, cwperpage);
+}
+
+static int qcom_nandc_alloc(struct qcom_nandc_data *this)
+{
+ int r;
+
+ r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
+ if (r) {
+ dev_err(this->dev, "failed to set DMA mask\n");
+ return r;
+ }
+
+ /*
+ * we use the internal buffer for reading ONFI params, reading small
+ * data like ID and status, and preforming read-copy-write operations
+ * when writing to a codeword partially. 532 is the maximum possible
+ * size of a codeword for our nand controller
+ */
+ this->buf_size = 532;
+
+ this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
+ if (!this->data_buffer)
+ return -ENOMEM;
+
+ this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL);
+ if (!this->regs)
+ return -ENOMEM;
+
+ this->reg_read_buf = devm_kzalloc(this->dev,
+ MAX_REG_RD * sizeof(*this->reg_read_buf),
+ GFP_KERNEL);
+ if (!this->reg_read_buf)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&this->list);
+
+ this->chan = dma_request_slave_channel(this->dev, "rxtx");
+ if (!this->chan) {
+ dev_err(this->dev, "failed to request slave channel\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
+{
+ dma_release_channel(this->chan);
+}
+
+static int qcom_nandc_init(struct qcom_nandc_data *this)
+{
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->chip;
+ struct device_node *np = this->dev->of_node;
+ struct mtd_part_parser_data ppdata = { .of_node = np };
+ int r;
+
+ mtd->priv = chip;
+ mtd->name = "qcom-nandc";
+ mtd->owner = THIS_MODULE;
+
+ chip->priv = this;
+
+ chip->cmdfunc = qcom_nandc_command;
+ chip->select_chip = qcom_nandc_select_chip;
+ chip->read_byte = qcom_nandc_read_byte;
+ chip->read_buf = qcom_nandc_read_buf;
+ chip->write_buf = qcom_nandc_write_buf;
+
+ chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
+ if (this->bus_width == 16)
+ chip->options |= NAND_BUSWIDTH_16;
+
+ chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
+ if (of_get_nand_on_flash_bbt(np))
+ chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+
+ qcom_nandc_pre_init(this);
+
+ r = nand_scan_ident(mtd, 1, NULL);
+ if (r)
+ return r;
+
+ r = qcom_nandc_ecc_init(this);
+ if (r)
+ return r;
+
+ qcom_nandc_hw_post_init(this);
+
+ r = nand_scan_tail(mtd);
+ if (r)
+ return r;
+
+ return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+}
+
+static int qcom_nandc_parse_dt(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this = platform_get_drvdata(pdev);
+ struct device_node *np = this->dev->of_node;
+ int r;
+
+ this->ecc_strength = of_get_nand_ecc_strength(np);
+ if (this->ecc_strength < 0) {
+ dev_warn(this->dev,
+ "incorrect ecc strength, setting to 4 bits/step\n");
+ this->ecc_strength = 4;
+ }
+
+ this->bus_width = of_get_nand_bus_width(np);
+ if (this->bus_width < 0) {
+ dev_warn(this->dev, "incorrect bus width, setting to 8\n");
+ this->bus_width = 8;
+ }
+
+ r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
+ if (r) {
+ dev_err(this->dev, "command CRCI unspecified\n");
+ return r;
+ }
+
+ r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
+ if (r) {
+ dev_err(this->dev, "data CRCI unspecified\n");
+ return r;
+ }
+
+ return 0;
+}
+
+static int qcom_nandc_probe(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this;
+ const void *dev_data;
+ int r;
+
+ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
+ if (!this)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, this);
+
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+
+ dev_data = of_device_get_match_data(&pdev->dev);
+ if (!dev_data) {
+ dev_err(&pdev->dev, "failed to get device data\n");
+ return -ENODEV;
+ }
+
+ this->ecc_modes = (unsigned long)dev_data;
+
+ this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ this->base = devm_ioremap_resource(&pdev->dev, this->res);
+ if (IS_ERR(this->base))
+ return PTR_ERR(this->base);
+
+ this->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(this->core_clk))
+ return PTR_ERR(this->core_clk);
+
+ this->aon_clk = devm_clk_get(&pdev->dev, "aon");
+ if (IS_ERR(this->aon_clk))
+ return PTR_ERR(this->aon_clk);
+
+ r = qcom_nandc_parse_dt(pdev);
+ if (r)
+ return r;
+
+ r = qcom_nandc_alloc(this);
+ if (r)
+ return r;
+
+ r = clk_prepare_enable(this->core_clk);
+ if (r)
+ goto err_core_clk;
+
+ r = clk_prepare_enable(this->aon_clk);
+ if (r)
+ goto err_aon_clk;
+
+ r = qcom_nandc_init(this);
+ if (r)
+ goto err_init;
+
+ return 0;
+
+err_init:
+ clk_disable_unprepare(this->aon_clk);
+err_aon_clk:
+ clk_disable_unprepare(this->core_clk);
+err_core_clk:
+ qcom_nandc_unalloc(this);
+
+ return r;
+}
+
+static int qcom_nandc_remove(struct platform_device *pdev)
+{
+ struct qcom_nandc_data *this = platform_get_drvdata(pdev);
+
+ qcom_nandc_unalloc(this);
+
+ clk_disable_unprepare(this->aon_clk);
+ clk_disable_unprepare(this->core_clk);
+
+ return 0;
+}
+
+#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
+
+/*
+ * data will hold a struct pointer containing more differences once we support
+ * more IPs
+ */
+static const struct of_device_id qcom_nandc_of_match[] = {
+ { .compatible = "qcom,ebi2-nandc",
+ .data = (void *) EBI2_NANDC_ECC_MODES,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
+
+static struct platform_driver qcom_nandc_driver = {
+ .driver = {
+ .name = "qcom-nandc",
+ .of_match_table = qcom_nandc_of_match,
+ },
+ .probe = qcom_nandc_probe,
+ .remove = qcom_nandc_remove,
+};
+module_platform_driver(qcom_nandc_driver);
+
+MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
+MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-19 4:49 ` [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
@ 2015-08-19 4:49 ` Archit Taneja
2015-12-16 6:33 ` Boris Brezillon
2015-08-19 4:49 ` [PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-08-19 4:49 ` [PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
4 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-08-19 4:49 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja, devicetree
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicetree@vger.kernel.org
v4:
- No changes
v3:
- Don't use '0x' when specifying nand controller address space
- Add optional property for on-flash bbt usage
Acked-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
new file mode 100644
index 0000000..1de4643
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -0,0 +1,49 @@
+* Qualcomm NAND controller
+
+Required properties:
+- compatible: should be "qcom,ebi2-nand" for IPQ806x
+- reg: MMIO address range
+- clocks: must contain core clock and always on clock
+- clock-names: must contain "core" for the core clock and "aon" for the
+ always on clock
+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
+ controller node and the channel number to be used for
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
+- dma-names: must be "rxtx"
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+- qcom,data-crci: must contain the ADM data type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+
+Optional properties:
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
+ as default
+
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
+ bits. If not present, 4 is chosen as default
+- nand-on-flash-bbt: Create/use on-flash bad block table
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ partition@0 {
+ ...
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (2 preceding siblings ...)
2015-08-19 4:49 ` [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
@ 2015-08-19 4:49 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
4 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-19 4:49 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja, devicetree
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicetree@vger.kernel.org
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 1e1b3f0..a7f0ee5 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -350,5 +350,20 @@
status = "disabled";
};
+ nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ status = "disabled";
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
` (3 preceding siblings ...)
2015-08-19 4:49 ` [PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
@ 2015-08-19 4:49 ` Archit Taneja
4 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-08-19 4:49 UTC (permalink / raw)
To: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd
Cc: linux-arm-msm, agross, linux-kernel, Archit Taneja, devicetree
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
v4:
- Move bias-disable out of mux and create a separate group for it.
- Place the dma node inside soc node and give the full path with address.
v3, v2, v1:
- No changes
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40 ++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..648994c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,32 @@
bias-none;
};
};
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ };
+ disable {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38";
+ bias-disable;
+ };
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
gsbi@16300000 {
@@ -93,5 +119,19 @@
sata@29000000 {
status = "ok";
};
+
+ dma@18300000 {
+ status = "ok";
+ };
+
+ nand@1ac00000 {
+ status = "ok";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
@ 2015-08-26 23:37 ` Stephen Boyd
2015-09-13 13:42 ` Archit Taneja
2015-10-02 3:05 ` Brian Norris
` (2 subsequent siblings)
3 siblings, 1 reply; 71+ messages in thread
From: Stephen Boyd @ 2015-08-26 23:37 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace,
linux-arm-msm, agross, linux-kernel
On 08/19, Archit Taneja wrote:
> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
> MDM9x15 series.
>
> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
> and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
> broader interface for external slow peripheral devices such as LCD and
> NAND/NOR flash memory or SRAM like interfaces.
>
> We add support for the NAND controller found within EBI2. For the SoCs
> of our interest, we only use the NAND controller within EBI2. Therefore,
> it's safe for us to assume that the NAND controller is a standalone block
> within the SoC.
>
> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
> flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
> 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
> and spare data. The controller contains an internal 512 byte page buffer
> to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
> for register read/write and data transfers. The controller performs page
> reads and writes at a codeword/step level of 512 bytes. It can support up
> to 2 external chips of different configurations.
>
> The driver prepares register read and write configuration descriptors for
> each codeword, followed by data descriptors to read or write data from the
> controller's internal buffer. It uses a single ADM DMA channel that we get
> via dmaengine API. The controller requires 2 ADM CRCIs for command and
> data flow control. These are passed via DT.
>
> The ecc layout used by the controller is syndrome like, but we can't use
> the standard syndrome ecc ops because of several reasons. First, the amount
> of data bytes covered by ecc isn't same in each step. Second, writing to
> free oob space requires us writing to the entire step in which the oob
> lies. This forces us to create our own ecc ops.
>
> One more difference is how the controller accesses the bad block marker.
> The controller ignores reading the marker when ECC is enabled. ECC needs
> to be explicity disabled to read or write to the bad block marker. For
> this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
> read the factory provided bad block markers.
>
> v4:
> - Shrink submit_descs
> - add desc list node at the end of dma_prep_desc
> - Endianness and warning fixes
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>
> v3:
> - Refactor dma functions for maximum reuse
> - Use dma_slave_confing on stack
> - optimize and clean upempty_page_fixup using memchr_inv
> - ensure portability with dma register reads using le32_* funcs
> - use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
> - fix handling of return values of dmaengine funcs
> - constify wherever possible
> - Remove dependency on ADM DMA in Kconfig
> - Misc fixes and clean ups
>
> v2:
> - Use new BBT flag that allows us to read BBM in raw mode
> - reduce memcpy-s in the driver
> - some refactor and clean ups because of above changes
>
> Reviewed-by: Andy Gross <agross@codeaurora.org>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-26 23:37 ` Stephen Boyd
@ 2015-09-13 13:42 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-09-13 13:42 UTC (permalink / raw)
To: linux-mtd, computersforpeace
Cc: Stephen Boyd, dehrenberg, cernekee, linux-arm-msm, agross, linux-kernel
On 8/27/2015 5:07 AM, Stephen Boyd wrote:
> On 08/19, Archit Taneja wrote:
>> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
>> MDM9x15 series.
>>
>> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
>> and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
>> broader interface for external slow peripheral devices such as LCD and
>> NAND/NOR flash memory or SRAM like interfaces.
>>
>> We add support for the NAND controller found within EBI2. For the SoCs
>> of our interest, we only use the NAND controller within EBI2. Therefore,
>> it's safe for us to assume that the NAND controller is a standalone block
>> within the SoC.
>>
>> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
>> flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
>> 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
>> and spare data. The controller contains an internal 512 byte page buffer
>> to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
>> for register read/write and data transfers. The controller performs page
>> reads and writes at a codeword/step level of 512 bytes. It can support up
>> to 2 external chips of different configurations.
>>
>> The driver prepares register read and write configuration descriptors for
>> each codeword, followed by data descriptors to read or write data from the
>> controller's internal buffer. It uses a single ADM DMA channel that we get
>> via dmaengine API. The controller requires 2 ADM CRCIs for command and
>> data flow control. These are passed via DT.
>>
>> The ecc layout used by the controller is syndrome like, but we can't use
>> the standard syndrome ecc ops because of several reasons. First, the amount
>> of data bytes covered by ecc isn't same in each step. Second, writing to
>> free oob space requires us writing to the entire step in which the oob
>> lies. This forces us to create our own ecc ops.
>>
>> One more difference is how the controller accesses the bad block marker.
>> The controller ignores reading the marker when ECC is enabled. ECC needs
>> to be explicity disabled to read or write to the bad block marker. For
>> this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
>> read the factory provided bad block markers.
>>
>> v4:
>> - Shrink submit_descs
>> - add desc list node at the end of dma_prep_desc
>> - Endianness and warning fixes
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>>
>> v3:
>> - Refactor dma functions for maximum reuse
>> - Use dma_slave_confing on stack
>> - optimize and clean upempty_page_fixup using memchr_inv
>> - ensure portability with dma register reads using le32_* funcs
>> - use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
>> - fix handling of return values of dmaengine funcs
>> - constify wherever possible
>> - Remove dependency on ADM DMA in Kconfig
>> - Misc fixes and clean ups
>>
>> v2:
>> - Use new BBT flag that allows us to read BBM in raw mode
>> - reduce memcpy-s in the driver
>> - some refactor and clean ups because of above changes
>>
>> Reviewed-by: Andy Gross <agross@codeaurora.org>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>> ---
>
> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
>
Can someone from the the linux-mtd community review this?
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-08-19 4:49 ` [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
@ 2015-10-02 2:44 ` Brian Norris
2015-10-02 6:27 ` Boris Brezillon
0 siblings, 1 reply; 71+ messages in thread
From: Brian Norris @ 2015-10-02 2:44 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, sboyd, linux-arm-msm, agross,
linux-kernel
On Wed, Aug 19, 2015 at 10:19:02AM +0530, Archit Taneja wrote:
> Some controllers can access the factory bad block marker from OOB only
> when they read it in raw mode. When ECC is enabled, these controllers
> discard reading/writing bad block markers, preventing access to them
> altogether.
>
> The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
> This results in the nand driver's ecc->read_oob() op to be called, which
> works with ECC enabled.
>
> Create a new BBT option flag that tells nand_bbt to force the mode to
> MTD_OPS_RAW. This would result in the correct op being called for the
> underlying nand controller driver.
MTD_OPS_RAW is probably the best way to do this, and we should switch
back to it for all users (rather than a new flag). But to do this, we
need to fix up some things. Particularly, we need to extend
'badblockbits' support so that it is applied consistently in all places
(I recall there is one code path in which bad block scanning does take
this into account, and one that doesn't.)
About badblockbits: it allows us to do a relaxed heuristic on matching
bad block markers, where we say the BBM is "bad" if more than fewer than
N bits are '1'. Right now, we just say that if there are any 0 bits in
the Bad Block Marker (BBM) region, then the block is bad. But this is
problematic for pages that have been worn down and might have bitflips.
So right now, part of a (bad) solution is to read with ECC, so worn
blocks that have data won't be later interpreted as bad blocks if we
rescan the BBMs (ECC will correct the bitflips, if the OOB is
protected).
But that solution is not really good, since ECC is not really a panacea
for misinterpreted BBMs. And HW like yours apparently won't work like
this.
So in summary: if we can consistently make BBM checks look for 6 or 7
"one" bits (rather than a full 8 bits, i.e. BBM == 0xff), then we can
just unconditionally switch to RAW rather than PLACE_OOB. And we don't
need a flag like this pach introduces.
Brian
> Reviewed-by: Andy Gross <agross@codeaurora.org>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
> drivers/mtd/nand/nand_base.c | 6 +++++-
> drivers/mtd/nand/nand_bbt.c | 6 +++++-
> include/linux/mtd/bbm.h | 7 +++++++
> 3 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index ceb68ca..0a0c524 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -394,7 +394,11 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
> } else {
> ops.len = ops.ooblen = 1;
> }
> - ops.mode = MTD_OPS_PLACE_OOB;
> +
> + if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
> + ops.mode = MTD_OPS_RAW;
> + else
> + ops.mode = MTD_OPS_PLACE_OOB;
>
> /* Write to first/last page(s) if necessary */
> if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
> diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
> index 63a1a36..f2d89c9 100644
> --- a/drivers/mtd/nand/nand_bbt.c
> +++ b/drivers/mtd/nand/nand_bbt.c
> @@ -420,7 +420,11 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
> ops.oobbuf = buf;
> ops.ooboffs = 0;
> ops.datbuf = NULL;
> - ops.mode = MTD_OPS_PLACE_OOB;
> +
> + if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
> + ops.mode = MTD_OPS_RAW;
> + else
> + ops.mode = MTD_OPS_PLACE_OOB;
>
> for (j = 0; j < numpages; j++) {
> /*
> diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
> index 36bb6a5..f67f84a 100644
> --- a/include/linux/mtd/bbm.h
> +++ b/include/linux/mtd/bbm.h
> @@ -116,6 +116,13 @@ struct nand_bbt_descr {
> #define NAND_BBT_NO_OOB_BBM 0x00080000
>
> /*
> + * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
> + * be used by controllers which can access BBM only when ECC is disabled, i.e,
> + * when in RAW access mode
> + */
> +#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
> +
> +/*
> * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
> * was allocated dynamicaly and must be freed in nand_release(). Has no meaning
> * in nand_chip.bbt_options.
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-08-26 23:37 ` Stephen Boyd
@ 2015-10-02 3:05 ` Brian Norris
2015-10-05 6:51 ` Archit Taneja
2015-10-02 17:31 ` Brian Norris
2015-12-16 9:15 ` Boris Brezillon
3 siblings, 1 reply; 71+ messages in thread
From: Brian Norris @ 2015-10-02 3:05 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, sboyd, linux-arm-msm, agross,
linux-kernel, Boris Brezillon
Hi Archit,
On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
> MDM9x15 series.
>
> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
> and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
> broader interface for external slow peripheral devices such as LCD and
> NAND/NOR flash memory or SRAM like interfaces.
>
> We add support for the NAND controller found within EBI2. For the SoCs
> of our interest, we only use the NAND controller within EBI2. Therefore,
> it's safe for us to assume that the NAND controller is a standalone block
> within the SoC.
>
> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
> flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
> 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
> and spare data. The controller contains an internal 512 byte page buffer
> to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
> for register read/write and data transfers. The controller performs page
> reads and writes at a codeword/step level of 512 bytes. It can support up
> to 2 external chips of different configurations.
>
> The driver prepares register read and write configuration descriptors for
> each codeword, followed by data descriptors to read or write data from the
> controller's internal buffer. It uses a single ADM DMA channel that we get
> via dmaengine API. The controller requires 2 ADM CRCIs for command and
> data flow control. These are passed via DT.
>
> The ecc layout used by the controller is syndrome like, but we can't use
> the standard syndrome ecc ops because of several reasons. First, the amount
> of data bytes covered by ecc isn't same in each step. Second, writing to
> free oob space requires us writing to the entire step in which the oob
> lies. This forces us to create our own ecc ops.
>
> One more difference is how the controller accesses the bad block marker.
> The controller ignores reading the marker when ECC is enabled. ECC needs
> to be explicity disabled to read or write to the bad block marker. For
> this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
> read the factory provided bad block markers.
>
> v4:
> - Shrink submit_descs
> - add desc list node at the end of dma_prep_desc
> - Endianness and warning fixes
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Where does this sign-off come into play? It's not grouped with yours.
Did Stephen have something to do with v4 only? Also, we typically trim
the change log from the commit message (and place it below the '---' to
do this automatically). Or did you intend for these changelogs to stay
in the git history? I suppose it's not really harmful to keep it in if
you'd like...
>
> v3:
> - Refactor dma functions for maximum reuse
> - Use dma_slave_confing on stack
> - optimize and clean upempty_page_fixup using memchr_inv
> - ensure portability with dma register reads using le32_* funcs
> - use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
> - fix handling of return values of dmaengine funcs
> - constify wherever possible
> - Remove dependency on ADM DMA in Kconfig
> - Misc fixes and clean ups
>
> v2:
> - Use new BBT flag that allows us to read BBM in raw mode
> - reduce memcpy-s in the driver
> - some refactor and clean ups because of above changes
>
> Reviewed-by: Andy Gross <agross@codeaurora.org>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
Has this driver been tested with drivers/mtd/tests/? Which ones? I'm
particularly interested in oobtest, since you attempted to handle both
ECC and raw OOB.
> ---
> drivers/mtd/nand/Kconfig | 7 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qcom_nandc.c | 1910 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1918 insertions(+)
> create mode 100644 drivers/mtd/nand/qcom_nandc.c
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 5b2806a..6085b8a 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -538,4 +538,11 @@ config MTD_NAND_HISI504
> help
> Enables support for NAND controller on Hisilicon SoC Hip04.
>
> +config MTD_NAND_QCOM
> + tristate "Support for NAND on QCOM SoCs"
> + depends on ARCH_QCOM
> + help
> + Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> + controller. This controller is found on IPQ806x SoC.
> +
> endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 1f897ec..87b6a1d 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
> obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
> obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
> +obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>
> nand-objs := nand_base.o nand_bbt.o nand_timings.o
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> new file mode 100644
> index 0000000..2337731
> --- /dev/null
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -0,0 +1,1910 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/bitops.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> +#include <linux/module.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_mtd.h>
> +#include <linux/delay.h>
> +
> +/* NANDc reg offsets */
> +#define NAND_FLASH_CMD 0x00
> +#define NAND_ADDR0 0x04
> +#define NAND_ADDR1 0x08
> +#define NAND_FLASH_CHIP_SELECT 0x0c
> +#define NAND_EXEC_CMD 0x10
> +#define NAND_FLASH_STATUS 0x14
> +#define NAND_BUFFER_STATUS 0x18
> +#define NAND_DEV0_CFG0 0x20
> +#define NAND_DEV0_CFG1 0x24
> +#define NAND_DEV0_ECC_CFG 0x28
> +#define NAND_DEV1_ECC_CFG 0x2c
> +#define NAND_DEV1_CFG0 0x30
> +#define NAND_DEV1_CFG1 0x34
> +#define NAND_READ_ID 0x40
> +#define NAND_READ_STATUS 0x44
> +#define NAND_DEV_CMD0 0xa0
> +#define NAND_DEV_CMD1 0xa4
> +#define NAND_DEV_CMD2 0xa8
> +#define NAND_DEV_CMD_VLD 0xac
> +#define SFLASHC_BURST_CFG 0xe0
> +#define NAND_ERASED_CW_DETECT_CFG 0xe8
> +#define NAND_ERASED_CW_DETECT_STATUS 0xec
> +#define NAND_EBI2_ECC_BUF_CFG 0xf0
> +#define FLASH_BUF_ACC 0x100
> +
> +#define NAND_CTRL 0xf00
> +#define NAND_VERSION 0xf08
> +#define NAND_READ_LOCATION_0 0xf20
> +#define NAND_READ_LOCATION_1 0xf24
> +
> +/* dummy register offsets, used by write_reg_dma */
> +#define NAND_DEV_CMD1_RESTORE 0xdead
> +#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
> +
> +/* NAND_FLASH_CMD bits */
> +#define PAGE_ACC BIT(4)
> +#define LAST_PAGE BIT(5)
> +
> +/* NAND_FLASH_CHIP_SELECT bits */
> +#define NAND_DEV_SEL 0
> +#define DM_EN BIT(2)
> +
> +/* NAND_FLASH_STATUS bits */
> +#define FS_OP_ERR BIT(4)
> +#define FS_READY_BSY_N BIT(5)
> +#define FS_MPU_ERR BIT(8)
> +#define FS_DEVICE_STS_ERR BIT(16)
> +#define FS_DEVICE_WP BIT(23)
> +
> +/* NAND_BUFFER_STATUS bits */
> +#define BS_UNCORRECTABLE_BIT BIT(8)
> +#define BS_CORRECTABLE_ERR_MSK 0x1f
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DISABLE_STATUS_AFTER_WRITE 4
> +#define CW_PER_PAGE 6
> +#define UD_SIZE_BYTES 9
> +#define ECC_PARITY_SIZE_BYTES_RS 19
> +#define SPARE_SIZE_BYTES 23
> +#define NUM_ADDR_CYCLES 27
> +#define STATUS_BFR_READ 30
> +#define SET_RD_MODE_AFTER_STATUS 31
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DEV0_CFG1_ECC_DISABLE 0
> +#define WIDE_FLASH 1
> +#define NAND_RECOVERY_CYCLES 2
> +#define CS_ACTIVE_BSY 5
> +#define BAD_BLOCK_BYTE_NUM 6
> +#define BAD_BLOCK_IN_SPARE_AREA 16
> +#define WR_RD_BSY_GAP 17
> +#define ENABLE_BCH_ECC 27
> +
> +/* NAND_DEV0_ECC_CFG bits */
> +#define ECC_CFG_ECC_DISABLE 0
> +#define ECC_SW_RESET 1
> +#define ECC_MODE 4
> +#define ECC_PARITY_SIZE_BYTES_BCH 8
> +#define ECC_NUM_DATA_BYTES 16
> +#define ECC_FORCE_CLK_OPEN 30
> +
> +/* NAND_DEV_CMD1 bits */
> +#define READ_ADDR 0
> +
> +/* NAND_DEV_CMD_VLD bits */
> +#define READ_START_VLD 0
> +
> +/* NAND_EBI2_ECC_BUF_CFG bits */
> +#define NUM_STEPS 0
> +
> +/* NAND_ERASED_CW_DETECT_CFG bits */
> +#define ERASED_CW_ECC_MASK 1
> +#define AUTO_DETECT_RES 0
> +#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
> +#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
> +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
> +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
> +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
> +
> +/* NAND_ERASED_CW_DETECT_STATUS bits */
> +#define PAGE_ALL_ERASED BIT(7)
> +#define CODEWORD_ALL_ERASED BIT(6)
> +#define PAGE_ERASED BIT(5)
> +#define CODEWORD_ERASED BIT(4)
> +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
> +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
> +
> +/* Version Mask */
> +#define NAND_VERSION_MAJOR_MASK 0xf0000000
> +#define NAND_VERSION_MAJOR_SHIFT 28
> +#define NAND_VERSION_MINOR_MASK 0x0fff0000
> +#define NAND_VERSION_MINOR_SHIFT 16
> +
> +/* NAND OP_CMDs */
> +#define PAGE_READ 0x2
> +#define PAGE_READ_WITH_ECC 0x3
> +#define PAGE_READ_WITH_ECC_SPARE 0x4
> +#define PROGRAM_PAGE 0x6
> +#define PAGE_PROGRAM_WITH_ECC 0x7
> +#define PROGRAM_PAGE_SPARE 0x9
> +#define BLOCK_ERASE 0xa
> +#define FETCH_ID 0xb
> +#define RESET_DEVICE 0xd
> +
> +/*
> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> + * the driver calls the chunks 'step' or 'codeword' interchangeably
> + */
> +#define NANDC_STEP_SIZE 512
> +
> +/*
> + * the largest page size we support is 8K, this will have 16 steps/codewords
> + * of 512 bytes each
> + */
> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
> +
> +/* we read at most 3 registers per codeword scan */
> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
> +
> +/* ECC modes */
> +#define ECC_NONE BIT(0)
> +#define ECC_RS_4BIT BIT(1)
> +#define ECC_BCH_4BIT BIT(2)
> +#define ECC_BCH_8BIT BIT(3)
> +
> +struct desc_info {
> + struct list_head list;
> +
> + enum dma_data_direction dir;
> + struct scatterlist sgl;
> + struct dma_async_tx_descriptor *dma_desc;
> +};
> +
> +/*
> + * holds the current register values that we want to write. acts as a contiguous
> + * chunk of memory which we use to write the controller registers through DMA.
> + */
> +struct nandc_regs {
> + __le32 cmd;
> + __le32 addr0;
> + __le32 addr1;
> + __le32 chip_sel;
> + __le32 exec;
> +
> + __le32 cfg0;
> + __le32 cfg1;
> + __le32 ecc_bch_cfg;
> +
> + __le32 clrflashstatus;
> + __le32 clrreadstatus;
> +
> + __le32 cmd1;
> + __le32 vld;
> +
> + __le32 orig_cmd1;
> + __le32 orig_vld;
> +
> + __le32 ecc_buf_cfg;
> +};
> +
> +/*
> + * @cmd_crci: ADM DMA CRCI for command flow control
> + * @data_crci: ADM DMA CRCI for data flow control
> + * @list: DMA descriptor list (list of desc_infos)
> + * @data_buffer: our local DMA buffer for page read/writes,
> + * used when we can't use the buffer provided
> + * by upper layers directly
> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
> + * @reg_read_buf: buffer for reading register data via DMA
> + * @reg_read_pos: marker for data read in reg_read_buf
> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
> + * ecc/non-ecc mode for the current nand flash
> + * device
> + * @regs: a contiguous chunk of memory for DMA register
> + * writes
> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
> + * @ecc_modes: supported ECC modes by the current controller,
> + * initialized via DT match data
> + * @cw_size: the number of bytes in a single step/codeword
> + * of a page, consisting of all data, ecc, spare
> + * and reserved bytes
> + * @cw_data: the number of bytes within a codeword protected
> + * by ECC
> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
> + * @status: value to be returned if NAND_CMD_STATUS command
> + * is executed
> + */
> +struct qcom_nandc_data {
> + struct platform_device *pdev;
This field is only set once, but unused?
And it (and several others) aren't documented above.
> + struct device *dev;
> +
> + void __iomem *base;
> + struct resource *res;
> +
> + struct clk *core_clk;
> + struct clk *aon_clk;
> +
> + /* DMA stuff */
> + struct dma_chan *chan;
> + struct dma_slave_config slave_conf;
> + unsigned int cmd_crci;
> + unsigned int data_crci;
> + struct list_head list;
> +
> + /* MTD stuff */
> + struct nand_chip chip;
> + struct mtd_info mtd;
> +
> + /* local data buffer and markers */
> + u8 *data_buffer;
> + int buf_size;
> + int buf_count;
> + int buf_start;
> +
> + /* local buffer to read back registers */
> + __le32 *reg_read_buf;
> + int reg_read_pos;
> +
> + /* required configs */
> + u32 cfg0, cfg1;
> + u32 cfg0_raw, cfg1_raw;
> + u32 ecc_buf_cfg;
> + u32 ecc_bch_cfg;
> + u32 clrflashstatus;
> + u32 clrreadstatus;
> + u32 sflashc_burst_cfg;
> + u32 cmd1, vld;
> +
> + /* register state */
> + struct nandc_regs *regs;
> +
> + /* things we get from DT */
> + int ecc_strength;
> + int bus_width;
> +
> + u32 ecc_modes;
> +
> + /* misc params */
> + int cw_size;
> + int cw_data;
> + bool use_ecc;
> + bool bch_enabled;
> + u8 status;
> + int last_command;
> +};
> +
> +static inline u32 nandc_read(struct qcom_nandc_data *this, int offset)
> +{
> + return ioread32(this->base + offset);
> +}
> +
> +static inline void nandc_write(struct qcom_nandc_data *this, int offset,
> + u32 val)
> +{
> + iowrite32(val, this->base + offset);
> +}
> +
> +static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
> +{
> + switch (offset) {
> + case NAND_FLASH_CMD:
> + return ®s->cmd;
> + case NAND_ADDR0:
> + return ®s->addr0;
> + case NAND_ADDR1:
> + return ®s->addr1;
> + case NAND_FLASH_CHIP_SELECT:
> + return ®s->chip_sel;
> + case NAND_EXEC_CMD:
> + return ®s->exec;
> + case NAND_FLASH_STATUS:
> + return ®s->clrflashstatus;
> + case NAND_DEV0_CFG0:
> + return ®s->cfg0;
> + case NAND_DEV0_CFG1:
> + return ®s->cfg1;
> + case NAND_DEV0_ECC_CFG:
> + return ®s->ecc_bch_cfg;
> + case NAND_READ_STATUS:
> + return ®s->clrreadstatus;
> + case NAND_DEV_CMD1:
> + return ®s->cmd1;
> + case NAND_DEV_CMD1_RESTORE:
> + return ®s->orig_cmd1;
> + case NAND_DEV_CMD_VLD:
> + return ®s->vld;
> + case NAND_DEV_CMD_VLD_RESTORE:
> + return ®s->orig_vld;
> + case NAND_EBI2_ECC_BUF_CFG:
> + return ®s->ecc_buf_cfg;
> + default:
> + return NULL;
> + }
> +}
> +
> +static void set_nandc_reg(struct qcom_nandc_data *this, int offset, u32 val)
> +{
> + struct nandc_regs *regs = this->regs;
> + __le32 *reg;
> +
> + reg = offset_to_nandc_reg(regs, offset);
> +
> + if (reg)
> + *reg = cpu_to_le32(val);
> +}
> +
> +/* helper to configure address register values */
> +static void set_address(struct qcom_nandc_data *this, u16 column, int page)
> +{
> + struct nand_chip *chip = &this->chip;
> +
> + if (chip->options & NAND_BUSWIDTH_16)
> + column >>= 1;
> +
> + set_nandc_reg(this, NAND_ADDR0, page << 16 | column);
> + set_nandc_reg(this, NAND_ADDR1, page >> 16 & 0xff);
> +}
> +
> +/*
> + * update_rw_regs: set up read/write register values, these will be
> + * written to the NAND controller registers via DMA
> + *
> + * @num_cw: number of steps for the read/write operation
> + * @read: read or write operation
> + */
> +static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
> +{
> + u32 cmd, cfg0, cfg1, ecc_bch_cfg;
> +
> + if (read) {
> + if (this->use_ecc)
> + cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
> + else
> + cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
> + } else {
> + cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
> + }
> +
> + if (this->use_ecc) {
> + cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
> + (num_cw - 1) << CW_PER_PAGE;
> +
> + cfg1 = this->cfg1;
> + ecc_bch_cfg = this->ecc_bch_cfg;
> + } else {
> + cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
> + (num_cw - 1) << CW_PER_PAGE;
> +
> + cfg1 = this->cfg1_raw;
> + ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
> + }
> +
> + set_nandc_reg(this, NAND_FLASH_CMD, cmd);
> + set_nandc_reg(this, NAND_DEV0_CFG0, cfg0);
> + set_nandc_reg(this, NAND_DEV0_CFG1, cfg1);
> + set_nandc_reg(this, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
> + set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, this->ecc_buf_cfg);
> + set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
> + set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
> +}
> +
> +static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
> + const void *vaddr, int size, bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + struct dma_slave_config slave_conf;
> + enum dma_transfer_direction dir_eng;
> + int r;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + sgl = &desc->sgl;
> +
> + sg_init_one(sgl, vaddr, size);
> +
> + if (read) {
> + dir_eng = DMA_DEV_TO_MEM;
> + desc->dir = DMA_FROM_DEVICE;
> + } else {
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + }
> +
> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
> + if (r == 0) {
> + r = -ENOMEM;
> + goto err;
> + }
> +
> + memset(&slave_conf, 0x00, sizeof(slave_conf));
> +
> + slave_conf.device_fc = flow_control;
> + if (read) {
> + slave_conf.src_maxburst = 16;
> + slave_conf.src_addr = this->res->start + reg_off;
> + slave_conf.slave_id = this->data_crci;
> + } else {
> + slave_conf.dst_maxburst = 16;
> + slave_conf.dst_addr = this->res->start + reg_off;
> + slave_conf.slave_id = this->cmd_crci;
> + }
> +
> + r = dmaengine_slave_config(this->chan, &slave_conf);
> + if (r) {
> + dev_err(this->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, dir_eng, 0);
> + if (!dma_desc) {
> + dev_err(this->dev, "failed to prepare desc\n");
> + r = -EINVAL;
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + list_add_tail(&desc->list, &this->list);
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return r;
> +}
> +
> +/*
> + * read_reg_dma: prepares a descriptor to read a given number of
> + * contiguous registers to the reg_read_buf pointer
> + *
> + * @first: offset of the first register in the contiguous block
> + * @num_regs: number of registers to read
> + */
> +static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
> +{
> + bool flow_control = false;
> + void *vaddr;
> + int size;
> +
> + if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
> + flow_control = true;
> +
> + size = num_regs * sizeof(u32);
> + vaddr = this->reg_read_buf + this->reg_read_pos;
> + this->reg_read_pos += num_regs;
> +
> + return prep_dma_desc(this, true, first, vaddr, size, flow_control);
> +}
> +
> +/*
> + * write_reg_dma: prepares a descriptor to write a given number of
> + * contiguous registers
> + *
> + * @first: offset of the first register in the contiguous block
> + * @num_regs: number of registers to write
> + */
> +static int write_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
> +{
> + bool flow_control = false;
> + struct nandc_regs *regs = this->regs;
> + void *vaddr;
> + int size;
> +
> + vaddr = offset_to_nandc_reg(regs, first);
> +
> + if (first == NAND_FLASH_CMD)
> + flow_control = true;
> +
> + if (first == NAND_DEV_CMD1_RESTORE)
> + first = NAND_DEV_CMD1;
> +
> + if (first == NAND_DEV_CMD_VLD_RESTORE)
> + first = NAND_DEV_CMD_VLD;
> +
> + size = num_regs * sizeof(u32);
> +
> + return prep_dma_desc(this, false, first, vaddr, size, flow_control);
> +}
> +
> +/*
> + * read_data_dma: prepares a DMA descriptor to transfer data from the
> + * controller's internal buffer to the buffer 'vaddr'
> + *
> + * @reg_off: offset within the controller's data buffer
> + * @vaddr: virtual address of the buffer we want to write to
> + * @size: DMA transaction size in bytes
> + */
> +static int read_data_dma(struct qcom_nandc_data *this, int reg_off,
> + const u8 *vaddr, int size)
> +{
> + return prep_dma_desc(this, true, reg_off, vaddr, size, false);
> +}
> +
> +/*
> + * write_data_dma: prepares a DMA descriptor to transfer data from
> + * 'vaddr' to the controller's internal buffer
> + *
> + * @reg_off: offset within the controller's data buffer
> + * @vaddr: virtual address of the buffer we want to read from
> + * @size: DMA transaction size in bytes
> + */
> +static int write_data_dma(struct qcom_nandc_data *this, int reg_off,
> + const u8 *vaddr, int size)
> +{
> + return prep_dma_desc(this, false, reg_off, vaddr, size, false);
> +}
> +
> +/*
> + * helper to prepare dma descriptors to configure registers needed for reading a
> + * codeword/step in a page
> + */
> +static void config_cw_read(struct qcom_nandc_data *this)
> +{
> + write_reg_dma(this, NAND_FLASH_CMD, 3);
> + write_reg_dma(this, NAND_DEV0_CFG0, 3);
> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
> +
> + write_reg_dma(this, NAND_EXEC_CMD, 1);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 2);
> + read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1);
> +}
> +
> +/*
> + * helpers to prepare dma descriptors used to configure registers needed for
> + * writing a codeword/step in a page
> + */
> +static void config_cw_write_pre(struct qcom_nandc_data *this)
> +{
> + write_reg_dma(this, NAND_FLASH_CMD, 3);
> + write_reg_dma(this, NAND_DEV0_CFG0, 3);
> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
> +}
> +
> +static void config_cw_write_post(struct qcom_nandc_data *this)
> +{
> + write_reg_dma(this, NAND_EXEC_CMD, 1);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 1);
> +
> + write_reg_dma(this, NAND_FLASH_STATUS, 1);
> + write_reg_dma(this, NAND_READ_STATUS, 1);
> +}
> +
> +/*
> + * the following functions are used within chip->cmdfunc() to perform different
> + * NAND_CMD_* commands
> + */
> +
> +/* sets up descriptors for NAND_CMD_PARAM */
> +static int nandc_param(struct qcom_nandc_data *this)
> +{
> + /*
> + * NAND_CMD_PARAM is called before we know much about the FLASH chip
> + * in use. we configure the controller to perform a raw read of 512
> + * bytes to read onfi params
> + */
> + set_nandc_reg(this, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
> + set_nandc_reg(this, NAND_ADDR0, 0);
> + set_nandc_reg(this, NAND_ADDR1, 0);
> + set_nandc_reg(this, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
> + | 512 << UD_SIZE_BYTES
> + | 5 << NUM_ADDR_CYCLES
> + | 0 << SPARE_SIZE_BYTES);
> + set_nandc_reg(this, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | 17 << BAD_BLOCK_BYTE_NUM
> + | 1 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | 0 << WIDE_FLASH
> + | 1 << DEV0_CFG1_ECC_DISABLE);
> + set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
> +
> +
> + /* configure CMD1 and VLD for ONFI param probing */
> + set_nandc_reg(this, NAND_DEV_CMD_VLD,
> + (this->vld & ~(1 << READ_START_VLD))
> + | 0 << READ_START_VLD);
> + set_nandc_reg(this, NAND_DEV_CMD1,
> + (this->cmd1 & ~(0xFF << READ_ADDR))
> + | NAND_CMD_PARAM << READ_ADDR);
> +
> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
> +
> + set_nandc_reg(this, NAND_DEV_CMD1_RESTORE, this->cmd1);
> + set_nandc_reg(this, NAND_DEV_CMD_VLD_RESTORE, this->vld);
> +
> + write_reg_dma(this, NAND_DEV_CMD_VLD, 1);
> + write_reg_dma(this, NAND_DEV_CMD1, 1);
> +
> + this->buf_count = 512;
> + memset(this->data_buffer, 0xff, this->buf_count);
> +
> + config_cw_read(this);
> +
> + read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->buf_count);
> +
> + /* restore CMD1 and VLD regs */
> + write_reg_dma(this, NAND_DEV_CMD1_RESTORE, 1);
> + write_reg_dma(this, NAND_DEV_CMD_VLD_RESTORE, 1);
> +
> + return 0;
> +}
> +
> +/* sets up descriptors for NAND_CMD_ERASE1 */
> +static int erase_block(struct qcom_nandc_data *this, int page_addr)
> +{
> + set_nandc_reg(this, NAND_FLASH_CMD, BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
> + set_nandc_reg(this, NAND_ADDR0, page_addr);
> + set_nandc_reg(this, NAND_ADDR1, 0);
> + set_nandc_reg(this, NAND_DEV0_CFG0,
> + this->cfg0_raw & ~(7 << CW_PER_PAGE));
> + set_nandc_reg(this, NAND_DEV0_CFG1, this->cfg1_raw);
> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
> + set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
> + set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
> +
> + write_reg_dma(this, NAND_FLASH_CMD, 3);
> + write_reg_dma(this, NAND_DEV0_CFG0, 2);
> + write_reg_dma(this, NAND_EXEC_CMD, 1);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 1);
> +
> + write_reg_dma(this, NAND_FLASH_STATUS, 1);
> + write_reg_dma(this, NAND_READ_STATUS, 1);
> +
> + return 0;
> +}
> +
> +/* sets up descriptors for NAND_CMD_READID */
> +static int read_id(struct qcom_nandc_data *this, int column)
> +{
> + if (column == -1)
> + return 0;
> +
> + set_nandc_reg(this, NAND_FLASH_CMD, FETCH_ID);
> + set_nandc_reg(this, NAND_ADDR0, column);
> + set_nandc_reg(this, NAND_ADDR1, 0);
> + set_nandc_reg(this, NAND_FLASH_CHIP_SELECT, DM_EN);
> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
> +
> + write_reg_dma(this, NAND_FLASH_CMD, 4);
> + write_reg_dma(this, NAND_EXEC_CMD, 1);
> +
> + read_reg_dma(this, NAND_READ_ID, 1);
> +
> + return 0;
> +}
> +
> +/* sets up descriptors for NAND_CMD_RESET */
> +static int reset(struct qcom_nandc_data *this)
> +{
> + set_nandc_reg(this, NAND_FLASH_CMD, RESET_DEVICE);
> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
> +
> + write_reg_dma(this, NAND_FLASH_CMD, 1);
> + write_reg_dma(this, NAND_EXEC_CMD, 1);
> +
> + read_reg_dma(this, NAND_FLASH_STATUS, 1);
> +
> + return 0;
> +}
> +
> +/* helpers to submit/free our list of dma descriptors */
> +static int submit_descs(struct qcom_nandc_data *this)
> +{
> + struct desc_info *desc;
> + dma_cookie_t cookie = 0;
> +
> + list_for_each_entry(desc, &this->list, list)
> + cookie = dmaengine_submit(desc->dma_desc);
> +
> + if (dma_sync_wait(this->chan, cookie) != DMA_COMPLETE)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static void free_descs(struct qcom_nandc_data *this)
> +{
> + struct desc_info *desc, *n;
> +
> + list_for_each_entry_safe(desc, n, &this->list, list) {
> + list_del(&desc->list);
> + dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir);
> + kfree(desc);
> + }
> +}
> +
> +/* reset the register read buffer for next NAND operation */
> +static void clear_read_regs(struct qcom_nandc_data *this)
> +{
> + this->reg_read_pos = 0;
> + memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(*this->reg_read_buf));
> +}
> +
> +static void pre_command(struct qcom_nandc_data *this, int command)
> +{
> + this->buf_count = 0;
> + this->buf_start = 0;
> + this->use_ecc = false;
> + this->last_command = command;
> +
> + clear_read_regs(this);
> +}
> +
> +/*
> + * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
> + * privately maintained status byte, this status byte can be read after
> + * NAND_CMD_STATUS is called
> + */
> +static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int num_cw;
> + int i;
> +
> + num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
> +
> + for (i = 0; i < num_cw; i++) {
> + u32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
> +
> + if (flash_status & FS_MPU_ERR)
> + this->status &= ~NAND_STATUS_WP;
> +
> + if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
> + (flash_status & FS_DEVICE_STS_ERR)))
> + this->status |= NAND_STATUS_FAIL;
> + }
> +}
> +
> +static void post_command(struct qcom_nandc_data *this, int command)
> +{
> + switch (command) {
> + case NAND_CMD_READID:
> + memcpy(this->data_buffer, this->reg_read_buf, this->buf_count);
> + break;
> + case NAND_CMD_PAGEPROG:
> + case NAND_CMD_ERASE1:
> + parse_erase_write_errors(this, command);
> + break;
> + default:
> + break;
> + }
> +}
> +
> +/*
> + * Implements chip->cmdfunc. It's only used for a limited set of commands.
> + * The rest of the commands wouldn't be called by upper layers. For example,
> + * NAND_CMD_READOOB would never be called because we have our own versions
> + * of read_oob ops for nand_ecc_ctrl.
> + */
> +static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
> + int column, int page_addr)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + struct qcom_nandc_data *this = chip->priv;
> + bool wait = false;
> + int r = 0;
> +
> + pre_command(this, command);
> +
> + switch (command) {
> + case NAND_CMD_RESET:
> + r = reset(this);
> + wait = true;
> + break;
> +
> + case NAND_CMD_READID:
> + this->buf_count = 4;
> + r = read_id(this, column);
> + wait = true;
> + break;
> +
> + case NAND_CMD_PARAM:
> + r = nandc_param(this);
> + wait = true;
> + break;
> +
> + case NAND_CMD_ERASE1:
> + r = erase_block(this, page_addr);
> + wait = true;
> + break;
> +
> + case NAND_CMD_READ0:
> + /* we read the entire page for now */
> + WARN_ON(column != 0);
> +
> + this->use_ecc = true;
> + set_address(this, 0, page_addr);
> + update_rw_regs(this, ecc->steps, true);
> + break;
> +
> + case NAND_CMD_SEQIN:
> + WARN_ON(column != 0);
> + set_address(this, 0, page_addr);
> + break;
> +
> + case NAND_CMD_PAGEPROG:
> + case NAND_CMD_STATUS:
> + case NAND_CMD_NONE:
> + default:
> + break;
> + }
> +
> + if (r) {
> + dev_err(this->dev, "failure executing command %d\n",
> + command);
> + free_descs(this);
> + return;
> + }
> +
> + if (wait) {
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev,
> + "failure submitting descs for command %d\n",
> + command);
> + }
> +
> + free_descs(this);
> +
> + post_command(this, command);
> +}
> +
> +/*
> + * when using RS ECC, the NAND controller flags an error when reading an
> + * erased page. however, there are special characters at certain offsets when
> + * we read the erased page. we check here if the page is really empty. if so,
> + * we replace the magic characters with 0xffs
> + */
What's the nature of this erased page flagging? Does it only detect
all-0xff pages? What about if the erased page experiences any bitflips?
A lot of drivers have been attempting to handle that case too (which is
becoming more common on modern MLC, and even on SLC), and most of the
times they do it poorly.
See nand_check_erased_ecc_chunk() (in linux-next.git) as an example of a
brute force helper to assist for cases where HW ECC is not sufficient.
> +static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS];
> + int i, j;
> +
> + /* if BCH is enabled, HW will take care of detecting erased pages */
> + if (this->bch_enabled || !this->use_ecc)
> + return false;
> +
> + for (i = 0; i < cwperpage; i++) {
> + u8 *empty1, *empty2;
> + u32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
> +
> + /*
> + * an erased page flags an error in NAND_FLASH_STATUS, check if
> + * the page is erased by looking for 0x54s at offsets 3 and 175
> + * from the beginning of each codeword
> + */
> + if (!(flash_status & FS_OP_ERR))
> + break;
> +
> + empty1 = &data_buf[3 + i * this->cw_data];
> + empty2 = &data_buf[175 + i * this->cw_data];
> +
> + /*
> + * if the error wasn't because of an erased page, bail out and
> + * and let someone else do the error checking
> + */
> + if ((*empty1 == 0x54 && *empty2 == 0xff) ||
> + (*empty1 == 0xff && *empty2 == 0x54)) {
> + orig1[i] = *empty1;
> + orig2[i] = *empty2;
> +
> + *empty1 = 0xff;
> + *empty2 = 0xff;
> + } else {
> + break;
> + }
> + }
> +
> + if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize))
> + goto not_empty;
> +
> + /*
> + * tell the caller that the page was empty and is fixed up, so that
> + * parse_read_errors() doesn't think it's an error
> + */
> + return true;
> +
> +not_empty:
> + /* restore original values if not empty*/
> + for (j = 0; j < i; j++) {
> + data_buf[3 + j * this->cw_data] = orig1[j];
> + data_buf[175 + j * this->cw_data] = orig2[j];
> + }
> +
> + return false;
> +}
> +
> +struct read_stats {
> + __le32 flash;
> + __le32 buffer;
> + __le32 erased_cw;
> +};
> +
> +/*
> + * reads back status registers set by the controller to notify page read
> + * errors. this is equivalent to what 'ecc->correct()' would do.
> + */
> +static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + unsigned int max_bitflips = 0;
> + int i;
> + struct read_stats *buf;
> +
> + buf = (struct read_stats *)this->reg_read_buf;
> + for (i = 0; i < cwperpage; i++, buf++) {
> + unsigned int stat;
> + u32 flash, buffer, erased_cw;
> +
> + flash = le32_to_cpu(buf->flash);
> + buffer = le32_to_cpu(buf->buffer);
> + erased_cw = le32_to_cpu(buf->erased_cw);
> +
> + if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
> +
> + /* ignore erased codeword errors */
> + if (this->bch_enabled) {
> + if ((erased_cw & ERASED_CW) == ERASED_CW)
> + continue;
> + } else if (erased_page) {
> + continue;
> + }
> +
> + if (buffer & BS_UNCORRECTABLE_BIT) {
> + mtd->ecc_stats.failed++;
> + continue;
> + }
> + }
> +
> + stat = buffer & BS_CORRECTABLE_ERR_MSK;
> + mtd->ecc_stats.corrected += stat;
> +
> + max_bitflips = max(max_bitflips, stat);
> + }
> +
> + return max_bitflips;
> +}
> +
> +/*
> + * helper to perform the actual page read operation, used by ecc->read_page()
> + * and ecc->read_oob()
> + */
> +static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf,
> + u8 *oob_buf)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int i, r;
> +
> + /* queue cmd descs for each codeword */
> + for (i = 0; i < ecc->steps; i++) {
> + int data_size, oob_size;
> +
> + if (i == (ecc->steps - 1)) {
> + data_size = ecc->size - ((ecc->steps - 1) << 2);
> + oob_size = (ecc->steps << 2) + ecc->bytes;
> + } else {
> + data_size = this->cw_data;
> + oob_size = ecc->bytes;
> + }
> +
> + config_cw_read(this);
> +
> + if (data_buf)
> + read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
> +
> + if (oob_buf)
> + read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf,
> + oob_size);
> +
> + if (data_buf)
> + data_buf += data_size;
> + if (oob_buf)
> + oob_buf += oob_size;
> + }
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failure to read page/oob\n");
> +
> + free_descs(this);
> +
> + return r;
> +}
> +
> +/*
> + * a helper that copies the last step/codeword of a page (containing free oob)
> + * into our local buffer
> + */
> +static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page)
> +{
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int size;
> + int r;
> +
> + clear_read_regs(this);
> +
> + size = use_ecc ? this->cw_data : this->cw_size;
> +
> + /* prepare a clean read buffer */
> + memset(this->data_buffer, 0xff, size);
> +
> + this->use_ecc = use_ecc;
> + set_address(this, this->cw_size * (ecc->steps - 1), page);
> + update_rw_regs(this, 1, true);
> +
> + config_cw_read(this);
> +
> + read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size);
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failed to copy last codeword\n");
> +
> + free_descs(this);
> +
> + return r;
> +}
> +
> +/* implements ecc->read_page() */
> +static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
> + uint8_t *buf, int oob_required, int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + u8 *data_buf, *oob_buf = NULL;
> + bool erased_page;
> + int r;
> +
> + data_buf = buf;
> + oob_buf = oob_required ? chip->oob_poi : NULL;
> +
> + r = read_page_low(this, data_buf, oob_buf);
> + if (r) {
> + dev_err(this->dev, "failure to read page\n");
> + return r;
> + }
> +
> + erased_page = empty_page_fixup(this, data_buf);
> +
> + return parse_read_errors(this, erased_page);
> +}
> +
> +/* implements ecc->read_oob() */
> +static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int r;
> +
> + clear_read_regs(this);
> +
> + this->use_ecc = true;
> + set_address(this, 0, page);
> + update_rw_regs(this, ecc->steps, true);
> +
> + r = read_page_low(this, NULL, chip->oob_poi);
> + if (r)
> + dev_err(this->dev, "failure to read oob\n");
> +
> + return r;
> +}
> +
> +/* implements ecc->read_oob_raw(), used to read the bad block marker flag */
> +static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + uint8_t *oob = chip->oob_poi;
> + int start, length;
> + int r;
> +
> + /*
> + * configure registers for a raw page read, the address is set to the
> + * beginning of the last codeword, we don't care about reading ecc
> + * portion of oob, just the free stuff
> + */
> + r = copy_last_cw(this, false, page);
> + if (r)
> + return r;
> +
> + /*
> + * reading raw oob has 2 parts, first the bad block byte, then the
> + * actual free oob region. perform a memcpy in two steps
> + */
> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
> +
> + memcpy(oob, this->data_buffer + start, length);
> +
> + oob += length;
> +
> + start = this->cw_data - (ecc->steps << 2) + 1;
> + length = ecc->steps << 2;
> +
> + memcpy(oob, this->data_buffer + start, length);
> +
> + return 0;
> +}
> +
> +/* implements ecc->write_page() */
> +static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> + const uint8_t *buf, int oob_required)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + u8 *data_buf, *oob_buf;
> + int i, r = 0;
> +
> + clear_read_regs(this);
> +
> + data_buf = (u8 *) buf;
> + oob_buf = chip->oob_poi;
> +
> + this->use_ecc = true;
> + update_rw_regs(this, ecc->steps, false);
> +
> + for (i = 0; i < ecc->steps; i++) {
> + int data_size, oob_size;
> +
> + if (i == (ecc->steps - 1)) {
> + data_size = ecc->size - ((ecc->steps - 1) << 2);
> + oob_size = (ecc->steps << 2) + ecc->bytes;
> + } else {
> + data_size = this->cw_data;
> + oob_size = ecc->bytes;
> + }
> +
> + config_cw_write_pre(this);
> + write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
> +
> + /*
> + * we don't really need to write anything to oob for the
> + * first n - 1 codewords since these oob regions just
> + * contain ecc that's written by the controller itself
> + */
> + if (i == (ecc->steps - 1))
> + write_data_dma(this, FLASH_BUF_ACC + data_size,
> + oob_buf, oob_size);
> + config_cw_write_post(this);
> +
> + data_buf += data_size;
> + oob_buf += oob_size;
> + }
> +
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev, "failure to write page\n");
> +
> + free_descs(this);
> +
> + return r;
> +}
> +
> +/*
> + * implements ecc->write_oob()
> + *
> + * the NAND controller cannot write only data or only oob within a codeword,
> + * since ecc is calculated for the combined codeword. we first copy the
> + * entire contents for the last codeword(data + oob), replace the old oob
> + * with the new one in chip->oob_poi, and then write the entire codeword.
> + * this read-copy-write operation results in a slight perormance loss.
> + */
> +static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> + int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + uint8_t *oob = chip->oob_poi;
> + int free_boff;
> + int data_size, oob_size;
> + int r, status = 0;
> +
> + r = copy_last_cw(this, true, page);
> + if (r)
> + return r;
> +
> + clear_read_regs(this);
> +
> + /* calculate the data and oob size for the last codeword/step */
> + data_size = ecc->size - ((ecc->steps - 1) << 2);
> + oob_size = (ecc->steps << 2) + ecc->bytes;
> +
> + /*
> + * the location of spare data in the oob buffer, we could also use
> + * ecc->layout.oobfree here
> + */
> + free_boff = ecc->bytes * (ecc->steps - 1);
> +
> + /* override new oob content to last codeword */
> + memcpy(this->data_buffer + data_size, oob + free_boff, oob_size);
> +
> + this->use_ecc = true;
> + set_address(this, this->cw_size * (ecc->steps - 1), page);
> + update_rw_regs(this, 1, false);
> +
> + config_cw_write_pre(this);
> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer,
> + data_size + oob_size);
> + config_cw_write_post(this);
> +
> + r = submit_descs(this);
> +
> + free_descs(this);
> +
> + if (r) {
> + dev_err(this->dev, "failure to write oob\n");
> + return -EIO;
> + }
> +
> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +
> + status = chip->waitfunc(mtd, chip);
> +
> + return status & NAND_STATUS_FAIL ? -EIO : 0;
> +}
> +
> +/* implements ecc->write_oob_raw(), used to write bad block marker flag */
> +static int qcom_nandc_write_oob_raw(struct mtd_info *mtd,
> + struct nand_chip *chip, int page)
> +{
> + struct qcom_nandc_data *this = chip->priv;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + uint8_t *oob = chip->oob_poi;
> + int start, length;
> + int r, status = 0;
> +
> + r = copy_last_cw(this, false, page);
> + if (r)
> + return r;
> +
> + clear_read_regs(this);
> +
> + /*
> + * writing raw oob has 2 parts, first the bad block region, then the
> + * actual free region
> + */
> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
> +
> + memcpy(this->data_buffer + start, oob, length);
> +
> + oob += length;
> +
> + start = this->cw_data - (ecc->steps << 2) + 1;
> + length = ecc->steps << 2;
> +
> + memcpy(this->data_buffer + start, oob, length);
> +
> + /* prepare write */
> + this->use_ecc = false;
> + set_address(this, this->cw_size * (ecc->steps - 1), page);
> + update_rw_regs(this, 1, false);
> +
> + config_cw_write_pre(this);
> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size);
> + config_cw_write_post(this);
> +
> + r = submit_descs(this);
> +
> + free_descs(this);
> +
> + if (r) {
> + dev_err(this->dev, "failure to write updated oob\n");
> + return -EIO;
> + }
> +
> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +
> + status = chip->waitfunc(mtd, chip);
> +
> + return status & NAND_STATUS_FAIL ? -EIO : 0;
> +}
> +
> +/*
> + * the three functions below implement chip->read_byte(), chip->read_buf()
> + * and chip->write_buf() respectively. these aren't used for
> + * reading/writing page data, they are used for smaller data like reading
> + * id, status etc
> + */
> +static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> + uint8_t *buf = this->data_buffer;
> + uint8_t ret = 0x0;
> +
> + if (this->last_command == NAND_CMD_STATUS) {
> + ret = this->status;
> +
> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> +
> + return ret;
> + }
> +
> + if (this->buf_start < this->buf_count)
> + ret = buf[this->buf_start++];
> +
> + return ret;
> +}
> +
> +static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
> +
> + memcpy(buf, this->data_buffer + this->buf_start, real_len);
> + this->buf_start += real_len;
> +}
> +
> +static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
> + int len)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
> +
> + memcpy(this->data_buffer + this->buf_start, buf, real_len);
> +
> + this->buf_start += real_len;
> +}
> +
> +/* we support only one external chip for now */
> +static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct qcom_nandc_data *this = chip->priv;
> +
> + if (chipnr <= 0)
> + return;
> +
> + dev_warn(this->dev, "invalid chip select\n");
> +}
> +
> +/*
> + * NAND controller page layout info
> + *
> + * |-----------------------| |---------------------------------|
> + * | xx.......xx| | *********xx.......xx|
> + * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
> + * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
> + * | xx.......xx| | *********xx.......xx|
> + * |-----------------------| |---------------------------------|
> + * codeword 1,2..n-1 codeword n
> + * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
> + *
> + * n = number of codewords in the page
> + * . = ECC bytes
> + * * = spare bytes
> + * x = unused/reserved bytes
> + *
> + * 2K page: n = 4, spare = 16 bytes
> + * 4K page: n = 8, spare = 32 bytes
> + * 8K page: n = 16, spare = 64 bytes
> + *
> + * the qcom nand controller operates at a sub page/codeword level. each
> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
> + * the number of ECC bytes vary based on the ECC strength and the bus width.
> + *
> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
> + *
> + * the layout described above is used by the controller when the ECC block is
> + * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
> + * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
> + * layouts defined below doesn't consider the positions occupied by the reserved
> + * bytes
> + *
> + * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
> + * in the last codeword is the position of bad block marker. the bad block
> + * marker cannot be accessed when ECC is enabled.
> + *
> + */
> +
> +/*
> + * Layouts for different page sizes and ecc modes. We skip the eccpos field
> + * since it isn't needed for this driver
> + */
> +
> +/* 2K page, 4 bit ECC */
> +static struct nand_ecclayout layout_oob_64 = {
> + .eccbytes = 40,
> + .oobfree = {
> + { 30, 16 },
> + },
> +};
> +
> +/* 4K page, 4 bit ECC, 8/16 bit bus width */
> +static struct nand_ecclayout layout_oob_128 = {
> + .eccbytes = 80,
> + .oobfree = {
> + { 70, 32 },
> + },
> +};
> +
> +/* 4K page, 8 bit ECC, 8 bit bus width */
> +static struct nand_ecclayout layout_oob_224_x8 = {
> + .eccbytes = 104,
> + .oobfree = {
> + { 91, 32 },
> + },
> +};
> +
> +/* 4K page, 8 bit ECC, 16 bit bus width */
> +static struct nand_ecclayout layout_oob_224_x16 = {
> + .eccbytes = 112,
> + .oobfree = {
> + { 98, 32 },
> + },
> +};
> +
> +/* 8K page, 4 bit ECC, 8/16 bit bus width */
> +static struct nand_ecclayout layout_oob_256 = {
> + .eccbytes = 160,
> + .oobfree = {
> + { 151, 64 },
> + },
> +};
> +
> +/*
> + * this is called before scan_ident, we do some minimal configurations so
> + * that reading ID and ONFI params work
> + */
> +static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
> +{
> + /* kill onenand */
> + nandc_write(this, SFLASHC_BURST_CFG, 0);
> +
> + /* enable ADM DMA */
> + nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
> +
> + /* save the original values of these registers */
> + this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
> + this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
> +
> + /* initial status value */
> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> +}
> +
> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage;
> + bool wide_bus;
> +
> + /* the nand controller fetches codewords/chunks of 512 bytes */
> + cwperpage = mtd->writesize >> 9;
> +
> + ecc->strength = this->ecc_strength;
> +
> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> +
> + if (ecc->strength >= 8) {
> + /* 8 bit ECC defaults to BCH ECC on all platforms */
> + ecc->bytes = wide_bus ? 14 : 13;
> + } else {
> + /*
> + * if the controller supports BCH for 4 bit ECC, the controller
> + * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> + * always 10 bytes
> + */
> + if (this->ecc_modes & ECC_BCH_4BIT)
> + ecc->bytes = wide_bus ? 8 : 7;
> + else
> + ecc->bytes = 10;
> + }
> +
> + /* each step consists of 512 bytes of data */
> + ecc->size = NANDC_STEP_SIZE;
> +
> + ecc->read_page = qcom_nandc_read_page;
> + ecc->read_oob = qcom_nandc_read_oob;
> + ecc->write_page = qcom_nandc_write_page;
> + ecc->write_oob = qcom_nandc_write_oob;
> +
> + /*
> + * the bad block marker is readable only when we read the page with ECC
> + * disabled. all the ops above run with ECC enabled. We need raw read
> + * and write function for oob in order to access bad block marker.
> + */
> + ecc->read_oob_raw = qcom_nandc_read_oob_raw;
> + ecc->write_oob_raw = qcom_nandc_write_oob_raw;
> +
> + switch (mtd->oobsize) {
> + case 64:
> + ecc->layout = &layout_oob_64;
> + break;
> + case 128:
> + ecc->layout = &layout_oob_128;
> + break;
> + case 224:
> + if (wide_bus)
> + ecc->layout = &layout_oob_224_x16;
> + else
> + ecc->layout = &layout_oob_224_x8;
> + break;
> + case 256:
> + ecc->layout = &layout_oob_256;
> + break;
> + default:
> + dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
> + mtd->oobsize);
> + return -ENODEV;
> + }
> +
> + ecc->mode = NAND_ECC_HW;
> +
> + /* enable ecc by default */
> + this->use_ecc = true;
> +
> + return 0;
> +}
> +
> +static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = mtd->writesize / ecc->size;
> + int spare_bytes, bad_block_byte;
> + bool wide_bus;
> + int ecc_mode = 0;
> +
> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> +
> + if (ecc->strength >= 8) {
> + this->cw_size = 532;
> +
> + spare_bytes = wide_bus ? 0 : 2;
> +
> + this->bch_enabled = true;
> + ecc_mode = 1;
> + } else {
> + this->cw_size = 528;
> +
> + if (this->ecc_modes & ECC_BCH_4BIT) {
> + spare_bytes = wide_bus ? 2 : 4;
> +
> + this->bch_enabled = true;
> + ecc_mode = 0;
> + } else {
> + spare_bytes = wide_bus ? 0 : 1;
> + }
> + }
> +
> + /*
> + * DATA_UD_BYTES varies based on whether the read/write command protects
> + * spare data with ECC too. We protect spare data by default, so we set
> + * it to main + spare data, which are 512 and 4 bytes respectively.
> + */
> + this->cw_data = 516;
> +
> + bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
> +
> + this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
> + | this->cw_data << UD_SIZE_BYTES
> + | 0 << DISABLE_STATUS_AFTER_WRITE
> + | 5 << NUM_ADDR_CYCLES
> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
> + | 0 << STATUS_BFR_READ
> + | 1 << SET_RD_MODE_AFTER_STATUS
> + | spare_bytes << SPARE_SIZE_BYTES;
> +
> + this->cfg1 = 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | bad_block_byte << BAD_BLOCK_BYTE_NUM
> + | 0 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | wide_bus << WIDE_FLASH
> + | this->bch_enabled << ENABLE_BCH_ECC;
> +
> + this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
> + | this->cw_size << UD_SIZE_BYTES
> + | 5 << NUM_ADDR_CYCLES
> + | 0 << SPARE_SIZE_BYTES;
> +
> + this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | 17 << BAD_BLOCK_BYTE_NUM
> + | 1 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | wide_bus << WIDE_FLASH
> + | 1 << DEV0_CFG1_ECC_DISABLE;
> +
> + this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
> + | 0 << ECC_SW_RESET
> + | this->cw_data << ECC_NUM_DATA_BYTES
> + | 1 << ECC_FORCE_CLK_OPEN
> + | ecc_mode << ECC_MODE
> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
> +
> + this->ecc_buf_cfg = 0x203 << NUM_STEPS;
> +
> + this->clrflashstatus = FS_READY_BSY_N;
> + this->clrreadstatus = 0xc0;
> +
> + dev_dbg(this->dev,
> + "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
> + this->cfg0, this->cfg1, this->ecc_buf_cfg,
> + this->ecc_bch_cfg, this->cw_size, this->cw_data,
> + ecc->strength, ecc->bytes, cwperpage);
> +}
> +
> +static int qcom_nandc_alloc(struct qcom_nandc_data *this)
> +{
> + int r;
> +
> + r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
> + if (r) {
> + dev_err(this->dev, "failed to set DMA mask\n");
> + return r;
> + }
> +
> + /*
> + * we use the internal buffer for reading ONFI params, reading small
> + * data like ID and status, and preforming read-copy-write operations
> + * when writing to a codeword partially. 532 is the maximum possible
> + * size of a codeword for our nand controller
> + */
> + this->buf_size = 532;
> +
> + this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
> + if (!this->data_buffer)
> + return -ENOMEM;
> +
> + this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL);
> + if (!this->regs)
> + return -ENOMEM;
> +
> + this->reg_read_buf = devm_kzalloc(this->dev,
> + MAX_REG_RD * sizeof(*this->reg_read_buf),
> + GFP_KERNEL);
> + if (!this->reg_read_buf)
> + return -ENOMEM;
> +
> + INIT_LIST_HEAD(&this->list);
> +
> + this->chan = dma_request_slave_channel(this->dev, "rxtx");
> + if (!this->chan) {
> + dev_err(this->dev, "failed to request slave channel\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
> +{
> + dma_release_channel(this->chan);
> +}
> +
> +static int qcom_nandc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct device_node *np = this->dev->of_node;
> + struct mtd_part_parser_data ppdata = { .of_node = np };
> + int r;
> +
> + mtd->priv = chip;
> + mtd->name = "qcom-nandc";
> + mtd->owner = THIS_MODULE;
> +
> + chip->priv = this;
> +
> + chip->cmdfunc = qcom_nandc_command;
> + chip->select_chip = qcom_nandc_select_chip;
> + chip->read_byte = qcom_nandc_read_byte;
> + chip->read_buf = qcom_nandc_read_buf;
> + chip->write_buf = qcom_nandc_write_buf;
> +
> + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
> + if (this->bus_width == 16)
> + chip->options |= NAND_BUSWIDTH_16;
> +
> + chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
> + if (of_get_nand_on_flash_bbt(np))
Can you use nand_dt_init()? i.e., fill out chip->flash_node and let
nand_scan_ident() take care of most of the common DT parsing. You can
then clean up afterward with something like:
if (chip->bbt_options & NAND_BBT_USE_FLASH)
chip->bbt_options |= NAND_BBT_NO_OOB;
Similar for the bus width, ECC strength, and ECC step size parameters.
> + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
> +
> + qcom_nandc_pre_init(this);
> +
> + r = nand_scan_ident(mtd, 1, NULL);
> + if (r)
> + return r;
> +
> + r = qcom_nandc_ecc_init(this);
> + if (r)
> + return r;
> +
> + qcom_nandc_hw_post_init(this);
> +
> + r = nand_scan_tail(mtd);
> + if (r)
> + return r;
> +
> + return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
> +}
> +
> +static int qcom_nandc_parse_dt(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
> + struct device_node *np = this->dev->of_node;
> + int r;
> +
> + this->ecc_strength = of_get_nand_ecc_strength(np);
> + if (this->ecc_strength < 0) {
> + dev_warn(this->dev,
> + "incorrect ecc strength, setting to 4 bits/step\n");
> + this->ecc_strength = 4;
> + }
> +
> + this->bus_width = of_get_nand_bus_width(np);
> + if (this->bus_width < 0) {
> + dev_warn(this->dev, "incorrect bus width, setting to 8\n");
> + this->bus_width = 8;
> + }
> +
> + r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
> + if (r) {
> + dev_err(this->dev, "command CRCI unspecified\n");
> + return r;
> + }
> +
> + r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
> + if (r) {
> + dev_err(this->dev, "data CRCI unspecified\n");
> + return r;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_nandc_probe(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this;
> + const void *dev_data;
> + int r;
> +
> + this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
> + if (!this)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, this);
> +
> + this->pdev = pdev;
> + this->dev = &pdev->dev;
> +
> + dev_data = of_device_get_match_data(&pdev->dev);
> + if (!dev_data) {
> + dev_err(&pdev->dev, "failed to get device data\n");
> + return -ENODEV;
> + }
> +
> + this->ecc_modes = (unsigned long)dev_data;
> +
> + this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + this->base = devm_ioremap_resource(&pdev->dev, this->res);
> + if (IS_ERR(this->base))
> + return PTR_ERR(this->base);
> +
> + this->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(this->core_clk))
> + return PTR_ERR(this->core_clk);
> +
> + this->aon_clk = devm_clk_get(&pdev->dev, "aon");
> + if (IS_ERR(this->aon_clk))
> + return PTR_ERR(this->aon_clk);
> +
> + r = qcom_nandc_parse_dt(pdev);
> + if (r)
> + return r;
> +
> + r = qcom_nandc_alloc(this);
> + if (r)
> + return r;
> +
> + r = clk_prepare_enable(this->core_clk);
> + if (r)
> + goto err_core_clk;
> +
> + r = clk_prepare_enable(this->aon_clk);
> + if (r)
> + goto err_aon_clk;
> +
> + r = qcom_nandc_init(this);
> + if (r)
> + goto err_init;
> +
> + return 0;
> +
> +err_init:
> + clk_disable_unprepare(this->aon_clk);
> +err_aon_clk:
> + clk_disable_unprepare(this->core_clk);
> +err_core_clk:
> + qcom_nandc_unalloc(this);
> +
> + return r;
> +}
> +
> +static int qcom_nandc_remove(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
> +
> + qcom_nandc_unalloc(this);
> +
> + clk_disable_unprepare(this->aon_clk);
> + clk_disable_unprepare(this->core_clk);
> +
> + return 0;
> +}
> +
> +#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
> +
> +/*
> + * data will hold a struct pointer containing more differences once we support
> + * more IPs
> + */
> +static const struct of_device_id qcom_nandc_of_match[] = {
> + { .compatible = "qcom,ebi2-nandc",
> + .data = (void *) EBI2_NANDC_ECC_MODES,
> + },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
> +
> +static struct platform_driver qcom_nandc_driver = {
> + .driver = {
> + .name = "qcom-nandc",
> + .of_match_table = qcom_nandc_of_match,
> + },
> + .probe = qcom_nandc_probe,
> + .remove = qcom_nandc_remove,
> +};
> +module_platform_driver(qcom_nandc_driver);
> +
> +MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
> +MODULE_LICENSE("GPL v2");
Brian
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-10-02 2:44 ` Brian Norris
@ 2015-10-02 6:27 ` Boris Brezillon
2015-10-11 20:03 ` Brian Norris
0 siblings, 1 reply; 71+ messages in thread
From: Boris Brezillon @ 2015-10-02 6:27 UTC (permalink / raw)
To: Brian Norris
Cc: Archit Taneja, dehrenberg, linux-arm-msm, cernekee, sboyd,
linux-kernel, linux-mtd, agross, Andrea Scian
Brian, Archit,
On Thu, 1 Oct 2015 19:44:34 -0700
Brian Norris <computersforpeace@gmail.com> wrote:
> On Wed, Aug 19, 2015 at 10:19:02AM +0530, Archit Taneja wrote:
> > Some controllers can access the factory bad block marker from OOB only
> > when they read it in raw mode. When ECC is enabled, these controllers
> > discard reading/writing bad block markers, preventing access to them
> > altogether.
> >
> > The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
> > This results in the nand driver's ecc->read_oob() op to be called, which
> > works with ECC enabled.
> >
> > Create a new BBT option flag that tells nand_bbt to force the mode to
> > MTD_OPS_RAW. This would result in the correct op being called for the
> > underlying nand controller driver.
Actually I have the same kind of patch in my local tree (for a
different reason though: the HW randomizer can mess up with the BBM
byte if it's not disabled, and the only way to disable it in my current
implementation is to switch to raw mode).
>
> MTD_OPS_RAW is probably the best way to do this, and we should switch
> back to it for all users (rather than a new flag).
I'm fine with this solution, but will that be acceptable for everybody?
I mean, some NAND controllers are able to protect some OOB bytes, and
the BBM might fall in those OOB bytes. In this case, shouldn't we rely
on the ECC protection instead of reading the OOB in raw mode?
> But to do this, we
> need to fix up some things. Particularly, we need to extend
> 'badblockbits' support so that it is applied consistently in all places
> (I recall there is one code path in which bad block scanning does take
> this into account, and one that doesn't.)
Yes, IIRC Andrea has posted a patch addressing that problem [1].
Another problem I see is that badblockbits is currently assigned a
fixed value by the NAND controller driver (or a default value of 8).
There's no specific logic to correlate it to the required ECC strength.
IMO, we should not let each NAND controller driver decide what is the
appropriate value for each chip but rather implement the logic in
nand_base.c based on ecc->strength and ecc->size, and IIRC this was
the question Andrea asked when he posted his proposal.
>
> About badblockbits: it allows us to do a relaxed heuristic on matching
> bad block markers, where we say the BBM is "bad" if more than fewer than
> N bits are '1'. Right now, we just say that if there are any 0 bits in
> the Bad Block Marker (BBM) region, then the block is bad. But this is
> problematic for pages that have been worn down and might have bitflips.
> So right now, part of a (bad) solution is to read with ECC, so worn
> blocks that have data won't be later interpreted as bad blocks if we
> rescan the BBMs (ECC will correct the bitflips, if the OOB is
> protected).
>
> But that solution is not really good, since ECC is not really a panacea
> for misinterpreted BBMs. And HW like yours apparently won't work like
> this.
Okay, I see you gave pretty much the same explanation, which makes mine
useless :-).
>
> So in summary: if we can consistently make BBM checks look for 6 or 7
> "one" bits (rather than a full 8 bits, i.e. BBM == 0xff), then we can
> just unconditionally switch to RAW rather than PLACE_OOB. And we don't
> need a flag like this pach introduces.
I guess it all depends whether we want to let NAND controllers that can
protect their BBM keep doing it (which IMO is not such a bad idea).
Best Regards,
Boris
[1]http://thread.gmane.org/gmane.linux.drivers.mtd/57881
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-08-26 23:37 ` Stephen Boyd
2015-10-02 3:05 ` Brian Norris
@ 2015-10-02 17:31 ` Brian Norris
2015-12-16 9:15 ` Boris Brezillon
3 siblings, 0 replies; 71+ messages in thread
From: Brian Norris @ 2015-10-02 17:31 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, sboyd, linux-arm-msm, agross,
linux-kernel
One more nit noticed by my build tests:
On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
[...]
> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage;
drivers/mtd/nand/qcom_nandc.c: In function ‘qcom_nandc_ecc_init’:
drivers/mtd/nand/qcom_nandc.c:1517:6: warning: variable ‘cwperpage’ set but not used [-Wunused-but-set-variable]
> + bool wide_bus;
> +
> + /* the nand controller fetches codewords/chunks of 512 bytes */
> + cwperpage = mtd->writesize >> 9;
> +
> + ecc->strength = this->ecc_strength;
> +
> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> +
> + if (ecc->strength >= 8) {
> + /* 8 bit ECC defaults to BCH ECC on all platforms */
> + ecc->bytes = wide_bus ? 14 : 13;
> + } else {
> + /*
> + * if the controller supports BCH for 4 bit ECC, the controller
> + * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> + * always 10 bytes
> + */
> + if (this->ecc_modes & ECC_BCH_4BIT)
> + ecc->bytes = wide_bus ? 8 : 7;
> + else
> + ecc->bytes = 10;
> + }
> +
> + /* each step consists of 512 bytes of data */
> + ecc->size = NANDC_STEP_SIZE;
> +
> + ecc->read_page = qcom_nandc_read_page;
> + ecc->read_oob = qcom_nandc_read_oob;
> + ecc->write_page = qcom_nandc_write_page;
> + ecc->write_oob = qcom_nandc_write_oob;
> +
> + /*
> + * the bad block marker is readable only when we read the page with ECC
> + * disabled. all the ops above run with ECC enabled. We need raw read
> + * and write function for oob in order to access bad block marker.
> + */
> + ecc->read_oob_raw = qcom_nandc_read_oob_raw;
> + ecc->write_oob_raw = qcom_nandc_write_oob_raw;
> +
> + switch (mtd->oobsize) {
> + case 64:
> + ecc->layout = &layout_oob_64;
> + break;
> + case 128:
> + ecc->layout = &layout_oob_128;
> + break;
> + case 224:
> + if (wide_bus)
> + ecc->layout = &layout_oob_224_x16;
> + else
> + ecc->layout = &layout_oob_224_x8;
> + break;
> + case 256:
> + ecc->layout = &layout_oob_256;
> + break;
> + default:
> + dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
> + mtd->oobsize);
> + return -ENODEV;
> + }
> +
> + ecc->mode = NAND_ECC_HW;
> +
> + /* enable ecc by default */
> + this->use_ecc = true;
> +
> + return 0;
> +}
[...]
Brian
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-10-02 3:05 ` Brian Norris
@ 2015-10-05 6:51 ` Archit Taneja
2015-10-06 9:17 ` Brian Norris
0 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-10-05 6:51 UTC (permalink / raw)
To: Brian Norris
Cc: Boris Brezillon, dehrenberg, linux-arm-msm, cernekee, sboyd,
linux-kernel, linux-mtd, agross
Hi Brian,
Thanks for the review.
On 10/02/2015 08:35 AM, Brian Norris wrote:
> Hi Archit,
>
> On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
>> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
>> MDM9x15 series.
>>
>> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
>> and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
>> broader interface for external slow peripheral devices such as LCD and
>> NAND/NOR flash memory or SRAM like interfaces.
>>
>> We add support for the NAND controller found within EBI2. For the SoCs
>> of our interest, we only use the NAND controller within EBI2. Therefore,
>> it's safe for us to assume that the NAND controller is a standalone block
>> within the SoC.
>>
>> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
>> flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
>> 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
>> and spare data. The controller contains an internal 512 byte page buffer
>> to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
>> for register read/write and data transfers. The controller performs page
>> reads and writes at a codeword/step level of 512 bytes. It can support up
>> to 2 external chips of different configurations.
>>
>> The driver prepares register read and write configuration descriptors for
>> each codeword, followed by data descriptors to read or write data from the
>> controller's internal buffer. It uses a single ADM DMA channel that we get
>> via dmaengine API. The controller requires 2 ADM CRCIs for command and
>> data flow control. These are passed via DT.
>>
>> The ecc layout used by the controller is syndrome like, but we can't use
>> the standard syndrome ecc ops because of several reasons. First, the amount
>> of data bytes covered by ecc isn't same in each step. Second, writing to
>> free oob space requires us writing to the entire step in which the oob
>> lies. This forces us to create our own ecc ops.
>>
>> One more difference is how the controller accesses the bad block marker.
>> The controller ignores reading the marker when ECC is enabled. ECC needs
>> to be explicity disabled to read or write to the bad block marker. For
>> this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
>> read the factory provided bad block markers.
>>
>> v4:
>> - Shrink submit_descs
>> - add desc list node at the end of dma_prep_desc
>> - Endianness and warning fixes
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>
> Where does this sign-off come into play? It's not grouped with yours.
> Did Stephen have something to do with v4 only? Also, we typically trim
> the change log from the commit message (and place it below the '---' to
> do this automatically). Or did you intend for these changelogs to stay
> in the git history? I suppose it's not really harmful to keep it in if
> you'd like...
He'd corrected a piece of the code by sharing a patch with with me. You
can place his sign-off once you and Stephen accept the final patch
revision.
I don't have a problem with discarding the changelogs for the git
history. I can incorporate some of the major changes in the main
commit message above.
>
>>
>> v3:
>> - Refactor dma functions for maximum reuse
>> - Use dma_slave_confing on stack
>> - optimize and clean upempty_page_fixup using memchr_inv
>> - ensure portability with dma register reads using le32_* funcs
>> - use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
>> - fix handling of return values of dmaengine funcs
>> - constify wherever possible
>> - Remove dependency on ADM DMA in Kconfig
>> - Misc fixes and clean ups
>>
>> v2:
>> - Use new BBT flag that allows us to read BBM in raw mode
>> - reduce memcpy-s in the driver
>> - some refactor and clean ups because of above changes
>>
>> Reviewed-by: Andy Gross <agross@codeaurora.org>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>
> Has this driver been tested with drivers/mtd/tests/? Which ones? I'm
> particularly interested in oobtest, since you attempted to handle both
> ECC and raw OOB.
Yes. All the tests passed. Although, I couldn't figure out from the
oobtest console output if it tested both the ECC and RAW oob.
>
>> ---
>> drivers/mtd/nand/Kconfig | 7 +
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/qcom_nandc.c | 1910 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1918 insertions(+)
>> create mode 100644 drivers/mtd/nand/qcom_nandc.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 5b2806a..6085b8a 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -538,4 +538,11 @@ config MTD_NAND_HISI504
>> help
>> Enables support for NAND controller on Hisilicon SoC Hip04.
>>
>> +config MTD_NAND_QCOM
>> + tristate "Support for NAND on QCOM SoCs"
>> + depends on ARCH_QCOM
>> + help
>> + Enables support for NAND flash chips on SoCs containing the EBI2 NAND
>> + controller. This controller is found on IPQ806x SoC.
>> +
>> endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index 1f897ec..87b6a1d 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
>> obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
>> obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
>> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>> +obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>
>> nand-objs := nand_base.o nand_bbt.o nand_timings.o
>> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
>> new file mode 100644
>> index 0000000..2337731
>> --- /dev/null
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -0,0 +1,1910 @@
>> +/*
>> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/slab.h>
>> +#include <linux/bitops.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/dmaengine.h>
>> +#include <linux/module.h>
>> +#include <linux/mtd/nand.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/of_mtd.h>
>> +#include <linux/delay.h>
>> +
>> +/* NANDc reg offsets */
>> +#define NAND_FLASH_CMD 0x00
>> +#define NAND_ADDR0 0x04
>> +#define NAND_ADDR1 0x08
>> +#define NAND_FLASH_CHIP_SELECT 0x0c
>> +#define NAND_EXEC_CMD 0x10
>> +#define NAND_FLASH_STATUS 0x14
>> +#define NAND_BUFFER_STATUS 0x18
>> +#define NAND_DEV0_CFG0 0x20
>> +#define NAND_DEV0_CFG1 0x24
>> +#define NAND_DEV0_ECC_CFG 0x28
>> +#define NAND_DEV1_ECC_CFG 0x2c
>> +#define NAND_DEV1_CFG0 0x30
>> +#define NAND_DEV1_CFG1 0x34
>> +#define NAND_READ_ID 0x40
>> +#define NAND_READ_STATUS 0x44
>> +#define NAND_DEV_CMD0 0xa0
>> +#define NAND_DEV_CMD1 0xa4
>> +#define NAND_DEV_CMD2 0xa8
>> +#define NAND_DEV_CMD_VLD 0xac
>> +#define SFLASHC_BURST_CFG 0xe0
>> +#define NAND_ERASED_CW_DETECT_CFG 0xe8
>> +#define NAND_ERASED_CW_DETECT_STATUS 0xec
>> +#define NAND_EBI2_ECC_BUF_CFG 0xf0
>> +#define FLASH_BUF_ACC 0x100
>> +
>> +#define NAND_CTRL 0xf00
>> +#define NAND_VERSION 0xf08
>> +#define NAND_READ_LOCATION_0 0xf20
>> +#define NAND_READ_LOCATION_1 0xf24
>> +
>> +/* dummy register offsets, used by write_reg_dma */
>> +#define NAND_DEV_CMD1_RESTORE 0xdead
>> +#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
>> +
>> +/* NAND_FLASH_CMD bits */
>> +#define PAGE_ACC BIT(4)
>> +#define LAST_PAGE BIT(5)
>> +
>> +/* NAND_FLASH_CHIP_SELECT bits */
>> +#define NAND_DEV_SEL 0
>> +#define DM_EN BIT(2)
>> +
>> +/* NAND_FLASH_STATUS bits */
>> +#define FS_OP_ERR BIT(4)
>> +#define FS_READY_BSY_N BIT(5)
>> +#define FS_MPU_ERR BIT(8)
>> +#define FS_DEVICE_STS_ERR BIT(16)
>> +#define FS_DEVICE_WP BIT(23)
>> +
>> +/* NAND_BUFFER_STATUS bits */
>> +#define BS_UNCORRECTABLE_BIT BIT(8)
>> +#define BS_CORRECTABLE_ERR_MSK 0x1f
>> +
>> +/* NAND_DEVn_CFG0 bits */
>> +#define DISABLE_STATUS_AFTER_WRITE 4
>> +#define CW_PER_PAGE 6
>> +#define UD_SIZE_BYTES 9
>> +#define ECC_PARITY_SIZE_BYTES_RS 19
>> +#define SPARE_SIZE_BYTES 23
>> +#define NUM_ADDR_CYCLES 27
>> +#define STATUS_BFR_READ 30
>> +#define SET_RD_MODE_AFTER_STATUS 31
>> +
>> +/* NAND_DEVn_CFG0 bits */
>> +#define DEV0_CFG1_ECC_DISABLE 0
>> +#define WIDE_FLASH 1
>> +#define NAND_RECOVERY_CYCLES 2
>> +#define CS_ACTIVE_BSY 5
>> +#define BAD_BLOCK_BYTE_NUM 6
>> +#define BAD_BLOCK_IN_SPARE_AREA 16
>> +#define WR_RD_BSY_GAP 17
>> +#define ENABLE_BCH_ECC 27
>> +
>> +/* NAND_DEV0_ECC_CFG bits */
>> +#define ECC_CFG_ECC_DISABLE 0
>> +#define ECC_SW_RESET 1
>> +#define ECC_MODE 4
>> +#define ECC_PARITY_SIZE_BYTES_BCH 8
>> +#define ECC_NUM_DATA_BYTES 16
>> +#define ECC_FORCE_CLK_OPEN 30
>> +
>> +/* NAND_DEV_CMD1 bits */
>> +#define READ_ADDR 0
>> +
>> +/* NAND_DEV_CMD_VLD bits */
>> +#define READ_START_VLD 0
>> +
>> +/* NAND_EBI2_ECC_BUF_CFG bits */
>> +#define NUM_STEPS 0
>> +
>> +/* NAND_ERASED_CW_DETECT_CFG bits */
>> +#define ERASED_CW_ECC_MASK 1
>> +#define AUTO_DETECT_RES 0
>> +#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
>> +#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
>> +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
>> +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
>> +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
>> +
>> +/* NAND_ERASED_CW_DETECT_STATUS bits */
>> +#define PAGE_ALL_ERASED BIT(7)
>> +#define CODEWORD_ALL_ERASED BIT(6)
>> +#define PAGE_ERASED BIT(5)
>> +#define CODEWORD_ERASED BIT(4)
>> +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
>> +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
>> +
>> +/* Version Mask */
>> +#define NAND_VERSION_MAJOR_MASK 0xf0000000
>> +#define NAND_VERSION_MAJOR_SHIFT 28
>> +#define NAND_VERSION_MINOR_MASK 0x0fff0000
>> +#define NAND_VERSION_MINOR_SHIFT 16
>> +
>> +/* NAND OP_CMDs */
>> +#define PAGE_READ 0x2
>> +#define PAGE_READ_WITH_ECC 0x3
>> +#define PAGE_READ_WITH_ECC_SPARE 0x4
>> +#define PROGRAM_PAGE 0x6
>> +#define PAGE_PROGRAM_WITH_ECC 0x7
>> +#define PROGRAM_PAGE_SPARE 0x9
>> +#define BLOCK_ERASE 0xa
>> +#define FETCH_ID 0xb
>> +#define RESET_DEVICE 0xd
>> +
>> +/*
>> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>> + * the driver calls the chunks 'step' or 'codeword' interchangeably
>> + */
>> +#define NANDC_STEP_SIZE 512
>> +
>> +/*
>> + * the largest page size we support is 8K, this will have 16 steps/codewords
>> + * of 512 bytes each
>> + */
>> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
>> +
>> +/* we read at most 3 registers per codeword scan */
>> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
>> +
>> +/* ECC modes */
>> +#define ECC_NONE BIT(0)
>> +#define ECC_RS_4BIT BIT(1)
>> +#define ECC_BCH_4BIT BIT(2)
>> +#define ECC_BCH_8BIT BIT(3)
>> +
>> +struct desc_info {
>> + struct list_head list;
>> +
>> + enum dma_data_direction dir;
>> + struct scatterlist sgl;
>> + struct dma_async_tx_descriptor *dma_desc;
>> +};
>> +
>> +/*
>> + * holds the current register values that we want to write. acts as a contiguous
>> + * chunk of memory which we use to write the controller registers through DMA.
>> + */
>> +struct nandc_regs {
>> + __le32 cmd;
>> + __le32 addr0;
>> + __le32 addr1;
>> + __le32 chip_sel;
>> + __le32 exec;
>> +
>> + __le32 cfg0;
>> + __le32 cfg1;
>> + __le32 ecc_bch_cfg;
>> +
>> + __le32 clrflashstatus;
>> + __le32 clrreadstatus;
>> +
>> + __le32 cmd1;
>> + __le32 vld;
>> +
>> + __le32 orig_cmd1;
>> + __le32 orig_vld;
>> +
>> + __le32 ecc_buf_cfg;
>> +};
>> +
>> +/*
>> + * @cmd_crci: ADM DMA CRCI for command flow control
>> + * @data_crci: ADM DMA CRCI for data flow control
>> + * @list: DMA descriptor list (list of desc_infos)
>> + * @data_buffer: our local DMA buffer for page read/writes,
>> + * used when we can't use the buffer provided
>> + * by upper layers directly
>> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
>> + * @reg_read_buf: buffer for reading register data via DMA
>> + * @reg_read_pos: marker for data read in reg_read_buf
>> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
>> + * ecc/non-ecc mode for the current nand flash
>> + * device
>> + * @regs: a contiguous chunk of memory for DMA register
>> + * writes
>> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
>> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
>> + * @ecc_modes: supported ECC modes by the current controller,
>> + * initialized via DT match data
>> + * @cw_size: the number of bytes in a single step/codeword
>> + * of a page, consisting of all data, ecc, spare
>> + * and reserved bytes
>> + * @cw_data: the number of bytes within a codeword protected
>> + * by ECC
>> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
>> + * @status: value to be returned if NAND_CMD_STATUS command
>> + * is executed
>> + */
>> +struct qcom_nandc_data {
>> + struct platform_device *pdev;
>
> This field is only set once, but unused?
It is used in the driver remove (qcom_nandc_remove) to get a pointer to
this data struct.
>
> And it (and several others) aren't documented above.
The comments weren't meant to be a part of kernel docs. So, I left out
some of the more obvious params.
>
>> + struct device *dev;
>> +
>> + void __iomem *base;
>> + struct resource *res;
>> +
>> + struct clk *core_clk;
>> + struct clk *aon_clk;
>> +
>> + /* DMA stuff */
>> + struct dma_chan *chan;
>> + struct dma_slave_config slave_conf;
>> + unsigned int cmd_crci;
>> + unsigned int data_crci;
>> + struct list_head list;
>> +
>> + /* MTD stuff */
>> + struct nand_chip chip;
>> + struct mtd_info mtd;
>> +
>> + /* local data buffer and markers */
>> + u8 *data_buffer;
>> + int buf_size;
>> + int buf_count;
>> + int buf_start;
>> +
>> + /* local buffer to read back registers */
>> + __le32 *reg_read_buf;
>> + int reg_read_pos;
>> +
>> + /* required configs */
>> + u32 cfg0, cfg1;
>> + u32 cfg0_raw, cfg1_raw;
>> + u32 ecc_buf_cfg;
>> + u32 ecc_bch_cfg;
>> + u32 clrflashstatus;
>> + u32 clrreadstatus;
>> + u32 sflashc_burst_cfg;
>> + u32 cmd1, vld;
>> +
>> + /* register state */
>> + struct nandc_regs *regs;
>> +
>> + /* things we get from DT */
>> + int ecc_strength;
>> + int bus_width;
>> +
>> + u32 ecc_modes;
>> +
>> + /* misc params */
>> + int cw_size;
>> + int cw_data;
>> + bool use_ecc;
>> + bool bch_enabled;
>> + u8 status;
>> + int last_command;
>> +};
>> +
>> +static inline u32 nandc_read(struct qcom_nandc_data *this, int offset)
>> +{
>> + return ioread32(this->base + offset);
>> +}
>> +
>> +static inline void nandc_write(struct qcom_nandc_data *this, int offset,
>> + u32 val)
>> +{
>> + iowrite32(val, this->base + offset);
>> +}
>> +
>> +static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
>> +{
>> + switch (offset) {
>> + case NAND_FLASH_CMD:
>> + return ®s->cmd;
>> + case NAND_ADDR0:
>> + return ®s->addr0;
>> + case NAND_ADDR1:
>> + return ®s->addr1;
>> + case NAND_FLASH_CHIP_SELECT:
>> + return ®s->chip_sel;
>> + case NAND_EXEC_CMD:
>> + return ®s->exec;
>> + case NAND_FLASH_STATUS:
>> + return ®s->clrflashstatus;
>> + case NAND_DEV0_CFG0:
>> + return ®s->cfg0;
>> + case NAND_DEV0_CFG1:
>> + return ®s->cfg1;
>> + case NAND_DEV0_ECC_CFG:
>> + return ®s->ecc_bch_cfg;
>> + case NAND_READ_STATUS:
>> + return ®s->clrreadstatus;
>> + case NAND_DEV_CMD1:
>> + return ®s->cmd1;
>> + case NAND_DEV_CMD1_RESTORE:
>> + return ®s->orig_cmd1;
>> + case NAND_DEV_CMD_VLD:
>> + return ®s->vld;
>> + case NAND_DEV_CMD_VLD_RESTORE:
>> + return ®s->orig_vld;
>> + case NAND_EBI2_ECC_BUF_CFG:
>> + return ®s->ecc_buf_cfg;
>> + default:
>> + return NULL;
>> + }
>> +}
>> +
>> +static void set_nandc_reg(struct qcom_nandc_data *this, int offset, u32 val)
>> +{
>> + struct nandc_regs *regs = this->regs;
>> + __le32 *reg;
>> +
>> + reg = offset_to_nandc_reg(regs, offset);
>> +
>> + if (reg)
>> + *reg = cpu_to_le32(val);
>> +}
>> +
>> +/* helper to configure address register values */
>> +static void set_address(struct qcom_nandc_data *this, u16 column, int page)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> +
>> + if (chip->options & NAND_BUSWIDTH_16)
>> + column >>= 1;
>> +
>> + set_nandc_reg(this, NAND_ADDR0, page << 16 | column);
>> + set_nandc_reg(this, NAND_ADDR1, page >> 16 & 0xff);
>> +}
>> +
>> +/*
>> + * update_rw_regs: set up read/write register values, these will be
>> + * written to the NAND controller registers via DMA
>> + *
>> + * @num_cw: number of steps for the read/write operation
>> + * @read: read or write operation
>> + */
>> +static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read)
>> +{
>> + u32 cmd, cfg0, cfg1, ecc_bch_cfg;
>> +
>> + if (read) {
>> + if (this->use_ecc)
>> + cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
>> + else
>> + cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
>> + } else {
>> + cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
>> + }
>> +
>> + if (this->use_ecc) {
>> + cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) |
>> + (num_cw - 1) << CW_PER_PAGE;
>> +
>> + cfg1 = this->cfg1;
>> + ecc_bch_cfg = this->ecc_bch_cfg;
>> + } else {
>> + cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) |
>> + (num_cw - 1) << CW_PER_PAGE;
>> +
>> + cfg1 = this->cfg1_raw;
>> + ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
>> + }
>> +
>> + set_nandc_reg(this, NAND_FLASH_CMD, cmd);
>> + set_nandc_reg(this, NAND_DEV0_CFG0, cfg0);
>> + set_nandc_reg(this, NAND_DEV0_CFG1, cfg1);
>> + set_nandc_reg(this, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
>> + set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, this->ecc_buf_cfg);
>> + set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
>> + set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
>> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
>> +}
>> +
>> +static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off,
>> + const void *vaddr, int size, bool flow_control)
>> +{
>> + struct desc_info *desc;
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct scatterlist *sgl;
>> + struct dma_slave_config slave_conf;
>> + enum dma_transfer_direction dir_eng;
>> + int r;
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + sgl = &desc->sgl;
>> +
>> + sg_init_one(sgl, vaddr, size);
>> +
>> + if (read) {
>> + dir_eng = DMA_DEV_TO_MEM;
>> + desc->dir = DMA_FROM_DEVICE;
>> + } else {
>> + dir_eng = DMA_MEM_TO_DEV;
>> + desc->dir = DMA_TO_DEVICE;
>> + }
>> +
>> + r = dma_map_sg(this->dev, sgl, 1, desc->dir);
>> + if (r == 0) {
>> + r = -ENOMEM;
>> + goto err;
>> + }
>> +
>> + memset(&slave_conf, 0x00, sizeof(slave_conf));
>> +
>> + slave_conf.device_fc = flow_control;
>> + if (read) {
>> + slave_conf.src_maxburst = 16;
>> + slave_conf.src_addr = this->res->start + reg_off;
>> + slave_conf.slave_id = this->data_crci;
>> + } else {
>> + slave_conf.dst_maxburst = 16;
>> + slave_conf.dst_addr = this->res->start + reg_off;
>> + slave_conf.slave_id = this->cmd_crci;
>> + }
>> +
>> + r = dmaengine_slave_config(this->chan, &slave_conf);
>> + if (r) {
>> + dev_err(this->dev, "failed to configure dma channel\n");
>> + goto err;
>> + }
>> +
>> + dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, dir_eng, 0);
>> + if (!dma_desc) {
>> + dev_err(this->dev, "failed to prepare desc\n");
>> + r = -EINVAL;
>> + goto err;
>> + }
>> +
>> + desc->dma_desc = dma_desc;
>> +
>> + list_add_tail(&desc->list, &this->list);
>> +
>> + return 0;
>> +err:
>> + kfree(desc);
>> +
>> + return r;
>> +}
>> +
>> +/*
>> + * read_reg_dma: prepares a descriptor to read a given number of
>> + * contiguous registers to the reg_read_buf pointer
>> + *
>> + * @first: offset of the first register in the contiguous block
>> + * @num_regs: number of registers to read
>> + */
>> +static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
>> +{
>> + bool flow_control = false;
>> + void *vaddr;
>> + int size;
>> +
>> + if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>> + flow_control = true;
>> +
>> + size = num_regs * sizeof(u32);
>> + vaddr = this->reg_read_buf + this->reg_read_pos;
>> + this->reg_read_pos += num_regs;
>> +
>> + return prep_dma_desc(this, true, first, vaddr, size, flow_control);
>> +}
>> +
>> +/*
>> + * write_reg_dma: prepares a descriptor to write a given number of
>> + * contiguous registers
>> + *
>> + * @first: offset of the first register in the contiguous block
>> + * @num_regs: number of registers to write
>> + */
>> +static int write_reg_dma(struct qcom_nandc_data *this, int first, int num_regs)
>> +{
>> + bool flow_control = false;
>> + struct nandc_regs *regs = this->regs;
>> + void *vaddr;
>> + int size;
>> +
>> + vaddr = offset_to_nandc_reg(regs, first);
>> +
>> + if (first == NAND_FLASH_CMD)
>> + flow_control = true;
>> +
>> + if (first == NAND_DEV_CMD1_RESTORE)
>> + first = NAND_DEV_CMD1;
>> +
>> + if (first == NAND_DEV_CMD_VLD_RESTORE)
>> + first = NAND_DEV_CMD_VLD;
>> +
>> + size = num_regs * sizeof(u32);
>> +
>> + return prep_dma_desc(this, false, first, vaddr, size, flow_control);
>> +}
>> +
>> +/*
>> + * read_data_dma: prepares a DMA descriptor to transfer data from the
>> + * controller's internal buffer to the buffer 'vaddr'
>> + *
>> + * @reg_off: offset within the controller's data buffer
>> + * @vaddr: virtual address of the buffer we want to write to
>> + * @size: DMA transaction size in bytes
>> + */
>> +static int read_data_dma(struct qcom_nandc_data *this, int reg_off,
>> + const u8 *vaddr, int size)
>> +{
>> + return prep_dma_desc(this, true, reg_off, vaddr, size, false);
>> +}
>> +
>> +/*
>> + * write_data_dma: prepares a DMA descriptor to transfer data from
>> + * 'vaddr' to the controller's internal buffer
>> + *
>> + * @reg_off: offset within the controller's data buffer
>> + * @vaddr: virtual address of the buffer we want to read from
>> + * @size: DMA transaction size in bytes
>> + */
>> +static int write_data_dma(struct qcom_nandc_data *this, int reg_off,
>> + const u8 *vaddr, int size)
>> +{
>> + return prep_dma_desc(this, false, reg_off, vaddr, size, false);
>> +}
>> +
>> +/*
>> + * helper to prepare dma descriptors to configure registers needed for reading a
>> + * codeword/step in a page
>> + */
>> +static void config_cw_read(struct qcom_nandc_data *this)
>> +{
>> + write_reg_dma(this, NAND_FLASH_CMD, 3);
>> + write_reg_dma(this, NAND_DEV0_CFG0, 3);
>> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
>> +
>> + write_reg_dma(this, NAND_EXEC_CMD, 1);
>> +
>> + read_reg_dma(this, NAND_FLASH_STATUS, 2);
>> + read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1);
>> +}
>> +
>> +/*
>> + * helpers to prepare dma descriptors used to configure registers needed for
>> + * writing a codeword/step in a page
>> + */
>> +static void config_cw_write_pre(struct qcom_nandc_data *this)
>> +{
>> + write_reg_dma(this, NAND_FLASH_CMD, 3);
>> + write_reg_dma(this, NAND_DEV0_CFG0, 3);
>> + write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1);
>> +}
>> +
>> +static void config_cw_write_post(struct qcom_nandc_data *this)
>> +{
>> + write_reg_dma(this, NAND_EXEC_CMD, 1);
>> +
>> + read_reg_dma(this, NAND_FLASH_STATUS, 1);
>> +
>> + write_reg_dma(this, NAND_FLASH_STATUS, 1);
>> + write_reg_dma(this, NAND_READ_STATUS, 1);
>> +}
>> +
>> +/*
>> + * the following functions are used within chip->cmdfunc() to perform different
>> + * NAND_CMD_* commands
>> + */
>> +
>> +/* sets up descriptors for NAND_CMD_PARAM */
>> +static int nandc_param(struct qcom_nandc_data *this)
>> +{
>> + /*
>> + * NAND_CMD_PARAM is called before we know much about the FLASH chip
>> + * in use. we configure the controller to perform a raw read of 512
>> + * bytes to read onfi params
>> + */
>> + set_nandc_reg(this, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
>> + set_nandc_reg(this, NAND_ADDR0, 0);
>> + set_nandc_reg(this, NAND_ADDR1, 0);
>> + set_nandc_reg(this, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
>> + | 512 << UD_SIZE_BYTES
>> + | 5 << NUM_ADDR_CYCLES
>> + | 0 << SPARE_SIZE_BYTES);
>> + set_nandc_reg(this, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
>> + | 0 << CS_ACTIVE_BSY
>> + | 17 << BAD_BLOCK_BYTE_NUM
>> + | 1 << BAD_BLOCK_IN_SPARE_AREA
>> + | 2 << WR_RD_BSY_GAP
>> + | 0 << WIDE_FLASH
>> + | 1 << DEV0_CFG1_ECC_DISABLE);
>> + set_nandc_reg(this, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
>> +
>> +
>> + /* configure CMD1 and VLD for ONFI param probing */
>> + set_nandc_reg(this, NAND_DEV_CMD_VLD,
>> + (this->vld & ~(1 << READ_START_VLD))
>> + | 0 << READ_START_VLD);
>> + set_nandc_reg(this, NAND_DEV_CMD1,
>> + (this->cmd1 & ~(0xFF << READ_ADDR))
>> + | NAND_CMD_PARAM << READ_ADDR);
>> +
>> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
>> +
>> + set_nandc_reg(this, NAND_DEV_CMD1_RESTORE, this->cmd1);
>> + set_nandc_reg(this, NAND_DEV_CMD_VLD_RESTORE, this->vld);
>> +
>> + write_reg_dma(this, NAND_DEV_CMD_VLD, 1);
>> + write_reg_dma(this, NAND_DEV_CMD1, 1);
>> +
>> + this->buf_count = 512;
>> + memset(this->data_buffer, 0xff, this->buf_count);
>> +
>> + config_cw_read(this);
>> +
>> + read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->buf_count);
>> +
>> + /* restore CMD1 and VLD regs */
>> + write_reg_dma(this, NAND_DEV_CMD1_RESTORE, 1);
>> + write_reg_dma(this, NAND_DEV_CMD_VLD_RESTORE, 1);
>> +
>> + return 0;
>> +}
>> +
>> +/* sets up descriptors for NAND_CMD_ERASE1 */
>> +static int erase_block(struct qcom_nandc_data *this, int page_addr)
>> +{
>> + set_nandc_reg(this, NAND_FLASH_CMD, BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
>> + set_nandc_reg(this, NAND_ADDR0, page_addr);
>> + set_nandc_reg(this, NAND_ADDR1, 0);
>> + set_nandc_reg(this, NAND_DEV0_CFG0,
>> + this->cfg0_raw & ~(7 << CW_PER_PAGE));
>> + set_nandc_reg(this, NAND_DEV0_CFG1, this->cfg1_raw);
>> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
>> + set_nandc_reg(this, NAND_FLASH_STATUS, this->clrflashstatus);
>> + set_nandc_reg(this, NAND_READ_STATUS, this->clrreadstatus);
>> +
>> + write_reg_dma(this, NAND_FLASH_CMD, 3);
>> + write_reg_dma(this, NAND_DEV0_CFG0, 2);
>> + write_reg_dma(this, NAND_EXEC_CMD, 1);
>> +
>> + read_reg_dma(this, NAND_FLASH_STATUS, 1);
>> +
>> + write_reg_dma(this, NAND_FLASH_STATUS, 1);
>> + write_reg_dma(this, NAND_READ_STATUS, 1);
>> +
>> + return 0;
>> +}
>> +
>> +/* sets up descriptors for NAND_CMD_READID */
>> +static int read_id(struct qcom_nandc_data *this, int column)
>> +{
>> + if (column == -1)
>> + return 0;
>> +
>> + set_nandc_reg(this, NAND_FLASH_CMD, FETCH_ID);
>> + set_nandc_reg(this, NAND_ADDR0, column);
>> + set_nandc_reg(this, NAND_ADDR1, 0);
>> + set_nandc_reg(this, NAND_FLASH_CHIP_SELECT, DM_EN);
>> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
>> +
>> + write_reg_dma(this, NAND_FLASH_CMD, 4);
>> + write_reg_dma(this, NAND_EXEC_CMD, 1);
>> +
>> + read_reg_dma(this, NAND_READ_ID, 1);
>> +
>> + return 0;
>> +}
>> +
>> +/* sets up descriptors for NAND_CMD_RESET */
>> +static int reset(struct qcom_nandc_data *this)
>> +{
>> + set_nandc_reg(this, NAND_FLASH_CMD, RESET_DEVICE);
>> + set_nandc_reg(this, NAND_EXEC_CMD, 1);
>> +
>> + write_reg_dma(this, NAND_FLASH_CMD, 1);
>> + write_reg_dma(this, NAND_EXEC_CMD, 1);
>> +
>> + read_reg_dma(this, NAND_FLASH_STATUS, 1);
>> +
>> + return 0;
>> +}
>> +
>> +/* helpers to submit/free our list of dma descriptors */
>> +static int submit_descs(struct qcom_nandc_data *this)
>> +{
>> + struct desc_info *desc;
>> + dma_cookie_t cookie = 0;
>> +
>> + list_for_each_entry(desc, &this->list, list)
>> + cookie = dmaengine_submit(desc->dma_desc);
>> +
>> + if (dma_sync_wait(this->chan, cookie) != DMA_COMPLETE)
>> + return -ETIMEDOUT;
>> +
>> + return 0;
>> +}
>> +
>> +static void free_descs(struct qcom_nandc_data *this)
>> +{
>> + struct desc_info *desc, *n;
>> +
>> + list_for_each_entry_safe(desc, n, &this->list, list) {
>> + list_del(&desc->list);
>> + dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir);
>> + kfree(desc);
>> + }
>> +}
>> +
>> +/* reset the register read buffer for next NAND operation */
>> +static void clear_read_regs(struct qcom_nandc_data *this)
>> +{
>> + this->reg_read_pos = 0;
>> + memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(*this->reg_read_buf));
>> +}
>> +
>> +static void pre_command(struct qcom_nandc_data *this, int command)
>> +{
>> + this->buf_count = 0;
>> + this->buf_start = 0;
>> + this->use_ecc = false;
>> + this->last_command = command;
>> +
>> + clear_read_regs(this);
>> +}
>> +
>> +/*
>> + * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
>> + * privately maintained status byte, this status byte can be read after
>> + * NAND_CMD_STATUS is called
>> + */
>> +static void parse_erase_write_errors(struct qcom_nandc_data *this, int command)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int num_cw;
>> + int i;
>> +
>> + num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
>> +
>> + for (i = 0; i < num_cw; i++) {
>> + u32 flash_status = le32_to_cpu(this->reg_read_buf[i]);
>> +
>> + if (flash_status & FS_MPU_ERR)
>> + this->status &= ~NAND_STATUS_WP;
>> +
>> + if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
>> + (flash_status & FS_DEVICE_STS_ERR)))
>> + this->status |= NAND_STATUS_FAIL;
>> + }
>> +}
>> +
>> +static void post_command(struct qcom_nandc_data *this, int command)
>> +{
>> + switch (command) {
>> + case NAND_CMD_READID:
>> + memcpy(this->data_buffer, this->reg_read_buf, this->buf_count);
>> + break;
>> + case NAND_CMD_PAGEPROG:
>> + case NAND_CMD_ERASE1:
>> + parse_erase_write_errors(this, command);
>> + break;
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +/*
>> + * Implements chip->cmdfunc. It's only used for a limited set of commands.
>> + * The rest of the commands wouldn't be called by upper layers. For example,
>> + * NAND_CMD_READOOB would never be called because we have our own versions
>> + * of read_oob ops for nand_ecc_ctrl.
>> + */
>> +static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
>> + int column, int page_addr)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + struct qcom_nandc_data *this = chip->priv;
>> + bool wait = false;
>> + int r = 0;
>> +
>> + pre_command(this, command);
>> +
>> + switch (command) {
>> + case NAND_CMD_RESET:
>> + r = reset(this);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_READID:
>> + this->buf_count = 4;
>> + r = read_id(this, column);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_PARAM:
>> + r = nandc_param(this);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_ERASE1:
>> + r = erase_block(this, page_addr);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_READ0:
>> + /* we read the entire page for now */
>> + WARN_ON(column != 0);
>> +
>> + this->use_ecc = true;
>> + set_address(this, 0, page_addr);
>> + update_rw_regs(this, ecc->steps, true);
>> + break;
>> +
>> + case NAND_CMD_SEQIN:
>> + WARN_ON(column != 0);
>> + set_address(this, 0, page_addr);
>> + break;
>> +
>> + case NAND_CMD_PAGEPROG:
>> + case NAND_CMD_STATUS:
>> + case NAND_CMD_NONE:
>> + default:
>> + break;
>> + }
>> +
>> + if (r) {
>> + dev_err(this->dev, "failure executing command %d\n",
>> + command);
>> + free_descs(this);
>> + return;
>> + }
>> +
>> + if (wait) {
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev,
>> + "failure submitting descs for command %d\n",
>> + command);
>> + }
>> +
>> + free_descs(this);
>> +
>> + post_command(this, command);
>> +}
>> +
>> +/*
>> + * when using RS ECC, the NAND controller flags an error when reading an
>> + * erased page. however, there are special characters at certain offsets when
>> + * we read the erased page. we check here if the page is really empty. if so,
>> + * we replace the magic characters with 0xffs
>> + */
>
> What's the nature of this erased page flagging? Does it only detect
> all-0xff pages? What about if the erased page experiences any bitflips?
> A lot of drivers have been attempting to handle that case too (which is
> becoming more common on modern MLC, and even on SLC), and most of the
> times they do it poorly.
The hardware can raise an 'erased' flag per step, when all the bytes in
the step are 0xff. The code below would consider the page as
'not erased' if any step doesn't report an erased flag.
>
> See nand_check_erased_ecc_chunk() (in linux-next.git) as an example of a
> brute force helper to assist for cases where HW ECC is not sufficient.
I'll have a look. Thanks.
>
>> +static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS];
>> + int i, j;
>> +
>> + /* if BCH is enabled, HW will take care of detecting erased pages */
>> + if (this->bch_enabled || !this->use_ecc)
>> + return false;
>> +
>> + for (i = 0; i < cwperpage; i++) {
>> + u8 *empty1, *empty2;
>> + u32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
>> +
>> + /*
>> + * an erased page flags an error in NAND_FLASH_STATUS, check if
>> + * the page is erased by looking for 0x54s at offsets 3 and 175
>> + * from the beginning of each codeword
>> + */
>> + if (!(flash_status & FS_OP_ERR))
>> + break;
>> +
>> + empty1 = &data_buf[3 + i * this->cw_data];
>> + empty2 = &data_buf[175 + i * this->cw_data];
>> +
>> + /*
>> + * if the error wasn't because of an erased page, bail out and
>> + * and let someone else do the error checking
>> + */
>> + if ((*empty1 == 0x54 && *empty2 == 0xff) ||
>> + (*empty1 == 0xff && *empty2 == 0x54)) {
>> + orig1[i] = *empty1;
>> + orig2[i] = *empty2;
>> +
>> + *empty1 = 0xff;
>> + *empty2 = 0xff;
>> + } else {
>> + break;
>> + }
>> + }
>> +
>> + if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize))
>> + goto not_empty;
>> +
>> + /*
>> + * tell the caller that the page was empty and is fixed up, so that
>> + * parse_read_errors() doesn't think it's an error
>> + */
>> + return true;
>> +
>> +not_empty:
>> + /* restore original values if not empty*/
>> + for (j = 0; j < i; j++) {
>> + data_buf[3 + j * this->cw_data] = orig1[j];
>> + data_buf[175 + j * this->cw_data] = orig2[j];
>> + }
>> +
>> + return false;
>> +}
>> +
>> +struct read_stats {
>> + __le32 flash;
>> + __le32 buffer;
>> + __le32 erased_cw;
>> +};
>> +
>> +/*
>> + * reads back status registers set by the controller to notify page read
>> + * errors. this is equivalent to what 'ecc->correct()' would do.
>> + */
>> +static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + unsigned int max_bitflips = 0;
>> + int i;
>> + struct read_stats *buf;
>> +
>> + buf = (struct read_stats *)this->reg_read_buf;
>> + for (i = 0; i < cwperpage; i++, buf++) {
>> + unsigned int stat;
>> + u32 flash, buffer, erased_cw;
>> +
>> + flash = le32_to_cpu(buf->flash);
>> + buffer = le32_to_cpu(buf->buffer);
>> + erased_cw = le32_to_cpu(buf->erased_cw);
>> +
>> + if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
>> +
>> + /* ignore erased codeword errors */
>> + if (this->bch_enabled) {
>> + if ((erased_cw & ERASED_CW) == ERASED_CW)
>> + continue;
>> + } else if (erased_page) {
>> + continue;
>> + }
>> +
>> + if (buffer & BS_UNCORRECTABLE_BIT) {
>> + mtd->ecc_stats.failed++;
>> + continue;
>> + }
>> + }
>> +
>> + stat = buffer & BS_CORRECTABLE_ERR_MSK;
>> + mtd->ecc_stats.corrected += stat;
>> +
>> + max_bitflips = max(max_bitflips, stat);
>> + }
>> +
>> + return max_bitflips;
>> +}
>> +
>> +/*
>> + * helper to perform the actual page read operation, used by ecc->read_page()
>> + * and ecc->read_oob()
>> + */
>> +static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf,
>> + u8 *oob_buf)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int i, r;
>> +
>> + /* queue cmd descs for each codeword */
>> + for (i = 0; i < ecc->steps; i++) {
>> + int data_size, oob_size;
>> +
>> + if (i == (ecc->steps - 1)) {
>> + data_size = ecc->size - ((ecc->steps - 1) << 2);
>> + oob_size = (ecc->steps << 2) + ecc->bytes;
>> + } else {
>> + data_size = this->cw_data;
>> + oob_size = ecc->bytes;
>> + }
>> +
>> + config_cw_read(this);
>> +
>> + if (data_buf)
>> + read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
>> +
>> + if (oob_buf)
>> + read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf,
>> + oob_size);
>> +
>> + if (data_buf)
>> + data_buf += data_size;
>> + if (oob_buf)
>> + oob_buf += oob_size;
>> + }
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failure to read page/oob\n");
>> +
>> + free_descs(this);
>> +
>> + return r;
>> +}
>> +
>> +/*
>> + * a helper that copies the last step/codeword of a page (containing free oob)
>> + * into our local buffer
>> + */
>> +static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page)
>> +{
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int size;
>> + int r;
>> +
>> + clear_read_regs(this);
>> +
>> + size = use_ecc ? this->cw_data : this->cw_size;
>> +
>> + /* prepare a clean read buffer */
>> + memset(this->data_buffer, 0xff, size);
>> +
>> + this->use_ecc = use_ecc;
>> + set_address(this, this->cw_size * (ecc->steps - 1), page);
>> + update_rw_regs(this, 1, true);
>> +
>> + config_cw_read(this);
>> +
>> + read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size);
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failed to copy last codeword\n");
>> +
>> + free_descs(this);
>> +
>> + return r;
>> +}
>> +
>> +/* implements ecc->read_page() */
>> +static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + uint8_t *buf, int oob_required, int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + u8 *data_buf, *oob_buf = NULL;
>> + bool erased_page;
>> + int r;
>> +
>> + data_buf = buf;
>> + oob_buf = oob_required ? chip->oob_poi : NULL;
>> +
>> + r = read_page_low(this, data_buf, oob_buf);
>> + if (r) {
>> + dev_err(this->dev, "failure to read page\n");
>> + return r;
>> + }
>> +
>> + erased_page = empty_page_fixup(this, data_buf);
>> +
>> + return parse_read_errors(this, erased_page);
>> +}
>> +
>> +/* implements ecc->read_oob() */
>> +static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
>> + int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int r;
>> +
>> + clear_read_regs(this);
>> +
>> + this->use_ecc = true;
>> + set_address(this, 0, page);
>> + update_rw_regs(this, ecc->steps, true);
>> +
>> + r = read_page_low(this, NULL, chip->oob_poi);
>> + if (r)
>> + dev_err(this->dev, "failure to read oob\n");
>> +
>> + return r;
>> +}
>> +
>> +/* implements ecc->read_oob_raw(), used to read the bad block marker flag */
>> +static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
>> + int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + uint8_t *oob = chip->oob_poi;
>> + int start, length;
>> + int r;
>> +
>> + /*
>> + * configure registers for a raw page read, the address is set to the
>> + * beginning of the last codeword, we don't care about reading ecc
>> + * portion of oob, just the free stuff
>> + */
>> + r = copy_last_cw(this, false, page);
>> + if (r)
>> + return r;
>> +
>> + /*
>> + * reading raw oob has 2 parts, first the bad block byte, then the
>> + * actual free oob region. perform a memcpy in two steps
>> + */
>> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
>> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
>> +
>> + memcpy(oob, this->data_buffer + start, length);
>> +
>> + oob += length;
>> +
>> + start = this->cw_data - (ecc->steps << 2) + 1;
>> + length = ecc->steps << 2;
>> +
>> + memcpy(oob, this->data_buffer + start, length);
>> +
>> + return 0;
>> +}
>> +
>> +/* implements ecc->write_page() */
>> +static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + const uint8_t *buf, int oob_required)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + u8 *data_buf, *oob_buf;
>> + int i, r = 0;
>> +
>> + clear_read_regs(this);
>> +
>> + data_buf = (u8 *) buf;
>> + oob_buf = chip->oob_poi;
>> +
>> + this->use_ecc = true;
>> + update_rw_regs(this, ecc->steps, false);
>> +
>> + for (i = 0; i < ecc->steps; i++) {
>> + int data_size, oob_size;
>> +
>> + if (i == (ecc->steps - 1)) {
>> + data_size = ecc->size - ((ecc->steps - 1) << 2);
>> + oob_size = (ecc->steps << 2) + ecc->bytes;
>> + } else {
>> + data_size = this->cw_data;
>> + oob_size = ecc->bytes;
>> + }
>> +
>> + config_cw_write_pre(this);
>> + write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size);
>> +
>> + /*
>> + * we don't really need to write anything to oob for the
>> + * first n - 1 codewords since these oob regions just
>> + * contain ecc that's written by the controller itself
>> + */
>> + if (i == (ecc->steps - 1))
>> + write_data_dma(this, FLASH_BUF_ACC + data_size,
>> + oob_buf, oob_size);
>> + config_cw_write_post(this);
>> +
>> + data_buf += data_size;
>> + oob_buf += oob_size;
>> + }
>> +
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev, "failure to write page\n");
>> +
>> + free_descs(this);
>> +
>> + return r;
>> +}
>> +
>> +/*
>> + * implements ecc->write_oob()
>> + *
>> + * the NAND controller cannot write only data or only oob within a codeword,
>> + * since ecc is calculated for the combined codeword. we first copy the
>> + * entire contents for the last codeword(data + oob), replace the old oob
>> + * with the new one in chip->oob_poi, and then write the entire codeword.
>> + * this read-copy-write operation results in a slight perormance loss.
>> + */
>> +static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>> + int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + uint8_t *oob = chip->oob_poi;
>> + int free_boff;
>> + int data_size, oob_size;
>> + int r, status = 0;
>> +
>> + r = copy_last_cw(this, true, page);
>> + if (r)
>> + return r;
>> +
>> + clear_read_regs(this);
>> +
>> + /* calculate the data and oob size for the last codeword/step */
>> + data_size = ecc->size - ((ecc->steps - 1) << 2);
>> + oob_size = (ecc->steps << 2) + ecc->bytes;
>> +
>> + /*
>> + * the location of spare data in the oob buffer, we could also use
>> + * ecc->layout.oobfree here
>> + */
>> + free_boff = ecc->bytes * (ecc->steps - 1);
>> +
>> + /* override new oob content to last codeword */
>> + memcpy(this->data_buffer + data_size, oob + free_boff, oob_size);
>> +
>> + this->use_ecc = true;
>> + set_address(this, this->cw_size * (ecc->steps - 1), page);
>> + update_rw_regs(this, 1, false);
>> +
>> + config_cw_write_pre(this);
>> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer,
>> + data_size + oob_size);
>> + config_cw_write_post(this);
>> +
>> + r = submit_descs(this);
>> +
>> + free_descs(this);
>> +
>> + if (r) {
>> + dev_err(this->dev, "failure to write oob\n");
>> + return -EIO;
>> + }
>> +
>> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
>> +
>> + status = chip->waitfunc(mtd, chip);
>> +
>> + return status & NAND_STATUS_FAIL ? -EIO : 0;
>> +}
>> +
>> +/* implements ecc->write_oob_raw(), used to write bad block marker flag */
>> +static int qcom_nandc_write_oob_raw(struct mtd_info *mtd,
>> + struct nand_chip *chip, int page)
>> +{
>> + struct qcom_nandc_data *this = chip->priv;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + uint8_t *oob = chip->oob_poi;
>> + int start, length;
>> + int r, status = 0;
>> +
>> + r = copy_last_cw(this, false, page);
>> + if (r)
>> + return r;
>> +
>> + clear_read_regs(this);
>> +
>> + /*
>> + * writing raw oob has 2 parts, first the bad block region, then the
>> + * actual free region
>> + */
>> + start = mtd->writesize - (this->cw_size * (ecc->steps - 1));
>> + length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1;
>> +
>> + memcpy(this->data_buffer + start, oob, length);
>> +
>> + oob += length;
>> +
>> + start = this->cw_data - (ecc->steps << 2) + 1;
>> + length = ecc->steps << 2;
>> +
>> + memcpy(this->data_buffer + start, oob, length);
>> +
>> + /* prepare write */
>> + this->use_ecc = false;
>> + set_address(this, this->cw_size * (ecc->steps - 1), page);
>> + update_rw_regs(this, 1, false);
>> +
>> + config_cw_write_pre(this);
>> + write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size);
>> + config_cw_write_post(this);
>> +
>> + r = submit_descs(this);
>> +
>> + free_descs(this);
>> +
>> + if (r) {
>> + dev_err(this->dev, "failure to write updated oob\n");
>> + return -EIO;
>> + }
>> +
>> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
>> +
>> + status = chip->waitfunc(mtd, chip);
>> +
>> + return status & NAND_STATUS_FAIL ? -EIO : 0;
>> +}
>> +
>> +/*
>> + * the three functions below implement chip->read_byte(), chip->read_buf()
>> + * and chip->write_buf() respectively. these aren't used for
>> + * reading/writing page data, they are used for smaller data like reading
>> + * id, status etc
>> + */
>> +static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>> + struct qcom_nandc_data *this = chip->priv;
>> + uint8_t *buf = this->data_buffer;
>> + uint8_t ret = 0x0;
>> +
>> + if (this->last_command == NAND_CMD_STATUS) {
>> + ret = this->status;
>> +
>> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
>> +
>> + return ret;
>> + }
>> +
>> + if (this->buf_start < this->buf_count)
>> + ret = buf[this->buf_start++];
>> +
>> + return ret;
>> +}
>> +
>> +static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>> + struct qcom_nandc_data *this = chip->priv;
>> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
>> +
>> + memcpy(buf, this->data_buffer + this->buf_start, real_len);
>> + this->buf_start += real_len;
>> +}
>> +
>> +static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
>> + int len)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>> + struct qcom_nandc_data *this = chip->priv;
>> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
>> +
>> + memcpy(this->data_buffer + this->buf_start, buf, real_len);
>> +
>> + this->buf_start += real_len;
>> +}
>> +
>> +/* we support only one external chip for now */
>> +static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>> + struct qcom_nandc_data *this = chip->priv;
>> +
>> + if (chipnr <= 0)
>> + return;
>> +
>> + dev_warn(this->dev, "invalid chip select\n");
>> +}
>> +
>> +/*
>> + * NAND controller page layout info
>> + *
>> + * |-----------------------| |---------------------------------|
>> + * | xx.......xx| | *********xx.......xx|
>> + * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
>> + * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
>> + * | xx.......xx| | *********xx.......xx|
>> + * |-----------------------| |---------------------------------|
>> + * codeword 1,2..n-1 codeword n
>> + * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
>> + *
>> + * n = number of codewords in the page
>> + * . = ECC bytes
>> + * * = spare bytes
>> + * x = unused/reserved bytes
>> + *
>> + * 2K page: n = 4, spare = 16 bytes
>> + * 4K page: n = 8, spare = 32 bytes
>> + * 8K page: n = 16, spare = 64 bytes
>> + *
>> + * the qcom nand controller operates at a sub page/codeword level. each
>> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
>> + * the number of ECC bytes vary based on the ECC strength and the bus width.
>> + *
>> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
>> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
>> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
>> + *
>> + * the layout described above is used by the controller when the ECC block is
>> + * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
>> + * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
>> + * layouts defined below doesn't consider the positions occupied by the reserved
>> + * bytes
>> + *
>> + * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
>> + * in the last codeword is the position of bad block marker. the bad block
>> + * marker cannot be accessed when ECC is enabled.
>> + *
>> + */
>> +
>> +/*
>> + * Layouts for different page sizes and ecc modes. We skip the eccpos field
>> + * since it isn't needed for this driver
>> + */
>> +
>> +/* 2K page, 4 bit ECC */
>> +static struct nand_ecclayout layout_oob_64 = {
>> + .eccbytes = 40,
>> + .oobfree = {
>> + { 30, 16 },
>> + },
>> +};
>> +
>> +/* 4K page, 4 bit ECC, 8/16 bit bus width */
>> +static struct nand_ecclayout layout_oob_128 = {
>> + .eccbytes = 80,
>> + .oobfree = {
>> + { 70, 32 },
>> + },
>> +};
>> +
>> +/* 4K page, 8 bit ECC, 8 bit bus width */
>> +static struct nand_ecclayout layout_oob_224_x8 = {
>> + .eccbytes = 104,
>> + .oobfree = {
>> + { 91, 32 },
>> + },
>> +};
>> +
>> +/* 4K page, 8 bit ECC, 16 bit bus width */
>> +static struct nand_ecclayout layout_oob_224_x16 = {
>> + .eccbytes = 112,
>> + .oobfree = {
>> + { 98, 32 },
>> + },
>> +};
>> +
>> +/* 8K page, 4 bit ECC, 8/16 bit bus width */
>> +static struct nand_ecclayout layout_oob_256 = {
>> + .eccbytes = 160,
>> + .oobfree = {
>> + { 151, 64 },
>> + },
>> +};
>> +
>> +/*
>> + * this is called before scan_ident, we do some minimal configurations so
>> + * that reading ID and ONFI params work
>> + */
>> +static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
>> +{
>> + /* kill onenand */
>> + nandc_write(this, SFLASHC_BURST_CFG, 0);
>> +
>> + /* enable ADM DMA */
>> + nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +
>> + /* save the original values of these registers */
>> + this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
>> + this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
>> +
>> + /* initial status value */
>> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
>> +}
>> +
>> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage;
>> + bool wide_bus;
>> +
>> + /* the nand controller fetches codewords/chunks of 512 bytes */
>> + cwperpage = mtd->writesize >> 9;
>> +
>> + ecc->strength = this->ecc_strength;
>> +
>> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
>> +
>> + if (ecc->strength >= 8) {
>> + /* 8 bit ECC defaults to BCH ECC on all platforms */
>> + ecc->bytes = wide_bus ? 14 : 13;
>> + } else {
>> + /*
>> + * if the controller supports BCH for 4 bit ECC, the controller
>> + * uses lesser bytes for ECC. If RS is used, the ECC bytes is
>> + * always 10 bytes
>> + */
>> + if (this->ecc_modes & ECC_BCH_4BIT)
>> + ecc->bytes = wide_bus ? 8 : 7;
>> + else
>> + ecc->bytes = 10;
>> + }
>> +
>> + /* each step consists of 512 bytes of data */
>> + ecc->size = NANDC_STEP_SIZE;
>> +
>> + ecc->read_page = qcom_nandc_read_page;
>> + ecc->read_oob = qcom_nandc_read_oob;
>> + ecc->write_page = qcom_nandc_write_page;
>> + ecc->write_oob = qcom_nandc_write_oob;
>> +
>> + /*
>> + * the bad block marker is readable only when we read the page with ECC
>> + * disabled. all the ops above run with ECC enabled. We need raw read
>> + * and write function for oob in order to access bad block marker.
>> + */
>> + ecc->read_oob_raw = qcom_nandc_read_oob_raw;
>> + ecc->write_oob_raw = qcom_nandc_write_oob_raw;
>> +
>> + switch (mtd->oobsize) {
>> + case 64:
>> + ecc->layout = &layout_oob_64;
>> + break;
>> + case 128:
>> + ecc->layout = &layout_oob_128;
>> + break;
>> + case 224:
>> + if (wide_bus)
>> + ecc->layout = &layout_oob_224_x16;
>> + else
>> + ecc->layout = &layout_oob_224_x8;
>> + break;
>> + case 256:
>> + ecc->layout = &layout_oob_256;
>> + break;
>> + default:
>> + dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
>> + mtd->oobsize);
>> + return -ENODEV;
>> + }
>> +
>> + ecc->mode = NAND_ECC_HW;
>> +
>> + /* enable ecc by default */
>> + this->use_ecc = true;
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = mtd->writesize / ecc->size;
>> + int spare_bytes, bad_block_byte;
>> + bool wide_bus;
>> + int ecc_mode = 0;
>> +
>> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
>> +
>> + if (ecc->strength >= 8) {
>> + this->cw_size = 532;
>> +
>> + spare_bytes = wide_bus ? 0 : 2;
>> +
>> + this->bch_enabled = true;
>> + ecc_mode = 1;
>> + } else {
>> + this->cw_size = 528;
>> +
>> + if (this->ecc_modes & ECC_BCH_4BIT) {
>> + spare_bytes = wide_bus ? 2 : 4;
>> +
>> + this->bch_enabled = true;
>> + ecc_mode = 0;
>> + } else {
>> + spare_bytes = wide_bus ? 0 : 1;
>> + }
>> + }
>> +
>> + /*
>> + * DATA_UD_BYTES varies based on whether the read/write command protects
>> + * spare data with ECC too. We protect spare data by default, so we set
>> + * it to main + spare data, which are 512 and 4 bytes respectively.
>> + */
>> + this->cw_data = 516;
>> +
>> + bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
>> +
>> + this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
>> + | this->cw_data << UD_SIZE_BYTES
>> + | 0 << DISABLE_STATUS_AFTER_WRITE
>> + | 5 << NUM_ADDR_CYCLES
>> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
>> + | 0 << STATUS_BFR_READ
>> + | 1 << SET_RD_MODE_AFTER_STATUS
>> + | spare_bytes << SPARE_SIZE_BYTES;
>> +
>> + this->cfg1 = 7 << NAND_RECOVERY_CYCLES
>> + | 0 << CS_ACTIVE_BSY
>> + | bad_block_byte << BAD_BLOCK_BYTE_NUM
>> + | 0 << BAD_BLOCK_IN_SPARE_AREA
>> + | 2 << WR_RD_BSY_GAP
>> + | wide_bus << WIDE_FLASH
>> + | this->bch_enabled << ENABLE_BCH_ECC;
>> +
>> + this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
>> + | this->cw_size << UD_SIZE_BYTES
>> + | 5 << NUM_ADDR_CYCLES
>> + | 0 << SPARE_SIZE_BYTES;
>> +
>> + this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
>> + | 0 << CS_ACTIVE_BSY
>> + | 17 << BAD_BLOCK_BYTE_NUM
>> + | 1 << BAD_BLOCK_IN_SPARE_AREA
>> + | 2 << WR_RD_BSY_GAP
>> + | wide_bus << WIDE_FLASH
>> + | 1 << DEV0_CFG1_ECC_DISABLE;
>> +
>> + this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
>> + | 0 << ECC_SW_RESET
>> + | this->cw_data << ECC_NUM_DATA_BYTES
>> + | 1 << ECC_FORCE_CLK_OPEN
>> + | ecc_mode << ECC_MODE
>> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
>> +
>> + this->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> +
>> + this->clrflashstatus = FS_READY_BSY_N;
>> + this->clrreadstatus = 0xc0;
>> +
>> + dev_dbg(this->dev,
>> + "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
>> + this->cfg0, this->cfg1, this->ecc_buf_cfg,
>> + this->ecc_bch_cfg, this->cw_size, this->cw_data,
>> + ecc->strength, ecc->bytes, cwperpage);
>> +}
>> +
>> +static int qcom_nandc_alloc(struct qcom_nandc_data *this)
>> +{
>> + int r;
>> +
>> + r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
>> + if (r) {
>> + dev_err(this->dev, "failed to set DMA mask\n");
>> + return r;
>> + }
>> +
>> + /*
>> + * we use the internal buffer for reading ONFI params, reading small
>> + * data like ID and status, and preforming read-copy-write operations
>> + * when writing to a codeword partially. 532 is the maximum possible
>> + * size of a codeword for our nand controller
>> + */
>> + this->buf_size = 532;
>> +
>> + this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
>> + if (!this->data_buffer)
>> + return -ENOMEM;
>> +
>> + this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL);
>> + if (!this->regs)
>> + return -ENOMEM;
>> +
>> + this->reg_read_buf = devm_kzalloc(this->dev,
>> + MAX_REG_RD * sizeof(*this->reg_read_buf),
>> + GFP_KERNEL);
>> + if (!this->reg_read_buf)
>> + return -ENOMEM;
>> +
>> + INIT_LIST_HEAD(&this->list);
>> +
>> + this->chan = dma_request_slave_channel(this->dev, "rxtx");
>> + if (!this->chan) {
>> + dev_err(this->dev, "failed to request slave channel\n");
>> + return -ENODEV;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
>> +{
>> + dma_release_channel(this->chan);
>> +}
>> +
>> +static int qcom_nandc_init(struct qcom_nandc_data *this)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>> + struct device_node *np = this->dev->of_node;
>> + struct mtd_part_parser_data ppdata = { .of_node = np };
>> + int r;
>> +
>> + mtd->priv = chip;
>> + mtd->name = "qcom-nandc";
>> + mtd->owner = THIS_MODULE;
>> +
>> + chip->priv = this;
>> +
>> + chip->cmdfunc = qcom_nandc_command;
>> + chip->select_chip = qcom_nandc_select_chip;
>> + chip->read_byte = qcom_nandc_read_byte;
>> + chip->read_buf = qcom_nandc_read_buf;
>> + chip->write_buf = qcom_nandc_write_buf;
>> +
>> + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
>> + if (this->bus_width == 16)
>> + chip->options |= NAND_BUSWIDTH_16;
>> +
>> + chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
>> + if (of_get_nand_on_flash_bbt(np))
>
> Can you use nand_dt_init()? i.e., fill out chip->flash_node and let
> nand_scan_ident() take care of most of the common DT parsing. You can
> then clean up afterward with something like:
>
> if (chip->bbt_options & NAND_BBT_USE_FLASH)
> chip->bbt_options |= NAND_BBT_NO_OOB;
>
> Similar for the bus width, ECC strength, and ECC step size parameters.
Okay. I was a bit unsure about this.
The step size is fixed (512 bytes) for the controller hardware, but the
hardware supports 4 bit and 8 bit ECC. I didn't use nand_dt_init()
because it makes it necessary to mention both strength and step size
parameters.
Is it wrong to specify only what strength to use for the flash chip in
DT and not specify step size?
Archit
>
>> + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
>> +
>> + qcom_nandc_pre_init(this);
>> +
>> + r = nand_scan_ident(mtd, 1, NULL);
>> + if (r)
>> + return r;
>> +
>> + r = qcom_nandc_ecc_init(this);
>> + if (r)
>> + return r;
>> +
>> + qcom_nandc_hw_post_init(this);
>> +
>> + r = nand_scan_tail(mtd);
>> + if (r)
>> + return r;
>> +
>> + return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
>> +}
>> +
>> +static int qcom_nandc_parse_dt(struct platform_device *pdev)
>> +{
>> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
>> + struct device_node *np = this->dev->of_node;
>> + int r;
>> +
>> + this->ecc_strength = of_get_nand_ecc_strength(np);
>> + if (this->ecc_strength < 0) {
>> + dev_warn(this->dev,
>> + "incorrect ecc strength, setting to 4 bits/step\n");
>> + this->ecc_strength = 4;
>> + }
>> +
>> + this->bus_width = of_get_nand_bus_width(np);
>> + if (this->bus_width < 0) {
>> + dev_warn(this->dev, "incorrect bus width, setting to 8\n");
>> + this->bus_width = 8;
>> + }
>> +
>> + r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
>> + if (r) {
>> + dev_err(this->dev, "command CRCI unspecified\n");
>> + return r;
>> + }
>> +
>> + r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
>> + if (r) {
>> + dev_err(this->dev, "data CRCI unspecified\n");
>> + return r;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int qcom_nandc_probe(struct platform_device *pdev)
>> +{
>> + struct qcom_nandc_data *this;
>> + const void *dev_data;
>> + int r;
>> +
>> + this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
>> + if (!this)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, this);
>> +
>> + this->pdev = pdev;
>> + this->dev = &pdev->dev;
>> +
>> + dev_data = of_device_get_match_data(&pdev->dev);
>> + if (!dev_data) {
>> + dev_err(&pdev->dev, "failed to get device data\n");
>> + return -ENODEV;
>> + }
>> +
>> + this->ecc_modes = (unsigned long)dev_data;
>> +
>> + this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + this->base = devm_ioremap_resource(&pdev->dev, this->res);
>> + if (IS_ERR(this->base))
>> + return PTR_ERR(this->base);
>> +
>> + this->core_clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(this->core_clk))
>> + return PTR_ERR(this->core_clk);
>> +
>> + this->aon_clk = devm_clk_get(&pdev->dev, "aon");
>> + if (IS_ERR(this->aon_clk))
>> + return PTR_ERR(this->aon_clk);
>> +
>> + r = qcom_nandc_parse_dt(pdev);
>> + if (r)
>> + return r;
>> +
>> + r = qcom_nandc_alloc(this);
>> + if (r)
>> + return r;
>> +
>> + r = clk_prepare_enable(this->core_clk);
>> + if (r)
>> + goto err_core_clk;
>> +
>> + r = clk_prepare_enable(this->aon_clk);
>> + if (r)
>> + goto err_aon_clk;
>> +
>> + r = qcom_nandc_init(this);
>> + if (r)
>> + goto err_init;
>> +
>> + return 0;
>> +
>> +err_init:
>> + clk_disable_unprepare(this->aon_clk);
>> +err_aon_clk:
>> + clk_disable_unprepare(this->core_clk);
>> +err_core_clk:
>> + qcom_nandc_unalloc(this);
>> +
>> + return r;
>> +}
>> +
>> +static int qcom_nandc_remove(struct platform_device *pdev)
>> +{
>> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
>> +
>> + qcom_nandc_unalloc(this);
>> +
>> + clk_disable_unprepare(this->aon_clk);
>> + clk_disable_unprepare(this->core_clk);
>> +
>> + return 0;
>> +}
>> +
>> +#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
>> +
>> +/*
>> + * data will hold a struct pointer containing more differences once we support
>> + * more IPs
>> + */
>> +static const struct of_device_id qcom_nandc_of_match[] = {
>> + { .compatible = "qcom,ebi2-nandc",
>> + .data = (void *) EBI2_NANDC_ECC_MODES,
>> + },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
>> +
>> +static struct platform_driver qcom_nandc_driver = {
>> + .driver = {
>> + .name = "qcom-nandc",
>> + .of_match_table = qcom_nandc_of_match,
>> + },
>> + .probe = qcom_nandc_probe,
>> + .remove = qcom_nandc_remove,
>> +};
>> +module_platform_driver(qcom_nandc_driver);
>> +
>> +MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
>> +MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
>> +MODULE_LICENSE("GPL v2");
>
> Brian
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-10-05 6:51 ` Archit Taneja
@ 2015-10-06 9:17 ` Brian Norris
2015-10-07 4:11 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Brian Norris @ 2015-10-06 9:17 UTC (permalink / raw)
To: Archit Taneja
Cc: Boris Brezillon, dehrenberg, linux-arm-msm, cernekee, sboyd,
linux-kernel, linux-mtd, agross
Hi Archit,
On Mon, Oct 05, 2015 at 12:21:54PM +0530, Archit Taneja wrote:
> On 10/02/2015 08:35 AM, Brian Norris wrote:
> >On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
> >>The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
> >>MDM9x15 series.
> >>
> >>It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
> >>and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
> >>broader interface for external slow peripheral devices such as LCD and
> >>NAND/NOR flash memory or SRAM like interfaces.
> >>
> >>We add support for the NAND controller found within EBI2. For the SoCs
> >>of our interest, we only use the NAND controller within EBI2. Therefore,
> >>it's safe for us to assume that the NAND controller is a standalone block
> >>within the SoC.
> >>
> >>The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
> >>flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
> >>16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
> >>and spare data. The controller contains an internal 512 byte page buffer
> >>to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
> >>for register read/write and data transfers. The controller performs page
> >>reads and writes at a codeword/step level of 512 bytes. It can support up
> >>to 2 external chips of different configurations.
> >>
> >>The driver prepares register read and write configuration descriptors for
> >>each codeword, followed by data descriptors to read or write data from the
> >>controller's internal buffer. It uses a single ADM DMA channel that we get
> >>via dmaengine API. The controller requires 2 ADM CRCIs for command and
> >>data flow control. These are passed via DT.
> >>
> >>The ecc layout used by the controller is syndrome like, but we can't use
> >>the standard syndrome ecc ops because of several reasons. First, the amount
> >>of data bytes covered by ecc isn't same in each step. Second, writing to
> >>free oob space requires us writing to the entire step in which the oob
> >>lies. This forces us to create our own ecc ops.
> >>
> >>One more difference is how the controller accesses the bad block marker.
> >>The controller ignores reading the marker when ECC is enabled. ECC needs
> >>to be explicity disabled to read or write to the bad block marker. For
> >>this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
> >>read the factory provided bad block markers.
> >>
> >>v4:
> >>- Shrink submit_descs
> >>- add desc list node at the end of dma_prep_desc
> >>- Endianness and warning fixes
> >>
> >>Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> >
> >Where does this sign-off come into play? It's not grouped with yours.
> >Did Stephen have something to do with v4 only? Also, we typically trim
> >the change log from the commit message (and place it below the '---' to
> >do this automatically). Or did you intend for these changelogs to stay
> >in the git history? I suppose it's not really harmful to keep it in if
> >you'd like...
>
> He'd corrected a piece of the code by sharing a patch with with me. You
> can place his sign-off once you and Stephen accept the final patch
> revision.
OK, thanks for the clarification.
> I don't have a problem with discarding the changelogs for the git
> history. I can incorporate some of the major changes in the main
> commit message above.
Whatever works for you. I'd like to incorporate any useful info in the
commit message, but changelog is sometimes noise.
> >>v3:
> >>- Refactor dma functions for maximum reuse
> >>- Use dma_slave_confing on stack
> >>- optimize and clean upempty_page_fixup using memchr_inv
> >>- ensure portability with dma register reads using le32_* funcs
> >>- use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
> >>- fix handling of return values of dmaengine funcs
> >>- constify wherever possible
> >>- Remove dependency on ADM DMA in Kconfig
> >>- Misc fixes and clean ups
> >>
> >>v2:
> >>- Use new BBT flag that allows us to read BBM in raw mode
> >>- reduce memcpy-s in the driver
> >>- some refactor and clean ups because of above changes
> >>
> >>Reviewed-by: Andy Gross <agross@codeaurora.org>
> >>Signed-off-by: Archit Taneja <architt@codeaurora.org>
> >
> >Has this driver been tested with drivers/mtd/tests/? Which ones? I'm
> >particularly interested in oobtest, since you attempted to handle both
> >ECC and raw OOB.
>
> Yes. All the tests passed. Although, I couldn't figure out from the
> oobtest console output if it tested both the ECC and RAW oob.
No, it doesn't actually use raw OOB (which is possibly a flaw; we should
improve the test sometime). It just uses the auto-place mode, which is
more useful for something like JFFS2. I just wanted to make sure the
test passed, since it looks like you did put a little effort on OOB
support.
> >>---
[...]
> >>+/*
> >>+ * @cmd_crci: ADM DMA CRCI for command flow control
> >>+ * @data_crci: ADM DMA CRCI for data flow control
> >>+ * @list: DMA descriptor list (list of desc_infos)
> >>+ * @data_buffer: our local DMA buffer for page read/writes,
> >>+ * used when we can't use the buffer provided
> >>+ * by upper layers directly
> >>+ * @buf_size/count/start: markers for chip->read_buf/write_buf functions
> >>+ * @reg_read_buf: buffer for reading register data via DMA
> >>+ * @reg_read_pos: marker for data read in reg_read_buf
> >>+ * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
> >>+ * ecc/non-ecc mode for the current nand flash
> >>+ * device
> >>+ * @regs: a contiguous chunk of memory for DMA register
> >>+ * writes
> >>+ * @ecc_strength: 4 bit or 8 bit ecc, received via DT
> >>+ * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
> >>+ * @ecc_modes: supported ECC modes by the current controller,
> >>+ * initialized via DT match data
> >>+ * @cw_size: the number of bytes in a single step/codeword
> >>+ * of a page, consisting of all data, ecc, spare
> >>+ * and reserved bytes
> >>+ * @cw_data: the number of bytes within a codeword protected
> >>+ * by ECC
> >>+ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
> >>+ * @status: value to be returned if NAND_CMD_STATUS command
> >>+ * is executed
> >>+ */
> >>+struct qcom_nandc_data {
> >>+ struct platform_device *pdev;
> >
> >This field is only set once, but unused?
>
> It is used in the driver remove (qcom_nandc_remove) to get a pointer to
> this data struct.
Are you sure? Doesn't look true to me. Maybe your driver has changed
over time?
> >
> >And it (and several others) aren't documented above.
>
> The comments weren't meant to be a part of kernel docs. So, I left out
> some of the more obvious params.
Hmm, well it's probably nicer if you're consistent. pdev isn't so
important, but some of the others might be worth listing.
> >>+ struct device *dev;
> >>+
> >>+ void __iomem *base;
> >>+ struct resource *res;
> >>+
> >>+ struct clk *core_clk;
> >>+ struct clk *aon_clk;
> >>+
> >>+ /* DMA stuff */
> >>+ struct dma_chan *chan;
> >>+ struct dma_slave_config slave_conf;
> >>+ unsigned int cmd_crci;
> >>+ unsigned int data_crci;
> >>+ struct list_head list;
> >>+
> >>+ /* MTD stuff */
> >>+ struct nand_chip chip;
> >>+ struct mtd_info mtd;
> >>+
> >>+ /* local data buffer and markers */
> >>+ u8 *data_buffer;
> >>+ int buf_size;
> >>+ int buf_count;
> >>+ int buf_start;
> >>+
> >>+ /* local buffer to read back registers */
> >>+ __le32 *reg_read_buf;
> >>+ int reg_read_pos;
> >>+
> >>+ /* required configs */
> >>+ u32 cfg0, cfg1;
> >>+ u32 cfg0_raw, cfg1_raw;
> >>+ u32 ecc_buf_cfg;
> >>+ u32 ecc_bch_cfg;
> >>+ u32 clrflashstatus;
> >>+ u32 clrreadstatus;
> >>+ u32 sflashc_burst_cfg;
> >>+ u32 cmd1, vld;
> >>+
> >>+ /* register state */
> >>+ struct nandc_regs *regs;
> >>+
> >>+ /* things we get from DT */
> >>+ int ecc_strength;
> >>+ int bus_width;
> >>+
> >>+ u32 ecc_modes;
> >>+
> >>+ /* misc params */
> >>+ int cw_size;
> >>+ int cw_data;
> >>+ bool use_ecc;
> >>+ bool bch_enabled;
> >>+ u8 status;
> >>+ int last_command;
> >>+};
> >>+
[...]
> >>+/*
> >>+ * when using RS ECC, the NAND controller flags an error when reading an
> >>+ * erased page. however, there are special characters at certain offsets when
> >>+ * we read the erased page. we check here if the page is really empty. if so,
> >>+ * we replace the magic characters with 0xffs
> >>+ */
> >
> >What's the nature of this erased page flagging? Does it only detect
> >all-0xff pages? What about if the erased page experiences any bitflips?
> >A lot of drivers have been attempting to handle that case too (which is
> >becoming more common on modern MLC, and even on SLC), and most of the
> >times they do it poorly.
>
> The hardware can raise an 'erased' flag per step, when all the bytes in
> the step are 0xff. The code below would consider the page as
> 'not erased' if any step doesn't report an erased flag.
OK, so (if the HW is implemented as you say) that looks like a correct
test. But it's not sufficient for some modern cases. You might want to
consider whether you need to adopt some additional checks after your
driver gets merged.
> >See nand_check_erased_ecc_chunk() (in linux-next.git) as an example of a
> >brute force helper to assist for cases where HW ECC is not sufficient.
>
> I'll have a look. Thanks.
>
> >
[...]
> >>+static int qcom_nandc_init(struct qcom_nandc_data *this)
> >>+{
> >>+ struct mtd_info *mtd = &this->mtd;
> >>+ struct nand_chip *chip = &this->chip;
> >>+ struct device_node *np = this->dev->of_node;
> >>+ struct mtd_part_parser_data ppdata = { .of_node = np };
> >>+ int r;
> >>+
> >>+ mtd->priv = chip;
> >>+ mtd->name = "qcom-nandc";
> >>+ mtd->owner = THIS_MODULE;
> >>+
> >>+ chip->priv = this;
> >>+
> >>+ chip->cmdfunc = qcom_nandc_command;
> >>+ chip->select_chip = qcom_nandc_select_chip;
> >>+ chip->read_byte = qcom_nandc_read_byte;
> >>+ chip->read_buf = qcom_nandc_read_buf;
> >>+ chip->write_buf = qcom_nandc_write_buf;
> >>+
> >>+ chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
> >>+ if (this->bus_width == 16)
> >>+ chip->options |= NAND_BUSWIDTH_16;
> >>+
> >>+ chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
> >>+ if (of_get_nand_on_flash_bbt(np))
> >
> >Can you use nand_dt_init()? i.e., fill out chip->flash_node and let
> >nand_scan_ident() take care of most of the common DT parsing. You can
> >then clean up afterward with something like:
> >
> > if (chip->bbt_options & NAND_BBT_USE_FLASH)
> > chip->bbt_options |= NAND_BBT_NO_OOB;
> >
> >Similar for the bus width, ECC strength, and ECC step size parameters.
>
> Okay. I was a bit unsure about this.
>
> The step size is fixed (512 bytes) for the controller hardware, but the
> hardware supports 4 bit and 8 bit ECC. I didn't use nand_dt_init()
> because it makes it necessary to mention both strength and step size
> parameters.
>
> Is it wrong to specify only what strength to use for the flash chip in
> DT and not specify step size?
There are certainly cases where it can be sufficient to specify just a
strength (e.g., when your HW ECC only supports a single sector size),
but there have been some problems already with other drivers that
assumed at first they only need to support a single sector size, then
they later support new modes (either through new chip revisions, or
simply added driver support for features that were previously unused).
So we kinda decided to require both parameters. In fact, a strength by
itself is not really very descriptive; an ECC algorithm is (roughly)
defined by both the number or errors it can correct *and* the region
over which it acts. So a proper hardware description should probably
cover both.
Long story short: yes, please include both properties (in your DT
binding; or point to nand.txt -- and in your DTS source).
Brian
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-10-06 9:17 ` Brian Norris
@ 2015-10-07 4:11 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-10-07 4:11 UTC (permalink / raw)
To: Brian Norris
Cc: Boris Brezillon, dehrenberg, linux-arm-msm, cernekee, sboyd,
linux-kernel, linux-mtd, agross
Hi,
On 10/06/2015 02:47 PM, Brian Norris wrote:
> Hi Archit,
>
> On Mon, Oct 05, 2015 at 12:21:54PM +0530, Archit Taneja wrote:
>> On 10/02/2015 08:35 AM, Brian Norris wrote:
>>> On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
>>>> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
>>>> MDM9x15 series.
>>>>
>>>> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
>>>> and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
>>>> broader interface for external slow peripheral devices such as LCD and
>>>> NAND/NOR flash memory or SRAM like interfaces.
>>>>
>>>> We add support for the NAND controller found within EBI2. For the SoCs
>>>> of our interest, we only use the NAND controller within EBI2. Therefore,
>>>> it's safe for us to assume that the NAND controller is a standalone block
>>>> within the SoC.
>>>>
>>>> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
>>>> flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
>>>> 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
>>>> and spare data. The controller contains an internal 512 byte page buffer
>>>> to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
>>>> for register read/write and data transfers. The controller performs page
>>>> reads and writes at a codeword/step level of 512 bytes. It can support up
>>>> to 2 external chips of different configurations.
>>>>
>>>> The driver prepares register read and write configuration descriptors for
>>>> each codeword, followed by data descriptors to read or write data from the
>>>> controller's internal buffer. It uses a single ADM DMA channel that we get
>>>> via dmaengine API. The controller requires 2 ADM CRCIs for command and
>>>> data flow control. These are passed via DT.
>>>>
>>>> The ecc layout used by the controller is syndrome like, but we can't use
>>>> the standard syndrome ecc ops because of several reasons. First, the amount
>>>> of data bytes covered by ecc isn't same in each step. Second, writing to
>>>> free oob space requires us writing to the entire step in which the oob
>>>> lies. This forces us to create our own ecc ops.
>>>>
>>>> One more difference is how the controller accesses the bad block marker.
>>>> The controller ignores reading the marker when ECC is enabled. ECC needs
>>>> to be explicity disabled to read or write to the bad block marker. For
>>>> this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
>>>> read the factory provided bad block markers.
>>>>
>>>> v4:
>>>> - Shrink submit_descs
>>>> - add desc list node at the end of dma_prep_desc
>>>> - Endianness and warning fixes
>>>>
>>>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>>>
>>> Where does this sign-off come into play? It's not grouped with yours.
>>> Did Stephen have something to do with v4 only? Also, we typically trim
>>> the change log from the commit message (and place it below the '---' to
>>> do this automatically). Or did you intend for these changelogs to stay
>>> in the git history? I suppose it's not really harmful to keep it in if
>>> you'd like...
>>
>> He'd corrected a piece of the code by sharing a patch with with me. You
>> can place his sign-off once you and Stephen accept the final patch
>> revision.
>
> OK, thanks for the clarification.
>
>> I don't have a problem with discarding the changelogs for the git
>> history. I can incorporate some of the major changes in the main
>> commit message above.
>
> Whatever works for you. I'd like to incorporate any useful info in the
> commit message, but changelog is sometimes noise.
>
>>>> v3:
>>>> - Refactor dma functions for maximum reuse
>>>> - Use dma_slave_confing on stack
>>>> - optimize and clean upempty_page_fixup using memchr_inv
>>>> - ensure portability with dma register reads using le32_* funcs
>>>> - use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
>>>> - fix handling of return values of dmaengine funcs
>>>> - constify wherever possible
>>>> - Remove dependency on ADM DMA in Kconfig
>>>> - Misc fixes and clean ups
>>>>
>>>> v2:
>>>> - Use new BBT flag that allows us to read BBM in raw mode
>>>> - reduce memcpy-s in the driver
>>>> - some refactor and clean ups because of above changes
>>>>
>>>> Reviewed-by: Andy Gross <agross@codeaurora.org>
>>>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>>>
>>> Has this driver been tested with drivers/mtd/tests/? Which ones? I'm
>>> particularly interested in oobtest, since you attempted to handle both
>>> ECC and raw OOB.
>>
>> Yes. All the tests passed. Although, I couldn't figure out from the
>> oobtest console output if it tested both the ECC and RAW oob.
>
> No, it doesn't actually use raw OOB (which is possibly a flaw; we should
> improve the test sometime). It just uses the auto-place mode, which is
> more useful for something like JFFS2. I just wanted to make sure the
> test passed, since it looks like you did put a little effort on OOB
> support.
>
>>>> ---
> [...]
>>>> +/*
>>>> + * @cmd_crci: ADM DMA CRCI for command flow control
>>>> + * @data_crci: ADM DMA CRCI for data flow control
>>>> + * @list: DMA descriptor list (list of desc_infos)
>>>> + * @data_buffer: our local DMA buffer for page read/writes,
>>>> + * used when we can't use the buffer provided
>>>> + * by upper layers directly
>>>> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
>>>> + * @reg_read_buf: buffer for reading register data via DMA
>>>> + * @reg_read_pos: marker for data read in reg_read_buf
>>>> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
>>>> + * ecc/non-ecc mode for the current nand flash
>>>> + * device
>>>> + * @regs: a contiguous chunk of memory for DMA register
>>>> + * writes
>>>> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
>>>> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
>>>> + * @ecc_modes: supported ECC modes by the current controller,
>>>> + * initialized via DT match data
>>>> + * @cw_size: the number of bytes in a single step/codeword
>>>> + * of a page, consisting of all data, ecc, spare
>>>> + * and reserved bytes
>>>> + * @cw_data: the number of bytes within a codeword protected
>>>> + * by ECC
>>>> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
>>>> + * @status: value to be returned if NAND_CMD_STATUS command
>>>> + * is executed
>>>> + */
>>>> +struct qcom_nandc_data {
>>>> + struct platform_device *pdev;
>>>
>>> This field is only set once, but unused?
>>
>> It is used in the driver remove (qcom_nandc_remove) to get a pointer to
>> this data struct.
>
> Are you sure? Doesn't look true to me. Maybe your driver has changed
> over time?
I'm sorry, I overlooked. It isn't needed there. I'll get rid of it, and
other members if I find any more.
>
>>>
>>> And it (and several others) aren't documented above.
>>
>> The comments weren't meant to be a part of kernel docs. So, I left out
>> some of the more obvious params.
>
> Hmm, well it's probably nicer if you're consistent. pdev isn't so
> important, but some of the others might be worth listing.
Sure, I'll do that.
>
>>>> + struct device *dev;
>>>> +
>>>> + void __iomem *base;
>>>> + struct resource *res;
>>>> +
>>>> + struct clk *core_clk;
>>>> + struct clk *aon_clk;
>>>> +
>>>> + /* DMA stuff */
>>>> + struct dma_chan *chan;
>>>> + struct dma_slave_config slave_conf;
>>>> + unsigned int cmd_crci;
>>>> + unsigned int data_crci;
>>>> + struct list_head list;
>>>> +
>>>> + /* MTD stuff */
>>>> + struct nand_chip chip;
>>>> + struct mtd_info mtd;
>>>> +
>>>> + /* local data buffer and markers */
>>>> + u8 *data_buffer;
>>>> + int buf_size;
>>>> + int buf_count;
>>>> + int buf_start;
>>>> +
>>>> + /* local buffer to read back registers */
>>>> + __le32 *reg_read_buf;
>>>> + int reg_read_pos;
>>>> +
>>>> + /* required configs */
>>>> + u32 cfg0, cfg1;
>>>> + u32 cfg0_raw, cfg1_raw;
>>>> + u32 ecc_buf_cfg;
>>>> + u32 ecc_bch_cfg;
>>>> + u32 clrflashstatus;
>>>> + u32 clrreadstatus;
>>>> + u32 sflashc_burst_cfg;
>>>> + u32 cmd1, vld;
>>>> +
>>>> + /* register state */
>>>> + struct nandc_regs *regs;
>>>> +
>>>> + /* things we get from DT */
>>>> + int ecc_strength;
>>>> + int bus_width;
>>>> +
>>>> + u32 ecc_modes;
>>>> +
>>>> + /* misc params */
>>>> + int cw_size;
>>>> + int cw_data;
>>>> + bool use_ecc;
>>>> + bool bch_enabled;
>>>> + u8 status;
>>>> + int last_command;
>>>> +};
>>>> +
> [...]
>>>> +/*
>>>> + * when using RS ECC, the NAND controller flags an error when reading an
>>>> + * erased page. however, there are special characters at certain offsets when
>>>> + * we read the erased page. we check here if the page is really empty. if so,
>>>> + * we replace the magic characters with 0xffs
>>>> + */
>>>
>>> What's the nature of this erased page flagging? Does it only detect
>>> all-0xff pages? What about if the erased page experiences any bitflips?
>>> A lot of drivers have been attempting to handle that case too (which is
>>> becoming more common on modern MLC, and even on SLC), and most of the
>>> times they do it poorly.
>>
>> The hardware can raise an 'erased' flag per step, when all the bytes in
>> the step are 0xff. The code below would consider the page as
>> 'not erased' if any step doesn't report an erased flag.
>
> OK, so (if the HW is implemented as you say) that looks like a correct
> test. But it's not sufficient for some modern cases. You might want to
> consider whether you need to adopt some additional checks after your
> driver gets merged.
Sure. I can do that. Thanks.
>
>>> See nand_check_erased_ecc_chunk() (in linux-next.git) as an example of a
>>> brute force helper to assist for cases where HW ECC is not sufficient.
>>
>> I'll have a look. Thanks.
>>
>>>
> [...]
>>>> +static int qcom_nandc_init(struct qcom_nandc_data *this)
>>>> +{
>>>> + struct mtd_info *mtd = &this->mtd;
>>>> + struct nand_chip *chip = &this->chip;
>>>> + struct device_node *np = this->dev->of_node;
>>>> + struct mtd_part_parser_data ppdata = { .of_node = np };
>>>> + int r;
>>>> +
>>>> + mtd->priv = chip;
>>>> + mtd->name = "qcom-nandc";
>>>> + mtd->owner = THIS_MODULE;
>>>> +
>>>> + chip->priv = this;
>>>> +
>>>> + chip->cmdfunc = qcom_nandc_command;
>>>> + chip->select_chip = qcom_nandc_select_chip;
>>>> + chip->read_byte = qcom_nandc_read_byte;
>>>> + chip->read_buf = qcom_nandc_read_buf;
>>>> + chip->write_buf = qcom_nandc_write_buf;
>>>> +
>>>> + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
>>>> + if (this->bus_width == 16)
>>>> + chip->options |= NAND_BUSWIDTH_16;
>>>> +
>>>> + chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
>>>> + if (of_get_nand_on_flash_bbt(np))
>>>
>>> Can you use nand_dt_init()? i.e., fill out chip->flash_node and let
>>> nand_scan_ident() take care of most of the common DT parsing. You can
>>> then clean up afterward with something like:
>>>
>>> if (chip->bbt_options & NAND_BBT_USE_FLASH)
>>> chip->bbt_options |= NAND_BBT_NO_OOB;
>>>
>>> Similar for the bus width, ECC strength, and ECC step size parameters.
>>
>> Okay. I was a bit unsure about this.
>>
>> The step size is fixed (512 bytes) for the controller hardware, but the
>> hardware supports 4 bit and 8 bit ECC. I didn't use nand_dt_init()
>> because it makes it necessary to mention both strength and step size
>> parameters.
>>
>> Is it wrong to specify only what strength to use for the flash chip in
>> DT and not specify step size?
>
> There are certainly cases where it can be sufficient to specify just a
> strength (e.g., when your HW ECC only supports a single sector size),
> but there have been some problems already with other drivers that
> assumed at first they only need to support a single sector size, then
> they later support new modes (either through new chip revisions, or
> simply added driver support for features that were previously unused).
> So we kinda decided to require both parameters. In fact, a strength by
> itself is not really very descriptive; an ECC algorithm is (roughly)
> defined by both the number or errors it can correct *and* the region
> over which it acts. So a proper hardware description should probably
> cover both.
>
> Long story short: yes, please include both properties (in your DT
> binding; or point to nand.txt -- and in your DTS source).
Okay, that makes sense. I'll do the nand_dt_init conversion, and make
sure the change is reflected in the binding docs.
Thanks,
Archit
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-10-02 6:27 ` Boris Brezillon
@ 2015-10-11 20:03 ` Brian Norris
2015-11-10 5:13 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Brian Norris @ 2015-10-11 20:03 UTC (permalink / raw)
To: Boris Brezillon
Cc: Archit Taneja, dehrenberg, linux-arm-msm, cernekee, sboyd,
linux-kernel, linux-mtd, agross, Andrea Scian
Hi Boris,
On Fri, Oct 02, 2015 at 08:27:38AM +0200, Boris Brezillon wrote:
> Brian, Archit,
>
> On Thu, 1 Oct 2015 19:44:34 -0700
> Brian Norris <computersforpeace@gmail.com> wrote:
>
> > On Wed, Aug 19, 2015 at 10:19:02AM +0530, Archit Taneja wrote:
> > > Some controllers can access the factory bad block marker from OOB only
> > > when they read it in raw mode. When ECC is enabled, these controllers
> > > discard reading/writing bad block markers, preventing access to them
> > > altogether.
> > >
> > > The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
> > > This results in the nand driver's ecc->read_oob() op to be called, which
> > > works with ECC enabled.
> > >
> > > Create a new BBT option flag that tells nand_bbt to force the mode to
> > > MTD_OPS_RAW. This would result in the correct op being called for the
> > > underlying nand controller driver.
>
> Actually I have the same kind of patch in my local tree (for a
> different reason though: the HW randomizer can mess up with the BBM
> byte if it's not disabled, and the only way to disable it in my current
> implementation is to switch to raw mode).
>
> >
> > MTD_OPS_RAW is probably the best way to do this, and we should switch
> > back to it for all users (rather than a new flag).
>
> I'm fine with this solution, but will that be acceptable for everybody?
> I mean, some NAND controllers are able to protect some OOB bytes, and
> the BBM might fall in those OOB bytes. In this case, shouldn't we rely
> on the ECC protection instead of reading the OOB in raw mode?
I think ECC is kind of misused a bit here. It's not really meant for
protecting BBMs, and it's also really not sufficient, esp. given
bitflips in erased areas.
> > But to do this, we
> > need to fix up some things. Particularly, we need to extend
> > 'badblockbits' support so that it is applied consistently in all places
> > (I recall there is one code path in which bad block scanning does take
> > this into account, and one that doesn't.)
>
> Yes, IIRC Andrea has posted a patch addressing that problem [1].
> Another problem I see is that badblockbits is currently assigned a
> fixed value by the NAND controller driver (or a default value of 8).
> There's no specific logic to correlate it to the required ECC strength.
> IMO, we should not let each NAND controller driver decide what is the
> appropriate value for each chip but rather implement the logic in
> nand_base.c based on ecc->strength and ecc->size, and IIRC this was
> the question Andrea asked when he posted his proposal.
>
> >
> > About badblockbits: it allows us to do a relaxed heuristic on matching
> > bad block markers, where we say the BBM is "bad" if more than fewer than
> > N bits are '1'. Right now, we just say that if there are any 0 bits in
> > the Bad Block Marker (BBM) region, then the block is bad. But this is
> > problematic for pages that have been worn down and might have bitflips.
> > So right now, part of a (bad) solution is to read with ECC, so worn
> > blocks that have data won't be later interpreted as bad blocks if we
> > rescan the BBMs (ECC will correct the bitflips, if the OOB is
> > protected).
> >
> > But that solution is not really good, since ECC is not really a panacea
> > for misinterpreted BBMs. And HW like yours apparently won't work like
> > this.
>
> Okay, I see you gave pretty much the same explanation, which makes mine
> useless :-).
>
> >
> > So in summary: if we can consistently make BBM checks look for 6 or 7
> > "one" bits (rather than a full 8 bits, i.e. BBM == 0xff), then we can
> > just unconditionally switch to RAW rather than PLACE_OOB. And we don't
> > need a flag like this pach introduces.
>
> I guess it all depends whether we want to let NAND controllers that can
> protect their BBM keep doing it (which IMO is not such a bad idea).
I think I was the only one consciously trying to do this. (Though I
guess it's possible some people discreetly hacked it in by not
supporting raw mode properly.) And for my cases, I'm pretty sure a
properly-improved raw mode BBM scan would be just as good, or actually
better. So I'm not sure anyone would really notice if we switched back
and properly accounted for flips.
Brian
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode
2015-10-11 20:03 ` Brian Norris
@ 2015-11-10 5:13 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-11-10 5:13 UTC (permalink / raw)
To: Brian Norris, Boris Brezillon
Cc: dehrenberg, cernekee, sboyd, linux-kernel, linux-mtd,
linux-arm-msm, Andrea Scian, agross
Hi,
On 10/12/2015 01:33 AM, Brian Norris wrote:
> Hi Boris,
>
> On Fri, Oct 02, 2015 at 08:27:38AM +0200, Boris Brezillon wrote:
>> Brian, Archit,
>>
>> On Thu, 1 Oct 2015 19:44:34 -0700
>> Brian Norris <computersforpeace@gmail.com> wrote:
>>
>>> On Wed, Aug 19, 2015 at 10:19:02AM +0530, Archit Taneja wrote:
>>>> Some controllers can access the factory bad block marker from OOB only
>>>> when they read it in raw mode. When ECC is enabled, these controllers
>>>> discard reading/writing bad block markers, preventing access to them
>>>> altogether.
>>>>
>>>> The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
>>>> This results in the nand driver's ecc->read_oob() op to be called, which
>>>> works with ECC enabled.
>>>>
>>>> Create a new BBT option flag that tells nand_bbt to force the mode to
>>>> MTD_OPS_RAW. This would result in the correct op being called for the
>>>> underlying nand controller driver.
>>
>> Actually I have the same kind of patch in my local tree (for a
>> different reason though: the HW randomizer can mess up with the BBM
>> byte if it's not disabled, and the only way to disable it in my current
>> implementation is to switch to raw mode).
>>
>>>
>>> MTD_OPS_RAW is probably the best way to do this, and we should switch
>>> back to it for all users (rather than a new flag).
>>
>> I'm fine with this solution, but will that be acceptable for everybody?
>> I mean, some NAND controllers are able to protect some OOB bytes, and
>> the BBM might fall in those OOB bytes. In this case, shouldn't we rely
>> on the ECC protection instead of reading the OOB in raw mode?
>
> I think ECC is kind of misused a bit here. It's not really meant for
> protecting BBMs, and it's also really not sufficient, esp. given
> bitflips in erased areas.
>
>>> But to do this, we
>>> need to fix up some things. Particularly, we need to extend
>>> 'badblockbits' support so that it is applied consistently in all places
>>> (I recall there is one code path in which bad block scanning does take
>>> this into account, and one that doesn't.)
>>
>> Yes, IIRC Andrea has posted a patch addressing that problem [1].
>> Another problem I see is that badblockbits is currently assigned a
>> fixed value by the NAND controller driver (or a default value of 8).
>> There's no specific logic to correlate it to the required ECC strength.
>> IMO, we should not let each NAND controller driver decide what is the
>> appropriate value for each chip but rather implement the logic in
>> nand_base.c based on ecc->strength and ecc->size, and IIRC this was
>> the question Andrea asked when he posted his proposal.
>>
>>>
>>> About badblockbits: it allows us to do a relaxed heuristic on matching
>>> bad block markers, where we say the BBM is "bad" if more than fewer than
>>> N bits are '1'. Right now, we just say that if there are any 0 bits in
>>> the Bad Block Marker (BBM) region, then the block is bad. But this is
>>> problematic for pages that have been worn down and might have bitflips.
>>> So right now, part of a (bad) solution is to read with ECC, so worn
>>> blocks that have data won't be later interpreted as bad blocks if we
>>> rescan the BBMs (ECC will correct the bitflips, if the OOB is
>>> protected).
>>>
>>> But that solution is not really good, since ECC is not really a panacea
>>> for misinterpreted BBMs. And HW like yours apparently won't work like
>>> this.
>>
>> Okay, I see you gave pretty much the same explanation, which makes mine
>> useless :-).
>>
>>>
>>> So in summary: if we can consistently make BBM checks look for 6 or 7
>>> "one" bits (rather than a full 8 bits, i.e. BBM == 0xff), then we can
>>> just unconditionally switch to RAW rather than PLACE_OOB. And we don't
>>> need a flag like this pach introduces.
>>
>> I guess it all depends whether we want to let NAND controllers that can
>> protect their BBM keep doing it (which IMO is not such a bad idea).
>
> I think I was the only one consciously trying to do this. (Though I
> guess it's possible some people discreetly hacked it in by not
> supporting raw mode properly.) And for my cases, I'm pretty sure a
> properly-improved raw mode BBM scan would be just as good, or actually
> better. So I'm not sure anyone would really notice if we switched back
> and properly accounted for flips.
Was there any progress on the badblockbits work? I'd seen a thread on
linux-mtd but that had sort of died too.
Brian,
Could we get this driver merged for now without BBT support? In my next
revision, I could populate chip->block_bad and chip->block_markbad
and add NAND_SKIP_BBTSCAN to chip->options. I can remove this once
we have badblockbits support.
Thanks,
Archit
>
> Brian
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings
2015-08-19 4:49 ` [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
@ 2015-12-16 6:33 ` Boris Brezillon
2015-12-16 8:11 ` Archit Taneja
0 siblings, 1 reply; 71+ messages in thread
From: Boris Brezillon @ 2015-12-16 6:33 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd,
linux-arm-msm, linux-kernel, devicetree, agross
Hi Archit,
Sorry for the late review, but there are a few things I think should be
addressed.
On Wed, 19 Aug 2015 10:19:04 +0530
Archit Taneja <architt@codeaurora.org> wrote:
> Add DT bindings document for the Qualcomm NAND controller driver.
>
> Cc: devicetree@vger.kernel.org
>
> v4:
> - No changes
>
> v3:
> - Don't use '0x' when specifying nand controller address space
> - Add optional property for on-flash bbt usage
>
> Acked-by: Andy Gross <agross@codeaurora.org>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
> .../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> new file mode 100644
> index 0000000..1de4643
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -0,0 +1,49 @@
> +* Qualcomm NAND controller
> +
> +Required properties:
> +- compatible: should be "qcom,ebi2-nand" for IPQ806x
> +- reg: MMIO address range
> +- clocks: must contain core clock and always on clock
> +- clock-names: must contain "core" for the core clock and "aon" for the
> + always on clock
> +- dmas: DMA specifier, consisting of a phandle to the ADM DMA
> + controller node and the channel number to be used for
> + NAND. Refer to dma.txt and qcom_adm.txt for more details
> +- dma-names: must be "rxtx"
> +- qcom,cmd-crci: must contain the ADM command type CRCI block instance
> + number specified for the NAND controller on the given
> + platform
> +- qcom,data-crci: must contain the ADM data type CRCI block instance
> + number specified for the NAND controller on the given
> + platform
> +
> +Optional properties:
> +- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
> + as default
> +
> +- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
> + bits. If not present, 4 is chosen as default
> +- nand-on-flash-bbt: Create/use on-flash bad block table
> +
> +The device tree may optionally contain sub-nodes describing partitions of the
> +address space. See partition.txt for more detail.
> +
> +Example:
> +
> +nand@1ac00000 {
> + compatible = "qcom,ebi2-nandc";
> + reg = <0x1ac00000 0x800>;
> +
> + clocks = <&gcc EBI2_CLK>,
> + <&gcc EBI2_AON_CLK>;
> + clock-names = "core", "aon";
> +
> + dmas = <&adm_dma 3>;
> + dma-names = "rxtx";
> + qcom,cmd-crci = <15>;
> + qcom,data-crci = <3>;
> +
> + partition@0 {
> + ...
> + };
> +};
According to the registers layout defined in your driver, your NAND
controller can address multiple chips (NAND_DEV_SEL register). Since DT
bindings are supposed to be as stable as possible, I would recommend
separating the NAND controller and NAND chip declaration (as done here
[1] and here [2]).
Best Regards,
Boris
[1]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
[2]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings
2015-12-16 6:33 ` Boris Brezillon
@ 2015-12-16 8:11 ` Archit Taneja
0 siblings, 0 replies; 71+ messages in thread
From: Archit Taneja @ 2015-12-16 8:11 UTC (permalink / raw)
To: Boris Brezillon
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd,
linux-arm-msm, linux-kernel, devicetree, agross
Hi Boris,
On 12/16/2015 12:03 PM, Boris Brezillon wrote:
> Hi Archit,
>
> Sorry for the late review, but there are a few things I think should be
> addressed.
>
> On Wed, 19 Aug 2015 10:19:04 +0530
> Archit Taneja <architt@codeaurora.org> wrote:
>
>> Add DT bindings document for the Qualcomm NAND controller driver.
>>
>> Cc: devicetree@vger.kernel.org
>>
>> v4:
>> - No changes
>>
>> v3:
>> - Don't use '0x' when specifying nand controller address space
>> - Add optional property for on-flash bbt usage
>>
>> Acked-by: Andy Gross <agross@codeaurora.org>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>> ---
>> .../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
>> 1 file changed, 49 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> new file mode 100644
>> index 0000000..1de4643
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -0,0 +1,49 @@
>> +* Qualcomm NAND controller
>> +
>> +Required properties:
>> +- compatible: should be "qcom,ebi2-nand" for IPQ806x
>> +- reg: MMIO address range
>> +- clocks: must contain core clock and always on clock
>> +- clock-names: must contain "core" for the core clock and "aon" for the
>> + always on clock
>> +- dmas: DMA specifier, consisting of a phandle to the ADM DMA
>> + controller node and the channel number to be used for
>> + NAND. Refer to dma.txt and qcom_adm.txt for more details
>> +- dma-names: must be "rxtx"
>> +- qcom,cmd-crci: must contain the ADM command type CRCI block instance
>> + number specified for the NAND controller on the given
>> + platform
>> +- qcom,data-crci: must contain the ADM data type CRCI block instance
>> + number specified for the NAND controller on the given
>> + platform
>> +
>> +Optional properties:
>> +- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
>> + as default
>> +
>> +- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
>> + bits. If not present, 4 is chosen as default
>> +- nand-on-flash-bbt: Create/use on-flash bad block table
>> +
>> +The device tree may optionally contain sub-nodes describing partitions of the
>> +address space. See partition.txt for more detail.
>> +
>> +Example:
>> +
>> +nand@1ac00000 {
>> + compatible = "qcom,ebi2-nandc";
>> + reg = <0x1ac00000 0x800>;
>> +
>> + clocks = <&gcc EBI2_CLK>,
>> + <&gcc EBI2_AON_CLK>;
>> + clock-names = "core", "aon";
>> +
>> + dmas = <&adm_dma 3>;
>> + dma-names = "rxtx";
>> + qcom,cmd-crci = <15>;
>> + qcom,data-crci = <3>;
>> +
>> + partition@0 {
>> + ...
>> + };
>> +};
>
>
> According to the registers layout defined in your driver, your NAND
> controller can address multiple chips (NAND_DEV_SEL register). Since DT
> bindings are supposed to be as stable as possible, I would recommend
> separating the NAND controller and NAND chip declaration (as done here
> [1] and here [2]).
Yes, the controller does support multiple chips, but the driver only
supports one chip for now.
I'll make changes such that the driver works in accordance to the DT
bindings format you shared.
Thanks for the review.
Archit
>
> Best Regards,
>
> Boris
>
> [1]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> [2]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
>
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
` (2 preceding siblings ...)
2015-10-02 17:31 ` Brian Norris
@ 2015-12-16 9:15 ` Boris Brezillon
2015-12-16 11:57 ` Archit Taneja
3 siblings, 1 reply; 71+ messages in thread
From: Boris Brezillon @ 2015-12-16 9:15 UTC (permalink / raw)
To: Archit Taneja
Cc: linux-mtd, dehrenberg, cernekee, computersforpeace, sboyd,
linux-arm-msm, linux-kernel, agross
Hi Archit,
Again, sorry for the late review. It's probably not exhaustive but
points a few things that should be fixed.
On Wed, 19 Aug 2015 10:19:03 +0530
Archit Taneja <architt@codeaurora.org> wrote:
> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
> MDM9x15 series.
>
> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
> and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
> broader interface for external slow peripheral devices such as LCD and
> NAND/NOR flash memory or SRAM like interfaces.
>
> We add support for the NAND controller found within EBI2. For the SoCs
> of our interest, we only use the NAND controller within EBI2. Therefore,
> it's safe for us to assume that the NAND controller is a standalone block
> within the SoC.
>
> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
> flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
> 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
> and spare data. The controller contains an internal 512 byte page buffer
> to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
> for register read/write and data transfers. The controller performs page
> reads and writes at a codeword/step level of 512 bytes. It can support up
> to 2 external chips of different configurations.
>
> The driver prepares register read and write configuration descriptors for
> each codeword, followed by data descriptors to read or write data from the
> controller's internal buffer. It uses a single ADM DMA channel that we get
> via dmaengine API. The controller requires 2 ADM CRCIs for command and
> data flow control. These are passed via DT.
>
> The ecc layout used by the controller is syndrome like, but we can't use
> the standard syndrome ecc ops because of several reasons. First, the amount
> of data bytes covered by ecc isn't same in each step. Second, writing to
> free oob space requires us writing to the entire step in which the oob
> lies. This forces us to create our own ecc ops.
>
> One more difference is how the controller accesses the bad block marker.
> The controller ignores reading the marker when ECC is enabled. ECC needs
> to be explicity disabled to read or write to the bad block marker. For
> this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
> read the factory provided bad block markers.
>
> v4:
> - Shrink submit_descs
> - add desc list node at the end of dma_prep_desc
> - Endianness and warning fixes
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>
> v3:
> - Refactor dma functions for maximum reuse
> - Use dma_slave_confing on stack
> - optimize and clean upempty_page_fixup using memchr_inv
> - ensure portability with dma register reads using le32_* funcs
> - use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
> - fix handling of return values of dmaengine funcs
> - constify wherever possible
> - Remove dependency on ADM DMA in Kconfig
> - Misc fixes and clean ups
>
> v2:
> - Use new BBT flag that allows us to read BBM in raw mode
> - reduce memcpy-s in the driver
> - some refactor and clean ups because of above changes
>
> Reviewed-by: Andy Gross <agross@codeaurora.org>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
> drivers/mtd/nand/Kconfig | 7 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qcom_nandc.c | 1910 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1918 insertions(+)
> create mode 100644 drivers/mtd/nand/qcom_nandc.c
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 5b2806a..6085b8a 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -538,4 +538,11 @@ config MTD_NAND_HISI504
> help
> Enables support for NAND controller on Hisilicon SoC Hip04.
>
> +config MTD_NAND_QCOM
> + tristate "Support for NAND on QCOM SoCs"
> + depends on ARCH_QCOM
> + help
> + Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> + controller. This controller is found on IPQ806x SoC.
> +
> endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 1f897ec..87b6a1d 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
> obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
> obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
> +obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>
> nand-objs := nand_base.o nand_bbt.o nand_timings.o
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> new file mode 100644
> index 0000000..2337731
> --- /dev/null
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -0,0 +1,1910 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/bitops.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> +#include <linux/module.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_mtd.h>
> +#include <linux/delay.h>
> +
> +/* NANDc reg offsets */
> +#define NAND_FLASH_CMD 0x00
> +#define NAND_ADDR0 0x04
> +#define NAND_ADDR1 0x08
> +#define NAND_FLASH_CHIP_SELECT 0x0c
> +#define NAND_EXEC_CMD 0x10
> +#define NAND_FLASH_STATUS 0x14
> +#define NAND_BUFFER_STATUS 0x18
> +#define NAND_DEV0_CFG0 0x20
> +#define NAND_DEV0_CFG1 0x24
> +#define NAND_DEV0_ECC_CFG 0x28
> +#define NAND_DEV1_ECC_CFG 0x2c
> +#define NAND_DEV1_CFG0 0x30
> +#define NAND_DEV1_CFG1 0x34
> +#define NAND_READ_ID 0x40
> +#define NAND_READ_STATUS 0x44
> +#define NAND_DEV_CMD0 0xa0
> +#define NAND_DEV_CMD1 0xa4
> +#define NAND_DEV_CMD2 0xa8
> +#define NAND_DEV_CMD_VLD 0xac
> +#define SFLASHC_BURST_CFG 0xe0
> +#define NAND_ERASED_CW_DETECT_CFG 0xe8
> +#define NAND_ERASED_CW_DETECT_STATUS 0xec
> +#define NAND_EBI2_ECC_BUF_CFG 0xf0
> +#define FLASH_BUF_ACC 0x100
> +
> +#define NAND_CTRL 0xf00
> +#define NAND_VERSION 0xf08
> +#define NAND_READ_LOCATION_0 0xf20
> +#define NAND_READ_LOCATION_1 0xf24
> +
> +/* dummy register offsets, used by write_reg_dma */
> +#define NAND_DEV_CMD1_RESTORE 0xdead
> +#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
> +
> +/* NAND_FLASH_CMD bits */
> +#define PAGE_ACC BIT(4)
> +#define LAST_PAGE BIT(5)
> +
> +/* NAND_FLASH_CHIP_SELECT bits */
> +#define NAND_DEV_SEL 0
> +#define DM_EN BIT(2)
> +
> +/* NAND_FLASH_STATUS bits */
> +#define FS_OP_ERR BIT(4)
> +#define FS_READY_BSY_N BIT(5)
> +#define FS_MPU_ERR BIT(8)
> +#define FS_DEVICE_STS_ERR BIT(16)
> +#define FS_DEVICE_WP BIT(23)
> +
> +/* NAND_BUFFER_STATUS bits */
> +#define BS_UNCORRECTABLE_BIT BIT(8)
> +#define BS_CORRECTABLE_ERR_MSK 0x1f
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DISABLE_STATUS_AFTER_WRITE 4
> +#define CW_PER_PAGE 6
> +#define UD_SIZE_BYTES 9
> +#define ECC_PARITY_SIZE_BYTES_RS 19
> +#define SPARE_SIZE_BYTES 23
> +#define NUM_ADDR_CYCLES 27
> +#define STATUS_BFR_READ 30
> +#define SET_RD_MODE_AFTER_STATUS 31
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DEV0_CFG1_ECC_DISABLE 0
> +#define WIDE_FLASH 1
> +#define NAND_RECOVERY_CYCLES 2
> +#define CS_ACTIVE_BSY 5
> +#define BAD_BLOCK_BYTE_NUM 6
> +#define BAD_BLOCK_IN_SPARE_AREA 16
> +#define WR_RD_BSY_GAP 17
> +#define ENABLE_BCH_ECC 27
> +
> +/* NAND_DEV0_ECC_CFG bits */
> +#define ECC_CFG_ECC_DISABLE 0
> +#define ECC_SW_RESET 1
> +#define ECC_MODE 4
> +#define ECC_PARITY_SIZE_BYTES_BCH 8
> +#define ECC_NUM_DATA_BYTES 16
> +#define ECC_FORCE_CLK_OPEN 30
> +
> +/* NAND_DEV_CMD1 bits */
> +#define READ_ADDR 0
> +
> +/* NAND_DEV_CMD_VLD bits */
> +#define READ_START_VLD 0
> +
> +/* NAND_EBI2_ECC_BUF_CFG bits */
> +#define NUM_STEPS 0
> +
> +/* NAND_ERASED_CW_DETECT_CFG bits */
> +#define ERASED_CW_ECC_MASK 1
> +#define AUTO_DETECT_RES 0
> +#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
> +#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
> +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
> +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
> +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
> +
> +/* NAND_ERASED_CW_DETECT_STATUS bits */
> +#define PAGE_ALL_ERASED BIT(7)
> +#define CODEWORD_ALL_ERASED BIT(6)
> +#define PAGE_ERASED BIT(5)
> +#define CODEWORD_ERASED BIT(4)
> +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
> +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
> +
> +/* Version Mask */
> +#define NAND_VERSION_MAJOR_MASK 0xf0000000
> +#define NAND_VERSION_MAJOR_SHIFT 28
> +#define NAND_VERSION_MINOR_MASK 0x0fff0000
> +#define NAND_VERSION_MINOR_SHIFT 16
> +
> +/* NAND OP_CMDs */
> +#define PAGE_READ 0x2
> +#define PAGE_READ_WITH_ECC 0x3
> +#define PAGE_READ_WITH_ECC_SPARE 0x4
> +#define PROGRAM_PAGE 0x6
> +#define PAGE_PROGRAM_WITH_ECC 0x7
> +#define PROGRAM_PAGE_SPARE 0x9
> +#define BLOCK_ERASE 0xa
> +#define FETCH_ID 0xb
> +#define RESET_DEVICE 0xd
> +
> +/*
> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> + * the driver calls the chunks 'step' or 'codeword' interchangeably
> + */
> +#define NANDC_STEP_SIZE 512
> +
> +/*
> + * the largest page size we support is 8K, this will have 16 steps/codewords
> + * of 512 bytes each
> + */
> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
> +
> +/* we read at most 3 registers per codeword scan */
> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
> +
> +/* ECC modes */
> +#define ECC_NONE BIT(0)
> +#define ECC_RS_4BIT BIT(1)
> +#define ECC_BCH_4BIT BIT(2)
> +#define ECC_BCH_8BIT BIT(3)
> +
> +struct desc_info {
> + struct list_head list;
> +
> + enum dma_data_direction dir;
> + struct scatterlist sgl;
> + struct dma_async_tx_descriptor *dma_desc;
> +};
> +
> +/*
> + * holds the current register values that we want to write. acts as a contiguous
> + * chunk of memory which we use to write the controller registers through DMA.
> + */
> +struct nandc_regs {
> + __le32 cmd;
> + __le32 addr0;
> + __le32 addr1;
> + __le32 chip_sel;
> + __le32 exec;
> +
> + __le32 cfg0;
> + __le32 cfg1;
> + __le32 ecc_bch_cfg;
> +
> + __le32 clrflashstatus;
> + __le32 clrreadstatus;
> +
> + __le32 cmd1;
> + __le32 vld;
> +
> + __le32 orig_cmd1;
> + __le32 orig_vld;
> +
> + __le32 ecc_buf_cfg;
> +};
> +
> +/*
> + * @cmd_crci: ADM DMA CRCI for command flow control
> + * @data_crci: ADM DMA CRCI for data flow control
> + * @list: DMA descriptor list (list of desc_infos)
> + * @data_buffer: our local DMA buffer for page read/writes,
> + * used when we can't use the buffer provided
> + * by upper layers directly
> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
> + * @reg_read_buf: buffer for reading register data via DMA
> + * @reg_read_pos: marker for data read in reg_read_buf
> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
> + * ecc/non-ecc mode for the current nand flash
> + * device
> + * @regs: a contiguous chunk of memory for DMA register
> + * writes
> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
> + * @ecc_modes: supported ECC modes by the current controller,
> + * initialized via DT match data
> + * @cw_size: the number of bytes in a single step/codeword
> + * of a page, consisting of all data, ecc, spare
> + * and reserved bytes
> + * @cw_data: the number of bytes within a codeword protected
> + * by ECC
> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
> + * @status: value to be returned if NAND_CMD_STATUS command
> + * is executed
> + */
> +struct qcom_nandc_data {
> + struct platform_device *pdev;
> + struct device *dev;
> +
> + void __iomem *base;
> + struct resource *res;
> +
> + struct clk *core_clk;
> + struct clk *aon_clk;
> +
> + /* DMA stuff */
> + struct dma_chan *chan;
> + struct dma_slave_config slave_conf;
> + unsigned int cmd_crci;
> + unsigned int data_crci;
> + struct list_head list;
> +
> + /* MTD stuff */
> + struct nand_chip chip;
> + struct mtd_info mtd;
You can drop this field, since nand_chip now embeds its own mtd_info
instance (accessible through the nand_to_mtd() helper).
> +
> + /* local data buffer and markers */
> + u8 *data_buffer;
> + int buf_size;
> + int buf_count;
> + int buf_start;
> +
> + /* local buffer to read back registers */
> + __le32 *reg_read_buf;
> + int reg_read_pos;
> +
> + /* required configs */
> + u32 cfg0, cfg1;
> + u32 cfg0_raw, cfg1_raw;
> + u32 ecc_buf_cfg;
> + u32 ecc_bch_cfg;
> + u32 clrflashstatus;
> + u32 clrreadstatus;
> + u32 sflashc_burst_cfg;
> + u32 cmd1, vld;
> +
> + /* register state */
> + struct nandc_regs *regs;
> +
> + /* things we get from DT */
> + int ecc_strength;
> + int bus_width;
Do you really need these fields? You can directly change the
->chip.ecc.strength and ->chip.options field instead.
> +
> + u32 ecc_modes;
> +
> + /* misc params */
> + int cw_size;
> + int cw_data;
> + bool use_ecc;
> + bool bch_enabled;
> + u8 status;
> + int last_command;
> +};
You're mixing controller and chip stuff in this structure. As said in
my answer to your DT bindings proposal, I think it would be clearer to
separate the controller and chip specific fields.
Note that a NAND chip can be attached to a NAND controller through its
->controller field.
So here is how it would look like:
struct qcom_nandc_data {
struct nand_hw_control controller;
struct list_head chips;
/* controller specific fields */
};
struct qcom_nand_data {
struct list_head node;
struct nand_chip chip;
/* chip specific fields */
}
[...]
> +
> +/*
> + * Implements chip->cmdfunc. It's only used for a limited set of commands.
> + * The rest of the commands wouldn't be called by upper layers. For example,
> + * NAND_CMD_READOOB would never be called because we have our own versions
> + * of read_oob ops for nand_ecc_ctrl.
> + */
> +static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
> + int column, int page_addr)
> +{
> + struct nand_chip *chip = mtd->priv;
struct nand_chip *chip = mtd_to_nand(mtd);
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + struct qcom_nandc_data *this = chip->priv;
> + bool wait = false;
> + int r = 0;
> +
> + pre_command(this, command);
> +
> + switch (command) {
> + case NAND_CMD_RESET:
> + r = reset(this);
> + wait = true;
> + break;
> +
> + case NAND_CMD_READID:
> + this->buf_count = 4;
> + r = read_id(this, column);
> + wait = true;
> + break;
> +
> + case NAND_CMD_PARAM:
> + r = nandc_param(this);
> + wait = true;
> + break;
> +
> + case NAND_CMD_ERASE1:
> + r = erase_block(this, page_addr);
> + wait = true;
> + break;
> +
> + case NAND_CMD_READ0:
> + /* we read the entire page for now */
> + WARN_ON(column != 0);
> +
> + this->use_ecc = true;
> + set_address(this, 0, page_addr);
> + update_rw_regs(this, ecc->steps, true);
> + break;
> +
> + case NAND_CMD_SEQIN:
> + WARN_ON(column != 0);
> + set_address(this, 0, page_addr);
> + break;
> +
> + case NAND_CMD_PAGEPROG:
> + case NAND_CMD_STATUS:
> + case NAND_CMD_NONE:
> + default:
> + break;
> + }
> +
> + if (r) {
> + dev_err(this->dev, "failure executing command %d\n",
> + command);
> + free_descs(this);
> + return;
> + }
> +
> + if (wait) {
> + r = submit_descs(this);
> + if (r)
> + dev_err(this->dev,
> + "failure submitting descs for command %d\n",
> + command);
> + }
> +
> + free_descs(this);
> +
> + post_command(this, command);
> +}
> +
> +/*
> + * when using RS ECC, the NAND controller flags an error when reading an
> + * erased page. however, there are special characters at certain offsets when
> + * we read the erased page. we check here if the page is really empty. if so,
> + * we replace the magic characters with 0xffs
> + */
> +static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
struct nand_chip *chip = &this->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS];
> + int i, j;
> +
> + /* if BCH is enabled, HW will take care of detecting erased pages */
> + if (this->bch_enabled || !this->use_ecc)
> + return false;
> +
> + for (i = 0; i < cwperpage; i++) {
> + u8 *empty1, *empty2;
> + u32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
> +
> + /*
> + * an erased page flags an error in NAND_FLASH_STATUS, check if
> + * the page is erased by looking for 0x54s at offsets 3 and 175
> + * from the beginning of each codeword
> + */
> + if (!(flash_status & FS_OP_ERR))
> + break;
> +
> + empty1 = &data_buf[3 + i * this->cw_data];
> + empty2 = &data_buf[175 + i * this->cw_data];
> +
> + /*
> + * if the error wasn't because of an erased page, bail out and
> + * and let someone else do the error checking
> + */
> + if ((*empty1 == 0x54 && *empty2 == 0xff) ||
> + (*empty1 == 0xff && *empty2 == 0x54)) {
> + orig1[i] = *empty1;
> + orig2[i] = *empty2;
> +
> + *empty1 = 0xff;
> + *empty2 = 0xff;
> + } else {
> + break;
> + }
> + }
> +
> + if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize))
> + goto not_empty;
> +
> + /*
> + * tell the caller that the page was empty and is fixed up, so that
> + * parse_read_errors() doesn't think it's an error
> + */
> + return true;
> +
> +not_empty:
> + /* restore original values if not empty*/
> + for (j = 0; j < i; j++) {
> + data_buf[3 + j * this->cw_data] = orig1[j];
> + data_buf[175 + j * this->cw_data] = orig2[j];
> + }
> +
> + return false;
> +}
> +
> +struct read_stats {
> + __le32 flash;
> + __le32 buffer;
> + __le32 erased_cw;
> +};
> +
> +/*
> + * reads back status registers set by the controller to notify page read
> + * errors. this is equivalent to what 'ecc->correct()' would do.
> + */
> +static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
struct nand_chip *chip = &this->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = ecc->steps;
> + unsigned int max_bitflips = 0;
> + int i;
> + struct read_stats *buf;
> +
> + buf = (struct read_stats *)this->reg_read_buf;
> + for (i = 0; i < cwperpage; i++, buf++) {
> + unsigned int stat;
> + u32 flash, buffer, erased_cw;
> +
> + flash = le32_to_cpu(buf->flash);
> + buffer = le32_to_cpu(buf->buffer);
> + erased_cw = le32_to_cpu(buf->erased_cw);
> +
> + if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
> +
> + /* ignore erased codeword errors */
> + if (this->bch_enabled) {
> + if ((erased_cw & ERASED_CW) == ERASED_CW)
> + continue;
> + } else if (erased_page) {
> + continue;
> + }
> +
> + if (buffer & BS_UNCORRECTABLE_BIT) {
> + mtd->ecc_stats.failed++;
> + continue;
> + }
> + }
> +
> + stat = buffer & BS_CORRECTABLE_ERR_MSK;
> + mtd->ecc_stats.corrected += stat;
> +
> + max_bitflips = max(max_bitflips, stat);
> + }
> +
> + return max_bitflips;
> +}
> +
[...]
> +
> +/*
> + * the three functions below implement chip->read_byte(), chip->read_buf()
> + * and chip->write_buf() respectively. these aren't used for
> + * reading/writing page data, they are used for smaller data like reading
> + * id, status etc
> + */
> +static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd->priv;
struct nand_chip *chip = mtd_to_nand(mtd);
> + struct qcom_nandc_data *this = chip->priv;
> + uint8_t *buf = this->data_buffer;
> + uint8_t ret = 0x0;
> +
> + if (this->last_command == NAND_CMD_STATUS) {
> + ret = this->status;
> +
> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> +
> + return ret;
> + }
> +
> + if (this->buf_start < this->buf_count)
> + ret = buf[this->buf_start++];
> +
> + return ret;
> +}
> +
> +static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct nand_chip *chip = mtd->priv;
struct nand_chip *chip = mtd_to_nand(mtd);
> + struct qcom_nandc_data *this = chip->priv;
> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
> +
> + memcpy(buf, this->data_buffer + this->buf_start, real_len);
> + this->buf_start += real_len;
> +}
> +
> +static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
> + int len)
> +{
> + struct nand_chip *chip = mtd->priv;
struct nand_chip *chip = mtd_to_nand(mtd);
> + struct qcom_nandc_data *this = chip->priv;
> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
> +
> + memcpy(this->data_buffer + this->buf_start, buf, real_len);
> +
> + this->buf_start += real_len;
> +}
> +
> +/* we support only one external chip for now */
> +static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
> +{
> + struct nand_chip *chip = mtd->priv;
struct nand_chip *chip = mtd_to_nand(mtd);
> + struct qcom_nandc_data *this = chip->priv;
> +
> + if (chipnr <= 0)
> + return;
> +
> + dev_warn(this->dev, "invalid chip select\n");
> +}
> +
> +/*
> + * NAND controller page layout info
> + *
> + * |-----------------------| |---------------------------------|
> + * | xx.......xx| | *********xx.......xx|
> + * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
> + * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
> + * | xx.......xx| | *********xx.......xx|
> + * |-----------------------| |---------------------------------|
> + * codeword 1,2..n-1 codeword n
> + * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
> + *
> + * n = number of codewords in the page
> + * . = ECC bytes
> + * * = spare bytes
> + * x = unused/reserved bytes
> + *
> + * 2K page: n = 4, spare = 16 bytes
> + * 4K page: n = 8, spare = 32 bytes
> + * 8K page: n = 16, spare = 64 bytes
Is there a reason not to use the following layout?
(
n x (
data = 512 bytes
protected OOB data = 4 bytes
ECC bytes = 12 or 16
)
+
remaining unprotected OOB bytes
)
This way the ECC layout definition would be easier to define, and
you'll have something that is closer to what a NAND chip expect (ECC
block/step size of 512 or 1024).
I know this is also dependent on the bootloader, hence my question.
> + *
> + * the qcom nand controller operates at a sub page/codeword level. each
> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
> + * the number of ECC bytes vary based on the ECC strength and the bus width.
> + *
> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
> + *
> + * the layout described above is used by the controller when the ECC block is
> + * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
> + * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
> + * layouts defined below doesn't consider the positions occupied by the reserved
> + * bytes
You could just read this portion with the ECC engine disabled when
you're asked for OOB data.
> + *
> + * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
> + * in the last codeword is the position of bad block marker. the bad block
> + * marker cannot be accessed when ECC is enabled.
So, you're switching the BBM with the data at the BBM position
(possibly some in-band data), right?
> + *
> + */
> +
> +/*
> + * Layouts for different page sizes and ecc modes. We skip the eccpos field
> + * since it isn't needed for this driver
> + */
If you know where they are stored, please specify them, even if they
are not used by the upper layers (this helps analyzing raw nand dumps).
> +
> +/* 2K page, 4 bit ECC */
> +static struct nand_ecclayout layout_oob_64 = {
> + .eccbytes = 40,
> + .oobfree = {
> + { 30, 16 },
> + },
> +};
According to your description it should either be eccbytes = 48 (if
you're considering reserved bytes as ECC bytes) or 32 (if you're not
counting reserved bytes).
BTW, is the oobfree portion really starting at offset 30? I'd say that
in the 2K page, 4 bit ECC you don't have any oobfree bytes
(528 * 4 == 2048 + 64).
> +
> +/* 4K page, 4 bit ECC, 8/16 bit bus width */
> +static struct nand_ecclayout layout_oob_128 = {
> + .eccbytes = 80,
> + .oobfree = {
> + { 70, 32 },
> + },
> +};
> +
> +/* 4K page, 8 bit ECC, 8 bit bus width */
> +static struct nand_ecclayout layout_oob_224_x8 = {
> + .eccbytes = 104,
> + .oobfree = {
> + { 91, 32 },
> + },
> +};
> +
> +/* 4K page, 8 bit ECC, 16 bit bus width */
> +static struct nand_ecclayout layout_oob_224_x16 = {
> + .eccbytes = 112,
> + .oobfree = {
> + { 98, 32 },
> + },
> +};
> +
> +/* 8K page, 4 bit ECC, 8/16 bit bus width */
> +static struct nand_ecclayout layout_oob_256 = {
> + .eccbytes = 160,
> + .oobfree = {
> + { 151, 64 },
> + },
> +};
Those ECC layout definitions could probably be dynamically created
based on the detected ECC strength, bus-width and page size, instead of
defining a new one for each new combination.
> +
> +/*
> + * this is called before scan_ident, we do some minimal configurations so
> + * that reading ID and ONFI params work
> + */
> +static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
> +{
> + /* kill onenand */
> + nandc_write(this, SFLASHC_BURST_CFG, 0);
> +
> + /* enable ADM DMA */
> + nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
> +
> + /* save the original values of these registers */
> + this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
> + this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
> +
> + /* initial status value */
> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> +}
> +
> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
struct nand_chip *chip = &this->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage;
> + bool wide_bus;
> +
> + /* the nand controller fetches codewords/chunks of 512 bytes */
> + cwperpage = mtd->writesize >> 9;
> +
> + ecc->strength = this->ecc_strength;
> +
> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> +
> + if (ecc->strength >= 8) {
> + /* 8 bit ECC defaults to BCH ECC on all platforms */
> + ecc->bytes = wide_bus ? 14 : 13;
Maybe you'd better consider that reserved bytes (after the ECC bytes)
are actually ECC bytes. So, according to your description you would
always have 16 here.
> + } else {
> + /*
> + * if the controller supports BCH for 4 bit ECC, the controller
> + * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> + * always 10 bytes
> + */
> + if (this->ecc_modes & ECC_BCH_4BIT)
> + ecc->bytes = wide_bus ? 8 : 7;
Ditto, except it's 12 here.
> + else
> + ecc->bytes = 10;
> + }
> +
> + /* each step consists of 512 bytes of data */
> + ecc->size = NANDC_STEP_SIZE;
> +
> + ecc->read_page = qcom_nandc_read_page;
> + ecc->read_oob = qcom_nandc_read_oob;
> + ecc->write_page = qcom_nandc_write_page;
> + ecc->write_oob = qcom_nandc_write_oob;
> +
> + /*
> + * the bad block marker is readable only when we read the page with ECC
> + * disabled. all the ops above run with ECC enabled. We need raw read
> + * and write function for oob in order to access bad block marker.
> + */
> + ecc->read_oob_raw = qcom_nandc_read_oob_raw;
> + ecc->write_oob_raw = qcom_nandc_write_oob_raw;
> +
> + switch (mtd->oobsize) {
> + case 64:
> + ecc->layout = &layout_oob_64;
> + break;
> + case 128:
> + ecc->layout = &layout_oob_128;
> + break;
> + case 224:
> + if (wide_bus)
> + ecc->layout = &layout_oob_224_x16;
> + else
> + ecc->layout = &layout_oob_224_x8;
> + break;
> + case 256:
> + ecc->layout = &layout_oob_256;
> + break;
> + default:
> + dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
> + mtd->oobsize);
> + return -ENODEV;
> + }
> +
> + ecc->mode = NAND_ECC_HW;
> +
> + /* enable ecc by default */
> + this->use_ecc = true;
> +
> + return 0;
> +}
> +
> +static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
struct nand_chip *chip = &this->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> + int cwperpage = mtd->writesize / ecc->size;
> + int spare_bytes, bad_block_byte;
> + bool wide_bus;
> + int ecc_mode = 0;
> +
> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> +
> + if (ecc->strength >= 8) {
> + this->cw_size = 532;
> +
> + spare_bytes = wide_bus ? 0 : 2;
> +
> + this->bch_enabled = true;
> + ecc_mode = 1;
> + } else {
> + this->cw_size = 528;
> +
> + if (this->ecc_modes & ECC_BCH_4BIT) {
> + spare_bytes = wide_bus ? 2 : 4;
> +
> + this->bch_enabled = true;
> + ecc_mode = 0;
> + } else {
> + spare_bytes = wide_bus ? 0 : 1;
> + }
> + }
> +
> + /*
> + * DATA_UD_BYTES varies based on whether the read/write command protects
> + * spare data with ECC too. We protect spare data by default, so we set
> + * it to main + spare data, which are 512 and 4 bytes respectively.
> + */
> + this->cw_data = 516;
> +
> + bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
> +
> + this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
> + | this->cw_data << UD_SIZE_BYTES
> + | 0 << DISABLE_STATUS_AFTER_WRITE
> + | 5 << NUM_ADDR_CYCLES
> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
> + | 0 << STATUS_BFR_READ
> + | 1 << SET_RD_MODE_AFTER_STATUS
> + | spare_bytes << SPARE_SIZE_BYTES;
> +
> + this->cfg1 = 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | bad_block_byte << BAD_BLOCK_BYTE_NUM
> + | 0 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | wide_bus << WIDE_FLASH
> + | this->bch_enabled << ENABLE_BCH_ECC;
> +
> + this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
> + | this->cw_size << UD_SIZE_BYTES
> + | 5 << NUM_ADDR_CYCLES
> + | 0 << SPARE_SIZE_BYTES;
> +
> + this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
> + | 0 << CS_ACTIVE_BSY
> + | 17 << BAD_BLOCK_BYTE_NUM
> + | 1 << BAD_BLOCK_IN_SPARE_AREA
> + | 2 << WR_RD_BSY_GAP
> + | wide_bus << WIDE_FLASH
> + | 1 << DEV0_CFG1_ECC_DISABLE;
> +
> + this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
> + | 0 << ECC_SW_RESET
> + | this->cw_data << ECC_NUM_DATA_BYTES
> + | 1 << ECC_FORCE_CLK_OPEN
> + | ecc_mode << ECC_MODE
> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
> +
> + this->ecc_buf_cfg = 0x203 << NUM_STEPS;
> +
> + this->clrflashstatus = FS_READY_BSY_N;
> + this->clrreadstatus = 0xc0;
> +
> + dev_dbg(this->dev,
> + "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
> + this->cfg0, this->cfg1, this->ecc_buf_cfg,
> + this->ecc_bch_cfg, this->cw_size, this->cw_data,
> + ecc->strength, ecc->bytes, cwperpage);
> +}
> +
> +static int qcom_nandc_alloc(struct qcom_nandc_data *this)
> +{
> + int r;
> +
> + r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
> + if (r) {
> + dev_err(this->dev, "failed to set DMA mask\n");
> + return r;
> + }
> +
> + /*
> + * we use the internal buffer for reading ONFI params, reading small
> + * data like ID and status, and preforming read-copy-write operations
> + * when writing to a codeword partially. 532 is the maximum possible
> + * size of a codeword for our nand controller
> + */
> + this->buf_size = 532;
> +
> + this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
> + if (!this->data_buffer)
> + return -ENOMEM;
> +
> + this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL);
> + if (!this->regs)
> + return -ENOMEM;
> +
> + this->reg_read_buf = devm_kzalloc(this->dev,
> + MAX_REG_RD * sizeof(*this->reg_read_buf),
> + GFP_KERNEL);
> + if (!this->reg_read_buf)
> + return -ENOMEM;
> +
> + INIT_LIST_HEAD(&this->list);
> +
> + this->chan = dma_request_slave_channel(this->dev, "rxtx");
> + if (!this->chan) {
> + dev_err(this->dev, "failed to request slave channel\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
> +{
> + dma_release_channel(this->chan);
> +}
> +
> +static int qcom_nandc_init(struct qcom_nandc_data *this)
> +{
> + struct mtd_info *mtd = &this->mtd;
> + struct nand_chip *chip = &this->chip;
struct nand_chip *chip = &this->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
> + struct device_node *np = this->dev->of_node;
> + struct mtd_part_parser_data ppdata = { .of_node = np };
You don't need it anymore, because it's automatically extracted from
the ->flash_node field.
Just call, nand_set_flash_node() before calling nand_scan_ident().
> + int r;
> +
> + mtd->priv = chip;
> + mtd->name = "qcom-nandc";
> + mtd->owner = THIS_MODULE;
> +
> + chip->priv = this;
> +
> + chip->cmdfunc = qcom_nandc_command;
> + chip->select_chip = qcom_nandc_select_chip;
> + chip->read_byte = qcom_nandc_read_byte;
> + chip->read_buf = qcom_nandc_read_buf;
> + chip->write_buf = qcom_nandc_write_buf;
> +
> + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
> + if (this->bus_width == 16)
> + chip->options |= NAND_BUSWIDTH_16;
> +
> + chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
> + if (of_get_nand_on_flash_bbt(np))
> + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
Ditto: rely on the work done by nand_dt_init() which is
called by nand_scan_ident().
> +
> + qcom_nandc_pre_init(this);
> +
> + r = nand_scan_ident(mtd, 1, NULL);
> + if (r)
> + return r;
> +
> + r = qcom_nandc_ecc_init(this);
> + if (r)
> + return r;
> +
> + qcom_nandc_hw_post_init(this);
> +
> + r = nand_scan_tail(mtd);
> + if (r)
> + return r;
> +
> + return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
return mtd_device_parse_register(mtd, NULL, NULL, NULL 0);
> +}
> +
> +static int qcom_nandc_parse_dt(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
> + struct device_node *np = this->dev->of_node;
> + int r;
> +
> + this->ecc_strength = of_get_nand_ecc_strength(np);
> + if (this->ecc_strength < 0) {
> + dev_warn(this->dev,
> + "incorrect ecc strength, setting to 4 bits/step\n");
> + this->ecc_strength = 4;
> + }
> +
> + this->bus_width = of_get_nand_bus_width(np);
> + if (this->bus_width < 0) {
> + dev_warn(this->dev, "incorrect bus width, setting to 8\n");
> + this->bus_width = 8;
> + }
Those two properties are extracted when calling nand_scan_ident() if
you've called nand_set_flash_node() before that.
> +
> + r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
> + if (r) {
> + dev_err(this->dev, "command CRCI unspecified\n");
> + return r;
> + }
> +
> + r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
> + if (r) {
> + dev_err(this->dev, "data CRCI unspecified\n");
> + return r;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_nandc_probe(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this;
> + const void *dev_data;
> + int r;
> +
> + this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
> + if (!this)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, this);
> +
> + this->pdev = pdev;
> + this->dev = &pdev->dev;
> +
> + dev_data = of_device_get_match_data(&pdev->dev);
> + if (!dev_data) {
> + dev_err(&pdev->dev, "failed to get device data\n");
> + return -ENODEV;
> + }
> +
> + this->ecc_modes = (unsigned long)dev_data;
> +
> + this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + this->base = devm_ioremap_resource(&pdev->dev, this->res);
> + if (IS_ERR(this->base))
> + return PTR_ERR(this->base);
> +
> + this->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(this->core_clk))
> + return PTR_ERR(this->core_clk);
> +
> + this->aon_clk = devm_clk_get(&pdev->dev, "aon");
> + if (IS_ERR(this->aon_clk))
> + return PTR_ERR(this->aon_clk);
> +
> + r = qcom_nandc_parse_dt(pdev);
> + if (r)
> + return r;
> +
> + r = qcom_nandc_alloc(this);
> + if (r)
> + return r;
> +
> + r = clk_prepare_enable(this->core_clk);
> + if (r)
> + goto err_core_clk;
> +
> + r = clk_prepare_enable(this->aon_clk);
> + if (r)
> + goto err_aon_clk;
> +
> + r = qcom_nandc_init(this);
> + if (r)
> + goto err_init;
> +
> + return 0;
> +
> +err_init:
> + clk_disable_unprepare(this->aon_clk);
> +err_aon_clk:
> + clk_disable_unprepare(this->core_clk);
> +err_core_clk:
> + qcom_nandc_unalloc(this);
> +
> + return r;
> +}
> +
> +static int qcom_nandc_remove(struct platform_device *pdev)
> +{
> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
> +
You miss a call to nand_release() here, otherwise your device is still
registered to the MTD/NAND layer, even though you've released all the
resources attached to it.
That's all I got for now.
Best Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-12-16 9:15 ` Boris Brezillon
@ 2015-12-16 11:57 ` Archit Taneja
2015-12-16 14:18 ` Boris Brezillon
2015-12-16 19:16 ` Brian Norris
0 siblings, 2 replies; 71+ messages in thread
From: Archit Taneja @ 2015-12-16 11:57 UTC (permalink / raw)
To: Boris Brezillon
Cc: dehrenberg, cernekee, sboyd, linux-kernel, linux-mtd,
linux-arm-msm, computersforpeace, agross
Hi Boris,
On 12/16/2015 02:45 PM, Boris Brezillon wrote:
> Hi Archit,
>
> Again, sorry for the late review. It's probably not exhaustive but
> points a few things that should be fixed.
Thanks for the thorough review! Some comments below.
>
>
> On Wed, 19 Aug 2015 10:19:03 +0530
> Archit Taneja <architt@codeaurora.org> wrote:
>
>> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
>> MDM9x15 series.
>>
>> It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
>> and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
>> broader interface for external slow peripheral devices such as LCD and
>> NAND/NOR flash memory or SRAM like interfaces.
>>
>> We add support for the NAND controller found within EBI2. For the SoCs
>> of our interest, we only use the NAND controller within EBI2. Therefore,
>> it's safe for us to assume that the NAND controller is a standalone block
>> within the SoC.
>>
>> The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
>> flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
>> 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
>> and spare data. The controller contains an internal 512 byte page buffer
>> to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
>> for register read/write and data transfers. The controller performs page
>> reads and writes at a codeword/step level of 512 bytes. It can support up
>> to 2 external chips of different configurations.
>>
>> The driver prepares register read and write configuration descriptors for
>> each codeword, followed by data descriptors to read or write data from the
>> controller's internal buffer. It uses a single ADM DMA channel that we get
>> via dmaengine API. The controller requires 2 ADM CRCIs for command and
>> data flow control. These are passed via DT.
>>
>> The ecc layout used by the controller is syndrome like, but we can't use
>> the standard syndrome ecc ops because of several reasons. First, the amount
>> of data bytes covered by ecc isn't same in each step. Second, writing to
>> free oob space requires us writing to the entire step in which the oob
>> lies. This forces us to create our own ecc ops.
>>
>> One more difference is how the controller accesses the bad block marker.
>> The controller ignores reading the marker when ECC is enabled. ECC needs
>> to be explicity disabled to read or write to the bad block marker. For
>> this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to
>> read the factory provided bad block markers.
>>
>> v4:
>> - Shrink submit_descs
>> - add desc list node at the end of dma_prep_desc
>> - Endianness and warning fixes
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>>
>> v3:
>> - Refactor dma functions for maximum reuse
>> - Use dma_slave_confing on stack
>> - optimize and clean upempty_page_fixup using memchr_inv
>> - ensure portability with dma register reads using le32_* funcs
>> - use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves
>> - fix handling of return values of dmaengine funcs
>> - constify wherever possible
>> - Remove dependency on ADM DMA in Kconfig
>> - Misc fixes and clean ups
>>
>> v2:
>> - Use new BBT flag that allows us to read BBM in raw mode
>> - reduce memcpy-s in the driver
>> - some refactor and clean ups because of above changes
>>
>> Reviewed-by: Andy Gross <agross@codeaurora.org>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>> ---
>> drivers/mtd/nand/Kconfig | 7 +
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/qcom_nandc.c | 1910 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1918 insertions(+)
>> create mode 100644 drivers/mtd/nand/qcom_nandc.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 5b2806a..6085b8a 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -538,4 +538,11 @@ config MTD_NAND_HISI504
>> help
>> Enables support for NAND controller on Hisilicon SoC Hip04.
>>
>> +config MTD_NAND_QCOM
>> + tristate "Support for NAND on QCOM SoCs"
>> + depends on ARCH_QCOM
>> + help
>> + Enables support for NAND flash chips on SoCs containing the EBI2 NAND
>> + controller. This controller is found on IPQ806x SoC.
>> +
>> endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index 1f897ec..87b6a1d 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
>> obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
>> obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
>> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>> +obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>
>> nand-objs := nand_base.o nand_bbt.o nand_timings.o
>> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
>> new file mode 100644
>> index 0000000..2337731
>> --- /dev/null
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -0,0 +1,1910 @@
>> +/*
>> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/slab.h>
>> +#include <linux/bitops.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/dmaengine.h>
>> +#include <linux/module.h>
>> +#include <linux/mtd/nand.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/of_mtd.h>
>> +#include <linux/delay.h>
>> +
>> +/* NANDc reg offsets */
>> +#define NAND_FLASH_CMD 0x00
>> +#define NAND_ADDR0 0x04
>> +#define NAND_ADDR1 0x08
>> +#define NAND_FLASH_CHIP_SELECT 0x0c
>> +#define NAND_EXEC_CMD 0x10
>> +#define NAND_FLASH_STATUS 0x14
>> +#define NAND_BUFFER_STATUS 0x18
>> +#define NAND_DEV0_CFG0 0x20
>> +#define NAND_DEV0_CFG1 0x24
>> +#define NAND_DEV0_ECC_CFG 0x28
>> +#define NAND_DEV1_ECC_CFG 0x2c
>> +#define NAND_DEV1_CFG0 0x30
>> +#define NAND_DEV1_CFG1 0x34
>> +#define NAND_READ_ID 0x40
>> +#define NAND_READ_STATUS 0x44
>> +#define NAND_DEV_CMD0 0xa0
>> +#define NAND_DEV_CMD1 0xa4
>> +#define NAND_DEV_CMD2 0xa8
>> +#define NAND_DEV_CMD_VLD 0xac
>> +#define SFLASHC_BURST_CFG 0xe0
>> +#define NAND_ERASED_CW_DETECT_CFG 0xe8
>> +#define NAND_ERASED_CW_DETECT_STATUS 0xec
>> +#define NAND_EBI2_ECC_BUF_CFG 0xf0
>> +#define FLASH_BUF_ACC 0x100
>> +
>> +#define NAND_CTRL 0xf00
>> +#define NAND_VERSION 0xf08
>> +#define NAND_READ_LOCATION_0 0xf20
>> +#define NAND_READ_LOCATION_1 0xf24
>> +
>> +/* dummy register offsets, used by write_reg_dma */
>> +#define NAND_DEV_CMD1_RESTORE 0xdead
>> +#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
>> +
>> +/* NAND_FLASH_CMD bits */
>> +#define PAGE_ACC BIT(4)
>> +#define LAST_PAGE BIT(5)
>> +
>> +/* NAND_FLASH_CHIP_SELECT bits */
>> +#define NAND_DEV_SEL 0
>> +#define DM_EN BIT(2)
>> +
>> +/* NAND_FLASH_STATUS bits */
>> +#define FS_OP_ERR BIT(4)
>> +#define FS_READY_BSY_N BIT(5)
>> +#define FS_MPU_ERR BIT(8)
>> +#define FS_DEVICE_STS_ERR BIT(16)
>> +#define FS_DEVICE_WP BIT(23)
>> +
>> +/* NAND_BUFFER_STATUS bits */
>> +#define BS_UNCORRECTABLE_BIT BIT(8)
>> +#define BS_CORRECTABLE_ERR_MSK 0x1f
>> +
>> +/* NAND_DEVn_CFG0 bits */
>> +#define DISABLE_STATUS_AFTER_WRITE 4
>> +#define CW_PER_PAGE 6
>> +#define UD_SIZE_BYTES 9
>> +#define ECC_PARITY_SIZE_BYTES_RS 19
>> +#define SPARE_SIZE_BYTES 23
>> +#define NUM_ADDR_CYCLES 27
>> +#define STATUS_BFR_READ 30
>> +#define SET_RD_MODE_AFTER_STATUS 31
>> +
>> +/* NAND_DEVn_CFG0 bits */
>> +#define DEV0_CFG1_ECC_DISABLE 0
>> +#define WIDE_FLASH 1
>> +#define NAND_RECOVERY_CYCLES 2
>> +#define CS_ACTIVE_BSY 5
>> +#define BAD_BLOCK_BYTE_NUM 6
>> +#define BAD_BLOCK_IN_SPARE_AREA 16
>> +#define WR_RD_BSY_GAP 17
>> +#define ENABLE_BCH_ECC 27
>> +
>> +/* NAND_DEV0_ECC_CFG bits */
>> +#define ECC_CFG_ECC_DISABLE 0
>> +#define ECC_SW_RESET 1
>> +#define ECC_MODE 4
>> +#define ECC_PARITY_SIZE_BYTES_BCH 8
>> +#define ECC_NUM_DATA_BYTES 16
>> +#define ECC_FORCE_CLK_OPEN 30
>> +
>> +/* NAND_DEV_CMD1 bits */
>> +#define READ_ADDR 0
>> +
>> +/* NAND_DEV_CMD_VLD bits */
>> +#define READ_START_VLD 0
>> +
>> +/* NAND_EBI2_ECC_BUF_CFG bits */
>> +#define NUM_STEPS 0
>> +
>> +/* NAND_ERASED_CW_DETECT_CFG bits */
>> +#define ERASED_CW_ECC_MASK 1
>> +#define AUTO_DETECT_RES 0
>> +#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
>> +#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
>> +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
>> +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
>> +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
>> +
>> +/* NAND_ERASED_CW_DETECT_STATUS bits */
>> +#define PAGE_ALL_ERASED BIT(7)
>> +#define CODEWORD_ALL_ERASED BIT(6)
>> +#define PAGE_ERASED BIT(5)
>> +#define CODEWORD_ERASED BIT(4)
>> +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
>> +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
>> +
>> +/* Version Mask */
>> +#define NAND_VERSION_MAJOR_MASK 0xf0000000
>> +#define NAND_VERSION_MAJOR_SHIFT 28
>> +#define NAND_VERSION_MINOR_MASK 0x0fff0000
>> +#define NAND_VERSION_MINOR_SHIFT 16
>> +
>> +/* NAND OP_CMDs */
>> +#define PAGE_READ 0x2
>> +#define PAGE_READ_WITH_ECC 0x3
>> +#define PAGE_READ_WITH_ECC_SPARE 0x4
>> +#define PROGRAM_PAGE 0x6
>> +#define PAGE_PROGRAM_WITH_ECC 0x7
>> +#define PROGRAM_PAGE_SPARE 0x9
>> +#define BLOCK_ERASE 0xa
>> +#define FETCH_ID 0xb
>> +#define RESET_DEVICE 0xd
>> +
>> +/*
>> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>> + * the driver calls the chunks 'step' or 'codeword' interchangeably
>> + */
>> +#define NANDC_STEP_SIZE 512
>> +
>> +/*
>> + * the largest page size we support is 8K, this will have 16 steps/codewords
>> + * of 512 bytes each
>> + */
>> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
>> +
>> +/* we read at most 3 registers per codeword scan */
>> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
>> +
>> +/* ECC modes */
>> +#define ECC_NONE BIT(0)
>> +#define ECC_RS_4BIT BIT(1)
>> +#define ECC_BCH_4BIT BIT(2)
>> +#define ECC_BCH_8BIT BIT(3)
>> +
>> +struct desc_info {
>> + struct list_head list;
>> +
>> + enum dma_data_direction dir;
>> + struct scatterlist sgl;
>> + struct dma_async_tx_descriptor *dma_desc;
>> +};
>> +
>> +/*
>> + * holds the current register values that we want to write. acts as a contiguous
>> + * chunk of memory which we use to write the controller registers through DMA.
>> + */
>> +struct nandc_regs {
>> + __le32 cmd;
>> + __le32 addr0;
>> + __le32 addr1;
>> + __le32 chip_sel;
>> + __le32 exec;
>> +
>> + __le32 cfg0;
>> + __le32 cfg1;
>> + __le32 ecc_bch_cfg;
>> +
>> + __le32 clrflashstatus;
>> + __le32 clrreadstatus;
>> +
>> + __le32 cmd1;
>> + __le32 vld;
>> +
>> + __le32 orig_cmd1;
>> + __le32 orig_vld;
>> +
>> + __le32 ecc_buf_cfg;
>> +};
>> +
>> +/*
>> + * @cmd_crci: ADM DMA CRCI for command flow control
>> + * @data_crci: ADM DMA CRCI for data flow control
>> + * @list: DMA descriptor list (list of desc_infos)
>> + * @data_buffer: our local DMA buffer for page read/writes,
>> + * used when we can't use the buffer provided
>> + * by upper layers directly
>> + * @buf_size/count/start: markers for chip->read_buf/write_buf functions
>> + * @reg_read_buf: buffer for reading register data via DMA
>> + * @reg_read_pos: marker for data read in reg_read_buf
>> + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
>> + * ecc/non-ecc mode for the current nand flash
>> + * device
>> + * @regs: a contiguous chunk of memory for DMA register
>> + * writes
>> + * @ecc_strength: 4 bit or 8 bit ecc, received via DT
>> + * @bus_width: 8 bit or 16 bit NAND bus width, received via DT
>> + * @ecc_modes: supported ECC modes by the current controller,
>> + * initialized via DT match data
>> + * @cw_size: the number of bytes in a single step/codeword
>> + * of a page, consisting of all data, ecc, spare
>> + * and reserved bytes
>> + * @cw_data: the number of bytes within a codeword protected
>> + * by ECC
>> + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
>> + * @status: value to be returned if NAND_CMD_STATUS command
>> + * is executed
>> + */
>> +struct qcom_nandc_data {
>> + struct platform_device *pdev;
>> + struct device *dev;
>> +
>> + void __iomem *base;
>> + struct resource *res;
>> +
>> + struct clk *core_clk;
>> + struct clk *aon_clk;
>> +
>> + /* DMA stuff */
>> + struct dma_chan *chan;
>> + struct dma_slave_config slave_conf;
>> + unsigned int cmd_crci;
>> + unsigned int data_crci;
>> + struct list_head list;
>> +
>> + /* MTD stuff */
>> + struct nand_chip chip;
>> + struct mtd_info mtd;
>
> You can drop this field, since nand_chip now embeds its own mtd_info
> instance (accessible through the nand_to_mtd() helper).
Ah, alright. I'd posted this patchset during the 4.3-rc cycle, this must
have been in discussion then. I'll update accordingly.
>
>> +
>> + /* local data buffer and markers */
>> + u8 *data_buffer;
>> + int buf_size;
>> + int buf_count;
>> + int buf_start;
>> +
>> + /* local buffer to read back registers */
>> + __le32 *reg_read_buf;
>> + int reg_read_pos;
>> +
>> + /* required configs */
>> + u32 cfg0, cfg1;
>> + u32 cfg0_raw, cfg1_raw;
>> + u32 ecc_buf_cfg;
>> + u32 ecc_bch_cfg;
>> + u32 clrflashstatus;
>> + u32 clrreadstatus;
>> + u32 sflashc_burst_cfg;
>> + u32 cmd1, vld;
>> +
>> + /* register state */
>> + struct nandc_regs *regs;
>> +
>> + /* things we get from DT */
>> + int ecc_strength;
>> + int bus_width;
>
> Do you really need these fields? You can directly change the
> ->chip.ecc.strength and ->chip.options field instead.
Yes, these aren't required. I was forcibly reading these via
custom DT properties. I will replace this such that these are
populated via nand_dt_init().
>
>> +
>> + u32 ecc_modes;
>> +
>> + /* misc params */
>> + int cw_size;
>> + int cw_data;
>> + bool use_ecc;
>> + bool bch_enabled;
>> + u8 status;
>> + int last_command;
>> +};
>
> You're mixing controller and chip stuff in this structure. As said in
> my answer to your DT bindings proposal, I think it would be clearer to
> separate the controller and chip specific fields.
>
> Note that a NAND chip can be attached to a NAND controller through its
> ->controller field.
>
> So here is how it would look like:
>
> struct qcom_nandc_data {
> struct nand_hw_control controller;
>
> struct list_head chips;
> /* controller specific fields */
> };
>
> struct qcom_nand_data {
> struct list_head node;
> struct nand_chip chip;
>
> /* chip specific fields */
> }
Thanks for the explanation. I wasn't aware of this sort of
structure split. I was probably referring to the sinlge chip
nand controller drivers when I wrote it.
>
>
> [...]
>
>> +
>> +/*
>> + * Implements chip->cmdfunc. It's only used for a limited set of commands.
>> + * The rest of the commands wouldn't be called by upper layers. For example,
>> + * NAND_CMD_READOOB would never be called because we have our own versions
>> + * of read_oob ops for nand_ecc_ctrl.
>> + */
>> +static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
>> + int column, int page_addr)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>
> struct nand_chip *chip = mtd_to_nand(mtd);
>
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + struct qcom_nandc_data *this = chip->priv;
>> + bool wait = false;
>> + int r = 0;
>> +
>> + pre_command(this, command);
>> +
>> + switch (command) {
>> + case NAND_CMD_RESET:
>> + r = reset(this);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_READID:
>> + this->buf_count = 4;
>> + r = read_id(this, column);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_PARAM:
>> + r = nandc_param(this);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_ERASE1:
>> + r = erase_block(this, page_addr);
>> + wait = true;
>> + break;
>> +
>> + case NAND_CMD_READ0:
>> + /* we read the entire page for now */
>> + WARN_ON(column != 0);
>> +
>> + this->use_ecc = true;
>> + set_address(this, 0, page_addr);
>> + update_rw_regs(this, ecc->steps, true);
>> + break;
>> +
>> + case NAND_CMD_SEQIN:
>> + WARN_ON(column != 0);
>> + set_address(this, 0, page_addr);
>> + break;
>> +
>> + case NAND_CMD_PAGEPROG:
>> + case NAND_CMD_STATUS:
>> + case NAND_CMD_NONE:
>> + default:
>> + break;
>> + }
>> +
>> + if (r) {
>> + dev_err(this->dev, "failure executing command %d\n",
>> + command);
>> + free_descs(this);
>> + return;
>> + }
>> +
>> + if (wait) {
>> + r = submit_descs(this);
>> + if (r)
>> + dev_err(this->dev,
>> + "failure submitting descs for command %d\n",
>> + command);
>> + }
>> +
>> + free_descs(this);
>> +
>> + post_command(this, command);
>> +}
>> +
>> +/*
>> + * when using RS ECC, the NAND controller flags an error when reading an
>> + * erased page. however, there are special characters at certain offsets when
>> + * we read the erased page. we check here if the page is really empty. if so,
>> + * we replace the magic characters with 0xffs
>> + */
>> +static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>
> struct nand_chip *chip = &this->chip;
> struct mtd_info *mtd = nand_to_mtd(chip);
>
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS];
>> + int i, j;
>> +
>> + /* if BCH is enabled, HW will take care of detecting erased pages */
>> + if (this->bch_enabled || !this->use_ecc)
>> + return false;
>> +
>> + for (i = 0; i < cwperpage; i++) {
>> + u8 *empty1, *empty2;
>> + u32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]);
>> +
>> + /*
>> + * an erased page flags an error in NAND_FLASH_STATUS, check if
>> + * the page is erased by looking for 0x54s at offsets 3 and 175
>> + * from the beginning of each codeword
>> + */
>> + if (!(flash_status & FS_OP_ERR))
>> + break;
>> +
>> + empty1 = &data_buf[3 + i * this->cw_data];
>> + empty2 = &data_buf[175 + i * this->cw_data];
>> +
>> + /*
>> + * if the error wasn't because of an erased page, bail out and
>> + * and let someone else do the error checking
>> + */
>> + if ((*empty1 == 0x54 && *empty2 == 0xff) ||
>> + (*empty1 == 0xff && *empty2 == 0x54)) {
>> + orig1[i] = *empty1;
>> + orig2[i] = *empty2;
>> +
>> + *empty1 = 0xff;
>> + *empty2 = 0xff;
>> + } else {
>> + break;
>> + }
>> + }
>> +
>> + if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize))
>> + goto not_empty;
>> +
>> + /*
>> + * tell the caller that the page was empty and is fixed up, so that
>> + * parse_read_errors() doesn't think it's an error
>> + */
>> + return true;
>> +
>> +not_empty:
>> + /* restore original values if not empty*/
>> + for (j = 0; j < i; j++) {
>> + data_buf[3 + j * this->cw_data] = orig1[j];
>> + data_buf[175 + j * this->cw_data] = orig2[j];
>> + }
>> +
>> + return false;
>> +}
>> +
>> +struct read_stats {
>> + __le32 flash;
>> + __le32 buffer;
>> + __le32 erased_cw;
>> +};
>> +
>> +/*
>> + * reads back status registers set by the controller to notify page read
>> + * errors. this is equivalent to what 'ecc->correct()' would do.
>> + */
>> +static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>
> struct nand_chip *chip = &this->chip;
> struct mtd_info *mtd = nand_to_mtd(chip);
>
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = ecc->steps;
>> + unsigned int max_bitflips = 0;
>> + int i;
>> + struct read_stats *buf;
>> +
>> + buf = (struct read_stats *)this->reg_read_buf;
>> + for (i = 0; i < cwperpage; i++, buf++) {
>> + unsigned int stat;
>> + u32 flash, buffer, erased_cw;
>> +
>> + flash = le32_to_cpu(buf->flash);
>> + buffer = le32_to_cpu(buf->buffer);
>> + erased_cw = le32_to_cpu(buf->erased_cw);
>> +
>> + if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
>> +
>> + /* ignore erased codeword errors */
>> + if (this->bch_enabled) {
>> + if ((erased_cw & ERASED_CW) == ERASED_CW)
>> + continue;
>> + } else if (erased_page) {
>> + continue;
>> + }
>> +
>> + if (buffer & BS_UNCORRECTABLE_BIT) {
>> + mtd->ecc_stats.failed++;
>> + continue;
>> + }
>> + }
>> +
>> + stat = buffer & BS_CORRECTABLE_ERR_MSK;
>> + mtd->ecc_stats.corrected += stat;
>> +
>> + max_bitflips = max(max_bitflips, stat);
>> + }
>> +
>> + return max_bitflips;
>> +}
>> +
>
> [...]
>
>> +
>> +/*
>> + * the three functions below implement chip->read_byte(), chip->read_buf()
>> + * and chip->write_buf() respectively. these aren't used for
>> + * reading/writing page data, they are used for smaller data like reading
>> + * id, status etc
>> + */
>> +static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>
> struct nand_chip *chip = mtd_to_nand(mtd);
>
>> + struct qcom_nandc_data *this = chip->priv;
>> + uint8_t *buf = this->data_buffer;
>> + uint8_t ret = 0x0;
>> +
>> + if (this->last_command == NAND_CMD_STATUS) {
>> + ret = this->status;
>> +
>> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
>> +
>> + return ret;
>> + }
>> +
>> + if (this->buf_start < this->buf_count)
>> + ret = buf[this->buf_start++];
>> +
>> + return ret;
>> +}
>> +
>> +static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>
> struct nand_chip *chip = mtd_to_nand(mtd);
>
>> + struct qcom_nandc_data *this = chip->priv;
>> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
>> +
>> + memcpy(buf, this->data_buffer + this->buf_start, real_len);
>> + this->buf_start += real_len;
>> +}
>> +
>> +static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
>> + int len)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>
> struct nand_chip *chip = mtd_to_nand(mtd);
>
>> + struct qcom_nandc_data *this = chip->priv;
>> + int real_len = min_t(size_t, len, this->buf_count - this->buf_start);
>> +
>> + memcpy(this->data_buffer + this->buf_start, buf, real_len);
>> +
>> + this->buf_start += real_len;
>> +}
>> +
>> +/* we support only one external chip for now */
>> +static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
>> +{
>> + struct nand_chip *chip = mtd->priv;
>
> struct nand_chip *chip = mtd_to_nand(mtd);
>
>> + struct qcom_nandc_data *this = chip->priv;
>> +
>> + if (chipnr <= 0)
>> + return;
>> +
>> + dev_warn(this->dev, "invalid chip select\n");
>> +}
>> +
>> +/*
>> + * NAND controller page layout info
>> + *
>> + * |-----------------------| |---------------------------------|
>> + * | xx.......xx| | *********xx.......xx|
>> + * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
>> + * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
>> + * | xx.......xx| | *********xx.......xx|
>> + * |-----------------------| |---------------------------------|
>> + * codeword 1,2..n-1 codeword n
>> + * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
>> + *
>> + * n = number of codewords in the page
>> + * . = ECC bytes
>> + * * = spare bytes
>> + * x = unused/reserved bytes
>> + *
>> + * 2K page: n = 4, spare = 16 bytes
>> + * 4K page: n = 8, spare = 32 bytes
>> + * 8K page: n = 16, spare = 64 bytes
>
> Is there a reason not to use the following layout?
>
> (
> n x (
> data = 512 bytes
> protected OOB data = 4 bytes
> ECC bytes = 12 or 16
> )
>
> +
>
> remaining unprotected OOB bytes
> )
>
> This way the ECC layout definition would be easier to define, and
> you'll have something that is closer to what a NAND chip expect (ECC
> block/step size of 512 or 1024).
>
> I know this is also dependent on the bootloader, hence my question.
I tried to figure this out looking at documentation and the downstream
drivers. What I understood was that all the OOB was intentionally kept
in the last step, so that things are faster when we only want to access
OOB. In that case, the controller will need to write to only one
step/codeword.
The bootloaders also use the same layout.
>
>> + *
>> + * the qcom nand controller operates at a sub page/codeword level. each
>> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
>> + * the number of ECC bytes vary based on the ECC strength and the bus width.
>> + *
>> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
>> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
>> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
>> + *
>> + * the layout described above is used by the controller when the ECC block is
>> + * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
>> + * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
>> + * layouts defined below doesn't consider the positions occupied by the reserved
>> + * bytes
>
> You could just read this portion with the ECC engine disabled when
> you're asked for OOB data.
Yes, but there are ecc ops (like ecc->read_page/ecc->write_page) that
have an argument called 'oob_required'. We need to have ECC enabled when
running these ops.
In order to read this additional portion, I'll need to read/write each
step again with ECC disabled, which would really slow things down.
>
>> + *
>> + * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
>> + * in the last codeword is the position of bad block marker. the bad block
>> + * marker cannot be accessed when ECC is enabled.
>
> So, you're switching the BBM with the data at the BBM position
> (possibly some in-band data), right?
Yes. When ECC isn't enabled, the BBM byte lies within the in-band data
of the last step. In fact, there are dummy BBM bytes in the previous
steps at the same offset.
With ECC enabled, the controller just skips that position (and the
dummy BBM bytes in previous steps) altogether.
>
>> + *
>> + */
>> +
>> +/*
>> + * Layouts for different page sizes and ecc modes. We skip the eccpos field
>> + * since it isn't needed for this driver
>> + */
>
> If you know where they are stored, please specify them, even if they
> are not used by the upper layers (this helps analyzing raw nand dumps).
>
>> +
>> +/* 2K page, 4 bit ECC */
>> +static struct nand_ecclayout layout_oob_64 = {
>> + .eccbytes = 40,
>> + .oobfree = {
>> + { 30, 16 },
>> + },
>> +};
>
> According to your description it should either be eccbytes = 48 (if
> you're considering reserved bytes as ECC bytes) or 32 (if you're not
> counting reserved bytes).
Each step is 528 bytes in total. The first 3 steps contain 516 bytes
of data, 10 bytes of ECC and 2 bytes of resrved data. The last step
contains 500 bytes of data, 16 bytes of OOB, 10 bytes of ECC and 2
reserved bytes.
If I don't count the reserved bytes as part of ECC, I get 40. If I
do count it as part of ECC, I get 48. In the way I described
layouts, I ignored the ECC parts. How did you get 32?
>
> BTW, is the oobfree portion really starting at offset 30?
I thought the offsets mentioned here also had to incorporate positions
taken by ECC bytes? If I strip all the the in-band data (real data)
from each step, we get:
ECC(10 bytes).ECC(10 bytes).ECC(10 bytes).OOB(16 bytes).ECC(10 bytes)
Wouldn't this result in the offset as 30?
We are still only taking into account 56 bytes out of the 64 bytes
in the chip's OOB. This is because I'm discaring the 2 bytes from
each step (summing up to 8) which aren't accessible when ECC is
enabled.
>I'd say that in the 2K page, 4 bit ECC you don't have any oobfree bytes
> (528 * 4 == 2048 + 64).
528 contains both oob and in-band data. If you ignore the weird layout
and assume we have at an average 512 bytes for each step, we get:
512 * 4 == 2048 bytes of data, and 64 bytes of OOB (16 bytes free, 40
ECC, and 8 reserved/unused).
>
>> +
>> +/* 4K page, 4 bit ECC, 8/16 bit bus width */
>> +static struct nand_ecclayout layout_oob_128 = {
>> + .eccbytes = 80,
>> + .oobfree = {
>> + { 70, 32 },
>> + },
>> +};
>> +
>> +/* 4K page, 8 bit ECC, 8 bit bus width */
>> +static struct nand_ecclayout layout_oob_224_x8 = {
>> + .eccbytes = 104,
>> + .oobfree = {
>> + { 91, 32 },
>> + },
>> +};
>> +
>> +/* 4K page, 8 bit ECC, 16 bit bus width */
>> +static struct nand_ecclayout layout_oob_224_x16 = {
>> + .eccbytes = 112,
>> + .oobfree = {
>> + { 98, 32 },
>> + },
>> +};
>> +
>> +/* 8K page, 4 bit ECC, 8/16 bit bus width */
>> +static struct nand_ecclayout layout_oob_256 = {
>> + .eccbytes = 160,
>> + .oobfree = {
>> + { 151, 64 },
>> + },
>> +};
>
> Those ECC layout definitions could probably be dynamically created
> based on the detected ECC strength, bus-width and page size, instead of
> defining a new one for each new combination.
That's true. I can try that out.
>
>> +
>> +/*
>> + * this is called before scan_ident, we do some minimal configurations so
>> + * that reading ID and ONFI params work
>> + */
>> +static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
>> +{
>> + /* kill onenand */
>> + nandc_write(this, SFLASHC_BURST_CFG, 0);
>> +
>> + /* enable ADM DMA */
>> + nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +
>> + /* save the original values of these registers */
>> + this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
>> + this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
>> +
>> + /* initial status value */
>> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
>> +}
>> +
>> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>
> struct nand_chip *chip = &this->chip;
> struct mtd_info *mtd = nand_to_mtd(chip);
>
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage;
>> + bool wide_bus;
>> +
>> + /* the nand controller fetches codewords/chunks of 512 bytes */
>> + cwperpage = mtd->writesize >> 9;
>> +
>> + ecc->strength = this->ecc_strength;
>> +
>> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
>> +
>> + if (ecc->strength >= 8) {
>> + /* 8 bit ECC defaults to BCH ECC on all platforms */
>> + ecc->bytes = wide_bus ? 14 : 13;
>
> Maybe you'd better consider that reserved bytes (after the ECC bytes)
> are actually ECC bytes. So, according to your description you would
> always have 16 here.
The thing is that if I consider the reserved bytes as a part of the ECC
bytes, and if I use this bigger value when configuring the controller
and dma, I will get bad results; becase the hardware doesn't touch these
when ECC is enabled.
I could set the ecc->bytes to '16' and still use the actual values when
configuring the controller. Do you think that will help in any way?
>
>> + } else {
>> + /*
>> + * if the controller supports BCH for 4 bit ECC, the controller
>> + * uses lesser bytes for ECC. If RS is used, the ECC bytes is
>> + * always 10 bytes
>> + */
>> + if (this->ecc_modes & ECC_BCH_4BIT)
>> + ecc->bytes = wide_bus ? 8 : 7;
>
> Ditto, except it's 12 here.
>
>> + else
>> + ecc->bytes = 10;
>> + }
>> +
>> + /* each step consists of 512 bytes of data */
>> + ecc->size = NANDC_STEP_SIZE;
>> +
>> + ecc->read_page = qcom_nandc_read_page;
>> + ecc->read_oob = qcom_nandc_read_oob;
>> + ecc->write_page = qcom_nandc_write_page;
>> + ecc->write_oob = qcom_nandc_write_oob;
>> +
>> + /*
>> + * the bad block marker is readable only when we read the page with ECC
>> + * disabled. all the ops above run with ECC enabled. We need raw read
>> + * and write function for oob in order to access bad block marker.
>> + */
>> + ecc->read_oob_raw = qcom_nandc_read_oob_raw;
>> + ecc->write_oob_raw = qcom_nandc_write_oob_raw;
>> +
>> + switch (mtd->oobsize) {
>> + case 64:
>> + ecc->layout = &layout_oob_64;
>> + break;
>> + case 128:
>> + ecc->layout = &layout_oob_128;
>> + break;
>> + case 224:
>> + if (wide_bus)
>> + ecc->layout = &layout_oob_224_x16;
>> + else
>> + ecc->layout = &layout_oob_224_x8;
>> + break;
>> + case 256:
>> + ecc->layout = &layout_oob_256;
>> + break;
>> + default:
>> + dev_err(this->dev, "unsupported NAND device, oobsize %d\n",
>> + mtd->oobsize);
>> + return -ENODEV;
>> + }
>> +
>> + ecc->mode = NAND_ECC_HW;
>> +
>> + /* enable ecc by default */
>> + this->use_ecc = true;
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>
> struct nand_chip *chip = &this->chip;
> struct mtd_info *mtd = nand_to_mtd(chip);
>
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> + int cwperpage = mtd->writesize / ecc->size;
>> + int spare_bytes, bad_block_byte;
>> + bool wide_bus;
>> + int ecc_mode = 0;
>> +
>> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
>> +
>> + if (ecc->strength >= 8) {
>> + this->cw_size = 532;
>> +
>> + spare_bytes = wide_bus ? 0 : 2;
>> +
>> + this->bch_enabled = true;
>> + ecc_mode = 1;
>> + } else {
>> + this->cw_size = 528;
>> +
>> + if (this->ecc_modes & ECC_BCH_4BIT) {
>> + spare_bytes = wide_bus ? 2 : 4;
>> +
>> + this->bch_enabled = true;
>> + ecc_mode = 0;
>> + } else {
>> + spare_bytes = wide_bus ? 0 : 1;
>> + }
>> + }
>> +
>> + /*
>> + * DATA_UD_BYTES varies based on whether the read/write command protects
>> + * spare data with ECC too. We protect spare data by default, so we set
>> + * it to main + spare data, which are 512 and 4 bytes respectively.
>> + */
>> + this->cw_data = 516;
>> +
>> + bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1;
>> +
>> + this->cfg0 = (cwperpage - 1) << CW_PER_PAGE
>> + | this->cw_data << UD_SIZE_BYTES
>> + | 0 << DISABLE_STATUS_AFTER_WRITE
>> + | 5 << NUM_ADDR_CYCLES
>> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS
>> + | 0 << STATUS_BFR_READ
>> + | 1 << SET_RD_MODE_AFTER_STATUS
>> + | spare_bytes << SPARE_SIZE_BYTES;
>> +
>> + this->cfg1 = 7 << NAND_RECOVERY_CYCLES
>> + | 0 << CS_ACTIVE_BSY
>> + | bad_block_byte << BAD_BLOCK_BYTE_NUM
>> + | 0 << BAD_BLOCK_IN_SPARE_AREA
>> + | 2 << WR_RD_BSY_GAP
>> + | wide_bus << WIDE_FLASH
>> + | this->bch_enabled << ENABLE_BCH_ECC;
>> +
>> + this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
>> + | this->cw_size << UD_SIZE_BYTES
>> + | 5 << NUM_ADDR_CYCLES
>> + | 0 << SPARE_SIZE_BYTES;
>> +
>> + this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
>> + | 0 << CS_ACTIVE_BSY
>> + | 17 << BAD_BLOCK_BYTE_NUM
>> + | 1 << BAD_BLOCK_IN_SPARE_AREA
>> + | 2 << WR_RD_BSY_GAP
>> + | wide_bus << WIDE_FLASH
>> + | 1 << DEV0_CFG1_ECC_DISABLE;
>> +
>> + this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE
>> + | 0 << ECC_SW_RESET
>> + | this->cw_data << ECC_NUM_DATA_BYTES
>> + | 1 << ECC_FORCE_CLK_OPEN
>> + | ecc_mode << ECC_MODE
>> + | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH;
>> +
>> + this->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> +
>> + this->clrflashstatus = FS_READY_BSY_N;
>> + this->clrreadstatus = 0xc0;
>> +
>> + dev_dbg(this->dev,
>> + "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
>> + this->cfg0, this->cfg1, this->ecc_buf_cfg,
>> + this->ecc_bch_cfg, this->cw_size, this->cw_data,
>> + ecc->strength, ecc->bytes, cwperpage);
>> +}
>> +
>> +static int qcom_nandc_alloc(struct qcom_nandc_data *this)
>> +{
>> + int r;
>> +
>> + r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32));
>> + if (r) {
>> + dev_err(this->dev, "failed to set DMA mask\n");
>> + return r;
>> + }
>> +
>> + /*
>> + * we use the internal buffer for reading ONFI params, reading small
>> + * data like ID and status, and preforming read-copy-write operations
>> + * when writing to a codeword partially. 532 is the maximum possible
>> + * size of a codeword for our nand controller
>> + */
>> + this->buf_size = 532;
>> +
>> + this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL);
>> + if (!this->data_buffer)
>> + return -ENOMEM;
>> +
>> + this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL);
>> + if (!this->regs)
>> + return -ENOMEM;
>> +
>> + this->reg_read_buf = devm_kzalloc(this->dev,
>> + MAX_REG_RD * sizeof(*this->reg_read_buf),
>> + GFP_KERNEL);
>> + if (!this->reg_read_buf)
>> + return -ENOMEM;
>> +
>> + INIT_LIST_HEAD(&this->list);
>> +
>> + this->chan = dma_request_slave_channel(this->dev, "rxtx");
>> + if (!this->chan) {
>> + dev_err(this->dev, "failed to request slave channel\n");
>> + return -ENODEV;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_nandc_unalloc(struct qcom_nandc_data *this)
>> +{
>> + dma_release_channel(this->chan);
>> +}
>> +
>> +static int qcom_nandc_init(struct qcom_nandc_data *this)
>> +{
>> + struct mtd_info *mtd = &this->mtd;
>> + struct nand_chip *chip = &this->chip;
>
> struct nand_chip *chip = &this->chip;
> struct mtd_info *mtd = nand_to_mtd(chip);
>
>> + struct device_node *np = this->dev->of_node;
>> + struct mtd_part_parser_data ppdata = { .of_node = np };
>
> You don't need it anymore, because it's automatically extracted from
> the ->flash_node field.
> Just call, nand_set_flash_node() before calling nand_scan_ident().
That's convinient. I'll remove this.
>
>> + int r;
>> +
>> + mtd->priv = chip;
>> + mtd->name = "qcom-nandc";
>> + mtd->owner = THIS_MODULE;
>> +
>> + chip->priv = this;
>> +
>> + chip->cmdfunc = qcom_nandc_command;
>> + chip->select_chip = qcom_nandc_select_chip;
>> + chip->read_byte = qcom_nandc_read_byte;
>> + chip->read_buf = qcom_nandc_read_buf;
>> + chip->write_buf = qcom_nandc_write_buf;
>> +
>> + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
>> + if (this->bus_width == 16)
>> + chip->options |= NAND_BUSWIDTH_16;
>> +
>> + chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW;
>> + if (of_get_nand_on_flash_bbt(np))
>> + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
>
> Ditto: rely on the work done by nand_dt_init() which is
> called by nand_scan_ident().
Yes, I'll remove this.
>
>> +
>> + qcom_nandc_pre_init(this);
>> +
>> + r = nand_scan_ident(mtd, 1, NULL);
>> + if (r)
>> + return r;
>> +
>> + r = qcom_nandc_ecc_init(this);
>> + if (r)
>> + return r;
>> +
>> + qcom_nandc_hw_post_init(this);
>> +
>> + r = nand_scan_tail(mtd);
>> + if (r)
>> + return r;
>> +
>> + return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
>
> return mtd_device_parse_register(mtd, NULL, NULL, NULL 0);
Will fix.
>
>> +}
>> +
>> +static int qcom_nandc_parse_dt(struct platform_device *pdev)
>> +{
>> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
>> + struct device_node *np = this->dev->of_node;
>> + int r;
>> +
>> + this->ecc_strength = of_get_nand_ecc_strength(np);
>> + if (this->ecc_strength < 0) {
>> + dev_warn(this->dev,
>> + "incorrect ecc strength, setting to 4 bits/step\n");
>> + this->ecc_strength = 4;
>> + }
>> +
>> + this->bus_width = of_get_nand_bus_width(np);
>> + if (this->bus_width < 0) {
>> + dev_warn(this->dev, "incorrect bus width, setting to 8\n");
>> + this->bus_width = 8;
>> + }
>
> Those two properties are extracted when calling nand_scan_ident() if
> you've called nand_set_flash_node() before that.
Yeah, I'll remove these.
>
>> +
>> + r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci);
>> + if (r) {
>> + dev_err(this->dev, "command CRCI unspecified\n");
>> + return r;
>> + }
>> +
>> + r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci);
>> + if (r) {
>> + dev_err(this->dev, "data CRCI unspecified\n");
>> + return r;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int qcom_nandc_probe(struct platform_device *pdev)
>> +{
>> + struct qcom_nandc_data *this;
>> + const void *dev_data;
>> + int r;
>> +
>> + this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
>> + if (!this)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, this);
>> +
>> + this->pdev = pdev;
>> + this->dev = &pdev->dev;
>> +
>> + dev_data = of_device_get_match_data(&pdev->dev);
>> + if (!dev_data) {
>> + dev_err(&pdev->dev, "failed to get device data\n");
>> + return -ENODEV;
>> + }
>> +
>> + this->ecc_modes = (unsigned long)dev_data;
>> +
>> + this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + this->base = devm_ioremap_resource(&pdev->dev, this->res);
>> + if (IS_ERR(this->base))
>> + return PTR_ERR(this->base);
>> +
>> + this->core_clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(this->core_clk))
>> + return PTR_ERR(this->core_clk);
>> +
>> + this->aon_clk = devm_clk_get(&pdev->dev, "aon");
>> + if (IS_ERR(this->aon_clk))
>> + return PTR_ERR(this->aon_clk);
>> +
>> + r = qcom_nandc_parse_dt(pdev);
>> + if (r)
>> + return r;
>> +
>> + r = qcom_nandc_alloc(this);
>> + if (r)
>> + return r;
>> +
>> + r = clk_prepare_enable(this->core_clk);
>> + if (r)
>> + goto err_core_clk;
>> +
>> + r = clk_prepare_enable(this->aon_clk);
>> + if (r)
>> + goto err_aon_clk;
>> +
>> + r = qcom_nandc_init(this);
>> + if (r)
>> + goto err_init;
>> +
>> + return 0;
>> +
>> +err_init:
>> + clk_disable_unprepare(this->aon_clk);
>> +err_aon_clk:
>> + clk_disable_unprepare(this->core_clk);
>> +err_core_clk:
>> + qcom_nandc_unalloc(this);
>> +
>> + return r;
>> +}
>> +
>> +static int qcom_nandc_remove(struct platform_device *pdev)
>> +{
>> + struct qcom_nandc_data *this = platform_get_drvdata(pdev);
>> +
>
> You miss a call to nand_release() here, otherwise your device is still
> registered to the MTD/NAND layer, even though you've released all the
> resources attached to it.
I'll fix this.
>
> That's all I got for now.
Thanks again for taking the time for the review. Really appreciate it.
Archit
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-12-16 11:57 ` Archit Taneja
@ 2015-12-16 14:18 ` Boris Brezillon
2015-12-17 9:48 ` Archit Taneja
2015-12-16 19:16 ` Brian Norris
1 sibling, 1 reply; 71+ messages in thread
From: Boris Brezillon @ 2015-12-16 14:18 UTC (permalink / raw)
To: Archit Taneja
Cc: dehrenberg, cernekee, sboyd, linux-kernel, linux-mtd,
linux-arm-msm, computersforpeace, agross
On Wed, 16 Dec 2015 17:27:48 +0530
Archit Taneja <architt@codeaurora.org> wrote:
> >> +/*
> >> + * NAND controller page layout info
> >> + *
> >> + * |-----------------------| |---------------------------------|
> >> + * | xx.......xx| | *********xx.......xx|
> >> + * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
> >> + * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
> >> + * | xx.......xx| | *********xx.......xx|
> >> + * |-----------------------| |---------------------------------|
> >> + * codeword 1,2..n-1 codeword n
> >> + * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
> >> + *
> >> + * n = number of codewords in the page
> >> + * . = ECC bytes
> >> + * * = spare bytes
> >> + * x = unused/reserved bytes
> >> + *
> >> + * 2K page: n = 4, spare = 16 bytes
> >> + * 4K page: n = 8, spare = 32 bytes
> >> + * 8K page: n = 16, spare = 64 bytes
> >
> > Is there a reason not to use the following layout?
> >
> > (
> > n x (
> > data = 512 bytes
> > protected OOB data = 4 bytes
> > ECC bytes = 12 or 16
> > )
> >
> > +
> >
> > remaining unprotected OOB bytes
> > )
> >
> > This way the ECC layout definition would be easier to define, and
> > you'll have something that is closer to what a NAND chip expect (ECC
> > block/step size of 512 or 1024).
> >
> > I know this is also dependent on the bootloader, hence my question.
>
> I tried to figure this out looking at documentation and the downstream
> drivers. What I understood was that all the OOB was intentionally kept
> in the last step, so that things are faster when we only want to access
> OOB. In that case, the controller will need to write to only one
> step/codeword.
Well, I don't think sending a column change command is that costly
compared to a page retrieval command or ECC calculation.
>
> The bootloaders also use the same layout.
Ok, then I guess we'll have to live with that (but it complicates a lot
the driver logic :-/)
>
> >
> >> + *
> >> + * the qcom nand controller operates at a sub page/codeword level. each
> >> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
> >> + * the number of ECC bytes vary based on the ECC strength and the bus width.
> >> + *
> >> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
> >> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
> >> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
> >> + *
> >> + * the layout described above is used by the controller when the ECC block is
> >> + * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
> >> + * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
> >> + * layouts defined below doesn't consider the positions occupied by the reserved
> >> + * bytes
> >
> > You could just read this portion with the ECC engine disabled when
> > you're asked for OOB data.
>
> Yes, but there are ecc ops (like ecc->read_page/ecc->write_page) that
> have an argument called 'oob_required'. We need to have ECC enabled when
> running these ops.
>
> In order to read this additional portion, I'll need to read/write each
> step again with ECC disabled, which would really slow things down.
Nowadays, MTD FS are not using the OOB area, and oob_required is only
passed if the MTD user asked for OOB data, so that can be an acceptable
penalty. Anyway, that's not really important if we loose a few OOB
bytes.
>
> >
> >> + *
> >> + * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
> >> + * in the last codeword is the position of bad block marker. the bad block
> >> + * marker cannot be accessed when ECC is enabled.
> >
> > So, you're switching the BBM with the data at the BBM position
> > (possibly some in-band data), right?
>
> Yes. When ECC isn't enabled, the BBM byte lies within the in-band data
> of the last step. In fact, there are dummy BBM bytes in the previous
> steps at the same offset.
>
> With ECC enabled, the controller just skips that position (and the
> dummy BBM bytes in previous steps) altogether.
Okay.
>
> >
> >> + *
> >> + */
> >> +
> >> +/*
> >> + * Layouts for different page sizes and ecc modes. We skip the eccpos field
> >> + * since it isn't needed for this driver
> >> + */
> >
> > If you know where they are stored, please specify them, even if they
> > are not used by the upper layers (this helps analyzing raw nand dumps).
> >
> >> +
> >> +/* 2K page, 4 bit ECC */
> >> +static struct nand_ecclayout layout_oob_64 = {
> >> + .eccbytes = 40,
> >> + .oobfree = {
> >> + { 30, 16 },
> >> + },
> >> +};
> >
> > According to your description it should either be eccbytes = 48 (if
> > you're considering reserved bytes as ECC bytes) or 32 (if you're not
> > counting reserved bytes).
>
> Each step is 528 bytes in total. The first 3 steps contain 516 bytes
> of data, 10 bytes of ECC and 2 bytes of resrved data. The last step
> contains 500 bytes of data, 16 bytes of OOB, 10 bytes of ECC and 2
> reserved bytes.
>
> If I don't count the reserved bytes as part of ECC, I get 40. If I
> do count it as part of ECC, I get 48. In the way I described
> layouts, I ignored the ECC parts. How did you get 32?
>From the ecc.bytes value you're filling in qcom_nandc_pre_init(). Just
multiplied it by 4 (the number of ECC steps).
And here is where weird things happen: you're setting ecc.size to 512
and ecc.strength to 4. But in reality, what you have is 4bits/516bytes
for the first 3 blocks, and 4bits/500bytes for the last one.
You're not only fooling the MTD user when faking a 4bits/512byte
strength, you're also sightly modifying the logic supposed to detect
the maximum number of bitflips found in a page.
This being said, I understand your constraints, just trying to explain
why we're trying to use the symmetric ECC block size.
>
> >
> > BTW, is the oobfree portion really starting at offset 30?
>
> I thought the offsets mentioned here also had to incorporate positions
> taken by ECC bytes? If I strip all the the in-band data (real data)
> from each step, we get:
>
> ECC(10 bytes).ECC(10 bytes).ECC(10 bytes).OOB(16 bytes).ECC(10 bytes)
>
> Wouldn't this result in the offset as 30?
Yep, as I said I thought it was 32 because of what you put in ecc.size.
And, you're putting OOB bytes before the last chunk of ECC bytes,
because they are protected, right?
Note that you could put the oobfree area at the end of the OOB area,
since this 10-10-10-16-10 representation is already a virtual
representation of the OOB area (ECC bytes are actually interleaved with
in-band data on the flash).
>
> We are still only taking into account 56 bytes out of the 64 bytes
> in the chip's OOB. This is because I'm discaring the 2 bytes from
> each step (summing up to 8) which aren't accessible when ECC is
> enabled.
Okay. As said above, those two bytes could be exposed without two much
overhead for most operations, but that's your call to make.
>
>
> >I'd say that in the 2K page, 4 bit ECC you don't have any oobfree bytes
> > (528 * 4 == 2048 + 64).
>
> 528 contains both oob and in-band data. If you ignore the weird layout
> and assume we have at an average 512 bytes for each step, we get:
>
> 512 * 4 == 2048 bytes of data, and 64 bytes of OOB (16 bytes free, 40
> ECC, and 8 reserved/unused).
Okay. Still think the ECC block asymmetry is not a good idea, but I get
your point ;-).
>
> >
> >> +
> >> +/* 4K page, 4 bit ECC, 8/16 bit bus width */
> >> +static struct nand_ecclayout layout_oob_128 = {
> >> + .eccbytes = 80,
> >> + .oobfree = {
> >> + { 70, 32 },
> >> + },
> >> +};
> >> +
> >> +/* 4K page, 8 bit ECC, 8 bit bus width */
> >> +static struct nand_ecclayout layout_oob_224_x8 = {
> >> + .eccbytes = 104,
> >> + .oobfree = {
> >> + { 91, 32 },
> >> + },
> >> +};
> >> +
> >> +/* 4K page, 8 bit ECC, 16 bit bus width */
> >> +static struct nand_ecclayout layout_oob_224_x16 = {
> >> + .eccbytes = 112,
> >> + .oobfree = {
> >> + { 98, 32 },
> >> + },
> >> +};
> >> +
> >> +/* 8K page, 4 bit ECC, 8/16 bit bus width */
> >> +static struct nand_ecclayout layout_oob_256 = {
> >> + .eccbytes = 160,
> >> + .oobfree = {
> >> + { 151, 64 },
> >> + },
> >> +};
> >
> > Those ECC layout definitions could probably be dynamically created
> > based on the detected ECC strength, bus-width and page size, instead of
> > defining a new one for each new combination.
>
> That's true. I can try that out.
Cool.
>
> >
> >> +
> >> +/*
> >> + * this is called before scan_ident, we do some minimal configurations so
> >> + * that reading ID and ONFI params work
> >> + */
> >> +static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
> >> +{
> >> + /* kill onenand */
> >> + nandc_write(this, SFLASHC_BURST_CFG, 0);
> >> +
> >> + /* enable ADM DMA */
> >> + nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
> >> +
> >> + /* save the original values of these registers */
> >> + this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
> >> + this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
> >> +
> >> + /* initial status value */
> >> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
> >> +}
> >> +
> >> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
> >> +{
> >> + struct mtd_info *mtd = &this->mtd;
> >> + struct nand_chip *chip = &this->chip;
> >
> > struct nand_chip *chip = &this->chip;
> > struct mtd_info *mtd = nand_to_mtd(chip);
> >
> >> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> >> + int cwperpage;
> >> + bool wide_bus;
> >> +
> >> + /* the nand controller fetches codewords/chunks of 512 bytes */
> >> + cwperpage = mtd->writesize >> 9;
> >> +
> >> + ecc->strength = this->ecc_strength;
> >> +
> >> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
> >> +
> >> + if (ecc->strength >= 8) {
> >> + /* 8 bit ECC defaults to BCH ECC on all platforms */
> >> + ecc->bytes = wide_bus ? 14 : 13;
> >
> > Maybe you'd better consider that reserved bytes (after the ECC bytes)
> > are actually ECC bytes. So, according to your description you would
> > always have 16 here.
>
> The thing is that if I consider the reserved bytes as a part of the ECC
> bytes, and if I use this bigger value when configuring the controller
> and dma, I will get bad results; becase the hardware doesn't touch these
> when ECC is enabled.
You should at least be consistent with what you put in your ECC layout.
Choose one solution and stick to it. Since reserved bytes are not
accessible I would suggest to count them in the number of ECC bytes.
>
> I could set the ecc->bytes to '16' and still use the actual values when
> configuring the controller. Do you think that will help in any way?
You can have you own private field(s) to store you controller config,
if that helps, or create a function which would convert ecc.bytes into
something appropriate.
>
> >
> > That's all I got for now.
>
> Thanks again for taking the time for the review. Really appreciate it.
No problem.
Best Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-12-16 11:57 ` Archit Taneja
2015-12-16 14:18 ` Boris Brezillon
@ 2015-12-16 19:16 ` Brian Norris
1 sibling, 0 replies; 71+ messages in thread
From: Brian Norris @ 2015-12-16 19:16 UTC (permalink / raw)
To: Archit Taneja
Cc: Boris Brezillon, dehrenberg, cernekee, sboyd, linux-kernel,
linux-mtd, linux-arm-msm, agross
On Wed, Dec 16, 2015 at 05:27:48PM +0530, Archit Taneja wrote:
> On 12/16/2015 02:45 PM, Boris Brezillon wrote:
> >On Wed, 19 Aug 2015 10:19:03 +0530
> >Archit Taneja <architt@codeaurora.org> wrote:
> >>+ return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
> >
> > return mtd_device_parse_register(mtd, NULL, NULL, NULL 0);
>
> Will fix.
Or just:
return mtd_device_register(mtd, NULL, 0);
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-12-16 14:18 ` Boris Brezillon
@ 2015-12-17 9:48 ` Archit Taneja
2015-12-18 18:48 ` Boris Brezillon
0 siblings, 1 reply; 71+ messages in thread
From: Archit Taneja @ 2015-12-17 9:48 UTC (permalink / raw)
To: Boris Brezillon
Cc: dehrenberg, cernekee, sboyd, linux-kernel, linux-mtd,
linux-arm-msm, computersforpeace, agross
On 12/16/2015 07:48 PM, Boris Brezillon wrote:
> On Wed, 16 Dec 2015 17:27:48 +0530
> Archit Taneja <architt@codeaurora.org> wrote:
>
>>>> +/*
>>>> + * NAND controller page layout info
>>>> + *
>>>> + * |-----------------------| |---------------------------------|
>>>> + * | xx.......xx| | *********xx.......xx|
>>>> + * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx|
>>>> + * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx|
>>>> + * | xx.......xx| | *********xx.......xx|
>>>> + * |-----------------------| |---------------------------------|
>>>> + * codeword 1,2..n-1 codeword n
>>>> + * <---(528/532 Bytes)----> <-------(528/532 Bytes)---------->
>>>> + *
>>>> + * n = number of codewords in the page
>>>> + * . = ECC bytes
>>>> + * * = spare bytes
>>>> + * x = unused/reserved bytes
>>>> + *
>>>> + * 2K page: n = 4, spare = 16 bytes
>>>> + * 4K page: n = 8, spare = 32 bytes
>>>> + * 8K page: n = 16, spare = 64 bytes
>>>
>>> Is there a reason not to use the following layout?
>>>
>>> (
>>> n x (
>>> data = 512 bytes
>>> protected OOB data = 4 bytes
>>> ECC bytes = 12 or 16
>>> )
>>>
>>> +
>>>
>>> remaining unprotected OOB bytes
>>> )
>>>
>>> This way the ECC layout definition would be easier to define, and
>>> you'll have something that is closer to what a NAND chip expect (ECC
>>> block/step size of 512 or 1024).
>>>
>>> I know this is also dependent on the bootloader, hence my question.
>>
>> I tried to figure this out looking at documentation and the downstream
>> drivers. What I understood was that all the OOB was intentionally kept
>> in the last step, so that things are faster when we only want to access
>> OOB. In that case, the controller will need to write to only one
>> step/codeword.
>
> Well, I don't think sending a column change command is that costly
> compared to a page retrieval command or ECC calculation.
Yeah, that's probably true. Although, for this controller, we have
a fixed behavior: if you read a step within a page, the controller
reads the entire 516 bytes into its internal buffer. In other words, the
controller would need to read the entire page for just 16 bytes
of free OOB if we have the standard ECC layout.
>
>>
>> The bootloaders also use the same layout.
>
> Ok, then I guess we'll have to live with that (but it complicates a lot
> the driver logic :-/)
Yeah, it does :/
The controller does support a mode (where free OOB isn't protected by
ECC). In that case, the flash layout is similar to the one you
mentioned. But again, if the bootloaders use the weird layout, then
we don't have much choice.
>
>>
>>>
>>>> + *
>>>> + * the qcom nand controller operates at a sub page/codeword level. each
>>>> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
>>>> + * the number of ECC bytes vary based on the ECC strength and the bus width.
>>>> + *
>>>> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
>>>> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
>>>> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
>>>> + *
>>>> + * the layout described above is used by the controller when the ECC block is
>>>> + * enabled. When we read a page with ECC enabled, the unused/reserved bytes are
>>>> + * skipped and not copied to our internal buffer. therefore, the nand_ecclayout
>>>> + * layouts defined below doesn't consider the positions occupied by the reserved
>>>> + * bytes
>>>
>>> You could just read this portion with the ECC engine disabled when
>>> you're asked for OOB data.
>>
>> Yes, but there are ecc ops (like ecc->read_page/ecc->write_page) that
>> have an argument called 'oob_required'. We need to have ECC enabled when
>> running these ops.
>>
>> In order to read this additional portion, I'll need to read/write each
>> step again with ECC disabled, which would really slow things down.
>
> Nowadays, MTD FS are not using the OOB area, and oob_required is only
> passed if the MTD user asked for OOB data, so that can be an acceptable
> penalty. Anyway, that's not really important if we loose a few OOB
> bytes.
Ah, okay.
>
>>
>>>
>>>> + *
>>>> + * when the ECC block is disabled, one unused byte (or two for 16 bit bus width)
>>>> + * in the last codeword is the position of bad block marker. the bad block
>>>> + * marker cannot be accessed when ECC is enabled.
>>>
>>> So, you're switching the BBM with the data at the BBM position
>>> (possibly some in-band data), right?
>>
>> Yes. When ECC isn't enabled, the BBM byte lies within the in-band data
>> of the last step. In fact, there are dummy BBM bytes in the previous
>> steps at the same offset.
>>
>> With ECC enabled, the controller just skips that position (and the
>> dummy BBM bytes in previous steps) altogether.
>
> Okay.
>
>>
>>>
>>>> + *
>>>> + */
>>>> +
>>>> +/*
>>>> + * Layouts for different page sizes and ecc modes. We skip the eccpos field
>>>> + * since it isn't needed for this driver
>>>> + */
>>>
>>> If you know where they are stored, please specify them, even if they
>>> are not used by the upper layers (this helps analyzing raw nand dumps).
>>>
>>>> +
>>>> +/* 2K page, 4 bit ECC */
>>>> +static struct nand_ecclayout layout_oob_64 = {
>>>> + .eccbytes = 40,
>>>> + .oobfree = {
>>>> + { 30, 16 },
>>>> + },
>>>> +};
>>>
>>> According to your description it should either be eccbytes = 48 (if
>>> you're considering reserved bytes as ECC bytes) or 32 (if you're not
>>> counting reserved bytes).
>>
>> Each step is 528 bytes in total. The first 3 steps contain 516 bytes
>> of data, 10 bytes of ECC and 2 bytes of resrved data. The last step
>> contains 500 bytes of data, 16 bytes of OOB, 10 bytes of ECC and 2
>> reserved bytes.
>>
>> If I don't count the reserved bytes as part of ECC, I get 40. If I
>> do count it as part of ECC, I get 48. In the way I described
>> layouts, I ignored the ECC parts. How did you get 32?
>
> From the ecc.bytes value you're filling in qcom_nandc_pre_init(). Just
> multiplied it by 4 (the number of ECC steps).
Oh, sorry, I didn't point that earlier, but this controller only
supports Reed Solomon for 4 bit ECC. That requires 10 bytes per step.
>
> And here is where weird things happen: you're setting ecc.size to 512
> and ecc.strength to 4. But in reality, what you have is 4bits/516bytes
> for the first 3 blocks, and 4bits/500bytes for the last one.
> You're not only fooling the MTD user when faking a 4bits/512byte
> strength, you're also sightly modifying the logic supposed to detect
> the maximum number of bitflips found in a page.
>
> This being said, I understand your constraints, just trying to explain
> why we're trying to use the symmetric ECC block size.
You're right. The lack of symmetry does cause complications. I can try
to report this for the future, so that the people deciding the layouts
keep this in mind.
>
>>
>>>
>>> BTW, is the oobfree portion really starting at offset 30?
>>
>> I thought the offsets mentioned here also had to incorporate positions
>> taken by ECC bytes? If I strip all the the in-band data (real data)
>> from each step, we get:
>>
>> ECC(10 bytes).ECC(10 bytes).ECC(10 bytes).OOB(16 bytes).ECC(10 bytes)
>>
>> Wouldn't this result in the offset as 30?
>
> Yep, as I said I thought it was 32 because of what you put in ecc.size.
> And, you're putting OOB bytes before the last chunk of ECC bytes,
> because they are protected, right?
Yes.
>
> Note that you could put the oobfree area at the end of the OOB area,
> since this 10-10-10-16-10 representation is already a virtual
> representation of the OOB area (ECC bytes are actually interleaved with
> in-band data on the flash).
But, when I read from the controller's internal buffer via DMA, I first
get the oobfree area, and only then the last step's ECC bytes. So, the
content in chip->oob_poi is in the same order as mentioned
above (10-10-10-16-10).
If the upper layers uses MTD_OPS_AUTO_OOB, and if I have a different
layout as what it is in the oob_poi buffer, then it'll end up
reading/writing the wrong bytes in nand_transfer_oob/nand_fill_oob.
Are you suggesting that I modify the contents of oob_poi by hand such
that it has a cleaner 10-10-10-10-16 representation?
>
>>
>> We are still only taking into account 56 bytes out of the 64 bytes
>> in the chip's OOB. This is because I'm discaring the 2 bytes from
>> each step (summing up to 8) which aren't accessible when ECC is
>> enabled.
>
> Okay. As said above, those two bytes could be exposed without two much
> overhead for most operations, but that's your call to make.
When I read the oob regions into a buffer via DMA, I get a total of 56
bytes. For the extra 8 bytes, I will have to insert 2 dummy bytes
manually for each step by hand. If I don't, then I'll end up messing
what I read/write to oob.
Are you suggesting I do that? It will make the code slightly more messy,
but as you said, at least give a more clearer description of the layout.
>
>>
>>
>>> I'd say that in the 2K page, 4 bit ECC you don't have any oobfree bytes
>>> (528 * 4 == 2048 + 64).
>>
>> 528 contains both oob and in-band data. If you ignore the weird layout
>> and assume we have at an average 512 bytes for each step, we get:
>>
>> 512 * 4 == 2048 bytes of data, and 64 bytes of OOB (16 bytes free, 40
>> ECC, and 8 reserved/unused).
>
> Okay. Still think the ECC block asymmetry is not a good idea, but I get
> your point ;-).
haha yeah, I don't think it's a good idea either :p. Sadly, we're stuck
with it.
>
>>
>>>
>>>> +
>>>> +/* 4K page, 4 bit ECC, 8/16 bit bus width */
>>>> +static struct nand_ecclayout layout_oob_128 = {
>>>> + .eccbytes = 80,
>>>> + .oobfree = {
>>>> + { 70, 32 },
>>>> + },
>>>> +};
>>>> +
>>>> +/* 4K page, 8 bit ECC, 8 bit bus width */
>>>> +static struct nand_ecclayout layout_oob_224_x8 = {
>>>> + .eccbytes = 104,
>>>> + .oobfree = {
>>>> + { 91, 32 },
>>>> + },
>>>> +};
>>>> +
>>>> +/* 4K page, 8 bit ECC, 16 bit bus width */
>>>> +static struct nand_ecclayout layout_oob_224_x16 = {
>>>> + .eccbytes = 112,
>>>> + .oobfree = {
>>>> + { 98, 32 },
>>>> + },
>>>> +};
>>>> +
>>>> +/* 8K page, 4 bit ECC, 8/16 bit bus width */
>>>> +static struct nand_ecclayout layout_oob_256 = {
>>>> + .eccbytes = 160,
>>>> + .oobfree = {
>>>> + { 151, 64 },
>>>> + },
>>>> +};
>>>
>>> Those ECC layout definitions could probably be dynamically created
>>> based on the detected ECC strength, bus-width and page size, instead of
>>> defining a new one for each new combination.
>>
>> That's true. I can try that out.
>
> Cool.
>
>>
>>>
>>>> +
>>>> +/*
>>>> + * this is called before scan_ident, we do some minimal configurations so
>>>> + * that reading ID and ONFI params work
>>>> + */
>>>> +static void qcom_nandc_pre_init(struct qcom_nandc_data *this)
>>>> +{
>>>> + /* kill onenand */
>>>> + nandc_write(this, SFLASHC_BURST_CFG, 0);
>>>> +
>>>> + /* enable ADM DMA */
>>>> + nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN);
>>>> +
>>>> + /* save the original values of these registers */
>>>> + this->cmd1 = nandc_read(this, NAND_DEV_CMD1);
>>>> + this->vld = nandc_read(this, NAND_DEV_CMD_VLD);
>>>> +
>>>> + /* initial status value */
>>>> + this->status = NAND_STATUS_READY | NAND_STATUS_WP;
>>>> +}
>>>> +
>>>> +static int qcom_nandc_ecc_init(struct qcom_nandc_data *this)
>>>> +{
>>>> + struct mtd_info *mtd = &this->mtd;
>>>> + struct nand_chip *chip = &this->chip;
>>>
>>> struct nand_chip *chip = &this->chip;
>>> struct mtd_info *mtd = nand_to_mtd(chip);
>>>
>>>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>>>> + int cwperpage;
>>>> + bool wide_bus;
>>>> +
>>>> + /* the nand controller fetches codewords/chunks of 512 bytes */
>>>> + cwperpage = mtd->writesize >> 9;
>>>> +
>>>> + ecc->strength = this->ecc_strength;
>>>> +
>>>> + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
>>>> +
>>>> + if (ecc->strength >= 8) {
>>>> + /* 8 bit ECC defaults to BCH ECC on all platforms */
>>>> + ecc->bytes = wide_bus ? 14 : 13;
>>>
>>> Maybe you'd better consider that reserved bytes (after the ECC bytes)
>>> are actually ECC bytes. So, according to your description you would
>>> always have 16 here.
>>
>> The thing is that if I consider the reserved bytes as a part of the ECC
>> bytes, and if I use this bigger value when configuring the controller
>> and dma, I will get bad results; becase the hardware doesn't touch these
>> when ECC is enabled.
>
> You should at least be consistent with what you put in your ECC layout.
> Choose one solution and stick to it. Since reserved bytes are not
> accessible I would suggest to count them in the number of ECC bytes.
>
>>
>> I could set the ecc->bytes to '16' and still use the actual values when
>> configuring the controller. Do you think that will help in any way?
>
> You can have you own private field(s) to store you controller config,
> if that helps, or create a function which would convert ecc.bytes into
> something appropriate.
Right. Got it.
Thanks,
Archit
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver
2015-12-17 9:48 ` Archit Taneja
@ 2015-12-18 18:48 ` Boris Brezillon
0 siblings, 0 replies; 71+ messages in thread
From: Boris Brezillon @ 2015-12-18 18:48 UTC (permalink / raw)
To: Archit Taneja
Cc: dehrenberg, cernekee, sboyd, linux-kernel, linux-mtd,
linux-arm-msm, computersforpeace, agross
Hi Archit,
On Thu, 17 Dec 2015 15:18:46 +0530
Archit Taneja <architt@codeaurora.org> wrote:
>
> >
> > Note that you could put the oobfree area at the end of the OOB area,
> > since this 10-10-10-16-10 representation is already a virtual
> > representation of the OOB area (ECC bytes are actually interleaved with
> > in-band data on the flash).
>
> But, when I read from the controller's internal buffer via DMA, I first
> get the oobfree area, and only then the last step's ECC bytes. So, the
> content in chip->oob_poi is in the same order as mentioned
> above (10-10-10-16-10).
>
> If the upper layers uses MTD_OPS_AUTO_OOB, and if I have a different
> layout as what it is in the oob_poi buffer, then it'll end up
> reading/writing the wrong bytes in nand_transfer_oob/nand_fill_oob.
>
> Are you suggesting that I modify the contents of oob_poi by hand such
> that it has a cleaner 10-10-10-10-16 representation?
Hm, I thought you could just place the free oob bytes wherever you want
since there's only one oobfree region. AFAICS, it's just a matter of
passing ->oob_poi + 40 instead of passing ->oob_poi + 30 when preparing
the DMA descriptor (30 and 40 are just numbers for this specific use
case).
Anyway, I won't complain if you address all comments but this one.
Best Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 71+ messages in thread
end of thread, other threads:[~2015-12-18 18:48 UTC | newest]
Thread overview: 71+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-01-16 14:48 ` [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x Archit Taneja
2015-01-16 21:56 ` Stephen Boyd
2015-01-19 10:32 ` Archit Taneja
2015-01-29 22:21 ` Stephen Boyd
2015-01-16 14:48 ` [PATCH 2/5] mtd: nand: Add qcom nand controller driver Archit Taneja
2015-01-21 0:54 ` Daniel Ehrenberg
2015-01-22 6:36 ` Archit Taneja
2015-01-26 21:05 ` Kevin Cernekee
2015-01-27 3:56 ` Archit Taneja
2015-01-16 14:48 ` [PATCH 3/5] Documentaion: dt: add DT bindings for Qualcomm NAND controller Archit Taneja
2015-01-16 14:48 ` [PATCH 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-01-16 14:48 ` [PATCH 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 pplatform Archit Taneja
2015-02-18 6:03 ` [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
2015-07-21 10:34 ` [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-07-24 19:01 ` Andy Gross
2015-07-21 10:34 ` [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-07-24 19:39 ` Andy Gross
2015-07-25 0:51 ` Stephen Boyd
2015-07-28 4:34 ` Archit Taneja
2015-07-29 1:48 ` Stephen Boyd
2015-07-29 5:14 ` Archit Taneja
2015-07-29 18:33 ` Stephen Boyd
2015-07-30 6:53 ` Archit Taneja
2015-07-21 10:34 ` [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2015-07-24 18:57 ` Andy Gross
2015-07-24 19:37 ` Stephen Boyd
2015-07-21 10:34 ` [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-07-24 19:01 ` Andy Gross
2015-07-21 10:34 ` [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform Archit Taneja
2015-07-24 18:58 ` Andy Gross
2015-07-24 18:59 ` Andy Gross
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-03 5:08 ` [PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-08-03 5:08 ` [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-08-03 23:38 ` Stephen Boyd
2015-08-04 15:04 ` Archit Taneja
2015-08-04 17:53 ` Stephen Boyd
2015-08-03 5:08 ` [PATCH v3 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2015-08-03 5:08 ` [PATCH v3 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-08-03 5:08 ` [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
2015-08-03 19:35 ` Andy Gross
2015-08-04 15:05 ` Archit Taneja
2015-08-03 20:58 ` Stephen Boyd
2015-08-04 15:06 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-19 4:49 ` [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-10-02 2:44 ` Brian Norris
2015-10-02 6:27 ` Boris Brezillon
2015-10-11 20:03 ` Brian Norris
2015-11-10 5:13 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-08-26 23:37 ` Stephen Boyd
2015-09-13 13:42 ` Archit Taneja
2015-10-02 3:05 ` Brian Norris
2015-10-05 6:51 ` Archit Taneja
2015-10-06 9:17 ` Brian Norris
2015-10-07 4:11 ` Archit Taneja
2015-10-02 17:31 ` Brian Norris
2015-12-16 9:15 ` Boris Brezillon
2015-12-16 11:57 ` Archit Taneja
2015-12-16 14:18 ` Boris Brezillon
2015-12-17 9:48 ` Archit Taneja
2015-12-18 18:48 ` Boris Brezillon
2015-12-16 19:16 ` Brian Norris
2015-08-19 4:49 ` [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2015-12-16 6:33 ` Boris Brezillon
2015-12-16 8:11 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-08-19 4:49 ` [PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
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